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Magnus Damm0468b2d2013-03-28 00:49:34 +09001/*
2 * Device Tree Source for the r8a7790 SoC
3 *
Kazuya Mizuguchib621f6d2015-02-19 10:42:55 -05004 * Copyright (C) 2015 Renesas Electronics Corporation
Sergei Shtylyovd8913c62014-02-20 02:20:43 +03005 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
Magnus Damm0468b2d2013-03-28 00:49:34 +09007 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
Laurent Pinchart22a1f592013-12-11 15:05:14 +010013#include <dt-bindings/clock/r8a7790-clock.h>
Laurent Pinchart5f75e732013-11-19 03:18:25 +010014#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +010016#include <dt-bindings/power/r8a7790-sysc.h>
Laurent Pinchart5f75e732013-11-19 03:18:25 +010017
Magnus Damm0468b2d2013-03-28 00:49:34 +090018/ {
19 compatible = "renesas,r8a7790";
20 interrupt-parent = <&gic>;
Takashi Yoshii8585deb2013-03-29 16:49:17 +090021 #address-cells = <2>;
22 #size-cells = <2>;
Magnus Damm0468b2d2013-03-28 00:49:34 +090023
Wolfram Sang6b1d7c62014-02-16 10:40:58 +010024 aliases {
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
Wolfram Sang05f39912014-03-25 19:56:29 +010029 i2c4 = &iic0;
30 i2c5 = &iic1;
31 i2c6 = &iic2;
32 i2c7 = &iic3;
Geert Uytterhoevenfad6d452014-02-25 11:30:13 +010033 spi0 = &qspi;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +010034 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
37 spi4 = &msiof3;
Ben Dooks9f685bf2014-08-13 00:16:18 +040038 vin0 = &vin0;
39 vin1 = &vin1;
40 vin2 = &vin2;
41 vin3 = &vin3;
Wolfram Sang6b1d7c62014-02-16 10:40:58 +010042 };
43
Magnus Damm0468b2d2013-03-28 00:49:34 +090044 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
Magnus Dammdc378792016-06-28 16:10:40 +020047 enable-method = "renesas,apmu";
Magnus Damm0468b2d2013-03-28 00:49:34 +090048
49 cpu0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a15";
52 reg = <0>;
53 clock-frequency = <1300000000>;
Benoit Coussonb989e132014-06-03 21:02:24 +090054 voltage-tolerance = <1>; /* 1% */
55 clocks = <&cpg_clocks R8A7790_CLK_Z>;
56 clock-latency = <300000>; /* 300 us */
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +010057 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
Geert Uytterhoevenfb1cecd2015-06-02 14:31:39 +020058 next-level-cache = <&L2_CA15>;
Benoit Coussonb989e132014-06-03 21:02:24 +090059
60 /* kHz - uV - OPPs unknown yet */
61 operating-points = <1400000 1000000>,
62 <1225000 1000000>,
63 <1050000 1000000>,
64 < 875000 1000000>,
65 < 700000 1000000>,
66 < 350000 1000000>;
Magnus Damm0468b2d2013-03-28 00:49:34 +090067 };
Magnus Dammc1f95972013-08-29 08:22:17 +090068
69 cpu1: cpu@1 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a15";
72 reg = <1>;
73 clock-frequency = <1300000000>;
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +010074 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
Geert Uytterhoevenfb1cecd2015-06-02 14:31:39 +020075 next-level-cache = <&L2_CA15>;
Magnus Dammc1f95972013-08-29 08:22:17 +090076 };
77
78 cpu2: cpu@2 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a15";
81 reg = <2>;
82 clock-frequency = <1300000000>;
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +010083 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
Geert Uytterhoevenfb1cecd2015-06-02 14:31:39 +020084 next-level-cache = <&L2_CA15>;
Magnus Dammc1f95972013-08-29 08:22:17 +090085 };
86
87 cpu3: cpu@3 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a15";
90 reg = <3>;
91 clock-frequency = <1300000000>;
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +010092 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
Geert Uytterhoevenfb1cecd2015-06-02 14:31:39 +020093 next-level-cache = <&L2_CA15>;
Magnus Dammc1f95972013-08-29 08:22:17 +090094 };
Magnus Damm2007e742013-09-15 00:28:58 +090095
Geert Uytterhoeven1eed15e2016-05-13 09:38:33 +020096 cpu4: cpu@100 {
Magnus Damm2007e742013-09-15 00:28:58 +090097 device_type = "cpu";
98 compatible = "arm,cortex-a7";
99 reg = <0x100>;
100 clock-frequency = <780000000>;
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +0100101 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
Geert Uytterhoevenfb1cecd2015-06-02 14:31:39 +0200102 next-level-cache = <&L2_CA7>;
Magnus Damm2007e742013-09-15 00:28:58 +0900103 };
104
Geert Uytterhoeven1eed15e2016-05-13 09:38:33 +0200105 cpu5: cpu@101 {
Magnus Damm2007e742013-09-15 00:28:58 +0900106 device_type = "cpu";
107 compatible = "arm,cortex-a7";
108 reg = <0x101>;
109 clock-frequency = <780000000>;
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +0100110 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
Geert Uytterhoevenfb1cecd2015-06-02 14:31:39 +0200111 next-level-cache = <&L2_CA7>;
Magnus Damm2007e742013-09-15 00:28:58 +0900112 };
113
Geert Uytterhoeven1eed15e2016-05-13 09:38:33 +0200114 cpu6: cpu@102 {
Magnus Damm2007e742013-09-15 00:28:58 +0900115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x102>;
118 clock-frequency = <780000000>;
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +0100119 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
Geert Uytterhoevenfb1cecd2015-06-02 14:31:39 +0200120 next-level-cache = <&L2_CA7>;
Magnus Damm2007e742013-09-15 00:28:58 +0900121 };
122
Geert Uytterhoeven1eed15e2016-05-13 09:38:33 +0200123 cpu7: cpu@103 {
Magnus Damm2007e742013-09-15 00:28:58 +0900124 device_type = "cpu";
125 compatible = "arm,cortex-a7";
126 reg = <0x103>;
127 clock-frequency = <780000000>;
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +0100128 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
Geert Uytterhoevenfb1cecd2015-06-02 14:31:39 +0200129 next-level-cache = <&L2_CA7>;
Magnus Damm2007e742013-09-15 00:28:58 +0900130 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +0200131
132 L2_CA15: cache-controller@0 {
133 compatible = "cache";
134 reg = <0>;
135 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
136 cache-unified;
137 cache-level = <2>;
138 };
139
140 L2_CA7: cache-controller@100 {
141 compatible = "cache";
142 reg = <0x100>;
143 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
144 cache-unified;
145 cache-level = <2>;
146 };
Magnus Damm0468b2d2013-03-28 00:49:34 +0900147 };
148
Kuninori Morimotoa8b805f2016-01-28 02:45:34 +0000149 thermal-zones {
150 cpu_thermal: cpu-thermal {
151 polling-delay-passive = <0>;
152 polling-delay = <0>;
153
154 thermal-sensors = <&thermal>;
155
156 trips {
157 cpu-crit {
158 temperature = <115000>;
159 hysteresis = <0>;
160 type = "critical";
161 };
162 };
163 cooling-maps {
164 };
165 };
166 };
167
Magnus Dammdc378792016-06-28 16:10:40 +0200168 apmu@e6151000 {
169 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
170 reg = <0 0xe6151000 0 0x188>;
171 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
172 };
173
174 apmu@e6152000 {
175 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
176 reg = <0 0xe6152000 0 0x188>;
177 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
178 };
179
Magnus Damm0468b2d2013-03-28 00:49:34 +0900180 gic: interrupt-controller@f1001000 {
Geert Uytterhoevene715e9c2015-06-17 15:03:33 +0200181 compatible = "arm,gic-400";
Magnus Damm0468b2d2013-03-28 00:49:34 +0900182 #interrupt-cells = <3>;
183 #address-cells = <0>;
184 interrupt-controller;
Takashi Yoshii8585deb2013-03-29 16:49:17 +0900185 reg = <0 0xf1001000 0 0x1000>,
186 <0 0xf1002000 0 0x1000>,
187 <0 0xf1004000 0 0x2000>,
188 <0 0xf1006000 0 0x2000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900189 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
Magnus Damm0468b2d2013-03-28 00:49:34 +0900190 };
191
Magnus Damm23de2272013-11-21 14:19:29 +0900192 gpio0: gpio@e6050000 {
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
Magnus Damm23de2272013-11-21 14:19:29 +0900194 reg = <0 0xe6050000 0 0x50>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900195 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 0 32>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
Geert Uytterhoeven81f68832014-04-23 10:25:27 +0200201 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100202 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200203 };
204
Magnus Damm23de2272013-11-21 14:19:29 +0900205 gpio1: gpio@e6051000 {
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
Magnus Damm23de2272013-11-21 14:19:29 +0900207 reg = <0 0xe6051000 0 0x50>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200209 #gpio-cells = <2>;
210 gpio-controller;
Sergei Shtylyov56a2182f2015-10-22 02:04:41 +0300211 gpio-ranges = <&pfc 0 32 30>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200212 #interrupt-cells = <2>;
213 interrupt-controller;
Geert Uytterhoeven81f68832014-04-23 10:25:27 +0200214 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100215 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200216 };
217
Magnus Damm23de2272013-11-21 14:19:29 +0900218 gpio2: gpio@e6052000 {
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
Magnus Damm23de2272013-11-21 14:19:29 +0900220 reg = <0 0xe6052000 0 0x50>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900221 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200222 #gpio-cells = <2>;
223 gpio-controller;
Sergei Shtylyov56a2182f2015-10-22 02:04:41 +0300224 gpio-ranges = <&pfc 0 64 30>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200225 #interrupt-cells = <2>;
226 interrupt-controller;
Geert Uytterhoeven81f68832014-04-23 10:25:27 +0200227 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100228 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200229 };
230
Magnus Damm23de2272013-11-21 14:19:29 +0900231 gpio3: gpio@e6053000 {
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
Magnus Damm23de2272013-11-21 14:19:29 +0900233 reg = <0 0xe6053000 0 0x50>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900234 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 96 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
Geert Uytterhoeven81f68832014-04-23 10:25:27 +0200240 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100241 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200242 };
243
Magnus Damm23de2272013-11-21 14:19:29 +0900244 gpio4: gpio@e6054000 {
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200245 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
Magnus Damm23de2272013-11-21 14:19:29 +0900246 reg = <0 0xe6054000 0 0x50>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900247 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200248 #gpio-cells = <2>;
249 gpio-controller;
250 gpio-ranges = <&pfc 0 128 32>;
251 #interrupt-cells = <2>;
252 interrupt-controller;
Geert Uytterhoeven81f68832014-04-23 10:25:27 +0200253 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100254 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200255 };
256
Magnus Damm23de2272013-11-21 14:19:29 +0900257 gpio5: gpio@e6055000 {
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200258 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
Magnus Damm23de2272013-11-21 14:19:29 +0900259 reg = <0 0xe6055000 0 0x50>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200261 #gpio-cells = <2>;
262 gpio-controller;
263 gpio-ranges = <&pfc 0 160 32>;
264 #interrupt-cells = <2>;
265 interrupt-controller;
Geert Uytterhoeven81f68832014-04-23 10:25:27 +0200266 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100267 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchartf98e10c2013-05-10 15:51:14 +0200268 };
269
Kuninori Morimotoa8b805f2016-01-28 02:45:34 +0000270 thermal: thermal@e61f0000 {
271 compatible = "renesas,thermal-r8a7790",
272 "renesas,rcar-gen2-thermal",
273 "renesas,rcar-thermal";
Magnus Damm03e2f562013-11-20 16:59:30 +0900274 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900275 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevend3a439d2014-01-07 19:57:14 +0100276 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100277 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Kuninori Morimotoa8b805f2016-01-28 02:45:34 +0000278 #thermal-sensor-cells = <0>;
Magnus Damm03e2f562013-11-20 16:59:30 +0900279 };
280
Magnus Damm0468b2d2013-03-28 00:49:34 +0900281 timer {
282 compatible = "arm,armv7-timer";
Simon Horman3abb4d52016-01-15 11:44:15 +0900283 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
284 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
285 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
286 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
Magnus Damm0468b2d2013-03-28 00:49:34 +0900287 };
Magnus Damm8f5ec0a2013-03-28 00:49:54 +0900288
Laurent Pinchart39cf6d72014-07-09 15:12:37 +0200289 cmt0: timer@ffca0000 {
Simon Horman37757032014-09-08 09:27:45 +0900290 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
Laurent Pinchart39cf6d72014-07-09 15:12:37 +0200291 reg = <0 0xffca0000 0 0x1004>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900292 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart39cf6d72014-07-09 15:12:37 +0200294 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
295 clock-names = "fck";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100296 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart39cf6d72014-07-09 15:12:37 +0200297
298 renesas,channels-mask = <0x60>;
299
300 status = "disabled";
301 };
302
303 cmt1: timer@e6130000 {
Simon Horman37757032014-09-08 09:27:45 +0900304 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
Laurent Pinchart39cf6d72014-07-09 15:12:37 +0200305 reg = <0 0xe6130000 0 0x1004>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900306 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart39cf6d72014-07-09 15:12:37 +0200314 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
315 clock-names = "fck";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100316 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart39cf6d72014-07-09 15:12:37 +0200317
318 renesas,channels-mask = <0xff>;
319
320 status = "disabled";
321 };
322
Magnus Damm8f5ec0a2013-03-28 00:49:54 +0900323 irqc0: interrupt-controller@e61c0000 {
Magnus Damm220fc352013-11-20 09:07:40 +0900324 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
Magnus Damm8f5ec0a2013-03-28 00:49:54 +0900325 #interrupt-cells = <2>;
326 interrupt-controller;
Takashi Yoshii8585deb2013-03-29 16:49:17 +0900327 reg = <0 0xe61c0000 0 0x200>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900328 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven61624ca2015-03-18 19:55:59 +0100332 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100333 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Magnus Damm8f5ec0a2013-03-28 00:49:54 +0900334 };
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200335
Laurent Pinchartb9fea492014-07-19 01:50:24 +0200336 dmac0: dma-controller@e6700000 {
Simon Horman4af0a662015-11-13 11:23:48 +0900337 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
Laurent Pinchartb9fea492014-07-19 01:50:24 +0200338 reg = <0 0xe6700000 0 0x20000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900339 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartb9fea492014-07-19 01:50:24 +0200355 interrupt-names = "error",
356 "ch0", "ch1", "ch2", "ch3",
357 "ch4", "ch5", "ch6", "ch7",
358 "ch8", "ch9", "ch10", "ch11",
359 "ch12", "ch13", "ch14";
360 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
361 clock-names = "fck";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100362 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchartb9fea492014-07-19 01:50:24 +0200363 #dma-cells = <1>;
364 dma-channels = <15>;
365 };
366
367 dmac1: dma-controller@e6720000 {
Simon Horman4af0a662015-11-13 11:23:48 +0900368 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
Laurent Pinchartb9fea492014-07-19 01:50:24 +0200369 reg = <0 0xe6720000 0 0x20000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900370 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchartb9fea492014-07-19 01:50:24 +0200386 interrupt-names = "error",
387 "ch0", "ch1", "ch2", "ch3",
388 "ch4", "ch5", "ch6", "ch7",
389 "ch8", "ch9", "ch10", "ch11",
390 "ch12", "ch13", "ch14";
391 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
392 clock-names = "fck";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100393 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchartb9fea492014-07-19 01:50:24 +0200394 #dma-cells = <1>;
395 dma-channels = <15>;
396 };
Kuninori Morimotoba3240b2014-11-03 17:44:51 -0800397
398 audma0: dma-controller@ec700000 {
Simon Horman4af0a662015-11-13 11:23:48 +0900399 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
Kuninori Morimotoba3240b2014-11-03 17:44:51 -0800400 reg = <0 0xec700000 0 0x10000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900401 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
402 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
403 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
404 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimotoba3240b2014-11-03 17:44:51 -0800415 interrupt-names = "error",
416 "ch0", "ch1", "ch2", "ch3",
417 "ch4", "ch5", "ch6", "ch7",
418 "ch8", "ch9", "ch10", "ch11",
419 "ch12";
420 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
421 clock-names = "fck";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100422 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Kuninori Morimotoba3240b2014-11-03 17:44:51 -0800423 #dma-cells = <1>;
424 dma-channels = <13>;
425 };
426
427 audma1: dma-controller@ec720000 {
Simon Horman4af0a662015-11-13 11:23:48 +0900428 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
Kuninori Morimotoba3240b2014-11-03 17:44:51 -0800429 reg = <0 0xec720000 0 0x10000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900430 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
431 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
432 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
433 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
435 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
436 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
437 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
438 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
439 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
440 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
441 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
442 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
443 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimotoba3240b2014-11-03 17:44:51 -0800444 interrupt-names = "error",
445 "ch0", "ch1", "ch2", "ch3",
446 "ch4", "ch5", "ch6", "ch7",
447 "ch8", "ch9", "ch10", "ch11",
448 "ch12";
449 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
450 clock-names = "fck";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100451 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Kuninori Morimotoba3240b2014-11-03 17:44:51 -0800452 #dma-cells = <1>;
453 dma-channels = <13>;
454 };
455
Yoshihiro Shimodaa3ff2092015-05-08 16:13:06 +0900456 usb_dmac0: dma-controller@e65a0000 {
Simon Hormand01c8be2015-12-11 11:59:38 +0900457 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
Yoshihiro Shimodaa3ff2092015-05-08 16:13:06 +0900458 reg = <0 0xe65a0000 0 0x100>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900459 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
460 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
Yoshihiro Shimodaa3ff2092015-05-08 16:13:06 +0900461 interrupt-names = "ch0", "ch1";
462 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100463 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Yoshihiro Shimodaa3ff2092015-05-08 16:13:06 +0900464 #dma-cells = <1>;
465 dma-channels = <2>;
466 };
467
468 usb_dmac1: dma-controller@e65b0000 {
Simon Hormand01c8be2015-12-11 11:59:38 +0900469 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
Yoshihiro Shimodaa3ff2092015-05-08 16:13:06 +0900470 reg = <0 0xe65b0000 0 0x100>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900471 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
472 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
Yoshihiro Shimodaa3ff2092015-05-08 16:13:06 +0900473 interrupt-names = "ch0", "ch1";
474 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100475 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Yoshihiro Shimodaa3ff2092015-05-08 16:13:06 +0900476 #dma-cells = <1>;
477 dma-channels = <2>;
478 };
479
Guennadi Liakhovetskiedd2b9f2013-09-26 19:20:58 +0200480 i2c0: i2c@e6508000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "renesas,i2c-r8a7790";
484 reg = <0 0xe6508000 0 0x40>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900485 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
Ben Dooks2450bad2014-01-20 11:44:21 +0000486 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100487 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Wolfram Sangac8e7f32015-12-08 10:37:50 +0100488 i2c-scl-internal-delay-ns = <110>;
Guennadi Liakhovetskiedd2b9f2013-09-26 19:20:58 +0200489 status = "disabled";
490 };
491
492 i2c1: i2c@e6518000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "renesas,i2c-r8a7790";
496 reg = <0 0xe6518000 0 0x40>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900497 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
Ben Dooks2450bad2014-01-20 11:44:21 +0000498 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100499 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Wolfram Sangac8e7f32015-12-08 10:37:50 +0100500 i2c-scl-internal-delay-ns = <6>;
Guennadi Liakhovetskiedd2b9f2013-09-26 19:20:58 +0200501 status = "disabled";
502 };
503
504 i2c2: i2c@e6530000 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a7790";
508 reg = <0 0xe6530000 0 0x40>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900509 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
Ben Dooks2450bad2014-01-20 11:44:21 +0000510 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100511 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Wolfram Sangac8e7f32015-12-08 10:37:50 +0100512 i2c-scl-internal-delay-ns = <6>;
Guennadi Liakhovetskiedd2b9f2013-09-26 19:20:58 +0200513 status = "disabled";
514 };
515
516 i2c3: i2c@e6540000 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 compatible = "renesas,i2c-r8a7790";
520 reg = <0 0xe6540000 0 0x40>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900521 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
Ben Dooks2450bad2014-01-20 11:44:21 +0000522 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100523 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Wolfram Sangac8e7f32015-12-08 10:37:50 +0100524 i2c-scl-internal-delay-ns = <110>;
Guennadi Liakhovetskiedd2b9f2013-09-26 19:20:58 +0200525 status = "disabled";
526 };
527
Wolfram Sang05f39912014-03-25 19:56:29 +0100528 iic0: i2c@e6500000 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
532 reg = <0 0xe6500000 0 0x425>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900533 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang05f39912014-03-25 19:56:29 +0100534 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200535 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
536 <&dmac1 0x61>, <&dmac1 0x62>;
537 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100538 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Wolfram Sang05f39912014-03-25 19:56:29 +0100539 status = "disabled";
540 };
541
542 iic1: i2c@e6510000 {
543 #address-cells = <1>;
544 #size-cells = <0>;
545 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
546 reg = <0 0xe6510000 0 0x425>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900547 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang05f39912014-03-25 19:56:29 +0100548 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200549 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
550 <&dmac1 0x65>, <&dmac1 0x66>;
551 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100552 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Wolfram Sang05f39912014-03-25 19:56:29 +0100553 status = "disabled";
554 };
555
556 iic2: i2c@e6520000 {
557 #address-cells = <1>;
558 #size-cells = <0>;
559 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
560 reg = <0 0xe6520000 0 0x425>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900561 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang05f39912014-03-25 19:56:29 +0100562 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200563 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
564 <&dmac1 0x69>, <&dmac1 0x6a>;
565 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100566 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Wolfram Sang05f39912014-03-25 19:56:29 +0100567 status = "disabled";
568 };
569
570 iic3: i2c@e60b0000 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
574 reg = <0 0xe60b0000 0 0x425>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900575 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
Wolfram Sang05f39912014-03-25 19:56:29 +0100576 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200577 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
578 <&dmac1 0x77>, <&dmac1 0x78>;
579 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100580 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Wolfram Sang05f39912014-03-25 19:56:29 +0100581 status = "disabled";
582 };
583
Laurent Pinchart22c2b782014-10-26 19:40:11 +0200584 mmcif0: mmc@ee200000 {
Magnus Damm063e85602013-11-20 09:05:53 +0900585 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200586 reg = <0 0xee200000 0 0x80>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900587 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart72197ca2013-12-11 15:05:15 +0100588 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200589 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
590 <&dmac1 0xd1>, <&dmac1 0xd2>;
591 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100592 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200593 reg-io-width = <4>;
594 status = "disabled";
Kuninori Morimoto96370052015-05-14 07:23:04 +0000595 max-frequency = <97500000>;
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200596 };
597
Kuninori Morimotob718aa42013-10-21 19:36:13 -0700598 mmcif1: mmc@ee220000 {
Magnus Damm063e85602013-11-20 09:05:53 +0900599 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200600 reg = <0 0xee220000 0 0x80>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900601 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart72197ca2013-12-11 15:05:15 +0100602 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200603 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
604 <&dmac1 0xe1>, <&dmac1 0xe2>;
605 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100606 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200607 reg-io-width = <4>;
608 status = "disabled";
Kuninori Morimoto96370052015-05-14 07:23:04 +0000609 max-frequency = <97500000>;
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200610 };
611
Laurent Pinchart9694c772013-05-09 15:05:57 +0200612 pfc: pfc@e6060000 {
613 compatible = "renesas,pfc-r8a7790";
614 reg = <0 0xe6060000 0 0x250>;
615 };
Olof Johansson55689bf2013-08-14 00:24:05 -0700616
Kuninori Morimotob718aa42013-10-21 19:36:13 -0700617 sdhi0: sd@ee100000 {
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200618 compatible = "renesas,sdhi-r8a7790";
Kuninori Morimoto66f47ed2015-02-24 02:20:37 +0000619 reg = <0 0xee100000 0 0x328>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900620 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart72197ca2013-12-11 15:05:15 +0100621 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200622 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
623 <&dmac1 0xcd>, <&dmac1 0xce>;
624 dma-names = "tx", "rx", "tx", "rx";
Wolfram Sang21c7d0f2016-04-18 11:41:30 +0200625 max-frequency = <195000000>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100626 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200627 status = "disabled";
628 };
629
Kuninori Morimotob718aa42013-10-21 19:36:13 -0700630 sdhi1: sd@ee120000 {
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200631 compatible = "renesas,sdhi-r8a7790";
Kuninori Morimoto66f47ed2015-02-24 02:20:37 +0000632 reg = <0 0xee120000 0 0x328>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900633 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart72197ca2013-12-11 15:05:15 +0100634 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200635 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
636 <&dmac1 0xc9>, <&dmac1 0xca>;
637 dma-names = "tx", "rx", "tx", "rx";
Wolfram Sang21c7d0f2016-04-18 11:41:30 +0200638 max-frequency = <195000000>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100639 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200640 status = "disabled";
641 };
642
Kuninori Morimotob718aa42013-10-21 19:36:13 -0700643 sdhi2: sd@ee140000 {
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200644 compatible = "renesas,sdhi-r8a7790";
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200645 reg = <0 0xee140000 0 0x100>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900646 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart72197ca2013-12-11 15:05:15 +0100647 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200648 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
649 <&dmac1 0xc1>, <&dmac1 0xc2>;
650 dma-names = "tx", "rx", "tx", "rx";
Ben Hutchings22f708b2016-04-01 17:44:38 +0200651 max-frequency = <97500000>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100652 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200653 status = "disabled";
654 };
655
Kuninori Morimotob718aa42013-10-21 19:36:13 -0700656 sdhi3: sd@ee160000 {
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200657 compatible = "renesas,sdhi-r8a7790";
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200658 reg = <0 0xee160000 0 0x100>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900659 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart72197ca2013-12-11 15:05:15 +0100660 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200661 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
662 <&dmac1 0xd3>, <&dmac1 0xd4>;
663 dma-names = "tx", "rx", "tx", "rx";
Ben Hutchings22f708b2016-04-01 17:44:38 +0200664 max-frequency = <97500000>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100665 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Guennadi Liakhovetski8c9b1aa2013-07-08 17:54:46 +0200666 status = "disabled";
667 };
Laurent Pinchart22a1f592013-12-11 15:05:14 +0100668
Laurent Pinchart597af202013-10-29 16:23:12 +0100669 scifa0: serial@e6c40000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100670 compatible = "renesas,scifa-r8a7790",
671 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart597af202013-10-29 16:23:12 +0100672 reg = <0 0xe6c40000 0 64>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900673 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100674 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
Laurent Pinchart6c6e12a2016-01-29 10:47:37 +0100675 clock-names = "fck";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200676 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
677 <&dmac1 0x21>, <&dmac1 0x22>;
678 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100679 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100680 status = "disabled";
681 };
682
683 scifa1: serial@e6c50000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100684 compatible = "renesas,scifa-r8a7790",
685 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart597af202013-10-29 16:23:12 +0100686 reg = <0 0xe6c50000 0 64>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900687 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100688 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
Laurent Pinchart6c6e12a2016-01-29 10:47:37 +0100689 clock-names = "fck";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200690 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
691 <&dmac1 0x25>, <&dmac1 0x26>;
692 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100693 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100694 status = "disabled";
695 };
696
697 scifa2: serial@e6c60000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100698 compatible = "renesas,scifa-r8a7790",
699 "renesas,rcar-gen2-scifa", "renesas,scifa";
Laurent Pinchart597af202013-10-29 16:23:12 +0100700 reg = <0 0xe6c60000 0 64>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900701 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100702 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
Laurent Pinchart6c6e12a2016-01-29 10:47:37 +0100703 clock-names = "fck";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200704 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
705 <&dmac1 0x27>, <&dmac1 0x28>;
706 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100707 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100708 status = "disabled";
709 };
710
711 scifb0: serial@e6c20000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100712 compatible = "renesas,scifb-r8a7790",
713 "renesas,rcar-gen2-scifb", "renesas,scifb";
Laurent Pinchart597af202013-10-29 16:23:12 +0100714 reg = <0 0xe6c20000 0 64>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900715 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100716 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
Laurent Pinchart6c6e12a2016-01-29 10:47:37 +0100717 clock-names = "fck";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200718 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
719 <&dmac1 0x3d>, <&dmac1 0x3e>;
720 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100721 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100722 status = "disabled";
723 };
724
725 scifb1: serial@e6c30000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100726 compatible = "renesas,scifb-r8a7790",
727 "renesas,rcar-gen2-scifb", "renesas,scifb";
Laurent Pinchart597af202013-10-29 16:23:12 +0100728 reg = <0 0xe6c30000 0 64>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900729 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100730 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
Laurent Pinchart6c6e12a2016-01-29 10:47:37 +0100731 clock-names = "fck";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200732 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
733 <&dmac1 0x19>, <&dmac1 0x1a>;
734 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100735 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100736 status = "disabled";
737 };
738
739 scifb2: serial@e6ce0000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100740 compatible = "renesas,scifb-r8a7790",
741 "renesas,rcar-gen2-scifb", "renesas,scifb";
Laurent Pinchart597af202013-10-29 16:23:12 +0100742 reg = <0 0xe6ce0000 0 64>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900743 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100744 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
Laurent Pinchart6c6e12a2016-01-29 10:47:37 +0100745 clock-names = "fck";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200746 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
747 <&dmac1 0x1d>, <&dmac1 0x1e>;
748 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100749 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100750 status = "disabled";
751 };
752
753 scif0: serial@e6e60000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100754 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
755 "renesas,scif";
Laurent Pinchart597af202013-10-29 16:23:12 +0100756 reg = <0 0xe6e60000 0 64>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900757 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven42af65e2016-01-29 11:04:39 +0100758 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
759 <&scif_clk>;
760 clock-names = "fck", "brg_int", "scif_clk";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200761 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
762 <&dmac1 0x29>, <&dmac1 0x2a>;
763 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100764 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100765 status = "disabled";
766 };
767
768 scif1: serial@e6e68000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100769 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
770 "renesas,scif";
Laurent Pinchart597af202013-10-29 16:23:12 +0100771 reg = <0 0xe6e68000 0 64>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900772 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven42af65e2016-01-29 11:04:39 +0100773 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
774 <&scif_clk>;
775 clock-names = "fck", "brg_int", "scif_clk";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200776 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
777 <&dmac1 0x2d>, <&dmac1 0x2e>;
778 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100779 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100780 status = "disabled";
781 };
782
Geert Uytterhoeven022869a2016-03-03 10:32:41 +0100783 scif2: serial@e6e56000 {
784 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
785 "renesas,scif";
786 reg = <0 0xe6e56000 0 64>;
787 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
789 <&scif_clk>;
790 clock-names = "fck", "brg_int", "scif_clk";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200791 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
792 <&dmac1 0x2b>, <&dmac1 0x2c>;
793 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100794 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Geert Uytterhoeven022869a2016-03-03 10:32:41 +0100795 status = "disabled";
796 };
797
Laurent Pinchart597af202013-10-29 16:23:12 +0100798 hscif0: serial@e62c0000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100799 compatible = "renesas,hscif-r8a7790",
800 "renesas,rcar-gen2-hscif", "renesas,hscif";
Laurent Pinchart597af202013-10-29 16:23:12 +0100801 reg = <0 0xe62c0000 0 96>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900802 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven42af65e2016-01-29 11:04:39 +0100803 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
804 <&scif_clk>;
805 clock-names = "fck", "brg_int", "scif_clk";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200806 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
807 <&dmac1 0x39>, <&dmac1 0x3a>;
808 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100809 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100810 status = "disabled";
811 };
812
813 hscif1: serial@e62c8000 {
Geert Uytterhoevena20dc9f2016-01-29 10:32:04 +0100814 compatible = "renesas,hscif-r8a7790",
815 "renesas,rcar-gen2-hscif", "renesas,hscif";
Laurent Pinchart597af202013-10-29 16:23:12 +0100816 reg = <0 0xe62c8000 0 96>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900817 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven42af65e2016-01-29 11:04:39 +0100818 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
819 <&scif_clk>;
820 clock-names = "fck", "brg_int", "scif_clk";
Niklas Söderlundbadf8572016-05-12 10:54:42 +0200821 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
822 <&dmac1 0x4d>, <&dmac1 0x4e>;
823 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100824 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart597af202013-10-29 16:23:12 +0100825 status = "disabled";
826 };
827
Sergei Shtylyovd8913c62014-02-20 02:20:43 +0300828 ether: ethernet@ee700000 {
829 compatible = "renesas,ether-r8a7790";
830 reg = <0 0xee700000 0 0x400>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900831 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyovd8913c62014-02-20 02:20:43 +0300832 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100833 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Sergei Shtylyovd8913c62014-02-20 02:20:43 +0300834 phy-mode = "rmii";
835 #address-cells = <1>;
836 #size-cells = <0>;
837 status = "disabled";
838 };
839
Sergei Shtylyovf25d6b92015-06-16 02:43:51 +0300840 avb: ethernet@e6800000 {
Simon Hormand92df7e2016-02-23 10:17:45 +0900841 compatible = "renesas,etheravb-r8a7790",
842 "renesas,etheravb-rcar-gen2";
Sergei Shtylyovf25d6b92015-06-16 02:43:51 +0300843 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900844 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyovf25d6b92015-06-16 02:43:51 +0300845 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100846 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Sergei Shtylyovf25d6b92015-06-16 02:43:51 +0300847 #address-cells = <1>;
848 #size-cells = <0>;
849 status = "disabled";
850 };
851
Valentine Barshakcde630f2014-01-14 21:05:30 +0400852 sata0: sata@ee300000 {
853 compatible = "renesas,sata-r8a7790";
854 reg = <0 0xee300000 0 0x2000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900855 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
Valentine Barshakcde630f2014-01-14 21:05:30 +0400856 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100857 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Valentine Barshakcde630f2014-01-14 21:05:30 +0400858 status = "disabled";
859 };
860
861 sata1: sata@ee500000 {
862 compatible = "renesas,sata-r8a7790";
863 reg = <0 0xee500000 0 0x2000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900864 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
Valentine Barshakcde630f2014-01-14 21:05:30 +0400865 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100866 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Valentine Barshakcde630f2014-01-14 21:05:30 +0400867 status = "disabled";
868 };
869
Yoshihiro Shimodaae0a5552014-10-24 19:44:33 +0900870 hsusb: usb@e6590000 {
Simon Hormand87ec942016-01-04 08:20:17 +1100871 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
Yoshihiro Shimodaae0a5552014-10-24 19:44:33 +0900872 reg = <0 0xe6590000 0 0x100>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900873 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
Yoshihiro Shimodaae0a5552014-10-24 19:44:33 +0900874 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
Yoshihiro Shimodae8295dc2015-05-08 16:13:07 +0900875 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
876 <&usb_dmac1 0>, <&usb_dmac1 1>;
877 dma-names = "ch0", "ch1", "ch2", "ch3";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100878 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Geert Uytterhoeven484adb02015-08-04 14:28:10 +0200879 renesas,buswait = <4>;
880 phys = <&usb0 1>;
881 phy-names = "usb";
Yoshihiro Shimodaae0a5552014-10-24 19:44:33 +0900882 status = "disabled";
883 };
884
Sergei Shtylyove089f652014-09-27 01:00:20 +0400885 usbphy: usb-phy@e6590100 {
886 compatible = "renesas,usb-phy-r8a7790";
887 reg = <0 0xe6590100 0 0x100>;
888 #address-cells = <1>;
889 #size-cells = <0>;
890 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
891 clock-names = "usbhs";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100892 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Sergei Shtylyove089f652014-09-27 01:00:20 +0400893 status = "disabled";
894
895 usb0: usb-channel@0 {
896 reg = <0>;
897 #phy-cells = <1>;
898 };
899 usb2: usb-channel@2 {
900 reg = <2>;
901 #phy-cells = <1>;
902 };
903 };
904
Ben Dooks9f685bf2014-08-13 00:16:18 +0400905 vin0: video@e6ef0000 {
906 compatible = "renesas,vin-r8a7790";
Ben Dooks9f685bf2014-08-13 00:16:18 +0400907 reg = <0 0xe6ef0000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900908 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven484adb02015-08-04 14:28:10 +0200909 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100910 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Ben Dooks9f685bf2014-08-13 00:16:18 +0400911 status = "disabled";
912 };
913
914 vin1: video@e6ef1000 {
915 compatible = "renesas,vin-r8a7790";
Ben Dooks9f685bf2014-08-13 00:16:18 +0400916 reg = <0 0xe6ef1000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900917 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven484adb02015-08-04 14:28:10 +0200918 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100919 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Ben Dooks9f685bf2014-08-13 00:16:18 +0400920 status = "disabled";
921 };
922
923 vin2: video@e6ef2000 {
924 compatible = "renesas,vin-r8a7790";
Ben Dooks9f685bf2014-08-13 00:16:18 +0400925 reg = <0 0xe6ef2000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900926 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven484adb02015-08-04 14:28:10 +0200927 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100928 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Ben Dooks9f685bf2014-08-13 00:16:18 +0400929 status = "disabled";
930 };
931
932 vin3: video@e6ef3000 {
933 compatible = "renesas,vin-r8a7790";
Ben Dooks9f685bf2014-08-13 00:16:18 +0400934 reg = <0 0xe6ef3000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900935 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven484adb02015-08-04 14:28:10 +0200936 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100937 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Ben Dooks9f685bf2014-08-13 00:16:18 +0400938 status = "disabled";
939 };
940
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100941 vsp1@fe920000 {
942 compatible = "renesas,vsp1";
943 reg = <0 0xfe920000 0 0x8000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900944 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100945 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100946 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100947
948 renesas,has-sru;
949 renesas,#rpf = <5>;
950 renesas,#uds = <1>;
951 renesas,#wpf = <4>;
952 };
953
954 vsp1@fe928000 {
955 compatible = "renesas,vsp1";
956 reg = <0 0xfe928000 0 0x8000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900957 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100958 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100959 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100960
961 renesas,has-lut;
962 renesas,has-sru;
963 renesas,#rpf = <5>;
964 renesas,#uds = <3>;
965 renesas,#wpf = <4>;
966 };
967
968 vsp1@fe930000 {
969 compatible = "renesas,vsp1";
970 reg = <0 0xfe930000 0 0x8000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900971 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100972 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100973 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100974
975 renesas,has-lif;
976 renesas,has-lut;
977 renesas,#rpf = <4>;
978 renesas,#uds = <1>;
979 renesas,#wpf = <4>;
980 };
981
982 vsp1@fe938000 {
983 compatible = "renesas,vsp1";
984 reg = <0 0xfe938000 0 0x8000>;
Simon Horman3abb4d52016-01-15 11:44:15 +0900985 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100986 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +0100987 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +0100988
989 renesas,has-lif;
990 renesas,has-lut;
991 renesas,#rpf = <4>;
992 renesas,#uds = <1>;
993 renesas,#wpf = <4>;
994 };
995
996 du: display@feb00000 {
997 compatible = "renesas,du-r8a7790";
998 reg = <0 0xfeb00000 0 0x70000>,
999 <0 0xfeb90000 0 0x1c>,
1000 <0 0xfeb94000 0 0x1c>;
1001 reg-names = "du", "lvds.0", "lvds.1";
Simon Horman3abb4d52016-01-15 11:44:15 +09001002 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart3ac6a832014-01-21 16:00:46 +01001005 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
1006 <&mstp7_clks R8A7790_CLK_DU1>,
1007 <&mstp7_clks R8A7790_CLK_DU2>,
1008 <&mstp7_clks R8A7790_CLK_LVDS0>,
1009 <&mstp7_clks R8A7790_CLK_LVDS1>;
1010 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
1011 status = "disabled";
1012
1013 ports {
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1016
1017 port@0 {
1018 reg = <0>;
1019 du_out_rgb: endpoint {
1020 };
1021 };
1022 port@1 {
1023 reg = <1>;
1024 du_out_lvds0: endpoint {
1025 };
1026 };
1027 port@2 {
1028 reg = <2>;
1029 du_out_lvds1: endpoint {
1030 };
1031 };
1032 };
1033 };
1034
Sergei Shtylyov6a7742b2015-01-06 00:34:42 +03001035 can0: can@e6e80000 {
Simon Horman28e941d2016-03-14 11:13:59 +09001036 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
Sergei Shtylyov6a7742b2015-01-06 00:34:42 +03001037 reg = <0 0xe6e80000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001038 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov6a7742b2015-01-06 00:34:42 +03001039 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
1040 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1041 clock-names = "clkp1", "clkp2", "can_clk";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001042 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Sergei Shtylyov6a7742b2015-01-06 00:34:42 +03001043 status = "disabled";
1044 };
1045
1046 can1: can@e6e88000 {
Simon Horman28e941d2016-03-14 11:13:59 +09001047 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
Sergei Shtylyov6a7742b2015-01-06 00:34:42 +03001048 reg = <0 0xe6e88000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001049 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov6a7742b2015-01-06 00:34:42 +03001050 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1051 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1052 clock-names = "clkp1", "clkp2", "can_clk";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001053 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Sergei Shtylyov6a7742b2015-01-06 00:34:42 +03001054 status = "disabled";
1055 };
1056
Mikhail Ulyanovfb847572015-07-24 16:25:45 +03001057 jpu: jpeg-codec@fe980000 {
Simon Horman1c4b68f2016-02-24 11:29:05 +09001058 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
Mikhail Ulyanovfb847572015-07-24 16:25:45 +03001059 reg = <0 0xfe980000 0 0x10300>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001060 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
Mikhail Ulyanovfb847572015-07-24 16:25:45 +03001061 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001062 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Mikhail Ulyanovfb847572015-07-24 16:25:45 +03001063 };
1064
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001065 clocks {
1066 #address-cells = <2>;
1067 #size-cells = <2>;
1068 ranges;
1069
1070 /* External root clock */
Simon Hormanb19dd472016-03-16 09:21:13 +09001071 extal_clk: extal {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001072 compatible = "fixed-clock";
1073 #clock-cells = <0>;
1074 /* This value must be overriden by the board. */
1075 clock-frequency = <0>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001076 };
1077
Phil Edworthy51d17912014-06-13 10:37:16 +01001078 /* External PCIe clock - can be overridden by the board */
Simon Hormanb19dd472016-03-16 09:21:13 +09001079 pcie_bus_clk: pcie_bus {
Phil Edworthy51d17912014-06-13 10:37:16 +01001080 compatible = "fixed-clock";
1081 #clock-cells = <0>;
Geert Uytterhoeven03adc182016-04-25 16:08:33 +02001082 clock-frequency = <0>;
Phil Edworthy51d17912014-06-13 10:37:16 +01001083 };
1084
Kuninori Morimotoc7c2ec32014-01-13 18:25:39 -08001085 /*
1086 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1087 * default. Boards that provide audio clocks should override them.
1088 */
1089 audio_clk_a: audio_clk_a {
1090 compatible = "fixed-clock";
1091 #clock-cells = <0>;
1092 clock-frequency = <0>;
Kuninori Morimotoc7c2ec32014-01-13 18:25:39 -08001093 };
1094 audio_clk_b: audio_clk_b {
1095 compatible = "fixed-clock";
1096 #clock-cells = <0>;
1097 clock-frequency = <0>;
Kuninori Morimotoc7c2ec32014-01-13 18:25:39 -08001098 };
1099 audio_clk_c: audio_clk_c {
1100 compatible = "fixed-clock";
1101 #clock-cells = <0>;
1102 clock-frequency = <0>;
Kuninori Morimotoc7c2ec32014-01-13 18:25:39 -08001103 };
1104
Geert Uytterhoeven42af65e2016-01-29 11:04:39 +01001105 /* External SCIF clock */
1106 scif_clk: scif {
1107 compatible = "fixed-clock";
1108 #clock-cells = <0>;
1109 /* This value must be overridden by the board. */
1110 clock-frequency = <0>;
Geert Uytterhoeven42af65e2016-01-29 11:04:39 +01001111 };
1112
Sergei Shtylyov41650f42015-01-06 00:33:25 +03001113 /* External USB clock - can be overridden by the board */
Simon Hormanb19dd472016-03-16 09:21:13 +09001114 usb_extal_clk: usb_extal {
Sergei Shtylyov41650f42015-01-06 00:33:25 +03001115 compatible = "fixed-clock";
1116 #clock-cells = <0>;
1117 clock-frequency = <48000000>;
Sergei Shtylyov41650f42015-01-06 00:33:25 +03001118 };
1119
1120 /* External CAN clock */
1121 can_clk: can_clk {
1122 compatible = "fixed-clock";
1123 #clock-cells = <0>;
1124 /* This value must be overridden by the board. */
1125 clock-frequency = <0>;
Sergei Shtylyov41650f42015-01-06 00:33:25 +03001126 };
1127
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001128 /* Special CPG clocks */
1129 cpg_clocks: cpg_clocks@e6150000 {
1130 compatible = "renesas,r8a7790-cpg-clocks",
1131 "renesas,rcar-gen2-cpg-clocks";
1132 reg = <0 0xe6150000 0 0x1000>;
Sergei Shtylyov41650f42015-01-06 00:33:25 +03001133 clocks = <&extal_clk &usb_extal_clk>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001134 #clock-cells = <1>;
1135 clock-output-names = "main", "pll0", "pll1", "pll3",
1136 "lb", "qspi", "sdh", "sd0", "sd1",
Sergei Shtylyov3453ca92014-12-30 23:21:45 +03001137 "z", "rcan", "adsp";
Geert Uytterhoeven484adb02015-08-04 14:28:10 +02001138 #power-domain-cells = <0>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001139 };
1140
1141 /* Variable factor clocks */
Simon Hormanb19dd472016-03-16 09:21:13 +09001142 sd2_clk: sd2@e6150078 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001143 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1144 reg = <0 0xe6150078 0 4>;
1145 clocks = <&pll1_div2_clk>;
1146 #clock-cells = <0>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001147 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001148 sd3_clk: sd3@e615026c {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001149 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
Shinobu Ueharaedd7b932014-10-30 14:57:57 +09001150 reg = <0 0xe615026c 0 4>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001151 clocks = <&pll1_div2_clk>;
1152 #clock-cells = <0>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001153 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001154 mmc0_clk: mmc0@e6150240 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001155 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1156 reg = <0 0xe6150240 0 4>;
1157 clocks = <&pll1_div2_clk>;
1158 #clock-cells = <0>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001159 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001160 mmc1_clk: mmc1@e6150244 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001161 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1162 reg = <0 0xe6150244 0 4>;
1163 clocks = <&pll1_div2_clk>;
1164 #clock-cells = <0>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001165 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001166 ssp_clk: ssp@e6150248 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001167 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1168 reg = <0 0xe6150248 0 4>;
1169 clocks = <&pll1_div2_clk>;
1170 #clock-cells = <0>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001171 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001172 ssprs_clk: ssprs@e615024c {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001173 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1174 reg = <0 0xe615024c 0 4>;
1175 clocks = <&pll1_div2_clk>;
1176 #clock-cells = <0>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001177 };
1178
1179 /* Fixed factor clocks */
Simon Hormanb19dd472016-03-16 09:21:13 +09001180 pll1_div2_clk: pll1_div2 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001181 compatible = "fixed-factor-clock";
1182 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1183 #clock-cells = <0>;
1184 clock-div = <2>;
1185 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001186 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001187 z2_clk: z2 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001188 compatible = "fixed-factor-clock";
1189 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1190 #clock-cells = <0>;
1191 clock-div = <2>;
1192 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001193 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001194 zg_clk: zg {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001195 compatible = "fixed-factor-clock";
1196 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1197 #clock-cells = <0>;
1198 clock-div = <3>;
1199 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001200 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001201 zx_clk: zx {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001202 compatible = "fixed-factor-clock";
1203 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1204 #clock-cells = <0>;
1205 clock-div = <3>;
1206 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001207 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001208 zs_clk: zs {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001209 compatible = "fixed-factor-clock";
1210 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1211 #clock-cells = <0>;
1212 clock-div = <6>;
1213 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001214 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001215 hp_clk: hp {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001216 compatible = "fixed-factor-clock";
1217 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1218 #clock-cells = <0>;
1219 clock-div = <12>;
1220 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001221 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001222 i_clk: i {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001223 compatible = "fixed-factor-clock";
1224 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1225 #clock-cells = <0>;
1226 clock-div = <2>;
1227 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001228 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001229 b_clk: b {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001230 compatible = "fixed-factor-clock";
1231 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1232 #clock-cells = <0>;
1233 clock-div = <12>;
1234 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001235 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001236 p_clk: p {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001237 compatible = "fixed-factor-clock";
1238 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1239 #clock-cells = <0>;
1240 clock-div = <24>;
1241 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001242 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001243 cl_clk: cl {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001244 compatible = "fixed-factor-clock";
1245 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1246 #clock-cells = <0>;
1247 clock-div = <48>;
1248 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001249 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001250 m2_clk: m2 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001251 compatible = "fixed-factor-clock";
1252 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1253 #clock-cells = <0>;
1254 clock-div = <8>;
1255 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001256 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001257 imp_clk: imp {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001258 compatible = "fixed-factor-clock";
1259 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1260 #clock-cells = <0>;
1261 clock-div = <4>;
1262 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001263 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001264 rclk_clk: rclk {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001265 compatible = "fixed-factor-clock";
1266 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1267 #clock-cells = <0>;
1268 clock-div = <(48 * 1024)>;
1269 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001270 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001271 oscclk_clk: oscclk {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001272 compatible = "fixed-factor-clock";
1273 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1274 #clock-cells = <0>;
1275 clock-div = <(12 * 1024)>;
1276 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001277 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001278 zb3_clk: zb3 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001279 compatible = "fixed-factor-clock";
1280 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1281 #clock-cells = <0>;
1282 clock-div = <4>;
1283 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001284 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001285 zb3d2_clk: zb3d2 {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001286 compatible = "fixed-factor-clock";
1287 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1288 #clock-cells = <0>;
1289 clock-div = <8>;
1290 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001291 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001292 ddr_clk: ddr {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001293 compatible = "fixed-factor-clock";
1294 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1295 #clock-cells = <0>;
1296 clock-div = <8>;
1297 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001298 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001299 mp_clk: mp {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001300 compatible = "fixed-factor-clock";
1301 clocks = <&pll1_div2_clk>;
1302 #clock-cells = <0>;
1303 clock-div = <15>;
1304 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001305 };
Simon Hormanb19dd472016-03-16 09:21:13 +09001306 cp_clk: cp {
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001307 compatible = "fixed-factor-clock";
1308 clocks = <&extal_clk>;
1309 #clock-cells = <0>;
1310 clock-div = <2>;
1311 clock-mult = <1>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001312 };
1313
1314 /* Gate clocks */
Laurent Pinchart9d909512013-12-19 16:51:01 +01001315 mstp0_clks: mstp0_clks@e6150130 {
1316 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1317 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1318 clocks = <&mp_clk>;
1319 #clock-cells = <1>;
Ben Dooksb54010a2014-11-10 19:49:37 +01001320 clock-indices = <R8A7790_CLK_MSIOF0>;
Laurent Pinchart9d909512013-12-19 16:51:01 +01001321 clock-output-names = "msiof0";
1322 };
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001323 mstp1_clks: mstp1_clks@e6150134 {
1324 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1325 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
Yoshifumi Hosoya4ba8f242014-10-14 16:01:42 +09001326 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1327 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1328 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1329 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001330 #clock-cells = <1>;
Ben Dooksb54010a2014-11-10 19:49:37 +01001331 clock-indices = <
Yoshifumi Hosoya4ba8f242014-10-14 16:01:42 +09001332 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1333 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1334 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1335 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1336 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1337 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1338 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001339 >;
1340 clock-output-names =
Yoshifumi Hosoya4ba8f242014-10-14 16:01:42 +09001341 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1342 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1343 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
Kouei Abe2284ff52014-10-14 16:01:40 +09001344 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001345 };
1346 mstp2_clks: mstp2_clks@e6150138 {
1347 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1348 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1349 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
Laurent Pinchartc819acd2014-07-19 01:50:23 +02001350 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1351 <&zs_clk>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001352 #clock-cells = <1>;
Ben Dooksb54010a2014-11-10 19:49:37 +01001353 clock-indices = <
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001354 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
Laurent Pinchart9d909512013-12-19 16:51:01 +01001355 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1356 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
Laurent Pinchartc819acd2014-07-19 01:50:23 +02001357 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001358 >;
1359 clock-output-names =
Laurent Pinchart9d909512013-12-19 16:51:01 +01001360 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
Laurent Pinchartc819acd2014-07-19 01:50:23 +02001361 "scifb1", "msiof1", "msiof3", "scifb2",
1362 "sys-dmac1", "sys-dmac0";
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001363 };
1364 mstp3_clks: mstp3_clks@e615013c {
1365 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1366 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
Geert Uytterhoeven38805822016-03-03 10:32:40 +01001367 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
Wolfram Sang17465142014-03-11 22:24:37 +01001368 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
Yoshihiro Shimodab02ce792014-11-17 18:25:13 +09001369 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1370 <&hp_clk>, <&hp_clk>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001371 #clock-cells = <1>;
Ben Dooksb54010a2014-11-10 19:49:37 +01001372 clock-indices = <
Geert Uytterhoeven38805822016-03-03 10:32:40 +01001373 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
Wolfram Sang17465142014-03-11 22:24:37 +01001374 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
Phil Edworthyecafea82014-06-13 10:37:15 +01001375 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
Yoshihiro Shimodab02ce792014-11-17 18:25:13 +09001376 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001377 >;
1378 clock-output-names =
Geert Uytterhoeven38805822016-03-03 10:32:40 +01001379 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
Wolfram Sang17465142014-03-11 22:24:37 +01001380 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
Yoshihiro Shimodab02ce792014-11-17 18:25:13 +09001381 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1382 "usbdmac0", "usbdmac1";
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001383 };
Geert Uytterhoeven61624ca2015-03-18 19:55:59 +01001384 mstp4_clks: mstp4_clks@e6150140 {
1385 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1386 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1387 clocks = <&cp_clk>;
1388 #clock-cells = <1>;
1389 clock-indices = <R8A7790_CLK_IRQC>;
1390 clock-output-names = "irqc";
1391 };
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001392 mstp5_clks: mstp5_clks@e6150144 {
1393 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1394 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
Sergei Shtylyov3453ca92014-12-30 23:21:45 +03001395 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1396 <&extal_clk>, <&p_clk>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001397 #clock-cells = <1>;
Ben Dooksb54010a2014-11-10 19:49:37 +01001398 clock-indices = <
1399 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
Sergei Shtylyov3453ca92014-12-30 23:21:45 +03001400 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1401 R8A7790_CLK_PWM
Ben Dooksb54010a2014-11-10 19:49:37 +01001402 >;
Sergei Shtylyov3453ca92014-12-30 23:21:45 +03001403 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1404 "thermal", "pwm";
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001405 };
1406 mstp7_clks: mstp7_clks@e615014c {
1407 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1408 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
Kazuya Mizuguchib621f6d2015-02-19 10:42:55 -05001409 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001410 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1411 <&zx_clk>;
1412 #clock-cells = <1>;
Ben Dooksb54010a2014-11-10 19:49:37 +01001413 clock-indices = <
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001414 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1415 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1416 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1417 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1418 >;
1419 clock-output-names =
1420 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1421 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1422 };
1423 mstp8_clks: mstp8_clks@e6150990 {
1424 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1425 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
Andrey Gusakovf6b5dd42014-12-18 23:41:52 +03001426 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
Sergei Shtylyov63d2d752015-06-16 02:42:42 +03001427 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1428 <&zs_clk>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001429 #clock-cells = <1>;
Ben Dooksb54010a2014-11-10 19:49:37 +01001430 clock-indices = <
Andrey Gusakovf6b5dd42014-12-18 23:41:52 +03001431 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
Sergei Shtylyov63d2d752015-06-16 02:42:42 +03001432 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1433 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
Andrey Gusakovf6b5dd42014-12-18 23:41:52 +03001434 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
Laurent Pinchart3f2beaa2014-01-07 09:22:53 +01001435 >;
Laurent Pinchartbccccc32014-01-07 09:22:55 +01001436 clock-output-names =
Sergei Shtylyov63d2d752015-06-16 02:42:42 +03001437 "mlb", "vin3", "vin2", "vin1", "vin0",
1438 "etheravb", "ether", "sata1", "sata0";
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001439 };
1440 mstp9_clks: mstp9_clks@e6150994 {
1441 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1442 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
Geert Uytterhoeven81f68832014-04-23 10:25:27 +02001443 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1444 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1445 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
Laurent Pinchart3672b052014-04-01 13:02:17 +02001446 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001447 #clock-cells = <1>;
Ben Dooksb54010a2014-11-10 19:49:37 +01001448 clock-indices = <
Geert Uytterhoeven81f68832014-04-23 10:25:27 +02001449 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1450 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
Wolfram Sang17465142014-03-11 22:24:37 +01001451 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1452 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001453 >;
Laurent Pinchart91b56ca2013-12-19 16:51:03 +01001454 clock-output-names =
Geert Uytterhoeven81f68832014-04-23 10:25:27 +02001455 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
Wolfram Sang17465142014-03-11 22:24:37 +01001456 "rcan1", "rcan0", "qspi_mod", "iic3",
1457 "i2c3", "i2c2", "i2c1", "i2c0";
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001458 };
Kuninori Morimotobcde3722014-06-10 23:53:27 -07001459 mstp10_clks: mstp10_clks@e6150998 {
1460 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1461 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1462 clocks = <&p_clk>,
1463 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1464 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1465 <&p_clk>,
1466 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1467 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1468 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1469 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1470 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
Kuninori Morimotoa7163782015-07-21 00:26:20 +00001471 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
Kuninori Morimotobcde3722014-06-10 23:53:27 -07001472 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1473
1474 #clock-cells = <1>;
1475 clock-indices = <
1476 R8A7790_CLK_SSI_ALL
1477 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1478 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1479 R8A7790_CLK_SCU_ALL
1480 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
Kuninori Morimotoa7163782015-07-21 00:26:20 +00001481 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
Kuninori Morimotobcde3722014-06-10 23:53:27 -07001482 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1483 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1484 >;
1485 clock-output-names =
1486 "ssi-all",
1487 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1488 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1489 "scu-all",
1490 "scu-dvc1", "scu-dvc0",
Kuninori Morimotoa7163782015-07-21 00:26:20 +00001491 "scu-ctu1-mix1", "scu-ctu0-mix0",
Kuninori Morimotobcde3722014-06-10 23:53:27 -07001492 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1493 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1494 };
Laurent Pinchart22a1f592013-12-11 15:05:14 +01001495 };
Geert Uytterhoeven7053e132014-02-10 11:47:29 +01001496
Geert Uytterhoeven4c8eb3c2015-01-20 14:44:58 +01001497 sysc: system-controller@e6180000 {
1498 compatible = "renesas,r8a7790-sysc";
1499 reg = <0 0xe6180000 0 0x0200>;
1500 #power-domain-cells = <1>;
1501 };
1502
Geert Uytterhoevenfad6d452014-02-25 11:30:13 +01001503 qspi: spi@e6b10000 {
Geert Uytterhoeven7053e132014-02-10 11:47:29 +01001504 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1505 reg = <0 0xe6b10000 0 0x2c>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001506 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven7053e132014-02-10 11:47:29 +01001507 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +02001508 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1509 <&dmac1 0x17>, <&dmac1 0x18>;
1510 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001511 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Geert Uytterhoeven7053e132014-02-10 11:47:29 +01001512 num-cs = <1>;
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1515 status = "disabled";
1516 };
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001517
1518 msiof0: spi@e6e20000 {
1519 compatible = "renesas,msiof-r8a7790";
Ryo Kataokac7d1f082015-04-05 01:54:31 +09001520 reg = <0 0xe6e20000 0 0x0064>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001521 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001522 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +02001523 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1524 <&dmac1 0x51>, <&dmac1 0x52>;
1525 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001526 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001527 #address-cells = <1>;
1528 #size-cells = <0>;
1529 status = "disabled";
1530 };
1531
1532 msiof1: spi@e6e10000 {
1533 compatible = "renesas,msiof-r8a7790";
Ryo Kataokac7d1f082015-04-05 01:54:31 +09001534 reg = <0 0xe6e10000 0 0x0064>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001535 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001536 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +02001537 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1538 <&dmac1 0x55>, <&dmac1 0x56>;
1539 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001540 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001541 #address-cells = <1>;
1542 #size-cells = <0>;
1543 status = "disabled";
1544 };
1545
1546 msiof2: spi@e6e00000 {
1547 compatible = "renesas,msiof-r8a7790";
Ryo Kataokac7d1f082015-04-05 01:54:31 +09001548 reg = <0 0xe6e00000 0 0x0064>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001549 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001550 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +02001551 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1552 <&dmac1 0x41>, <&dmac1 0x42>;
1553 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001554 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001555 #address-cells = <1>;
1556 #size-cells = <0>;
1557 status = "disabled";
1558 };
1559
1560 msiof3: spi@e6c90000 {
1561 compatible = "renesas,msiof-r8a7790";
Ryo Kataokac7d1f082015-04-05 01:54:31 +09001562 reg = <0 0xe6c90000 0 0x0064>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001563 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001564 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
Niklas Söderlundbadf8572016-05-12 10:54:42 +02001565 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
1566 <&dmac1 0x45>, <&dmac1 0x46>;
1567 dma-names = "tx", "rx", "tx", "rx";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001568 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Geert Uytterhoevenae8a6142014-02-25 11:30:15 +01001569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 status = "disabled";
1572 };
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001573
Yoshihiro Shimoda157fcd82014-10-24 19:41:46 +09001574 xhci: usb@ee000000 {
Simon Horman92cc7792016-03-24 11:01:07 +09001575 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
Yoshihiro Shimoda157fcd82014-10-24 19:41:46 +09001576 reg = <0 0xee000000 0 0xc00>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001577 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
Yoshihiro Shimoda157fcd82014-10-24 19:41:46 +09001578 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001579 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Yoshihiro Shimoda157fcd82014-10-24 19:41:46 +09001580 phys = <&usb2 1>;
1581 phy-names = "usb";
1582 status = "disabled";
1583 };
1584
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001585 pci0: pci@ee090000 {
Simon Horman2d82c142015-12-18 11:42:37 +09001586 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001587 device_type = "pci";
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001588 reg = <0 0xee090000 0 0xc00>,
1589 <0 0xee080000 0 0x1100>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001590 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven484adb02015-08-04 14:28:10 +02001591 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001592 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001593 status = "disabled";
1594
1595 bus-range = <0 0>;
1596 #address-cells = <3>;
1597 #size-cells = <2>;
1598 #interrupt-cells = <1>;
1599 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1600 interrupt-map-mask = <0xff00 0 0 0x7>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001601 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1602 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1603 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov538c40e2014-09-29 22:21:59 +04001604
1605 usb@0,1 {
1606 reg = <0x800 0 0 0 0>;
1607 device_type = "pci";
1608 phys = <&usb0 0>;
1609 phy-names = "usb";
1610 };
1611
1612 usb@0,2 {
1613 reg = <0x1000 0 0 0 0>;
1614 device_type = "pci";
1615 phys = <&usb0 0>;
1616 phy-names = "usb";
1617 };
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001618 };
1619
1620 pci1: pci@ee0b0000 {
Simon Horman2d82c142015-12-18 11:42:37 +09001621 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001622 device_type = "pci";
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001623 reg = <0 0xee0b0000 0 0xc00>,
1624 <0 0xee0a0000 0 0x1100>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001625 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoeven484adb02015-08-04 14:28:10 +02001626 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001627 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001628 status = "disabled";
1629
1630 bus-range = <1 1>;
1631 #address-cells = <3>;
1632 #size-cells = <2>;
1633 #interrupt-cells = <1>;
1634 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1635 interrupt-map-mask = <0xff00 0 0 0x7>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001636 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1637 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1638 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001639 };
1640
1641 pci2: pci@ee0d0000 {
Simon Horman2d82c142015-12-18 11:42:37 +09001642 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001643 device_type = "pci";
1644 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001645 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001646 reg = <0 0xee0d0000 0 0xc00>,
1647 <0 0xee0c0000 0 0x1100>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001648 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001649 status = "disabled";
1650
1651 bus-range = <2 2>;
1652 #address-cells = <3>;
1653 #size-cells = <2>;
1654 #interrupt-cells = <1>;
1655 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1656 interrupt-map-mask = <0xff00 0 0 0x7>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001657 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1658 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1659 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Sergei Shtylyov538c40e2014-09-29 22:21:59 +04001660
1661 usb@0,1 {
1662 reg = <0x800 0 0 0 0>;
1663 device_type = "pci";
1664 phys = <&usb2 0>;
1665 phy-names = "usb";
1666 };
1667
1668 usb@0,2 {
1669 reg = <0x1000 0 0 0 0>;
1670 device_type = "pci";
1671 phys = <&usb2 0>;
1672 phy-names = "usb";
1673 };
Ben Dooksff4f3eb2014-06-24 21:59:54 +04001674 };
1675
Phil Edworthy745329d2014-06-13 10:37:17 +01001676 pciec: pcie@fe000000 {
Simon Hormane670be82015-12-18 11:36:02 +09001677 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
Phil Edworthy745329d2014-06-13 10:37:17 +01001678 reg = <0 0xfe000000 0 0x80000>;
1679 #address-cells = <3>;
1680 #size-cells = <2>;
1681 bus-range = <0x00 0xff>;
1682 device_type = "pci";
1683 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1684 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1685 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1686 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1687 /* Map all possible DDR as inbound ranges */
1688 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1689 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001690 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1691 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1692 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
Phil Edworthy745329d2014-06-13 10:37:17 +01001693 #interrupt-cells = <1>;
1694 interrupt-map-mask = <0 0 0 0>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001695 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
Phil Edworthy745329d2014-06-13 10:37:17 +01001696 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1697 clock-names = "pcie", "pcie_bus";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001698 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Phil Edworthy745329d2014-06-13 10:37:17 +01001699 status = "disabled";
1700 };
1701
Geert Uytterhoevenb694e382015-04-27 14:55:28 +02001702 rcar_sound: sound@ec500000 {
Kuninori Morimotoad632412014-12-17 06:11:52 +00001703 /*
1704 * #sound-dai-cells is required
1705 *
1706 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1707 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1708 */
Geert Uytterhoeven31078ec2015-01-06 21:01:52 +01001709 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001710 reg = <0 0xec500000 0 0x1000>, /* SCU */
1711 <0 0xec5a0000 0 0x100>, /* ADG */
1712 <0 0xec540000 0 0x1000>, /* SSIU */
Kuninori Morimoto4bc4a202015-08-24 08:27:56 +00001713 <0 0xec541000 0 0x280>, /* SSI */
Kuninori Morimoto0c602672015-03-10 01:39:39 +00001714 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1715 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
Kuninori Morimoto46a158f2015-03-10 01:39:01 +00001716
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001717 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1718 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1719 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1720 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1721 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1722 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1723 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1724 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1725 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1726 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1727 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
Kuninori Morimotoa7163782015-07-21 00:26:20 +00001728 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
Kuninori Morimotofc67bf42015-07-21 00:26:42 +00001729 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
Kuninori Morimoto334d69a2014-06-25 17:52:17 -07001730 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001731 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1732 clock-names = "ssi-all",
1733 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1734 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1735 "src.9", "src.8", "src.7", "src.6", "src.5",
1736 "src.4", "src.3", "src.2", "src.1", "src.0",
Kuninori Morimotoa7163782015-07-21 00:26:20 +00001737 "ctu.0", "ctu.1",
Kuninori Morimotofc67bf42015-07-21 00:26:42 +00001738 "mix.0", "mix.1",
Kuninori Morimoto334d69a2014-06-25 17:52:17 -07001739 "dvc.0", "dvc.1",
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001740 "clk_a", "clk_b", "clk_c", "clk_i";
Geert Uytterhoeven36ee3c22015-01-20 14:44:58 +01001741 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001742
1743 status = "disabled";
1744
Kuninori Morimoto334d69a2014-06-25 17:52:17 -07001745 rcar_sound,dvc {
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001746 dvc0: dvc-0 {
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001747 dmas = <&audma0 0xbc>;
1748 dma-names = "tx";
1749 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001750 dvc1: dvc-1 {
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001751 dmas = <&audma0 0xbe>;
1752 dma-names = "tx";
1753 };
Kuninori Morimoto334d69a2014-06-25 17:52:17 -07001754 };
1755
Kuninori Morimotofc67bf42015-07-21 00:26:42 +00001756 rcar_sound,mix {
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001757 mix0: mix-0 { };
1758 mix1: mix-1 { };
Kuninori Morimotofc67bf42015-07-21 00:26:42 +00001759 };
1760
Kuninori Morimotoa7163782015-07-21 00:26:20 +00001761 rcar_sound,ctu {
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001762 ctu00: ctu-0 { };
1763 ctu01: ctu-1 { };
1764 ctu02: ctu-2 { };
1765 ctu03: ctu-3 { };
1766 ctu10: ctu-4 { };
1767 ctu11: ctu-5 { };
1768 ctu12: ctu-6 { };
1769 ctu13: ctu-7 { };
Kuninori Morimotoa7163782015-07-21 00:26:20 +00001770 };
1771
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001772 rcar_sound,src {
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001773 src0: src-0 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001774 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001775 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1776 dma-names = "rx", "tx";
1777 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001778 src1: src-1 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001779 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001780 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1781 dma-names = "rx", "tx";
1782 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001783 src2: src-2 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001784 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001785 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1786 dma-names = "rx", "tx";
1787 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001788 src3: src-3 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001789 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001790 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1791 dma-names = "rx", "tx";
1792 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001793 src4: src-4 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001794 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001795 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1796 dma-names = "rx", "tx";
1797 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001798 src5: src-5 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001799 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001800 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1801 dma-names = "rx", "tx";
1802 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001803 src6: src-6 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001804 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001805 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1806 dma-names = "rx", "tx";
1807 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001808 src7: src-7 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001809 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001810 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1811 dma-names = "rx", "tx";
1812 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001813 src8: src-8 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001814 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001815 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1816 dma-names = "rx", "tx";
1817 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001818 src9: src-9 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001819 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001820 dmas = <&audma0 0x97>, <&audma1 0xba>;
1821 dma-names = "rx", "tx";
1822 };
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001823 };
1824
1825 rcar_sound,ssi {
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001826 ssi0: ssi-0 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001827 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001828 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1829 dma-names = "rx", "tx", "rxu", "txu";
1830 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001831 ssi1: ssi-1 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001832 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001833 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1834 dma-names = "rx", "tx", "rxu", "txu";
1835 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001836 ssi2: ssi-2 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001837 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001838 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1839 dma-names = "rx", "tx", "rxu", "txu";
1840 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001841 ssi3: ssi-3 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001842 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001843 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1844 dma-names = "rx", "tx", "rxu", "txu";
1845 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001846 ssi4: ssi-4 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001847 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001848 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1849 dma-names = "rx", "tx", "rxu", "txu";
1850 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001851 ssi5: ssi-5 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001852 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001853 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1854 dma-names = "rx", "tx", "rxu", "txu";
1855 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001856 ssi6: ssi-6 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001857 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001858 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1859 dma-names = "rx", "tx", "rxu", "txu";
1860 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001861 ssi7: ssi-7 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001862 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001863 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1864 dma-names = "rx", "tx", "rxu", "txu";
1865 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001866 ssi8: ssi-8 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001867 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001868 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1869 dma-names = "rx", "tx", "rxu", "txu";
1870 };
Geert Uytterhoeven2c3de362016-05-20 09:09:56 +02001871 ssi9: ssi-9 {
Simon Horman3abb4d52016-01-15 11:44:15 +09001872 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
Kuninori Morimoto118a5092015-03-10 01:40:13 +00001873 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1874 dma-names = "rx", "tx", "rxu", "txu";
1875 };
Kuninori Morimoto7df2fd52014-06-10 23:53:54 -07001876 };
1877 };
Laurent Pinchart70496722015-01-27 11:13:23 +02001878
1879 ipmmu_sy0: mmu@e6280000 {
Magnus Dammc8d66862015-11-17 13:30:56 +09001880 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
Laurent Pinchart70496722015-01-27 11:13:23 +02001881 reg = <0 0xe6280000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001882 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart70496722015-01-27 11:13:23 +02001884 #iommu-cells = <1>;
1885 status = "disabled";
1886 };
1887
1888 ipmmu_sy1: mmu@e6290000 {
Magnus Dammc8d66862015-11-17 13:30:56 +09001889 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
Laurent Pinchart70496722015-01-27 11:13:23 +02001890 reg = <0 0xe6290000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001891 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart70496722015-01-27 11:13:23 +02001892 #iommu-cells = <1>;
1893 status = "disabled";
1894 };
1895
1896 ipmmu_ds: mmu@e6740000 {
Magnus Dammc8d66862015-11-17 13:30:56 +09001897 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
Laurent Pinchart70496722015-01-27 11:13:23 +02001898 reg = <0 0xe6740000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001899 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1900 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart70496722015-01-27 11:13:23 +02001901 #iommu-cells = <1>;
1902 status = "disabled";
1903 };
1904
1905 ipmmu_mp: mmu@ec680000 {
Magnus Dammc8d66862015-11-17 13:30:56 +09001906 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
Laurent Pinchart70496722015-01-27 11:13:23 +02001907 reg = <0 0xec680000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001908 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart70496722015-01-27 11:13:23 +02001909 #iommu-cells = <1>;
1910 status = "disabled";
1911 };
1912
1913 ipmmu_mx: mmu@fe951000 {
Magnus Dammc8d66862015-11-17 13:30:56 +09001914 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
Laurent Pinchart70496722015-01-27 11:13:23 +02001915 reg = <0 0xfe951000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001916 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart70496722015-01-27 11:13:23 +02001918 #iommu-cells = <1>;
1919 status = "disabled";
1920 };
1921
1922 ipmmu_rt: mmu@ffc80000 {
Magnus Dammc8d66862015-11-17 13:30:56 +09001923 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
Laurent Pinchart70496722015-01-27 11:13:23 +02001924 reg = <0 0xffc80000 0 0x1000>;
Simon Horman3abb4d52016-01-15 11:44:15 +09001925 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
Laurent Pinchart70496722015-01-27 11:13:23 +02001926 #iommu-cells = <1>;
1927 status = "disabled";
1928 };
Magnus Damm0468b2d2013-03-28 00:49:34 +09001929};