blob: 8ee63da25e6cc8d30d13a8685da7daba84389472 [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
Ben Hutchings37b5a602008-05-30 22:27:04 +010016#include <linux/i2c.h>
17#include <linux/i2c-algo-bit.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010018#include "net_driver.h"
19#include "bitfield.h"
20#include "efx.h"
21#include "mac.h"
22#include "gmii.h"
23#include "spi.h"
24#include "falcon.h"
25#include "falcon_hwdefs.h"
26#include "falcon_io.h"
27#include "mdio_10g.h"
28#include "phy.h"
29#include "boards.h"
30#include "workarounds.h"
31
32/* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
35 */
36
37/**
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
Ben Hutchings37b5a602008-05-30 22:27:04 +010041 * @i2c_data: Operations and state for I2C bit-bashing algorithm
Ben Hutchings8ceee662008-04-27 12:55:59 +010042 */
43struct falcon_nic_data {
44 unsigned next_buffer_table;
45 struct pci_dev *pci_dev2;
Ben Hutchings37b5a602008-05-30 22:27:04 +010046 struct i2c_algo_bit_data i2c_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +010047};
48
49/**************************************************************************
50 *
51 * Configurable values
52 *
53 **************************************************************************
54 */
55
56static int disable_dma_stats;
57
58/* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
63 * goes idle.
64 */
65#define TX_DC_ENTRIES 16
66#define TX_DC_ENTRIES_ORDER 0
67#define TX_DC_BASE 0x130000
68
69#define RX_DC_ENTRIES 64
70#define RX_DC_ENTRIES_ORDER 2
71#define RX_DC_BASE 0x100000
72
73/* RX FIFO XOFF watermark
74 *
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
78 */
79static int rx_xoff_thresh_bytes = -1;
80module_param(rx_xoff_thresh_bytes, int, 0644);
81MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
82
83/* RX FIFO XON watermark
84 *
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
88 */
89static int rx_xon_thresh_bytes = -1;
90module_param(rx_xon_thresh_bytes, int, 0644);
91MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
92
93/* TX descriptor ring size - min 512 max 4k */
94#define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95#define FALCON_TXD_RING_SIZE 1024
96#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
97
98/* RX descriptor ring size - min 512 max 4k */
99#define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100#define FALCON_RXD_RING_SIZE 1024
101#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
102
103/* Event queue size - max 32k */
104#define FALCON_EVQ_ORDER EVQ_SIZE_4K
105#define FALCON_EVQ_SIZE 4096
106#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
107
108/* Max number of internal errors. After this resets will not be performed */
109#define FALCON_MAX_INT_ERRORS 4
110
111/* Maximum period that we wait for flush events. If the flush event
112 * doesn't arrive in this period of time then we check if the queue
113 * was disabled anyway. */
114#define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
115
116/**************************************************************************
117 *
118 * Falcon constants
119 *
120 **************************************************************************
121 */
122
Ben Hutchings9bbd7d92008-05-16 21:18:48 +0100123/* DMA address mask */
124#define FALCON_DMA_MASK DMA_BIT_MASK(46)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100125
126/* TX DMA length mask (13-bit) */
127#define FALCON_TX_DMA_MASK (4096 - 1)
128
129/* Size and alignment of special buffers (4KB) */
130#define FALCON_BUF_SIZE 4096
131
132/* Dummy SRAM size code */
133#define SRM_NB_BSZ_ONCHIP_ONLY (-1)
134
135/* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136#define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
137#define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
138#define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
139#define PCI_EXP_LNKSTA_LNK_WID 0x3f0
140#define PCI_EXP_LNKSTA_LNK_WID_LBN 4
141
142#define FALCON_IS_DUAL_FUNC(efx) \
Ben Hutchings55668612008-05-16 21:16:10 +0100143 (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100144
145/**************************************************************************
146 *
147 * Falcon hardware access
148 *
149 **************************************************************************/
150
151/* Read the current event from the event queue */
152static inline efx_qword_t *falcon_event(struct efx_channel *channel,
153 unsigned int index)
154{
155 return (((efx_qword_t *) (channel->eventq.addr)) + index);
156}
157
158/* See if an event is present
159 *
160 * We check both the high and low dword of the event for all ones. We
161 * wrote all ones when we cleared the event, and no valid event can
162 * have all ones in either its high or low dwords. This approach is
163 * robust against reordering.
164 *
165 * Note that using a single 64-bit comparison is incorrect; even
166 * though the CPU read will be atomic, the DMA write may not be.
167 */
168static inline int falcon_event_present(efx_qword_t *event)
169{
170 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
171 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
172}
173
174/**************************************************************************
175 *
176 * I2C bus - this is a bit-bashing interface using GPIO pins
177 * Note that it uses the output enables to tristate the outputs
178 * SDA is the data pin and SCL is the clock
179 *
180 **************************************************************************
181 */
Ben Hutchings37b5a602008-05-30 22:27:04 +0100182static void falcon_setsda(void *data, int state)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100183{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100184 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100185 efx_oword_t reg;
186
Ben Hutchings37b5a602008-05-30 22:27:04 +0100187 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
188 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
189 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100190}
191
Ben Hutchings37b5a602008-05-30 22:27:04 +0100192static void falcon_setscl(void *data, int state)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100193{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100194 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100195 efx_oword_t reg;
196
Ben Hutchings37b5a602008-05-30 22:27:04 +0100197 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
198 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
199 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
200}
201
202static int falcon_getsda(void *data)
203{
204 struct efx_nic *efx = (struct efx_nic *)data;
205 efx_oword_t reg;
206
207 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100208 return EFX_OWORD_FIELD(reg, GPIO3_IN);
209}
210
Ben Hutchings37b5a602008-05-30 22:27:04 +0100211static int falcon_getscl(void *data)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100212{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100213 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100214 efx_oword_t reg;
215
Ben Hutchings37b5a602008-05-30 22:27:04 +0100216 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
217 return EFX_OWORD_FIELD(reg, GPIO0_IN);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100218}
219
Ben Hutchings37b5a602008-05-30 22:27:04 +0100220static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
221 .setsda = falcon_setsda,
222 .setscl = falcon_setscl,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100223 .getsda = falcon_getsda,
224 .getscl = falcon_getscl,
Ben Hutchings62c78322008-05-30 22:27:46 +0100225 .udelay = 5,
Ben Hutchings9dadae62008-07-18 18:59:12 +0100226 /* Wait up to 50 ms for slave to let us pull SCL high */
227 .timeout = DIV_ROUND_UP(HZ, 20),
Ben Hutchings8ceee662008-04-27 12:55:59 +0100228};
229
230/**************************************************************************
231 *
232 * Falcon special buffer handling
233 * Special buffers are used for event queues and the TX and RX
234 * descriptor rings.
235 *
236 *************************************************************************/
237
238/*
239 * Initialise a Falcon special buffer
240 *
241 * This will define a buffer (previously allocated via
242 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243 * it to be used for event queues, descriptor rings etc.
244 */
245static int
246falcon_init_special_buffer(struct efx_nic *efx,
247 struct efx_special_buffer *buffer)
248{
249 efx_qword_t buf_desc;
250 int index;
251 dma_addr_t dma_addr;
252 int i;
253
254 EFX_BUG_ON_PARANOID(!buffer->addr);
255
256 /* Write buffer descriptors to NIC */
257 for (i = 0; i < buffer->entries; i++) {
258 index = buffer->index + i;
259 dma_addr = buffer->dma_addr + (i * 4096);
260 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
261 index, (unsigned long long)dma_addr);
262 EFX_POPULATE_QWORD_4(buf_desc,
263 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
264 BUF_ADR_REGION, 0,
265 BUF_ADR_FBUF, (dma_addr >> 12),
266 BUF_OWNER_ID_FBUF, 0);
267 falcon_write_sram(efx, &buf_desc, index);
268 }
269
270 return 0;
271}
272
273/* Unmaps a buffer from Falcon and clears the buffer table entries */
274static void
275falcon_fini_special_buffer(struct efx_nic *efx,
276 struct efx_special_buffer *buffer)
277{
278 efx_oword_t buf_tbl_upd;
279 unsigned int start = buffer->index;
280 unsigned int end = (buffer->index + buffer->entries - 1);
281
282 if (!buffer->entries)
283 return;
284
285 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
286 buffer->index, buffer->index + buffer->entries - 1);
287
288 EFX_POPULATE_OWORD_4(buf_tbl_upd,
289 BUF_UPD_CMD, 0,
290 BUF_CLR_CMD, 1,
291 BUF_CLR_END_ID, end,
292 BUF_CLR_START_ID, start);
293 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
294}
295
296/*
297 * Allocate a new Falcon special buffer
298 *
299 * This allocates memory for a new buffer, clears it and allocates a
300 * new buffer ID range. It does not write into Falcon's buffer table.
301 *
302 * This call will allocate 4KB buffers, since Falcon can't use 8KB
303 * buffers for event queues and descriptor rings.
304 */
305static int falcon_alloc_special_buffer(struct efx_nic *efx,
306 struct efx_special_buffer *buffer,
307 unsigned int len)
308{
309 struct falcon_nic_data *nic_data = efx->nic_data;
310
311 len = ALIGN(len, FALCON_BUF_SIZE);
312
313 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
314 &buffer->dma_addr);
315 if (!buffer->addr)
316 return -ENOMEM;
317 buffer->len = len;
318 buffer->entries = len / FALCON_BUF_SIZE;
319 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
320
321 /* All zeros is a potentially valid event so memset to 0xff */
322 memset(buffer->addr, 0xff, len);
323
324 /* Select new buffer ID */
325 buffer->index = nic_data->next_buffer_table;
326 nic_data->next_buffer_table += buffer->entries;
327
328 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
329 "(virt %p phys %lx)\n", buffer->index,
330 buffer->index + buffer->entries - 1,
331 (unsigned long long)buffer->dma_addr, len,
332 buffer->addr, virt_to_phys(buffer->addr));
333
334 return 0;
335}
336
337static void falcon_free_special_buffer(struct efx_nic *efx,
338 struct efx_special_buffer *buffer)
339{
340 if (!buffer->addr)
341 return;
342
343 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
344 "(virt %p phys %lx)\n", buffer->index,
345 buffer->index + buffer->entries - 1,
346 (unsigned long long)buffer->dma_addr, buffer->len,
347 buffer->addr, virt_to_phys(buffer->addr));
348
349 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
350 buffer->dma_addr);
351 buffer->addr = NULL;
352 buffer->entries = 0;
353}
354
355/**************************************************************************
356 *
357 * Falcon generic buffer handling
358 * These buffers are used for interrupt status and MAC stats
359 *
360 **************************************************************************/
361
362static int falcon_alloc_buffer(struct efx_nic *efx,
363 struct efx_buffer *buffer, unsigned int len)
364{
365 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
366 &buffer->dma_addr);
367 if (!buffer->addr)
368 return -ENOMEM;
369 buffer->len = len;
370 memset(buffer->addr, 0, len);
371 return 0;
372}
373
374static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
375{
376 if (buffer->addr) {
377 pci_free_consistent(efx->pci_dev, buffer->len,
378 buffer->addr, buffer->dma_addr);
379 buffer->addr = NULL;
380 }
381}
382
383/**************************************************************************
384 *
385 * Falcon TX path
386 *
387 **************************************************************************/
388
389/* Returns a pointer to the specified transmit descriptor in the TX
390 * descriptor queue belonging to the specified channel.
391 */
392static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
393 unsigned int index)
394{
395 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
396}
397
398/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
399static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
400{
401 unsigned write_ptr;
402 efx_dword_t reg;
403
404 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
405 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
406 falcon_writel_page(tx_queue->efx, &reg,
407 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
408}
409
410
411/* For each entry inserted into the software descriptor ring, create a
412 * descriptor in the hardware TX descriptor ring (in host memory), and
413 * write a doorbell.
414 */
415void falcon_push_buffers(struct efx_tx_queue *tx_queue)
416{
417
418 struct efx_tx_buffer *buffer;
419 efx_qword_t *txd;
420 unsigned write_ptr;
421
422 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
423
424 do {
425 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
426 buffer = &tx_queue->buffer[write_ptr];
427 txd = falcon_tx_desc(tx_queue, write_ptr);
428 ++tx_queue->write_count;
429
430 /* Create TX descriptor ring entry */
431 EFX_POPULATE_QWORD_5(*txd,
432 TX_KER_PORT, 0,
433 TX_KER_CONT, buffer->continuation,
434 TX_KER_BYTE_CNT, buffer->len,
435 TX_KER_BUF_REGION, 0,
436 TX_KER_BUF_ADR, buffer->dma_addr);
437 } while (tx_queue->write_count != tx_queue->insert_count);
438
439 wmb(); /* Ensure descriptors are written before they are fetched */
440 falcon_notify_tx_desc(tx_queue);
441}
442
443/* Allocate hardware resources for a TX queue */
444int falcon_probe_tx(struct efx_tx_queue *tx_queue)
445{
446 struct efx_nic *efx = tx_queue->efx;
447 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
448 FALCON_TXD_RING_SIZE *
449 sizeof(efx_qword_t));
450}
451
452int falcon_init_tx(struct efx_tx_queue *tx_queue)
453{
454 efx_oword_t tx_desc_ptr;
455 struct efx_nic *efx = tx_queue->efx;
456 int rc;
457
458 /* Pin TX descriptor ring */
459 rc = falcon_init_special_buffer(efx, &tx_queue->txd);
460 if (rc)
461 return rc;
462
463 /* Push TX descriptor ring to card */
464 EFX_POPULATE_OWORD_10(tx_desc_ptr,
465 TX_DESCQ_EN, 1,
466 TX_ISCSI_DDIG_EN, 0,
467 TX_ISCSI_HDIG_EN, 0,
468 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
469 TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum,
470 TX_DESCQ_OWNER_ID, 0,
471 TX_DESCQ_LABEL, tx_queue->queue,
472 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
473 TX_DESCQ_TYPE, 0,
474 TX_NON_IP_DROP_DIS_B0, 1);
475
Ben Hutchings55668612008-05-16 21:16:10 +0100476 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings60ac1062008-09-01 12:44:59 +0100477 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
478 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
479 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100480 }
481
482 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
483 tx_queue->queue);
484
Ben Hutchings55668612008-05-16 21:16:10 +0100485 if (falcon_rev(efx) < FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100486 efx_oword_t reg;
487
Ben Hutchings60ac1062008-09-01 12:44:59 +0100488 /* Only 128 bits in this register */
489 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100490
491 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
Ben Hutchings60ac1062008-09-01 12:44:59 +0100492 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100493 clear_bit_le(tx_queue->queue, (void *)&reg);
494 else
495 set_bit_le(tx_queue->queue, (void *)&reg);
496 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
497 }
498
499 return 0;
500}
501
502static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
503{
504 struct efx_nic *efx = tx_queue->efx;
505 struct efx_channel *channel = &efx->channel[0];
506 efx_oword_t tx_flush_descq;
507 unsigned int read_ptr, i;
508
509 /* Post a flush command */
510 EFX_POPULATE_OWORD_2(tx_flush_descq,
511 TX_FLUSH_DESCQ_CMD, 1,
512 TX_FLUSH_DESCQ, tx_queue->queue);
513 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
514 msleep(FALCON_FLUSH_TIMEOUT);
515
516 if (EFX_WORKAROUND_7803(efx))
517 return 0;
518
519 /* Look for a flush completed event */
520 read_ptr = channel->eventq_read_ptr;
521 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
522 efx_qword_t *event = falcon_event(channel, read_ptr);
523 int ev_code, ev_sub_code, ev_queue;
524 if (!falcon_event_present(event))
525 break;
526
527 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
528 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
529 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
530 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
531 (ev_queue == tx_queue->queue)) {
532 EFX_LOG(efx, "tx queue %d flush command succesful\n",
533 tx_queue->queue);
534 return 0;
535 }
536
537 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
538 }
539
540 if (EFX_WORKAROUND_11557(efx)) {
541 efx_oword_t reg;
542 int enabled;
543
544 falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
545 tx_queue->queue);
546 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
547 if (!enabled) {
548 EFX_LOG(efx, "tx queue %d disabled without a "
549 "flush event seen\n", tx_queue->queue);
550 return 0;
551 }
552 }
553
554 EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
555 return -ETIMEDOUT;
556}
557
558void falcon_fini_tx(struct efx_tx_queue *tx_queue)
559{
560 struct efx_nic *efx = tx_queue->efx;
561 efx_oword_t tx_desc_ptr;
562
563 /* Stop the hardware using the queue */
564 if (falcon_flush_tx_queue(tx_queue))
565 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
566
567 /* Remove TX descriptor ring from card */
568 EFX_ZERO_OWORD(tx_desc_ptr);
569 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
570 tx_queue->queue);
571
572 /* Unpin TX descriptor ring */
573 falcon_fini_special_buffer(efx, &tx_queue->txd);
574}
575
576/* Free buffers backing TX queue */
577void falcon_remove_tx(struct efx_tx_queue *tx_queue)
578{
579 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
580}
581
582/**************************************************************************
583 *
584 * Falcon RX path
585 *
586 **************************************************************************/
587
588/* Returns a pointer to the specified descriptor in the RX descriptor queue */
589static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
590 unsigned int index)
591{
592 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
593}
594
595/* This creates an entry in the RX descriptor queue */
596static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
597 unsigned index)
598{
599 struct efx_rx_buffer *rx_buf;
600 efx_qword_t *rxd;
601
602 rxd = falcon_rx_desc(rx_queue, index);
603 rx_buf = efx_rx_buffer(rx_queue, index);
604 EFX_POPULATE_QWORD_3(*rxd,
605 RX_KER_BUF_SIZE,
606 rx_buf->len -
607 rx_queue->efx->type->rx_buffer_padding,
608 RX_KER_BUF_REGION, 0,
609 RX_KER_BUF_ADR, rx_buf->dma_addr);
610}
611
612/* This writes to the RX_DESC_WPTR register for the specified receive
613 * descriptor ring.
614 */
615void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
616{
617 efx_dword_t reg;
618 unsigned write_ptr;
619
620 while (rx_queue->notified_count != rx_queue->added_count) {
621 falcon_build_rx_desc(rx_queue,
622 rx_queue->notified_count &
623 FALCON_RXD_RING_MASK);
624 ++rx_queue->notified_count;
625 }
626
627 wmb();
628 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
629 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
630 falcon_writel_page(rx_queue->efx, &reg,
631 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
632}
633
634int falcon_probe_rx(struct efx_rx_queue *rx_queue)
635{
636 struct efx_nic *efx = rx_queue->efx;
637 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
638 FALCON_RXD_RING_SIZE *
639 sizeof(efx_qword_t));
640}
641
642int falcon_init_rx(struct efx_rx_queue *rx_queue)
643{
644 efx_oword_t rx_desc_ptr;
645 struct efx_nic *efx = rx_queue->efx;
646 int rc;
Ben Hutchings55668612008-05-16 21:16:10 +0100647 int is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100648 int iscsi_digest_en = is_b0;
649
650 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
651 rx_queue->queue, rx_queue->rxd.index,
652 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
653
654 /* Pin RX descriptor ring */
655 rc = falcon_init_special_buffer(efx, &rx_queue->rxd);
656 if (rc)
657 return rc;
658
659 /* Push RX descriptor ring to card */
660 EFX_POPULATE_OWORD_10(rx_desc_ptr,
661 RX_ISCSI_DDIG_EN, iscsi_digest_en,
662 RX_ISCSI_HDIG_EN, iscsi_digest_en,
663 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
664 RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum,
665 RX_DESCQ_OWNER_ID, 0,
666 RX_DESCQ_LABEL, rx_queue->queue,
667 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
668 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
669 /* For >=B0 this is scatter so disable */
670 RX_DESCQ_JUMBO, !is_b0,
671 RX_DESCQ_EN, 1);
672 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
673 rx_queue->queue);
674 return 0;
675}
676
677static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
678{
679 struct efx_nic *efx = rx_queue->efx;
680 struct efx_channel *channel = &efx->channel[0];
681 unsigned int read_ptr, i;
682 efx_oword_t rx_flush_descq;
683
684 /* Post a flush command */
685 EFX_POPULATE_OWORD_2(rx_flush_descq,
686 RX_FLUSH_DESCQ_CMD, 1,
687 RX_FLUSH_DESCQ, rx_queue->queue);
688 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
689 msleep(FALCON_FLUSH_TIMEOUT);
690
691 if (EFX_WORKAROUND_7803(efx))
692 return 0;
693
694 /* Look for a flush completed event */
695 read_ptr = channel->eventq_read_ptr;
696 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
697 efx_qword_t *event = falcon_event(channel, read_ptr);
698 int ev_code, ev_sub_code, ev_queue, ev_failed;
699 if (!falcon_event_present(event))
700 break;
701
702 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
703 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
704 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
705 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
706
707 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
708 (ev_queue == rx_queue->queue)) {
709 if (ev_failed) {
710 EFX_INFO(efx, "rx queue %d flush command "
711 "failed\n", rx_queue->queue);
712 return -EAGAIN;
713 } else {
714 EFX_LOG(efx, "rx queue %d flush command "
715 "succesful\n", rx_queue->queue);
716 return 0;
717 }
718 }
719
720 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
721 }
722
723 if (EFX_WORKAROUND_11557(efx)) {
724 efx_oword_t reg;
725 int enabled;
726
727 falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
728 rx_queue->queue);
729 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
730 if (!enabled) {
731 EFX_LOG(efx, "rx queue %d disabled without a "
732 "flush event seen\n", rx_queue->queue);
733 return 0;
734 }
735 }
736
737 EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
738 return -ETIMEDOUT;
739}
740
741void falcon_fini_rx(struct efx_rx_queue *rx_queue)
742{
743 efx_oword_t rx_desc_ptr;
744 struct efx_nic *efx = rx_queue->efx;
745 int i, rc;
746
747 /* Try and flush the rx queue. This may need to be repeated */
748 for (i = 0; i < 5; i++) {
749 rc = falcon_flush_rx_queue(rx_queue);
750 if (rc == -EAGAIN)
751 continue;
752 break;
753 }
Steve Hodgson23bdfdd2008-06-09 19:34:32 +0100754 if (rc) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100755 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
Steve Hodgson23bdfdd2008-06-09 19:34:32 +0100756 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
757 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100758
759 /* Remove RX descriptor ring from card */
760 EFX_ZERO_OWORD(rx_desc_ptr);
761 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
762 rx_queue->queue);
763
764 /* Unpin RX descriptor ring */
765 falcon_fini_special_buffer(efx, &rx_queue->rxd);
766}
767
768/* Free buffers backing RX queue */
769void falcon_remove_rx(struct efx_rx_queue *rx_queue)
770{
771 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
772}
773
774/**************************************************************************
775 *
776 * Falcon event queue processing
777 * Event queues are processed by per-channel tasklets.
778 *
779 **************************************************************************/
780
781/* Update a channel's event queue's read pointer (RPTR) register
782 *
783 * This writes the EVQ_RPTR_REG register for the specified channel's
784 * event queue.
785 *
786 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
787 * whereas channel->eventq_read_ptr contains the index of the "next to
788 * read" event.
789 */
790void falcon_eventq_read_ack(struct efx_channel *channel)
791{
792 efx_dword_t reg;
793 struct efx_nic *efx = channel->efx;
794
795 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
796 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
797 channel->evqnum);
798}
799
800/* Use HW to insert a SW defined event */
801void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
802{
803 efx_oword_t drv_ev_reg;
804
805 EFX_POPULATE_OWORD_2(drv_ev_reg,
806 DRV_EV_QID, channel->evqnum,
807 DRV_EV_DATA,
808 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
809 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
810}
811
812/* Handle a transmit completion event
813 *
814 * Falcon batches TX completion events; the message we receive is of
815 * the form "complete all TX events up to this index".
816 */
817static inline void falcon_handle_tx_event(struct efx_channel *channel,
818 efx_qword_t *event)
819{
820 unsigned int tx_ev_desc_ptr;
821 unsigned int tx_ev_q_label;
822 struct efx_tx_queue *tx_queue;
823 struct efx_nic *efx = channel->efx;
824
825 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
826 /* Transmit completion */
827 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
828 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
829 tx_queue = &efx->tx_queue[tx_ev_q_label];
830 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
831 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
832 /* Rewrite the FIFO write pointer */
833 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
834 tx_queue = &efx->tx_queue[tx_ev_q_label];
835
Ben Hutchings55668612008-05-16 21:16:10 +0100836 if (efx_dev_registered(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100837 netif_tx_lock(efx->net_dev);
838 falcon_notify_tx_desc(tx_queue);
Ben Hutchings55668612008-05-16 21:16:10 +0100839 if (efx_dev_registered(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100840 netif_tx_unlock(efx->net_dev);
841 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
842 EFX_WORKAROUND_10727(efx)) {
843 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
844 } else {
845 EFX_ERR(efx, "channel %d unexpected TX event "
846 EFX_QWORD_FMT"\n", channel->channel,
847 EFX_QWORD_VAL(*event));
848 }
849}
850
Ben Hutchings8ceee662008-04-27 12:55:59 +0100851/* Detect errors included in the rx_evt_pkt_ok bit. */
852static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
853 const efx_qword_t *event,
854 unsigned *rx_ev_pkt_ok,
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100855 int *discard)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100856{
857 struct efx_nic *efx = rx_queue->efx;
858 unsigned rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
859 unsigned rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
860 unsigned rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
861 unsigned rx_ev_pkt_type, rx_ev_other_err, rx_ev_pause_frm;
862 unsigned rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100863
864 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
865 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
866 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
867 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
868 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
869 RX_EV_BUF_OWNER_ID_ERR);
870 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
871 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
872 RX_EV_IP_HDR_CHKSUM_ERR);
873 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
874 RX_EV_TCP_UDP_CHKSUM_ERR);
875 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
876 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
Ben Hutchings55668612008-05-16 21:16:10 +0100877 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
Ben Hutchings8ceee662008-04-27 12:55:59 +0100878 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
879 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
880
881 /* Every error apart from tobe_disc and pause_frm */
882 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
883 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
884 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
885
Ben Hutchings8ceee662008-04-27 12:55:59 +0100886 /* Count errors that are not in MAC stats. */
887 if (rx_ev_frm_trunc)
888 ++rx_queue->channel->n_rx_frm_trunc;
889 else if (rx_ev_tobe_disc)
890 ++rx_queue->channel->n_rx_tobe_disc;
891 else if (rx_ev_ip_hdr_chksum_err)
892 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
893 else if (rx_ev_tcp_udp_chksum_err)
894 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
895 if (rx_ev_ip_frag_err)
896 ++rx_queue->channel->n_rx_ip_frag_err;
897
898 /* The frame must be discarded if any of these are true. */
899 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
900 rx_ev_tobe_disc | rx_ev_pause_frm);
901
902 /* TOBE_DISC is expected on unicast mismatches; don't print out an
903 * error message. FRM_TRUNC indicates RXDP dropped the packet due
904 * to a FIFO overflow.
905 */
906#ifdef EFX_ENABLE_DEBUG
907 if (rx_ev_other_err) {
908 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100909 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
Ben Hutchings8ceee662008-04-27 12:55:59 +0100910 rx_queue->queue, EFX_QWORD_VAL(*event),
911 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
912 rx_ev_ip_hdr_chksum_err ?
913 " [IP_HDR_CHKSUM_ERR]" : "",
914 rx_ev_tcp_udp_chksum_err ?
915 " [TCP_UDP_CHKSUM_ERR]" : "",
916 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
917 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
918 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
919 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100920 rx_ev_pause_frm ? " [PAUSE]" : "");
Ben Hutchings8ceee662008-04-27 12:55:59 +0100921 }
922#endif
923
924 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
925 efx->phy_type == PHY_TYPE_10XPRESS))
926 tenxpress_crc_err(efx);
927}
928
929/* Handle receive events that are not in-order. */
930static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
931 unsigned index)
932{
933 struct efx_nic *efx = rx_queue->efx;
934 unsigned expected, dropped;
935
936 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
937 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
938 FALCON_RXD_RING_MASK);
939 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
940 dropped, index, expected);
941
942 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
943 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
944}
945
946/* Handle a packet received event
947 *
948 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
949 * wrong destination address
950 * Also "is multicast" and "matches multicast filter" flags can be used to
951 * discard non-matching multicast packets.
952 */
953static inline int falcon_handle_rx_event(struct efx_channel *channel,
954 const efx_qword_t *event)
955{
956 unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt;
957 unsigned int rx_ev_pkt_ok, rx_ev_hdr_type, rx_ev_mcast_pkt;
958 unsigned expected_ptr;
959 int discard = 0, checksummed;
960 struct efx_rx_queue *rx_queue;
961 struct efx_nic *efx = channel->efx;
962
963 /* Basic packet information */
964 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
965 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
966 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
967 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
968 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
969
970 rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL);
971 rx_queue = &efx->rx_queue[rx_ev_q_label];
972
973 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
974 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
975 if (unlikely(rx_ev_desc_ptr != expected_ptr)) {
976 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
977 return rx_ev_q_label;
978 }
979
980 if (likely(rx_ev_pkt_ok)) {
981 /* If packet is marked as OK and packet type is TCP/IPv4 or
982 * UDP/IPv4, then we can rely on the hardware checksum.
983 */
984 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
985 } else {
986 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100987 &discard);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100988 checksummed = 0;
989 }
990
991 /* Detect multicast packets that didn't match the filter */
992 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
993 if (rx_ev_mcast_pkt) {
994 unsigned int rx_ev_mcast_hash_match =
995 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
996
997 if (unlikely(!rx_ev_mcast_hash_match))
998 discard = 1;
999 }
1000
1001 /* Handle received packet */
1002 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
1003 checksummed, discard);
1004
1005 return rx_ev_q_label;
1006}
1007
1008/* Global events are basically PHY events */
1009static void falcon_handle_global_event(struct efx_channel *channel,
1010 efx_qword_t *event)
1011{
1012 struct efx_nic *efx = channel->efx;
1013 int is_phy_event = 0, handled = 0;
1014
1015 /* Check for interrupt on either port. Some boards have a
1016 * single PHY wired to the interrupt line for port 1. */
1017 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1018 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1019 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
1020 is_phy_event = 1;
1021
Ben Hutchings55668612008-05-16 21:16:10 +01001022 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
Ben Hutchings8ceee662008-04-27 12:55:59 +01001023 EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
1024 is_phy_event = 1;
1025
1026 if (is_phy_event) {
1027 efx->phy_op->clear_interrupt(efx);
1028 queue_work(efx->workqueue, &efx->reconfigure_work);
1029 handled = 1;
1030 }
1031
1032 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1033 EFX_ERR(efx, "channel %d seen global RX_RESET "
1034 "event. Resetting.\n", channel->channel);
1035
1036 atomic_inc(&efx->rx_reset);
1037 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1038 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1039 handled = 1;
1040 }
1041
1042 if (!handled)
1043 EFX_ERR(efx, "channel %d unknown global event "
1044 EFX_QWORD_FMT "\n", channel->channel,
1045 EFX_QWORD_VAL(*event));
1046}
1047
1048static void falcon_handle_driver_event(struct efx_channel *channel,
1049 efx_qword_t *event)
1050{
1051 struct efx_nic *efx = channel->efx;
1052 unsigned int ev_sub_code;
1053 unsigned int ev_sub_data;
1054
1055 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1056 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1057
1058 switch (ev_sub_code) {
1059 case TX_DESCQ_FLS_DONE_EV_DECODE:
1060 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1061 channel->channel, ev_sub_data);
1062 break;
1063 case RX_DESCQ_FLS_DONE_EV_DECODE:
1064 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1065 channel->channel, ev_sub_data);
1066 break;
1067 case EVQ_INIT_DONE_EV_DECODE:
1068 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1069 channel->channel, ev_sub_data);
1070 break;
1071 case SRM_UPD_DONE_EV_DECODE:
1072 EFX_TRACE(efx, "channel %d SRAM update done\n",
1073 channel->channel);
1074 break;
1075 case WAKE_UP_EV_DECODE:
1076 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1077 channel->channel, ev_sub_data);
1078 break;
1079 case TIMER_EV_DECODE:
1080 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1081 channel->channel, ev_sub_data);
1082 break;
1083 case RX_RECOVERY_EV_DECODE:
1084 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1085 "Resetting.\n", channel->channel);
Ben Hutchings05e3ec02008-05-07 13:00:39 +01001086 atomic_inc(&efx->rx_reset);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001087 efx_schedule_reset(efx,
1088 EFX_WORKAROUND_6555(efx) ?
1089 RESET_TYPE_RX_RECOVERY :
1090 RESET_TYPE_DISABLE);
1091 break;
1092 case RX_DSC_ERROR_EV_DECODE:
1093 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1094 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1095 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1096 break;
1097 case TX_DSC_ERROR_EV_DECODE:
1098 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1099 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1100 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1101 break;
1102 default:
1103 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1104 "data %04x\n", channel->channel, ev_sub_code,
1105 ev_sub_data);
1106 break;
1107 }
1108}
1109
1110int falcon_process_eventq(struct efx_channel *channel, int *rx_quota)
1111{
1112 unsigned int read_ptr;
1113 efx_qword_t event, *p_event;
1114 int ev_code;
1115 int rxq;
1116 int rxdmaqs = 0;
1117
1118 read_ptr = channel->eventq_read_ptr;
1119
1120 do {
1121 p_event = falcon_event(channel, read_ptr);
1122 event = *p_event;
1123
1124 if (!falcon_event_present(&event))
1125 /* End of events */
1126 break;
1127
1128 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1129 channel->channel, EFX_QWORD_VAL(event));
1130
1131 /* Clear this event by marking it all ones */
1132 EFX_SET_QWORD(*p_event);
1133
1134 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1135
1136 switch (ev_code) {
1137 case RX_IP_EV_DECODE:
1138 rxq = falcon_handle_rx_event(channel, &event);
1139 rxdmaqs |= (1 << rxq);
1140 (*rx_quota)--;
1141 break;
1142 case TX_IP_EV_DECODE:
1143 falcon_handle_tx_event(channel, &event);
1144 break;
1145 case DRV_GEN_EV_DECODE:
1146 channel->eventq_magic
1147 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1148 EFX_LOG(channel->efx, "channel %d received generated "
1149 "event "EFX_QWORD_FMT"\n", channel->channel,
1150 EFX_QWORD_VAL(event));
1151 break;
1152 case GLOBAL_EV_DECODE:
1153 falcon_handle_global_event(channel, &event);
1154 break;
1155 case DRIVER_EV_DECODE:
1156 falcon_handle_driver_event(channel, &event);
1157 break;
1158 default:
1159 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1160 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1161 ev_code, EFX_QWORD_VAL(event));
1162 }
1163
1164 /* Increment read pointer */
1165 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1166
1167 } while (*rx_quota);
1168
1169 channel->eventq_read_ptr = read_ptr;
1170 return rxdmaqs;
1171}
1172
1173void falcon_set_int_moderation(struct efx_channel *channel)
1174{
1175 efx_dword_t timer_cmd;
1176 struct efx_nic *efx = channel->efx;
1177
1178 /* Set timer register */
1179 if (channel->irq_moderation) {
1180 /* Round to resolution supported by hardware. The value we
1181 * program is based at 0. So actual interrupt moderation
1182 * achieved is ((x + 1) * res).
1183 */
1184 unsigned int res = 5;
1185 channel->irq_moderation -= (channel->irq_moderation % res);
1186 if (channel->irq_moderation < res)
1187 channel->irq_moderation = res;
1188 EFX_POPULATE_DWORD_2(timer_cmd,
1189 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1190 TIMER_VAL,
1191 (channel->irq_moderation / res) - 1);
1192 } else {
1193 EFX_POPULATE_DWORD_2(timer_cmd,
1194 TIMER_MODE, TIMER_MODE_DIS,
1195 TIMER_VAL, 0);
1196 }
1197 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1198 channel->evqnum);
1199
1200}
1201
1202/* Allocate buffer table entries for event queue */
1203int falcon_probe_eventq(struct efx_channel *channel)
1204{
1205 struct efx_nic *efx = channel->efx;
1206 unsigned int evq_size;
1207
1208 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1209 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1210}
1211
1212int falcon_init_eventq(struct efx_channel *channel)
1213{
1214 efx_oword_t evq_ptr;
1215 struct efx_nic *efx = channel->efx;
1216 int rc;
1217
1218 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1219 channel->channel, channel->eventq.index,
1220 channel->eventq.index + channel->eventq.entries - 1);
1221
1222 /* Pin event queue buffer */
1223 rc = falcon_init_special_buffer(efx, &channel->eventq);
1224 if (rc)
1225 return rc;
1226
1227 /* Fill event queue with all ones (i.e. empty events) */
1228 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1229
1230 /* Push event queue to card */
1231 EFX_POPULATE_OWORD_3(evq_ptr,
1232 EVQ_EN, 1,
1233 EVQ_SIZE, FALCON_EVQ_ORDER,
1234 EVQ_BUF_BASE_ID, channel->eventq.index);
1235 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1236 channel->evqnum);
1237
1238 falcon_set_int_moderation(channel);
1239
1240 return 0;
1241}
1242
1243void falcon_fini_eventq(struct efx_channel *channel)
1244{
1245 efx_oword_t eventq_ptr;
1246 struct efx_nic *efx = channel->efx;
1247
1248 /* Remove event queue from card */
1249 EFX_ZERO_OWORD(eventq_ptr);
1250 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1251 channel->evqnum);
1252
1253 /* Unpin event queue */
1254 falcon_fini_special_buffer(efx, &channel->eventq);
1255}
1256
1257/* Free buffers backing event queue */
1258void falcon_remove_eventq(struct efx_channel *channel)
1259{
1260 falcon_free_special_buffer(channel->efx, &channel->eventq);
1261}
1262
1263
1264/* Generates a test event on the event queue. A subsequent call to
1265 * process_eventq() should pick up the event and place the value of
1266 * "magic" into channel->eventq_magic;
1267 */
1268void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1269{
1270 efx_qword_t test_event;
1271
1272 EFX_POPULATE_QWORD_2(test_event,
1273 EV_CODE, DRV_GEN_EV_DECODE,
1274 EVQ_MAGIC, magic);
1275 falcon_generate_event(channel, &test_event);
1276}
1277
1278
1279/**************************************************************************
1280 *
1281 * Falcon hardware interrupts
1282 * The hardware interrupt handler does very little work; all the event
1283 * queue processing is carried out by per-channel tasklets.
1284 *
1285 **************************************************************************/
1286
1287/* Enable/disable/generate Falcon interrupts */
1288static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1289 int force)
1290{
1291 efx_oword_t int_en_reg_ker;
1292
1293 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1294 KER_INT_KER, force,
1295 DRV_INT_EN_KER, enabled);
1296 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1297}
1298
1299void falcon_enable_interrupts(struct efx_nic *efx)
1300{
1301 efx_oword_t int_adr_reg_ker;
1302 struct efx_channel *channel;
1303
1304 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1305 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1306
1307 /* Program address */
1308 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1309 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1310 INT_ADR_KER, efx->irq_status.dma_addr);
1311 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1312
1313 /* Enable interrupts */
1314 falcon_interrupts(efx, 1, 0);
1315
1316 /* Force processing of all the channels to get the EVQ RPTRs up to
1317 date */
1318 efx_for_each_channel_with_interrupt(channel, efx)
1319 efx_schedule_channel(channel);
1320}
1321
1322void falcon_disable_interrupts(struct efx_nic *efx)
1323{
1324 /* Disable interrupts */
1325 falcon_interrupts(efx, 0, 0);
1326}
1327
1328/* Generate a Falcon test interrupt
1329 * Interrupt must already have been enabled, otherwise nasty things
1330 * may happen.
1331 */
1332void falcon_generate_interrupt(struct efx_nic *efx)
1333{
1334 falcon_interrupts(efx, 1, 1);
1335}
1336
1337/* Acknowledge a legacy interrupt from Falcon
1338 *
1339 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1340 *
1341 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1342 * BIU. Interrupt acknowledge is read sensitive so must write instead
1343 * (then read to ensure the BIU collector is flushed)
1344 *
1345 * NB most hardware supports MSI interrupts
1346 */
1347static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1348{
1349 efx_dword_t reg;
1350
1351 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1352 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1353 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1354}
1355
1356/* Process a fatal interrupt
1357 * Disable bus mastering ASAP and schedule a reset
1358 */
1359static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1360{
1361 struct falcon_nic_data *nic_data = efx->nic_data;
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001362 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001363 efx_oword_t fatal_intr;
1364 int error, mem_perr;
1365 static int n_int_errors;
1366
1367 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1368 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1369
1370 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1371 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1372 EFX_OWORD_VAL(fatal_intr),
1373 error ? "disabling bus mastering" : "no recognised error");
1374 if (error == 0)
1375 goto out;
1376
1377 /* If this is a memory parity error dump which blocks are offending */
1378 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1379 if (mem_perr) {
1380 efx_oword_t reg;
1381 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1382 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1383 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1384 }
1385
1386 /* Disable DMA bus mastering on both devices */
1387 pci_disable_device(efx->pci_dev);
1388 if (FALCON_IS_DUAL_FUNC(efx))
1389 pci_disable_device(nic_data->pci_dev2);
1390
1391 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1392 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1393 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1394 } else {
1395 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1396 "NIC will be disabled\n");
1397 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1398 }
1399out:
1400 return IRQ_HANDLED;
1401}
1402
1403/* Handle a legacy interrupt from Falcon
1404 * Acknowledges the interrupt and schedule event queue processing.
1405 */
1406static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1407{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001408 struct efx_nic *efx = dev_id;
1409 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001410 struct efx_channel *channel;
1411 efx_dword_t reg;
1412 u32 queues;
1413 int syserr;
1414
1415 /* Read the ISR which also ACKs the interrupts */
1416 falcon_readl(efx, &reg, INT_ISR0_B0);
1417 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1418
1419 /* Check to see if we have a serious error condition */
1420 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1421 if (unlikely(syserr))
1422 return falcon_fatal_interrupt(efx);
1423
1424 if (queues == 0)
1425 return IRQ_NONE;
1426
1427 efx->last_irq_cpu = raw_smp_processor_id();
1428 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1429 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1430
1431 /* Schedule processing of any interrupting queues */
1432 channel = &efx->channel[0];
1433 while (queues) {
1434 if (queues & 0x01)
1435 efx_schedule_channel(channel);
1436 channel++;
1437 queues >>= 1;
1438 }
1439
1440 return IRQ_HANDLED;
1441}
1442
1443
1444static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1445{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001446 struct efx_nic *efx = dev_id;
1447 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001448 struct efx_channel *channel;
1449 int syserr;
1450 int queues;
1451
1452 /* Check to see if this is our interrupt. If it isn't, we
1453 * exit without having touched the hardware.
1454 */
1455 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1456 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1457 raw_smp_processor_id());
1458 return IRQ_NONE;
1459 }
1460 efx->last_irq_cpu = raw_smp_processor_id();
1461 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1462 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1463
1464 /* Check to see if we have a serious error condition */
1465 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1466 if (unlikely(syserr))
1467 return falcon_fatal_interrupt(efx);
1468
1469 /* Determine interrupting queues, clear interrupt status
1470 * register and acknowledge the device interrupt.
1471 */
1472 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1473 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1474 EFX_ZERO_OWORD(*int_ker);
1475 wmb(); /* Ensure the vector is cleared before interrupt ack */
1476 falcon_irq_ack_a1(efx);
1477
1478 /* Schedule processing of any interrupting queues */
1479 channel = &efx->channel[0];
1480 while (queues) {
1481 if (queues & 0x01)
1482 efx_schedule_channel(channel);
1483 channel++;
1484 queues >>= 1;
1485 }
1486
1487 return IRQ_HANDLED;
1488}
1489
1490/* Handle an MSI interrupt from Falcon
1491 *
1492 * Handle an MSI hardware interrupt. This routine schedules event
1493 * queue processing. No interrupt acknowledgement cycle is necessary.
1494 * Also, we never need to check that the interrupt is for us, since
1495 * MSI interrupts cannot be shared.
1496 */
1497static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1498{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001499 struct efx_channel *channel = dev_id;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001500 struct efx_nic *efx = channel->efx;
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001501 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001502 int syserr;
1503
1504 efx->last_irq_cpu = raw_smp_processor_id();
1505 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1506 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1507
1508 /* Check to see if we have a serious error condition */
1509 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1510 if (unlikely(syserr))
1511 return falcon_fatal_interrupt(efx);
1512
1513 /* Schedule processing of the channel */
1514 efx_schedule_channel(channel);
1515
1516 return IRQ_HANDLED;
1517}
1518
1519
1520/* Setup RSS indirection table.
1521 * This maps from the hash value of the packet to RXQ
1522 */
1523static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1524{
1525 int i = 0;
1526 unsigned long offset;
1527 efx_dword_t dword;
1528
Ben Hutchings55668612008-05-16 21:16:10 +01001529 if (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001530 return;
1531
1532 for (offset = RX_RSS_INDIR_TBL_B0;
1533 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1534 offset += 0x10) {
1535 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1536 i % efx->rss_queues);
1537 falcon_writel(efx, &dword, offset);
1538 i++;
1539 }
1540}
1541
1542/* Hook interrupt handler(s)
1543 * Try MSI and then legacy interrupts.
1544 */
1545int falcon_init_interrupt(struct efx_nic *efx)
1546{
1547 struct efx_channel *channel;
1548 int rc;
1549
1550 if (!EFX_INT_MODE_USE_MSI(efx)) {
1551 irq_handler_t handler;
Ben Hutchings55668612008-05-16 21:16:10 +01001552 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001553 handler = falcon_legacy_interrupt_b0;
1554 else
1555 handler = falcon_legacy_interrupt_a1;
1556
1557 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1558 efx->name, efx);
1559 if (rc) {
1560 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1561 efx->pci_dev->irq);
1562 goto fail1;
1563 }
1564 return 0;
1565 }
1566
1567 /* Hook MSI or MSI-X interrupt */
1568 efx_for_each_channel_with_interrupt(channel, efx) {
1569 rc = request_irq(channel->irq, falcon_msi_interrupt,
1570 IRQF_PROBE_SHARED, /* Not shared */
1571 efx->name, channel);
1572 if (rc) {
1573 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1574 goto fail2;
1575 }
1576 }
1577
1578 return 0;
1579
1580 fail2:
1581 efx_for_each_channel_with_interrupt(channel, efx)
1582 free_irq(channel->irq, channel);
1583 fail1:
1584 return rc;
1585}
1586
1587void falcon_fini_interrupt(struct efx_nic *efx)
1588{
1589 struct efx_channel *channel;
1590 efx_oword_t reg;
1591
1592 /* Disable MSI/MSI-X interrupts */
Ben Hutchingsb3475642008-05-16 21:15:49 +01001593 efx_for_each_channel_with_interrupt(channel, efx) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001594 if (channel->irq)
1595 free_irq(channel->irq, channel);
Ben Hutchingsb3475642008-05-16 21:15:49 +01001596 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001597
1598 /* ACK legacy interrupt */
Ben Hutchings55668612008-05-16 21:16:10 +01001599 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001600 falcon_read(efx, &reg, INT_ISR0_B0);
1601 else
1602 falcon_irq_ack_a1(efx);
1603
1604 /* Disable legacy interrupt */
1605 if (efx->legacy_irq)
1606 free_irq(efx->legacy_irq, efx);
1607}
1608
1609/**************************************************************************
1610 *
1611 * EEPROM/flash
1612 *
1613 **************************************************************************
1614 */
1615
1616#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1617
1618/* Wait for SPI command completion */
1619static int falcon_spi_wait(struct efx_nic *efx)
1620{
1621 efx_oword_t reg;
1622 int cmd_en, timer_active;
1623 int count;
1624
1625 count = 0;
1626 do {
1627 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1628 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1629 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1630 if (!cmd_en && !timer_active)
1631 return 0;
1632 udelay(10);
1633 } while (++count < 10000); /* wait upto 100msec */
1634 EFX_ERR(efx, "timed out waiting for SPI\n");
1635 return -ETIMEDOUT;
1636}
1637
1638static int
1639falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command,
1640 unsigned int address, unsigned int addr_len,
1641 void *data, unsigned int len)
1642{
1643 efx_oword_t reg;
1644 int rc;
1645
1646 BUG_ON(len > FALCON_SPI_MAX_LEN);
1647
1648 /* Check SPI not currently being accessed */
1649 rc = falcon_spi_wait(efx);
1650 if (rc)
1651 return rc;
1652
1653 /* Program address register */
1654 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1655 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1656
1657 /* Issue read command */
1658 EFX_POPULATE_OWORD_7(reg,
1659 EE_SPI_HCMD_CMD_EN, 1,
1660 EE_SPI_HCMD_SF_SEL, device_id,
1661 EE_SPI_HCMD_DABCNT, len,
1662 EE_SPI_HCMD_READ, EE_SPI_READ,
1663 EE_SPI_HCMD_DUBCNT, 0,
1664 EE_SPI_HCMD_ADBCNT, addr_len,
1665 EE_SPI_HCMD_ENC, command);
1666 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1667
1668 /* Wait for read to complete */
1669 rc = falcon_spi_wait(efx);
1670 if (rc)
1671 return rc;
1672
1673 /* Read data */
1674 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1675 memcpy(data, &reg, len);
1676 return 0;
1677}
1678
1679/**************************************************************************
1680 *
1681 * MAC wrapper
1682 *
1683 **************************************************************************
1684 */
1685void falcon_drain_tx_fifo(struct efx_nic *efx)
1686{
1687 efx_oword_t temp;
1688 int count;
1689
Ben Hutchings55668612008-05-16 21:16:10 +01001690 if ((falcon_rev(efx) < FALCON_REV_B0) ||
Ben Hutchings3273c2e2008-05-07 13:36:19 +01001691 (efx->loopback_mode != LOOPBACK_NONE))
Ben Hutchings8ceee662008-04-27 12:55:59 +01001692 return;
1693
1694 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1695 /* There is no point in draining more than once */
1696 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1697 return;
1698
1699 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1700 * the drain sequence with the statistics fetch */
1701 spin_lock(&efx->stats_lock);
1702
1703 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1704 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1705
1706 /* Reset the MAC and EM block. */
1707 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1708 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1709 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1710 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1711 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1712
1713 count = 0;
1714 while (1) {
1715 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1716 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1717 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1718 !EFX_OWORD_FIELD(temp, RST_EM)) {
1719 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1720 count);
1721 break;
1722 }
1723 if (count > 20) {
1724 EFX_ERR(efx, "MAC reset failed\n");
1725 break;
1726 }
1727 count++;
1728 udelay(10);
1729 }
1730
1731 spin_unlock(&efx->stats_lock);
1732
1733 /* If we've reset the EM block and the link is up, then
1734 * we'll have to kick the XAUI link so the PHY can recover */
1735 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1736 falcon_reset_xaui(efx);
1737}
1738
1739void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1740{
1741 efx_oword_t temp;
1742
Ben Hutchings55668612008-05-16 21:16:10 +01001743 if (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001744 return;
1745
1746 /* Isolate the MAC -> RX */
1747 falcon_read(efx, &temp, RX_CFG_REG_KER);
1748 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1749 falcon_write(efx, &temp, RX_CFG_REG_KER);
1750
1751 if (!efx->link_up)
1752 falcon_drain_tx_fifo(efx);
1753}
1754
1755void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1756{
1757 efx_oword_t reg;
1758 int link_speed;
1759 unsigned int tx_fc;
1760
1761 if (efx->link_options & GM_LPA_10000)
1762 link_speed = 0x3;
1763 else if (efx->link_options & GM_LPA_1000)
1764 link_speed = 0x2;
1765 else if (efx->link_options & GM_LPA_100)
1766 link_speed = 0x1;
1767 else
1768 link_speed = 0x0;
1769 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1770 * as advertised. Disable to ensure packets are not
1771 * indefinitely held and TX queue can be flushed at any point
1772 * while the link is down. */
1773 EFX_POPULATE_OWORD_5(reg,
1774 MAC_XOFF_VAL, 0xffff /* max pause time */,
1775 MAC_BCAD_ACPT, 1,
1776 MAC_UC_PROM, efx->promiscuous,
1777 MAC_LINK_STATUS, 1, /* always set */
1778 MAC_SPEED, link_speed);
1779 /* On B0, MAC backpressure can be disabled and packets get
1780 * discarded. */
Ben Hutchings55668612008-05-16 21:16:10 +01001781 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001782 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1783 !efx->link_up);
1784 }
1785
1786 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1787
1788 /* Restore the multicast hash registers. */
1789 falcon_set_multicast_hash(efx);
1790
1791 /* Transmission of pause frames when RX crosses the threshold is
1792 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1793 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1794 tx_fc = (efx->flow_control & EFX_FC_TX) ? 1 : 0;
1795 falcon_read(efx, &reg, RX_CFG_REG_KER);
1796 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1797
1798 /* Unisolate the MAC -> RX */
Ben Hutchings55668612008-05-16 21:16:10 +01001799 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001800 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1801 falcon_write(efx, &reg, RX_CFG_REG_KER);
1802}
1803
1804int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1805{
1806 efx_oword_t reg;
1807 u32 *dma_done;
1808 int i;
1809
1810 if (disable_dma_stats)
1811 return 0;
1812
1813 /* Statistics fetch will fail if the MAC is in TX drain */
Ben Hutchings55668612008-05-16 21:16:10 +01001814 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001815 efx_oword_t temp;
1816 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1817 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1818 return 0;
1819 }
1820
1821 dma_done = (efx->stats_buffer.addr + done_offset);
1822 *dma_done = FALCON_STATS_NOT_DONE;
1823 wmb(); /* ensure done flag is clear */
1824
1825 /* Initiate DMA transfer of stats */
1826 EFX_POPULATE_OWORD_2(reg,
1827 MAC_STAT_DMA_CMD, 1,
1828 MAC_STAT_DMA_ADR,
1829 efx->stats_buffer.dma_addr);
1830 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1831
1832 /* Wait for transfer to complete */
1833 for (i = 0; i < 400; i++) {
1834 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1835 return 0;
1836 udelay(10);
1837 }
1838
1839 EFX_ERR(efx, "timed out waiting for statistics\n");
1840 return -ETIMEDOUT;
1841}
1842
1843/**************************************************************************
1844 *
1845 * PHY access via GMII
1846 *
1847 **************************************************************************
1848 */
1849
1850/* Use the top bit of the MII PHY id to indicate the PHY type
1851 * (1G/10G), with the remaining bits as the actual PHY id.
1852 *
1853 * This allows us to avoid leaking information from the mii_if_info
1854 * structure into other data structures.
1855 */
1856#define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1857#define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1858#define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1859#define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1860#define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1861
1862
1863/* Packing the clause 45 port and device fields into a single value */
1864#define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1865#define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1866#define MD_DEV_ADR_COMP_LBN 0
1867#define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1868
1869
1870/* Wait for GMII access to complete */
1871static int falcon_gmii_wait(struct efx_nic *efx)
1872{
1873 efx_dword_t md_stat;
1874 int count;
1875
1876 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
1877 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
1878 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
1879 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
1880 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
1881 EFX_ERR(efx, "error from GMII access "
1882 EFX_DWORD_FMT"\n",
1883 EFX_DWORD_VAL(md_stat));
1884 return -EIO;
1885 }
1886 return 0;
1887 }
1888 udelay(10);
1889 }
1890 EFX_ERR(efx, "timed out waiting for GMII\n");
1891 return -ETIMEDOUT;
1892}
1893
1894/* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1895static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
1896 int addr, int value)
1897{
Ben Hutchings767e4682008-09-01 12:43:14 +01001898 struct efx_nic *efx = netdev_priv(net_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001899 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
1900 efx_oword_t reg;
1901
1902 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1903 * chosen so that the only current user, Falcon, can take the
1904 * packed value and use them directly.
1905 * Fail to build if this assumption is broken.
1906 */
1907 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
1908 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
1909 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
1910 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
1911
1912 if (phy_id2 == PHY_ADDR_INVALID)
1913 return;
1914
1915 /* See falcon_mdio_read for an explanation. */
1916 if (!(phy_id & FALCON_PHY_ID_10G)) {
1917 int mmd = ffs(efx->phy_op->mmds) - 1;
1918 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
1919 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
1920 & FALCON_PHY_ID_ID_MASK;
1921 }
1922
1923 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
1924 addr, value);
1925
1926 spin_lock_bh(&efx->phy_lock);
1927
1928 /* Check MII not currently being accessed */
1929 if (falcon_gmii_wait(efx) != 0)
1930 goto out;
1931
1932 /* Write the address/ID register */
1933 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
1934 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
1935
1936 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
1937 falcon_write(efx, &reg, MD_ID_REG_KER);
1938
1939 /* Write data */
1940 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
1941 falcon_write(efx, &reg, MD_TXD_REG_KER);
1942
1943 EFX_POPULATE_OWORD_2(reg,
1944 MD_WRC, 1,
1945 MD_GC, 0);
1946 falcon_write(efx, &reg, MD_CS_REG_KER);
1947
1948 /* Wait for data to be written */
1949 if (falcon_gmii_wait(efx) != 0) {
1950 /* Abort the write operation */
1951 EFX_POPULATE_OWORD_2(reg,
1952 MD_WRC, 0,
1953 MD_GC, 1);
1954 falcon_write(efx, &reg, MD_CS_REG_KER);
1955 udelay(10);
1956 }
1957
1958 out:
1959 spin_unlock_bh(&efx->phy_lock);
1960}
1961
1962/* Reads a GMII register from a PHY connected to Falcon. If no value
1963 * could be read, -1 will be returned. */
1964static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
1965{
Ben Hutchings767e4682008-09-01 12:43:14 +01001966 struct efx_nic *efx = netdev_priv(net_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001967 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
1968 efx_oword_t reg;
1969 int value = -1;
1970
1971 if (phy_addr == PHY_ADDR_INVALID)
1972 return -1;
1973
1974 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
1975 * but the generic Linux code does not make any distinction or have
1976 * any state for this.
1977 * We spot the case where someone tried to talk 22 to a 45 PHY and
1978 * redirect the request to the lowest numbered MMD as a clause45
1979 * request. This is enough to allow simple queries like id and link
1980 * state to succeed. TODO: We may need to do more in future.
1981 */
1982 if (!(phy_id & FALCON_PHY_ID_10G)) {
1983 int mmd = ffs(efx->phy_op->mmds) - 1;
1984 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
1985 phy_addr = mdio_clause45_pack(phy_addr, mmd)
1986 & FALCON_PHY_ID_ID_MASK;
1987 }
1988
1989 spin_lock_bh(&efx->phy_lock);
1990
1991 /* Check MII not currently being accessed */
1992 if (falcon_gmii_wait(efx) != 0)
1993 goto out;
1994
1995 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
1996 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
1997
1998 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
1999 falcon_write(efx, &reg, MD_ID_REG_KER);
2000
2001 /* Request data to be read */
2002 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2003 falcon_write(efx, &reg, MD_CS_REG_KER);
2004
2005 /* Wait for data to become available */
2006 value = falcon_gmii_wait(efx);
2007 if (value == 0) {
2008 falcon_read(efx, &reg, MD_RXD_REG_KER);
2009 value = EFX_OWORD_FIELD(reg, MD_RXD);
2010 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2011 phy_id, addr, value);
2012 } else {
2013 /* Abort the read operation */
2014 EFX_POPULATE_OWORD_2(reg,
2015 MD_RIC, 0,
2016 MD_GC, 1);
2017 falcon_write(efx, &reg, MD_CS_REG_KER);
2018
2019 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2020 "error %d\n", phy_id, addr, value);
2021 }
2022
2023 out:
2024 spin_unlock_bh(&efx->phy_lock);
2025
2026 return value;
2027}
2028
2029static void falcon_init_mdio(struct mii_if_info *gmii)
2030{
2031 gmii->mdio_read = falcon_mdio_read;
2032 gmii->mdio_write = falcon_mdio_write;
2033 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2034 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2035}
2036
2037static int falcon_probe_phy(struct efx_nic *efx)
2038{
2039 switch (efx->phy_type) {
2040 case PHY_TYPE_10XPRESS:
2041 efx->phy_op = &falcon_tenxpress_phy_ops;
2042 break;
2043 case PHY_TYPE_XFP:
2044 efx->phy_op = &falcon_xfp_phy_ops;
2045 break;
2046 default:
2047 EFX_ERR(efx, "Unknown PHY type %d\n",
2048 efx->phy_type);
2049 return -1;
2050 }
Ben Hutchings3273c2e2008-05-07 13:36:19 +01002051
2052 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002053 return 0;
2054}
2055
2056/* This call is responsible for hooking in the MAC and PHY operations */
2057int falcon_probe_port(struct efx_nic *efx)
2058{
2059 int rc;
2060
2061 /* Hook in PHY operations table */
2062 rc = falcon_probe_phy(efx);
2063 if (rc)
2064 return rc;
2065
2066 /* Set up GMII structure for PHY */
2067 efx->mii.supports_gmii = 1;
2068 falcon_init_mdio(&efx->mii);
2069
2070 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
Ben Hutchings55668612008-05-16 21:16:10 +01002071 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002072 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2073 else
2074 efx->flow_control = EFX_FC_RX;
2075
2076 /* Allocate buffer for stats */
2077 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2078 FALCON_MAC_STATS_SIZE);
2079 if (rc)
2080 return rc;
2081 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2082 (unsigned long long)efx->stats_buffer.dma_addr,
2083 efx->stats_buffer.addr,
2084 virt_to_phys(efx->stats_buffer.addr));
2085
2086 return 0;
2087}
2088
2089void falcon_remove_port(struct efx_nic *efx)
2090{
2091 falcon_free_buffer(efx, &efx->stats_buffer);
2092}
2093
2094/**************************************************************************
2095 *
2096 * Multicast filtering
2097 *
2098 **************************************************************************
2099 */
2100
2101void falcon_set_multicast_hash(struct efx_nic *efx)
2102{
2103 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2104
2105 /* Broadcast packets go through the multicast hash filter.
2106 * ether_crc_le() of the broadcast address is 0xbe2612ff
2107 * so we always add bit 0xff to the mask.
2108 */
2109 set_bit_le(0xff, mc_hash->byte);
2110
2111 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2112 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2113}
2114
2115/**************************************************************************
2116 *
2117 * Device reset
2118 *
2119 **************************************************************************
2120 */
2121
2122/* Resets NIC to known state. This routine must be called in process
2123 * context and is allowed to sleep. */
2124int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2125{
2126 struct falcon_nic_data *nic_data = efx->nic_data;
2127 efx_oword_t glb_ctl_reg_ker;
2128 int rc;
2129
2130 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2131
2132 /* Initiate device reset */
2133 if (method == RESET_TYPE_WORLD) {
2134 rc = pci_save_state(efx->pci_dev);
2135 if (rc) {
2136 EFX_ERR(efx, "failed to backup PCI state of primary "
2137 "function prior to hardware reset\n");
2138 goto fail1;
2139 }
2140 if (FALCON_IS_DUAL_FUNC(efx)) {
2141 rc = pci_save_state(nic_data->pci_dev2);
2142 if (rc) {
2143 EFX_ERR(efx, "failed to backup PCI state of "
2144 "secondary function prior to "
2145 "hardware reset\n");
2146 goto fail2;
2147 }
2148 }
2149
2150 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2151 EXT_PHY_RST_DUR, 0x7,
2152 SWRST, 1);
2153 } else {
2154 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2155 EXCLUDE_FROM_RESET : 0);
2156
2157 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2158 EXT_PHY_RST_CTL, reset_phy,
2159 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2160 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2161 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2162 EE_RST_CTL, EXCLUDE_FROM_RESET,
2163 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2164 SWRST, 1);
2165 }
2166 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2167
2168 EFX_LOG(efx, "waiting for hardware reset\n");
2169 schedule_timeout_uninterruptible(HZ / 20);
2170
2171 /* Restore PCI configuration if needed */
2172 if (method == RESET_TYPE_WORLD) {
2173 if (FALCON_IS_DUAL_FUNC(efx)) {
2174 rc = pci_restore_state(nic_data->pci_dev2);
2175 if (rc) {
2176 EFX_ERR(efx, "failed to restore PCI config for "
2177 "the secondary function\n");
2178 goto fail3;
2179 }
2180 }
2181 rc = pci_restore_state(efx->pci_dev);
2182 if (rc) {
2183 EFX_ERR(efx, "failed to restore PCI config for the "
2184 "primary function\n");
2185 goto fail4;
2186 }
2187 EFX_LOG(efx, "successfully restored PCI config\n");
2188 }
2189
2190 /* Assert that reset complete */
2191 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2192 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2193 rc = -ETIMEDOUT;
2194 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2195 goto fail5;
2196 }
2197 EFX_LOG(efx, "hardware reset complete\n");
2198
2199 return 0;
2200
2201 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2202fail2:
2203fail3:
2204 pci_restore_state(efx->pci_dev);
2205fail1:
2206fail4:
2207fail5:
2208 return rc;
2209}
2210
2211/* Zeroes out the SRAM contents. This routine must be called in
2212 * process context and is allowed to sleep.
2213 */
2214static int falcon_reset_sram(struct efx_nic *efx)
2215{
2216 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2217 int count;
2218
2219 /* Set the SRAM wake/sleep GPIO appropriately. */
2220 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2221 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2222 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2223 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2224
2225 /* Initiate SRAM reset */
2226 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2227 SRAM_OOB_BT_INIT_EN, 1,
2228 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2229 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2230
2231 /* Wait for SRAM reset to complete */
2232 count = 0;
2233 do {
2234 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2235
2236 /* SRAM reset is slow; expect around 16ms */
2237 schedule_timeout_uninterruptible(HZ / 50);
2238
2239 /* Check for reset complete */
2240 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2241 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2242 EFX_LOG(efx, "SRAM reset complete\n");
2243
2244 return 0;
2245 }
2246 } while (++count < 20); /* wait upto 0.4 sec */
2247
2248 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2249 return -ETIMEDOUT;
2250}
2251
2252/* Extract non-volatile configuration */
2253static int falcon_probe_nvconfig(struct efx_nic *efx)
2254{
2255 struct falcon_nvconfig *nvconfig;
2256 efx_oword_t nic_stat;
2257 int device_id;
2258 unsigned addr_len;
2259 size_t offset, len;
2260 int magic_num, struct_ver, board_rev;
2261 int rc;
2262
2263 /* Find the boot device. */
2264 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2265 if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) {
2266 device_id = EE_SPI_FLASH;
2267 addr_len = 3;
2268 } else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) {
2269 device_id = EE_SPI_EEPROM;
2270 addr_len = 2;
2271 } else {
2272 return -ENODEV;
2273 }
2274
2275 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2276
2277 /* Read the whole configuration structure into memory. */
2278 for (offset = 0; offset < sizeof(*nvconfig); offset += len) {
2279 len = min(sizeof(*nvconfig) - offset,
2280 (size_t) FALCON_SPI_MAX_LEN);
2281 rc = falcon_spi_read(efx, device_id, SPI_READ,
2282 NVCONFIG_BASE + offset, addr_len,
2283 (char *)nvconfig + offset, len);
2284 if (rc)
2285 goto out;
2286 }
2287
2288 /* Read the MAC addresses */
2289 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2290
2291 /* Read the board configuration. */
2292 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2293 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2294
2295 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
2296 EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
2297 "therefore using defaults\n", magic_num, struct_ver);
2298 efx->phy_type = PHY_TYPE_NONE;
2299 efx->mii.phy_id = PHY_ADDR_INVALID;
2300 board_rev = 0;
2301 } else {
2302 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2303
2304 efx->phy_type = v2->port0_phy_type;
2305 efx->mii.phy_id = v2->port0_phy_addr;
2306 board_rev = le16_to_cpu(v2->board_revision);
2307 }
2308
2309 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2310
2311 efx_set_board_info(efx, board_rev);
2312
2313 out:
2314 kfree(nvconfig);
2315 return rc;
2316}
2317
2318/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2319 * count, port speed). Set workaround and feature flags accordingly.
2320 */
2321static int falcon_probe_nic_variant(struct efx_nic *efx)
2322{
2323 efx_oword_t altera_build;
2324
2325 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2326 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2327 EFX_ERR(efx, "Falcon FPGA not supported\n");
2328 return -ENODEV;
2329 }
2330
Ben Hutchings55668612008-05-16 21:16:10 +01002331 switch (falcon_rev(efx)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002332 case FALCON_REV_A0:
2333 case 0xff:
2334 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2335 return -ENODEV;
2336
2337 case FALCON_REV_A1:{
2338 efx_oword_t nic_stat;
2339
2340 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2341
2342 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2343 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2344 return -ENODEV;
2345 }
2346 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2347 EFX_ERR(efx, "1G mode not supported\n");
2348 return -ENODEV;
2349 }
2350 break;
2351 }
2352
2353 case FALCON_REV_B0:
2354 break;
2355
2356 default:
Ben Hutchings55668612008-05-16 21:16:10 +01002357 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002358 return -ENODEV;
2359 }
2360
2361 return 0;
2362}
2363
2364int falcon_probe_nic(struct efx_nic *efx)
2365{
2366 struct falcon_nic_data *nic_data;
2367 int rc;
2368
Ben Hutchings8ceee662008-04-27 12:55:59 +01002369 /* Allocate storage for hardware specific data */
2370 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
Ben Hutchings5daab962008-05-16 21:19:43 +01002371 efx->nic_data = nic_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002372
2373 /* Determine number of ports etc. */
2374 rc = falcon_probe_nic_variant(efx);
2375 if (rc)
2376 goto fail1;
2377
2378 /* Probe secondary function if expected */
2379 if (FALCON_IS_DUAL_FUNC(efx)) {
2380 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2381
2382 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2383 dev))) {
2384 if (dev->bus == efx->pci_dev->bus &&
2385 dev->devfn == efx->pci_dev->devfn + 1) {
2386 nic_data->pci_dev2 = dev;
2387 break;
2388 }
2389 }
2390 if (!nic_data->pci_dev2) {
2391 EFX_ERR(efx, "failed to find secondary function\n");
2392 rc = -ENODEV;
2393 goto fail2;
2394 }
2395 }
2396
2397 /* Now we can reset the NIC */
2398 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2399 if (rc) {
2400 EFX_ERR(efx, "failed to reset NIC\n");
2401 goto fail3;
2402 }
2403
2404 /* Allocate memory for INT_KER */
2405 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2406 if (rc)
2407 goto fail4;
2408 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2409
2410 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2411 (unsigned long long)efx->irq_status.dma_addr,
2412 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2413
2414 /* Read in the non-volatile configuration */
2415 rc = falcon_probe_nvconfig(efx);
2416 if (rc)
2417 goto fail5;
2418
Ben Hutchings37b5a602008-05-30 22:27:04 +01002419 /* Initialise I2C adapter */
2420 efx->i2c_adap.owner = THIS_MODULE;
Ben Hutchings37b5a602008-05-30 22:27:04 +01002421 nic_data->i2c_data = falcon_i2c_bit_operations;
2422 nic_data->i2c_data.data = efx;
2423 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2424 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
Ben Hutchings9dadae62008-07-18 18:59:12 +01002425 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
Ben Hutchings37b5a602008-05-30 22:27:04 +01002426 rc = i2c_bit_add_bus(&efx->i2c_adap);
2427 if (rc)
2428 goto fail5;
2429
Ben Hutchings8ceee662008-04-27 12:55:59 +01002430 return 0;
2431
2432 fail5:
2433 falcon_free_buffer(efx, &efx->irq_status);
2434 fail4:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002435 fail3:
2436 if (nic_data->pci_dev2) {
2437 pci_dev_put(nic_data->pci_dev2);
2438 nic_data->pci_dev2 = NULL;
2439 }
2440 fail2:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002441 fail1:
2442 kfree(efx->nic_data);
2443 return rc;
2444}
2445
2446/* This call performs hardware-specific global initialisation, such as
2447 * defining the descriptor cache sizes and number of RSS channels.
2448 * It does not set up any buffers, descriptor rings or event queues.
2449 */
2450int falcon_init_nic(struct efx_nic *efx)
2451{
Ben Hutchings8ceee662008-04-27 12:55:59 +01002452 efx_oword_t temp;
2453 unsigned thresh;
2454 int rc;
2455
Ben Hutchings8ceee662008-04-27 12:55:59 +01002456 /* Set up the address region register. This is only needed
2457 * for the B0 FPGA, but since we are just pushing in the
2458 * reset defaults this may as well be unconditional. */
2459 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2460 ADR_REGION1, (1 << 16),
2461 ADR_REGION2, (2 << 16),
2462 ADR_REGION3, (3 << 16));
2463 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2464
2465 /* Use on-chip SRAM */
2466 falcon_read(efx, &temp, NIC_STAT_REG);
2467 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2468 falcon_write(efx, &temp, NIC_STAT_REG);
2469
2470 /* Set buffer table mode */
2471 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2472 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2473
2474 rc = falcon_reset_sram(efx);
2475 if (rc)
2476 return rc;
2477
2478 /* Set positions of descriptor caches in SRAM. */
2479 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2480 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2481 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2482 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2483
2484 /* Set TX descriptor cache size. */
2485 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2486 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2487 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2488
2489 /* Set RX descriptor cache size. Set low watermark to size-8, as
2490 * this allows most efficient prefetching.
2491 */
2492 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2493 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2494 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2495 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2496 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2497
2498 /* Clear the parity enables on the TX data fifos as
2499 * they produce false parity errors because of timing issues
2500 */
2501 if (EFX_WORKAROUND_5129(efx)) {
2502 falcon_read(efx, &temp, SPARE_REG_KER);
2503 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2504 falcon_write(efx, &temp, SPARE_REG_KER);
2505 }
2506
2507 /* Enable all the genuinely fatal interrupts. (They are still
2508 * masked by the overall interrupt mask, controlled by
2509 * falcon_interrupts()).
2510 *
2511 * Note: All other fatal interrupts are enabled
2512 */
2513 EFX_POPULATE_OWORD_3(temp,
2514 ILL_ADR_INT_KER_EN, 1,
2515 RBUF_OWN_INT_KER_EN, 1,
2516 TBUF_OWN_INT_KER_EN, 1);
2517 EFX_INVERT_OWORD(temp);
2518 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2519
2520 /* Set number of RSS queues for receive path. */
2521 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
Ben Hutchings55668612008-05-16 21:16:10 +01002522 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002523 EFX_SET_OWORD_FIELD(temp, NUM_KER, 0);
2524 else
2525 EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1);
2526 if (EFX_WORKAROUND_7244(efx)) {
2527 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2528 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2529 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2530 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2531 }
2532 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2533
2534 falcon_setup_rss_indir_table(efx);
2535
2536 /* Setup RX. Wait for descriptor is broken and must
2537 * be disabled. RXDP recovery shouldn't be needed, but is.
2538 */
2539 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2540 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2541 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2542 if (EFX_WORKAROUND_5583(efx))
2543 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2544 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2545
2546 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2547 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2548 */
2549 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2550 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2551 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2552 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2553 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2554 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2555 /* Enable SW_EV to inherit in char driver - assume harmless here */
2556 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2557 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2558 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2559 /* Squash TX of packets of 16 bytes or less */
Ben Hutchings55668612008-05-16 21:16:10 +01002560 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +01002561 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2562 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2563
2564 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2565 * descriptors (which is bad).
2566 */
2567 falcon_read(efx, &temp, TX_CFG_REG_KER);
2568 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2569 falcon_write(efx, &temp, TX_CFG_REG_KER);
2570
2571 /* RX config */
2572 falcon_read(efx, &temp, RX_CFG_REG_KER);
2573 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2574 if (EFX_WORKAROUND_7575(efx))
2575 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2576 (3 * 4096) / 32);
Ben Hutchings55668612008-05-16 21:16:10 +01002577 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002578 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2579
2580 /* RX FIFO flow control thresholds */
2581 thresh = ((rx_xon_thresh_bytes >= 0) ?
2582 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2583 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2584 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2585 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2586 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2587 /* RX control FIFO thresholds [32 entries] */
Ben Hutchingsc84a6f12008-09-01 12:46:21 +01002588 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
2589 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002590 falcon_write(efx, &temp, RX_CFG_REG_KER);
2591
2592 /* Set destination of both TX and RX Flush events */
Ben Hutchings55668612008-05-16 21:16:10 +01002593 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002594 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2595 falcon_write(efx, &temp, DP_CTRL_REG);
2596 }
2597
2598 return 0;
2599}
2600
2601void falcon_remove_nic(struct efx_nic *efx)
2602{
2603 struct falcon_nic_data *nic_data = efx->nic_data;
Ben Hutchings37b5a602008-05-30 22:27:04 +01002604 int rc;
2605
2606 rc = i2c_del_adapter(&efx->i2c_adap);
2607 BUG_ON(rc);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002608
2609 falcon_free_buffer(efx, &efx->irq_status);
2610
Ben Hutchings91ad7572008-05-16 21:14:27 +01002611 falcon_reset_hw(efx, RESET_TYPE_ALL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002612
2613 /* Release the second function after the reset */
2614 if (nic_data->pci_dev2) {
2615 pci_dev_put(nic_data->pci_dev2);
2616 nic_data->pci_dev2 = NULL;
2617 }
2618
2619 /* Tear down the private nic state */
2620 kfree(efx->nic_data);
2621 efx->nic_data = NULL;
2622}
2623
2624void falcon_update_nic_stats(struct efx_nic *efx)
2625{
2626 efx_oword_t cnt;
2627
2628 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
2629 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
2630}
2631
2632/**************************************************************************
2633 *
2634 * Revision-dependent attributes used by efx.c
2635 *
2636 **************************************************************************
2637 */
2638
2639struct efx_nic_type falcon_a_nic_type = {
2640 .mem_bar = 2,
2641 .mem_map_size = 0x20000,
2642 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
2643 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
2644 .buf_tbl_base = BUF_TBL_KER_A1,
2645 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
2646 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
2647 .txd_ring_mask = FALCON_TXD_RING_MASK,
2648 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2649 .evq_size = FALCON_EVQ_SIZE,
2650 .max_dma_mask = FALCON_DMA_MASK,
2651 .tx_dma_mask = FALCON_TX_DMA_MASK,
2652 .bug5391_mask = 0xf,
2653 .rx_xoff_thresh = 2048,
2654 .rx_xon_thresh = 512,
2655 .rx_buffer_padding = 0x24,
2656 .max_interrupt_mode = EFX_INT_MODE_MSI,
2657 .phys_addr_channels = 4,
2658};
2659
2660struct efx_nic_type falcon_b_nic_type = {
2661 .mem_bar = 2,
2662 /* Map everything up to and including the RSS indirection
2663 * table. Don't map MSI-X table, MSI-X PBA since Linux
2664 * requires that they not be mapped. */
2665 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
2666 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
2667 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
2668 .buf_tbl_base = BUF_TBL_KER_B0,
2669 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
2670 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
2671 .txd_ring_mask = FALCON_TXD_RING_MASK,
2672 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2673 .evq_size = FALCON_EVQ_SIZE,
2674 .max_dma_mask = FALCON_DMA_MASK,
2675 .tx_dma_mask = FALCON_TX_DMA_MASK,
2676 .bug5391_mask = 0,
2677 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
2678 .rx_xon_thresh = 27648, /* ~3*max MTU */
2679 .rx_buffer_padding = 0,
2680 .max_interrupt_mode = EFX_INT_MODE_MSIX,
2681 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
2682 * interrupt handler only supports 32
2683 * channels */
2684};
2685