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gerrit-public.fairphone.software / kernel / msm-4.9 / dd2d62dfede7aa2bd87b3fb07db0c7450ca7ea41 / . / arch / arm / boot / dts / imx6sx.dtsi
blob: f4b9da65bc0f19e65ed1c2aa71cb1f11f447757c [file] [log] [blame]
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6sx-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "imx6sx-pinfunc.h"
13#include "skeleton.dtsi"
14
15/ {
16 aliases {
17 can0 = &flexcan1;
18 can1 = &flexcan2;
19 ethernet0 = &fec1;
20 ethernet1 = &fec2;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 gpio6 = &gpio7;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 mmc3 = &usdhc4;
36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 serial5 = &uart6;
42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &ecspi3;
45 spi3 = &ecspi4;
46 spi4 = &ecspi5;
47 usbphy0 = &usbphy1;
48 usbphy1 = &usbphy2;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu0: cpu@0 {
56 compatible = "arm,cortex-a9";
57 device_type = "cpu";
58 reg = <0>;
59 next-level-cache = <&L2>;
60 operating-points = <
61 /* kHz uV */
62 996000 1250000
63 792000 1175000
64 396000 1075000
65 >;
66 fsl,soc-operating-points = <
67 /* ARM kHz SOC uV */
68 996000 1175000
69 792000 1175000
70 396000 1175000
71 >;
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
78 clock-names = "arm", "pll2_pfd2_396m", "step",
79 "pll1_sw", "pll1_sys";
80 arm-supply = <&reg_arm>;
81 soc-supply = <&reg_soc>;
82 };
83 };
84
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
88 interrupt-controller;
89 reg = <0x00a01000 0x1000>,
90 <0x00a00100 0x100>;
91 };
92
93 clocks {
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 ckil: clock@0 {
98 compatible = "fixed-clock";
99 reg = <0>;
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock@1 {
106 compatible = "fixed-clock";
107 reg = <1>;
108 #clock-cells = <0>;
109 clock-frequency = <24000000>;
110 clock-output-names = "osc";
111 };
112
113 ipp_di0: clock@2 {
114 compatible = "fixed-clock";
115 reg = <2>;
116 #clock-cells = <0>;
117 clock-frequency = <0>;
118 clock-output-names = "ipp_di0";
119 };
120
121 ipp_di1: clock@3 {
122 compatible = "fixed-clock";
123 reg = <3>;
124 #clock-cells = <0>;
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
127 };
128 };
129
130 soc {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 compatible = "simple-bus";
134 interrupt-parent = <&intc>;
135 ranges;
136
137 pmu {
138 compatible = "arm,cortex-a9-pmu";
139 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
140 };
141
142 ocram: sram@00900000 {
143 compatible = "mmio-sram";
144 reg = <0x00900000 0x20000>;
145 clocks = <&clks IMX6SX_CLK_OCRAM>;
146 };
147
148 L2: l2-cache@00a02000 {
149 compatible = "arm,pl310-cache";
150 reg = <0x00a02000 0x1000>;
151 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
152 cache-unified;
153 cache-level = <2>;
154 arm,tag-latency = <4 2 3>;
155 arm,data-latency = <4 2 3>;
156 };
157
158 dma_apbh: dma-apbh@01804000 {
159 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
160 reg = <0x01804000 0x2000>;
161 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
165 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
166 #dma-cells = <1>;
167 dma-channels = <4>;
168 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
169 };
170
171 gpmi: gpmi-nand@01806000{
172 compatible = "fsl,imx6sx-gpmi-nand";
173 #address-cells = <1>;
174 #size-cells = <1>;
175 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
176 reg-names = "gpmi-nand", "bch";
177 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "bch";
179 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
180 <&clks IMX6SX_CLK_GPMI_APB>,
181 <&clks IMX6SX_CLK_GPMI_BCH>,
182 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
183 <&clks IMX6SX_CLK_PER1_BCH>;
184 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
185 "gpmi_bch_apb", "per1_bch";
186 dmas = <&dma_apbh 0>;
187 dma-names = "rx-tx";
188 status = "disabled";
189 };
190
191 aips1: aips-bus@02000000 {
192 compatible = "fsl,aips-bus", "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 reg = <0x02000000 0x100000>;
196 ranges;
197
198 spba-bus@02000000 {
199 compatible = "fsl,spba-bus", "simple-bus";
200 #address-cells = <1>;
201 #size-cells = <1>;
202 reg = <0x02000000 0x40000>;
203 ranges;
204
205 spdif: spdif@02004000 {
206 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
207 reg = <0x02004000 0x4000>;
208 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
209 dmas = <&sdma 14 18 0>,
210 <&sdma 15 18 0>;
211 dma-names = "rx", "tx";
212 clocks = <&clks IMX6SX_CLK_SPDIF>,
213 <&clks IMX6SX_CLK_OSC>,
214 <&clks IMX6SX_CLK_SPDIF>,
215 <&clks 0>, <&clks 0>, <&clks 0>,
216 <&clks IMX6SX_CLK_IPG>,
217 <&clks 0>, <&clks 0>,
218 <&clks IMX6SX_CLK_SPBA>;
219 clock-names = "core", "rxtx0",
220 "rxtx1", "rxtx2",
221 "rxtx3", "rxtx4",
222 "rxtx5", "rxtx6",
223 "rxtx7", "dma";
224 status = "disabled";
225 };
226
227 ecspi1: ecspi@02008000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
231 reg = <0x02008000 0x4000>;
232 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6SX_CLK_ECSPI1>,
234 <&clks IMX6SX_CLK_ECSPI1>;
235 clock-names = "ipg", "per";
236 status = "disabled";
237 };
238
239 ecspi2: ecspi@0200c000 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
243 reg = <0x0200c000 0x4000>;
244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6SX_CLK_ECSPI2>,
246 <&clks IMX6SX_CLK_ECSPI2>;
247 clock-names = "ipg", "per";
248 status = "disabled";
249 };
250
251 ecspi3: ecspi@02010000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02010000 0x4000>;
256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI3>,
258 <&clks IMX6SX_CLK_ECSPI3>;
259 clock-names = "ipg", "per";
260 status = "disabled";
261 };
262
263 ecspi4: ecspi@02014000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI4>,
270 <&clks IMX6SX_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
272 status = "disabled";
273 };
274
275 uart1: serial@02020000 {
276 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
277 reg = <0x02020000 0x4000>;
278 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6SX_CLK_UART_IPG>,
280 <&clks IMX6SX_CLK_UART_SERIAL>;
281 clock-names = "ipg", "per";
282 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
283 dma-names = "rx", "tx";
284 status = "disabled";
285 };
286
287 esai: esai@02024000 {
288 reg = <0x02024000 0x4000>;
289 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
291 <&clks IMX6SX_CLK_ESAI_MEM>,
292 <&clks IMX6SX_CLK_ESAI_EXTAL>,
293 <&clks IMX6SX_CLK_ESAI_IPG>,
294 <&clks IMX6SX_CLK_SPBA>;
295 clock-names = "core", "mem", "extal",
296 "fsys", "dma";
297 status = "disabled";
298 };
299
300 ssi1: ssi@02028000 {
Fabio Estevam4c035272014-07-07 10:04:52 -0300[diff] [blame]301 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]302 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
305 <&clks IMX6SX_CLK_SSI1>;
306 clock-names = "ipg", "baud";
307 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
308 dma-names = "rx", "tx";
Fabio Estevam3a462a62014-07-02 11:58:50 -0300[diff] [blame]309 fsl,fifo-depth = <15>;
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]310 status = "disabled";
311 };
312
313 ssi2: ssi@0202c000 {
Fabio Estevam4c035272014-07-07 10:04:52 -0300[diff] [blame]314 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]315 reg = <0x0202c000 0x4000>;
316 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
318 <&clks IMX6SX_CLK_SSI2>;
319 clock-names = "ipg", "baud";
320 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
321 dma-names = "rx", "tx";
Fabio Estevam3a462a62014-07-02 11:58:50 -0300[diff] [blame]322 fsl,fifo-depth = <15>;
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]323 status = "disabled";
324 };
325
326 ssi3: ssi@02030000 {
Fabio Estevam4c035272014-07-07 10:04:52 -0300[diff] [blame]327 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]328 reg = <0x02030000 0x4000>;
329 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
331 <&clks IMX6SX_CLK_SSI3>;
332 clock-names = "ipg", "baud";
333 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
334 dma-names = "rx", "tx";
Fabio Estevam3a462a62014-07-02 11:58:50 -0300[diff] [blame]335 fsl,fifo-depth = <15>;
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]336 status = "disabled";
337 };
338
339 asrc: asrc@02034000 {
340 reg = <0x02034000 0x4000>;
341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
343 <&clks IMX6SX_CLK_ASRC_IPG>,
344 <&clks IMX6SX_CLK_SPDIF>,
345 <&clks IMX6SX_CLK_SPBA>;
346 clock-names = "mem", "ipg", "asrck", "dma";
347 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
348 <&sdma 19 20 1>, <&sdma 20 20 1>,
349 <&sdma 21 20 1>, <&sdma 22 20 1>;
350 dma-names = "rxa", "rxb", "rxc",
351 "txa", "txb", "txc";
352 status = "okay";
353 };
354 };
355
356 pwm1: pwm@02080000 {
357 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
358 reg = <0x02080000 0x4000>;
359 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks IMX6SX_CLK_PWM1>,
361 <&clks IMX6SX_CLK_PWM1>;
362 clock-names = "ipg", "per";
363 #pwm-cells = <2>;
364 };
365
366 pwm2: pwm@02084000 {
367 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
368 reg = <0x02084000 0x4000>;
369 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6SX_CLK_PWM2>,
371 <&clks IMX6SX_CLK_PWM2>;
372 clock-names = "ipg", "per";
373 #pwm-cells = <2>;
374 };
375
376 pwm3: pwm@02088000 {
377 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
378 reg = <0x02088000 0x4000>;
379 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6SX_CLK_PWM3>,
381 <&clks IMX6SX_CLK_PWM3>;
382 clock-names = "ipg", "per";
383 #pwm-cells = <2>;
384 };
385
386 pwm4: pwm@0208c000 {
387 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
388 reg = <0x0208c000 0x4000>;
389 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6SX_CLK_PWM4>,
391 <&clks IMX6SX_CLK_PWM4>;
392 clock-names = "ipg", "per";
393 #pwm-cells = <2>;
394 };
395
396 flexcan1: can@02090000 {
397 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
398 reg = <0x02090000 0x4000>;
399 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
401 <&clks IMX6SX_CLK_CAN1_SERIAL>;
402 clock-names = "ipg", "per";
403 status = "disabled";
404 };
405
406 flexcan2: can@02094000 {
407 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
408 reg = <0x02094000 0x4000>;
409 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
411 <&clks IMX6SX_CLK_CAN2_SERIAL>;
412 clock-names = "ipg", "per";
413 status = "disabled";
414 };
415
416 gpt: gpt@02098000 {
417 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
418 reg = <0x02098000 0x4000>;
419 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
421 <&clks IMX6SX_CLK_GPT_SERIAL>;
422 clock-names = "ipg", "per";
423 };
424
425 gpio1: gpio@0209c000 {
426 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
427 reg = <0x0209c000 0x4000>;
428 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
430 gpio-controller;
431 #gpio-cells = <2>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
435
436 gpio2: gpio@020a0000 {
437 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
438 reg = <0x020a0000 0x4000>;
439 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
441 gpio-controller;
442 #gpio-cells = <2>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 };
446
447 gpio3: gpio@020a4000 {
448 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
449 reg = <0x020a4000 0x4000>;
450 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
452 gpio-controller;
453 #gpio-cells = <2>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 };
457
458 gpio4: gpio@020a8000 {
459 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
460 reg = <0x020a8000 0x4000>;
461 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
467 };
468
469 gpio5: gpio@020ac000 {
470 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
471 reg = <0x020ac000 0x4000>;
472 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
474 gpio-controller;
475 #gpio-cells = <2>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 };
479
480 gpio6: gpio@020b0000 {
481 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
482 reg = <0x020b0000 0x4000>;
483 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
485 gpio-controller;
486 #gpio-cells = <2>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 };
490
491 gpio7: gpio@020b4000 {
492 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
493 reg = <0x020b4000 0x4000>;
494 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
496 gpio-controller;
497 #gpio-cells = <2>;
498 interrupt-controller;
499 #interrupt-cells = <2>;
500 };
501
502 kpp: kpp@020b8000 {
503 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
504 reg = <0x020b8000 0x4000>;
505 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6SX_CLK_DUMMY>;
507 status = "disabled";
508 };
509
510 wdog1: wdog@020bc000 {
511 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
512 reg = <0x020bc000 0x4000>;
513 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clks IMX6SX_CLK_DUMMY>;
515 };
516
517 wdog2: wdog@020c0000 {
518 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
519 reg = <0x020c0000 0x4000>;
520 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&clks IMX6SX_CLK_DUMMY>;
522 status = "disabled";
523 };
524
525 clks: ccm@020c4000 {
526 compatible = "fsl,imx6sx-ccm";
527 reg = <0x020c4000 0x4000>;
528 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
530 #clock-cells = <1>;
531 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
532 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
533 };
534
535 anatop: anatop@020c8000 {
536 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
537 "syscon", "simple-bus";
538 reg = <0x020c8000 0x1000>;
539 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
542
543 regulator-1p1@110 {
544 compatible = "fsl,anatop-regulator";
545 regulator-name = "vdd1p1";
546 regulator-min-microvolt = <800000>;
547 regulator-max-microvolt = <1375000>;
548 regulator-always-on;
549 anatop-reg-offset = <0x110>;
550 anatop-vol-bit-shift = <8>;
551 anatop-vol-bit-width = <5>;
552 anatop-min-bit-val = <4>;
553 anatop-min-voltage = <800000>;
554 anatop-max-voltage = <1375000>;
555 };
556
557 regulator-3p0@120 {
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vdd3p0";
560 regulator-min-microvolt = <2800000>;
561 regulator-max-microvolt = <3150000>;
562 regulator-always-on;
563 anatop-reg-offset = <0x120>;
564 anatop-vol-bit-shift = <8>;
565 anatop-vol-bit-width = <5>;
566 anatop-min-bit-val = <0>;
567 anatop-min-voltage = <2625000>;
568 anatop-max-voltage = <3400000>;
569 };
570
571 regulator-2p5@130 {
572 compatible = "fsl,anatop-regulator";
573 regulator-name = "vdd2p5";
574 regulator-min-microvolt = <2100000>;
575 regulator-max-microvolt = <2875000>;
576 regulator-always-on;
577 anatop-reg-offset = <0x130>;
578 anatop-vol-bit-shift = <8>;
579 anatop-vol-bit-width = <5>;
580 anatop-min-bit-val = <0>;
581 anatop-min-voltage = <2100000>;
582 anatop-max-voltage = <2875000>;
583 };
584
585 reg_arm: regulator-vddcore@140 {
586 compatible = "fsl,anatop-regulator";
Fabio Estevamf78a5972014-06-17 01:07:35 -0300[diff] [blame]587 regulator-name = "vddarm";
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]588 regulator-min-microvolt = <725000>;
589 regulator-max-microvolt = <1450000>;
590 regulator-always-on;
591 anatop-reg-offset = <0x140>;
592 anatop-vol-bit-shift = <0>;
593 anatop-vol-bit-width = <5>;
594 anatop-delay-reg-offset = <0x170>;
595 anatop-delay-bit-shift = <24>;
596 anatop-delay-bit-width = <2>;
597 anatop-min-bit-val = <1>;
598 anatop-min-voltage = <725000>;
599 anatop-max-voltage = <1450000>;
600 };
601
602 reg_pcie: regulator-vddpcie@140 {
603 compatible = "fsl,anatop-regulator";
604 regulator-name = "vddpcie";
605 regulator-min-microvolt = <725000>;
606 regulator-max-microvolt = <1450000>;
607 anatop-reg-offset = <0x140>;
608 anatop-vol-bit-shift = <9>;
609 anatop-vol-bit-width = <5>;
610 anatop-delay-reg-offset = <0x170>;
611 anatop-delay-bit-shift = <26>;
612 anatop-delay-bit-width = <2>;
613 anatop-min-bit-val = <1>;
614 anatop-min-voltage = <725000>;
615 anatop-max-voltage = <1450000>;
616 };
617
618 reg_soc: regulator-vddsoc@140 {
619 compatible = "fsl,anatop-regulator";
620 regulator-name = "vddsoc";
621 regulator-min-microvolt = <725000>;
622 regulator-max-microvolt = <1450000>;
623 regulator-always-on;
624 anatop-reg-offset = <0x140>;
625 anatop-vol-bit-shift = <18>;
626 anatop-vol-bit-width = <5>;
627 anatop-delay-reg-offset = <0x170>;
628 anatop-delay-bit-shift = <28>;
629 anatop-delay-bit-width = <2>;
630 anatop-min-bit-val = <1>;
631 anatop-min-voltage = <725000>;
632 anatop-max-voltage = <1450000>;
633 };
634 };
635
636 tempmon: tempmon {
637 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
638 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
639 fsl,tempmon = <&anatop>;
640 fsl,tempmon-data = <&ocotp>;
641 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
642 };
643
644 usbphy1: usbphy@020c9000 {
645 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
646 reg = <0x020c9000 0x1000>;
647 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clks IMX6SX_CLK_USBPHY1>;
649 fsl,anatop = <&anatop>;
650 };
651
652 usbphy2: usbphy@020ca000 {
653 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
654 reg = <0x020ca000 0x1000>;
655 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&clks IMX6SX_CLK_USBPHY2>;
657 fsl,anatop = <&anatop>;
658 };
659
660 snvs: snvs@020cc000 {
661 compatible = "fsl,sec-v4.0-mon", "simple-bus";
662 #address-cells = <1>;
663 #size-cells = <1>;
664 ranges = <0 0x020cc000 0x4000>;
665
666 snvs-rtc-lp@34 {
667 compatible = "fsl,sec-v4.0-mon-rtc-lp";
668 reg = <0x34 0x58>;
669 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
670 };
671 };
672
673 epit1: epit@020d0000 {
674 reg = <0x020d0000 0x4000>;
675 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
676 };
677
678 epit2: epit@020d4000 {
679 reg = <0x020d4000 0x4000>;
680 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
681 };
682
683 src: src@020d8000 {
684 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
685 reg = <0x020d8000 0x4000>;
686 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
688 #reset-cells = <1>;
689 };
690
691 gpc: gpc@020dc000 {
692 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
693 reg = <0x020dc000 0x4000>;
694 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
695 };
696
697 iomuxc: iomuxc@020e0000 {
698 compatible = "fsl,imx6sx-iomuxc";
699 reg = <0x020e0000 0x4000>;
700 };
701
702 gpr: iomuxc-gpr@020e4000 {
Anson Huang77e0d1c2014-06-23 14:04:01 +0800[diff] [blame]703 compatible = "fsl,imx6sx-iomuxc-gpr",
704 "fsl,imx6q-iomuxc-gpr", "syscon";
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]705 reg = <0x020e4000 0x4000>;
706 };
707
708 sdma: sdma@020ec000 {
Shawn Guo811e76852014-07-04 14:30:27 +0800[diff] [blame]709 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]710 reg = <0x020ec000 0x4000>;
711 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clks IMX6SX_CLK_SDMA>,
713 <&clks IMX6SX_CLK_SDMA>;
714 clock-names = "ipg", "ahb";
715 #dma-cells = <3>;
Fabio Estevamaeb88532014-07-02 11:58:49 -0300[diff] [blame]716 /* imx6sx reuses imx6q sdma firmware */
717 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]718 };
719 };
720
721 aips2: aips-bus@02100000 {
722 compatible = "fsl,aips-bus", "simple-bus";
723 #address-cells = <1>;
724 #size-cells = <1>;
725 reg = <0x02100000 0x100000>;
726 ranges;
727
728 usbotg1: usb@02184000 {
729 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
730 reg = <0x02184000 0x200>;
731 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clks IMX6SX_CLK_USBOH3>;
733 fsl,usbphy = <&usbphy1>;
734 fsl,usbmisc = <&usbmisc 0>;
735 fsl,anatop = <&anatop>;
736 status = "disabled";
737 };
738
739 usbotg2: usb@02184200 {
740 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
741 reg = <0x02184200 0x200>;
742 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clks IMX6SX_CLK_USBOH3>;
744 fsl,usbphy = <&usbphy2>;
745 fsl,usbmisc = <&usbmisc 1>;
746 status = "disabled";
747 };
748
749 usbh: usb@02184400 {
750 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
751 reg = <0x02184400 0x200>;
752 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clks IMX6SX_CLK_USBOH3>;
754 fsl,usbmisc = <&usbmisc 2>;
755 phy_type = "hsic";
756 fsl,anatop = <&anatop>;
757 status = "disabled";
758 };
759
760 usbmisc: usbmisc@02184800 {
761 #index-cells = <1>;
Fabio Estevamb29f4fa2014-06-23 11:21:04 -0300[diff] [blame]762 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
Shawn Guob1d17f62014-05-13 20:21:35 +0800[diff] [blame]763 reg = <0x02184800 0x200>;
764 clocks = <&clks IMX6SX_CLK_USBOH3>;
765 };
766
767 fec1: ethernet@02188000 {
768 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
769 reg = <0x02188000 0x4000>;
770 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&clks IMX6SX_CLK_ENET>,
773 <&clks IMX6SX_CLK_ENET_AHB>,
774 <&clks IMX6SX_CLK_ENET_PTP>,
775 <&clks IMX6SX_CLK_ENET_REF>,
776 <&clks IMX6SX_CLK_ENET_PTP>;
777 clock-names = "ipg", "ahb", "ptp",
778 "enet_clk_ref", "enet_out";
779 status = "disabled";
780 };
781
782 mlb: mlb@0218c000 {
783 reg = <0x0218c000 0x4000>;
784 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clks IMX6SX_CLK_MLB>;
788 status = "disabled";
789 };
790
791 usdhc1: usdhc@02190000 {
792 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
793 reg = <0x02190000 0x4000>;
794 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clks IMX6SX_CLK_USDHC1>,
796 <&clks IMX6SX_CLK_USDHC1>,
797 <&clks IMX6SX_CLK_USDHC1>;
798 clock-names = "ipg", "ahb", "per";
799 bus-width = <4>;
800 status = "disabled";
801 };
802
803 usdhc2: usdhc@02194000 {
804 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
805 reg = <0x02194000 0x4000>;
806 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clks IMX6SX_CLK_USDHC2>,
808 <&clks IMX6SX_CLK_USDHC2>,
809 <&clks IMX6SX_CLK_USDHC2>;
810 clock-names = "ipg", "ahb", "per";
811 bus-width = <4>;
812 status = "disabled";
813 };
814
815 usdhc3: usdhc@02198000 {
816 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
817 reg = <0x02198000 0x4000>;
818 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6SX_CLK_USDHC3>,
820 <&clks IMX6SX_CLK_USDHC3>,
821 <&clks IMX6SX_CLK_USDHC3>;
822 clock-names = "ipg", "ahb", "per";
823 bus-width = <4>;
824 status = "disabled";
825 };
826
827 usdhc4: usdhc@0219c000 {
828 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
829 reg = <0x0219c000 0x4000>;
830 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&clks IMX6SX_CLK_USDHC4>,
832 <&clks IMX6SX_CLK_USDHC4>,
833 <&clks IMX6SX_CLK_USDHC4>;
834 clock-names = "ipg", "ahb", "per";
835 bus-width = <4>;
836 status = "disabled";
837 };
838
839 i2c1: i2c@021a0000 {
840 #address-cells = <1>;
841 #size-cells = <0>;
842 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
843 reg = <0x021a0000 0x4000>;
844 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&clks IMX6SX_CLK_I2C1>;
846 status = "disabled";
847 };
848
849 i2c2: i2c@021a4000 {
850 #address-cells = <1>;
851 #size-cells = <0>;
852 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
853 reg = <0x021a4000 0x4000>;
854 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX6SX_CLK_I2C2>;
856 status = "disabled";
857 };
858
859 i2c3: i2c@021a8000 {
860 #address-cells = <1>;
861 #size-cells = <0>;
862 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
863 reg = <0x021a8000 0x4000>;
864 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX6SX_CLK_I2C3>;
866 status = "disabled";
867 };
868
869 mmdc: mmdc@021b0000 {
870 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
871 reg = <0x021b0000 0x4000>;
872 };
873
874 fec2: ethernet@021b4000 {
875 compatible = "fsl,imx6sx-fec";
876 reg = <0x021b4000 0x4000>;
877 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX6SX_CLK_ENET>,
880 <&clks IMX6SX_CLK_ENET_AHB>,
881 <&clks IMX6SX_CLK_ENET_PTP>,
882 <&clks IMX6SX_CLK_ENET2_REF_125M>,
883 <&clks IMX6SX_CLK_ENET_PTP>;
884 clock-names = "ipg", "ahb", "ptp",
885 "enet_clk_ref", "enet_out";
886 status = "disabled";
887 };
888
889 weim: weim@021b8000 {
890 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
891 reg = <0x021b8000 0x4000>;
892 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
894 };
895
896 ocotp: ocotp@021bc000 {
897 compatible = "fsl,imx6sx-ocotp", "syscon";
898 reg = <0x021bc000 0x4000>;
899 clocks = <&clks IMX6SX_CLK_OCOTP>;
900 };
901
902 sai1: sai@021d4000 {
903 compatible = "fsl,imx6sx-sai";
904 reg = <0x021d4000 0x4000>;
905 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
907 <&clks IMX6SX_CLK_SAI1>,
908 <&clks 0>, <&clks 0>;
909 clock-names = "bus", "mclk1", "mclk2", "mclk3";
910 dma-names = "rx", "tx";
911 dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
912 dma-source = <&gpr 0 15 0 16>;
913 status = "disabled";
914 };
915
916 audmux: audmux@021d8000 {
917 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
918 reg = <0x021d8000 0x4000>;
919 status = "disabled";
920 };
921
922 sai2: sai@021dc000 {
923 compatible = "fsl,imx6sx-sai";
924 reg = <0x021dc000 0x4000>;
925 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
927 <&clks IMX6SX_CLK_SAI2>,
928 <&clks 0>, <&clks 0>;
929 clock-names = "bus", "mclk1", "mclk2", "mclk3";
930 dma-names = "rx", "tx";
931 dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
932 dma-source = <&gpr 0 17 0 18>;
933 status = "disabled";
934 };
935
936 qspi1: qspi@021e0000 {
937 #address-cells = <1>;
938 #size-cells = <0>;
939 compatible = "fsl,imx6sx-qspi";
940 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
941 reg-names = "QuadSPI", "QuadSPI-memory";
942 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clks IMX6SX_CLK_QSPI1>,
944 <&clks IMX6SX_CLK_QSPI1>;
945 clock-names = "qspi_en", "qspi";
946 status = "disabled";
947 };
948
949 qspi2: qspi@021e4000 {
950 #address-cells = <1>;
951 #size-cells = <0>;
952 compatible = "fsl,imx6sx-qspi";
953 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
954 reg-names = "QuadSPI", "QuadSPI-memory";
955 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clks IMX6SX_CLK_QSPI2>,
957 <&clks IMX6SX_CLK_QSPI2>;
958 clock-names = "qspi_en", "qspi";
959 status = "disabled";
960 };
961
962 uart2: serial@021e8000 {
963 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
964 reg = <0x021e8000 0x4000>;
965 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&clks IMX6SX_CLK_UART_IPG>,
967 <&clks IMX6SX_CLK_UART_SERIAL>;
968 clock-names = "ipg", "per";
969 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
970 dma-names = "rx", "tx";
971 status = "disabled";
972 };
973
974 uart3: serial@021ec000 {
975 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
976 reg = <0x021ec000 0x4000>;
977 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clks IMX6SX_CLK_UART_IPG>,
979 <&clks IMX6SX_CLK_UART_SERIAL>;
980 clock-names = "ipg", "per";
981 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
982 dma-names = "rx", "tx";
983 status = "disabled";
984 };
985
986 uart4: serial@021f0000 {
987 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
988 reg = <0x021f0000 0x4000>;
989 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&clks IMX6SX_CLK_UART_IPG>,
991 <&clks IMX6SX_CLK_UART_SERIAL>;
992 clock-names = "ipg", "per";
993 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
994 dma-names = "rx", "tx";
995 status = "disabled";
996 };
997
998 uart5: serial@021f4000 {
999 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1000 reg = <0x021f4000 0x4000>;
1001 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1003 <&clks IMX6SX_CLK_UART_SERIAL>;
1004 clock-names = "ipg", "per";
1005 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1006 dma-names = "rx", "tx";
1007 status = "disabled";
1008 };
1009
1010 i2c4: i2c@021f8000 {
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1014 reg = <0x021f8000 0x4000>;
1015 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&clks IMX6SX_CLK_I2C4>;
1017 status = "disabled";
1018 };
1019 };
1020
1021 aips3: aips-bus@02200000 {
1022 compatible = "fsl,aips-bus", "simple-bus";
1023 #address-cells = <1>;
1024 #size-cells = <1>;
1025 reg = <0x02200000 0x100000>;
1026 ranges;
1027
1028 spba-bus@02200000 {
1029 compatible = "fsl,spba-bus", "simple-bus";
1030 #address-cells = <1>;
1031 #size-cells = <1>;
1032 reg = <0x02240000 0x40000>;
1033 ranges;
1034
1035 csi1: csi@02214000 {
1036 reg = <0x02214000 0x4000>;
1037 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1039 <&clks IMX6SX_CLK_CSI>,
1040 <&clks IMX6SX_CLK_DCIC1>;
1041 clock-names = "disp-axi", "csi_mclk", "dcic";
1042 status = "disabled";
1043 };
1044
1045 pxp: pxp@02218000 {
1046 reg = <0x02218000 0x4000>;
1047 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1049 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1050 clock-names = "pxp-axi", "disp-axi";
1051 status = "disabled";
1052 };
1053
1054 csi2: csi@0221c000 {
1055 reg = <0x0221c000 0x4000>;
1056 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1058 <&clks IMX6SX_CLK_CSI>,
1059 <&clks IMX6SX_CLK_DCIC2>;
1060 clock-names = "disp-axi", "csi_mclk", "dcic";
1061 status = "disabled";
1062 };
1063
1064 lcdif1: lcdif@02220000 {
1065 reg = <0x02220000 0x4000>;
1066 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1068 <&clks IMX6SX_CLK_LCDIF_APB>,
1069 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1070 clock-names = "pix", "axi", "disp_axi";
1071 status = "disabled";
1072 };
1073
1074 lcdif2: lcdif@02224000 {
1075 reg = <0x02224000 0x4000>;
1076 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1078 <&clks IMX6SX_CLK_LCDIF_APB>,
1079 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1080 clock-names = "pix", "axi", "disp_axi";
1081 status = "disabled";
1082 };
1083
1084 vadc: vadc@02228000 {
1085 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1086 reg-names = "vadc-vafe", "vadc-vdec";
1087 clocks = <&clks IMX6SX_CLK_VADC>,
1088 <&clks IMX6SX_CLK_CSI>;
1089 clock-names = "vadc", "csi";
1090 status = "disabled";
1091 };
1092 };
1093
1094 adc1: adc@02280000 {
1095 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1096 reg = <0x02280000 0x4000>;
1097 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&clks IMX6SX_CLK_IPG>;
1099 clock-names = "adc";
1100 status = "disabled";
1101 };
1102
1103 adc2: adc@02284000 {
1104 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1105 reg = <0x02284000 0x4000>;
1106 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&clks IMX6SX_CLK_IPG>;
1108 clock-names = "adc";
1109 status = "disabled";
1110 };
1111
1112 wdog3: wdog@02288000 {
1113 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1114 reg = <0x02288000 0x4000>;
1115 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&clks IMX6SX_CLK_DUMMY>;
1117 status = "disabled";
1118 };
1119
1120 ecspi5: ecspi@0228c000 {
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1124 reg = <0x0228c000 0x4000>;
1125 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1127 <&clks IMX6SX_CLK_ECSPI5>;
1128 clock-names = "ipg", "per";
1129 status = "disabled";
1130 };
1131
1132 uart6: serial@022a0000 {
1133 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1134 reg = <0x022a0000 0x4000>;
1135 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1137 <&clks IMX6SX_CLK_UART_SERIAL>;
1138 clock-names = "ipg", "per";
1139 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1140 dma-names = "rx", "tx";
1141 status = "disabled";
1142 };
1143
1144 pwm5: pwm@022a4000 {
1145 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1146 reg = <0x022a4000 0x4000>;
1147 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&clks IMX6SX_CLK_PWM5>,
1149 <&clks IMX6SX_CLK_PWM5>;
1150 clock-names = "ipg", "per";
1151 #pwm-cells = <2>;
1152 };
1153
1154 pwm6: pwm@022a8000 {
1155 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1156 reg = <0x022a8000 0x4000>;
1157 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1158 clocks = <&clks IMX6SX_CLK_PWM6>,
1159 <&clks IMX6SX_CLK_PWM6>;
1160 clock-names = "ipg", "per";
1161 #pwm-cells = <2>;
1162 };
1163
1164 pwm7: pwm@022ac000 {
1165 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1166 reg = <0x022ac000 0x4000>;
1167 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&clks IMX6SX_CLK_PWM7>,
1169 <&clks IMX6SX_CLK_PWM7>;
1170 clock-names = "ipg", "per";
1171 #pwm-cells = <2>;
1172 };
1173
1174 pwm8: pwm@0022b0000 {
1175 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1176 reg = <0x0022b0000 0x4000>;
1177 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&clks IMX6SX_CLK_PWM8>,
1179 <&clks IMX6SX_CLK_PWM8>;
1180 clock-names = "ipg", "per";
1181 #pwm-cells = <2>;
1182 };
1183 };
1184
1185 pcie: pcie@0x08000000 {
1186 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1187 reg = <0x08ffc000 0x4000>; /* DBI */
1188 #address-cells = <3>;
1189 #size-cells = <2>;
1190 device_type = "pci";
1191 /* configuration space */
1192 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1193 /* downstream I/O */
1194 0x81000000 0 0 0x08f80000 0 0x00010000
1195 /* non-prefetchable memory */
1196 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1197 num-lanes = <1>;
1198 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1200 <&clks IMX6SX_CLK_PCIE_AXI>,
1201 <&clks IMX6SX_CLK_LVDS1_OUT>,
1202 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1203 clock-names = "pcie_ref_125m", "pcie_axi",
1204 "lvds_gate", "display_axi";
1205 status = "disabled";
1206 };
1207 };
1208};