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Catalin Marinas9cce7a42012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/include/asm/processor.h
3 *
4 * Copyright (C) 1995-1999 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASM_PROCESSOR_H
20#define __ASM_PROCESSOR_H
21
22/*
23 * Default implementation of macro that returns current
24 * instruction pointer ("program counter").
25 */
26#define current_text_addr() ({ __label__ _l; _l: &&_l;})
27
28#ifdef __KERNEL__
29
30#include <linux/string.h>
31
32#include <asm/fpsimd.h>
33#include <asm/hw_breakpoint.h>
Paul Walmsley2ec45602015-01-05 17:38:41 -070034#include <asm/pgtable-hwdef.h>
Catalin Marinas9cce7a42012-03-05 11:49:28 +000035#include <asm/ptrace.h>
36#include <asm/types.h>
37
38#ifdef __KERNEL__
39#define STACK_TOP_MAX TASK_SIZE_64
40#ifdef CONFIG_COMPAT
41#define AARCH32_VECTORS_BASE 0xffff0000
42#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
43 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
44#else
45#define STACK_TOP STACK_TOP_MAX
46#endif /* CONFIG_COMPAT */
Will Deaconf483a852012-11-08 16:00:16 +000047
48#define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK
Catalin Marinas9cce7a42012-03-05 11:49:28 +000049#endif /* __KERNEL__ */
50
51struct debug_info {
52 /* Have we suspended stepping by a debugger? */
53 int suspended_step;
54 /* Allow breakpoints and watchpoints to be disabled for this thread. */
55 int bps_disabled;
56 int wps_disabled;
57 /* Hardware breakpoints pinned to this task. */
58 struct perf_event *hbp_break[ARM_MAX_BRP];
59 struct perf_event *hbp_watch[ARM_MAX_WRP];
60};
61
62struct cpu_context {
63 unsigned long x19;
64 unsigned long x20;
65 unsigned long x21;
66 unsigned long x22;
67 unsigned long x23;
68 unsigned long x24;
69 unsigned long x25;
70 unsigned long x26;
71 unsigned long x27;
72 unsigned long x28;
73 unsigned long fp;
74 unsigned long sp;
75 unsigned long pc;
76};
77
78struct thread_struct {
79 struct cpu_context cpu_context; /* cpu context */
80 unsigned long tp_value;
81 struct fpsimd_state fpsimd_state;
82 unsigned long fault_address; /* fault info */
Catalin Marinas91413002014-04-06 23:04:12 +010083 unsigned long fault_code; /* ESR_EL1 value */
Catalin Marinas9cce7a42012-03-05 11:49:28 +000084 struct debug_info debug; /* debugging */
85};
86
87#define INIT_THREAD { }
88
89static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
90{
91 memset(regs, 0, sizeof(*regs));
92 regs->syscallno = ~0UL;
93 regs->pc = pc;
94}
95
96static inline void start_thread(struct pt_regs *regs, unsigned long pc,
97 unsigned long sp)
98{
Catalin Marinas9cce7a42012-03-05 11:49:28 +000099 start_thread_common(regs, pc);
100 regs->pstate = PSR_MODE_EL0t;
101 regs->sp = sp;
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000102}
103
104#ifdef CONFIG_COMPAT
105static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
106 unsigned long sp)
107{
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000108 start_thread_common(regs, pc);
109 regs->pstate = COMPAT_PSR_MODE_USR;
110 if (pc & 1)
111 regs->pstate |= COMPAT_PSR_T_BIT;
Will Deacona795a382013-10-11 14:52:12 +0100112
113#ifdef __AARCH64EB__
114 regs->pstate |= COMPAT_PSR_E_BIT;
115#endif
116
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000117 regs->compat_sp = sp;
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000118}
119#endif
120
121/* Forward declaration, a strange C thing */
122struct task_struct;
123
124/* Free all resources held by a thread. */
125extern void release_thread(struct task_struct *);
126
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000127unsigned long get_wchan(struct task_struct *p);
128
129#define cpu_relax() barrier()
Davidlohr Bueso3a6bfbc2014-06-29 15:09:33 -0700130#define cpu_relax_lowlatency() cpu_relax()
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000131
132/* Thread switching */
133extern struct task_struct *cpu_switch_to(struct task_struct *prev,
134 struct task_struct *next);
135
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000136#define task_pt_regs(p) \
137 ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
138
Catalin Marinasebe61522014-07-10 11:37:40 +0100139#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
Will Deacon3168a742014-08-29 16:11:10 +0100140#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000141
142/*
143 * Prefetching support
144 */
145#define ARCH_HAS_PREFETCH
146static inline void prefetch(const void *ptr)
147{
148 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
149}
150
151#define ARCH_HAS_PREFETCHW
152static inline void prefetchw(const void *ptr)
153{
154 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
155}
156
157#define ARCH_HAS_SPINLOCK_PREFETCH
158static inline void spin_lock_prefetch(const void *x)
159{
160 prefetchw(x);
161}
162
163#define HAVE_ARCH_PICK_MMAP_LAYOUT
164
165#endif
166
167#endif /* __ASM_PROCESSOR_H */