Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/io.h> |
| 14 | #include <linux/errno.h> |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 15 | #include <linux/delay.h> |
| 16 | #include <linux/mutex.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/types.h> |
Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 19 | #include <linux/qcom_scm.h> |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 20 | #include <linux/arm-smccc.h> |
| 21 | #include <linux/dma-mapping.h> |
| 22 | |
| 23 | #include "qcom_scm.h" |
| 24 | |
| 25 | #define QCOM_SCM_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) |
| 26 | |
| 27 | #define MAX_QCOM_SCM_ARGS 10 |
| 28 | #define MAX_QCOM_SCM_RETS 3 |
| 29 | |
Bjorn Andersson | f01e90f | 2015-09-23 12:56:12 -0700 | [diff] [blame] | 30 | enum qcom_scm_arg_types { |
| 31 | QCOM_SCM_VAL, |
| 32 | QCOM_SCM_RO, |
| 33 | QCOM_SCM_RW, |
| 34 | QCOM_SCM_BUFVAL, |
| 35 | }; |
| 36 | |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 37 | #define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\ |
| 38 | (((a) & 0x3) << 4) | \ |
| 39 | (((b) & 0x3) << 6) | \ |
| 40 | (((c) & 0x3) << 8) | \ |
| 41 | (((d) & 0x3) << 10) | \ |
| 42 | (((e) & 0x3) << 12) | \ |
| 43 | (((f) & 0x3) << 14) | \ |
| 44 | (((g) & 0x3) << 16) | \ |
| 45 | (((h) & 0x3) << 18) | \ |
| 46 | (((i) & 0x3) << 20) | \ |
| 47 | (((j) & 0x3) << 22) | \ |
| 48 | ((num) & 0xf)) |
| 49 | |
| 50 | #define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) |
| 51 | |
| 52 | /** |
| 53 | * struct qcom_scm_desc |
| 54 | * @arginfo: Metadata describing the arguments in args[] |
| 55 | * @args: The array of arguments for the secure syscall |
| 56 | * @res: The values returned by the secure syscall |
| 57 | */ |
| 58 | struct qcom_scm_desc { |
| 59 | u32 arginfo; |
| 60 | u64 args[MAX_QCOM_SCM_ARGS]; |
| 61 | }; |
| 62 | |
| 63 | static u64 qcom_smccc_convention = -1; |
| 64 | static DEFINE_MUTEX(qcom_scm_lock); |
| 65 | |
| 66 | #define QCOM_SCM_EBUSY_WAIT_MS 30 |
| 67 | #define QCOM_SCM_EBUSY_MAX_RETRY 20 |
| 68 | |
| 69 | #define N_EXT_QCOM_SCM_ARGS 7 |
| 70 | #define FIRST_EXT_ARG_IDX 3 |
| 71 | #define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1) |
| 72 | |
| 73 | /** |
| 74 | * qcom_scm_call() - Invoke a syscall in the secure world |
| 75 | * @dev: device |
| 76 | * @svc_id: service identifier |
| 77 | * @cmd_id: command identifier |
| 78 | * @desc: Descriptor structure containing arguments and return values |
| 79 | * |
| 80 | * Sends a command to the SCM and waits for the command to finish processing. |
| 81 | * This should *only* be called in pre-emptible context. |
| 82 | */ |
| 83 | static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, |
| 84 | const struct qcom_scm_desc *desc, |
| 85 | struct arm_smccc_res *res) |
| 86 | { |
| 87 | int arglen = desc->arginfo & 0xf; |
| 88 | int retry_count = 0, i; |
| 89 | u32 fn_id = QCOM_SCM_FNID(svc_id, cmd_id); |
| 90 | u64 cmd, x5 = desc->args[FIRST_EXT_ARG_IDX]; |
| 91 | dma_addr_t args_phys = 0; |
| 92 | void *args_virt = NULL; |
| 93 | size_t alloc_len; |
| 94 | |
| 95 | if (unlikely(arglen > N_REGISTER_ARGS)) { |
| 96 | alloc_len = N_EXT_QCOM_SCM_ARGS * sizeof(u64); |
| 97 | args_virt = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL); |
| 98 | |
| 99 | if (!args_virt) |
| 100 | return -ENOMEM; |
| 101 | |
| 102 | if (qcom_smccc_convention == ARM_SMCCC_SMC_32) { |
| 103 | __le32 *args = args_virt; |
| 104 | |
| 105 | for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++) |
| 106 | args[i] = cpu_to_le32(desc->args[i + |
| 107 | FIRST_EXT_ARG_IDX]); |
| 108 | } else { |
| 109 | __le64 *args = args_virt; |
| 110 | |
| 111 | for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++) |
| 112 | args[i] = cpu_to_le64(desc->args[i + |
| 113 | FIRST_EXT_ARG_IDX]); |
| 114 | } |
| 115 | |
| 116 | args_phys = dma_map_single(dev, args_virt, alloc_len, |
| 117 | DMA_TO_DEVICE); |
| 118 | |
| 119 | if (dma_mapping_error(dev, args_phys)) { |
| 120 | kfree(args_virt); |
| 121 | return -ENOMEM; |
| 122 | } |
| 123 | |
| 124 | x5 = args_phys; |
| 125 | } |
| 126 | |
| 127 | do { |
| 128 | mutex_lock(&qcom_scm_lock); |
| 129 | |
| 130 | cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, |
| 131 | qcom_smccc_convention, |
| 132 | ARM_SMCCC_OWNER_SIP, fn_id); |
| 133 | |
| 134 | do { |
| 135 | arm_smccc_smc(cmd, desc->arginfo, desc->args[0], |
| 136 | desc->args[1], desc->args[2], x5, 0, 0, |
| 137 | res); |
| 138 | } while (res->a0 == QCOM_SCM_INTERRUPTED); |
| 139 | |
| 140 | mutex_unlock(&qcom_scm_lock); |
| 141 | |
| 142 | if (res->a0 == QCOM_SCM_V2_EBUSY) { |
| 143 | if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) |
| 144 | break; |
| 145 | msleep(QCOM_SCM_EBUSY_WAIT_MS); |
| 146 | } |
| 147 | } while (res->a0 == QCOM_SCM_V2_EBUSY); |
| 148 | |
| 149 | if (args_virt) { |
| 150 | dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE); |
| 151 | kfree(args_virt); |
| 152 | } |
| 153 | |
| 154 | if (res->a0 < 0) |
| 155 | return qcom_scm_remap_error(res->a0); |
| 156 | |
| 157 | return 0; |
| 158 | } |
Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 159 | |
| 160 | /** |
| 161 | * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus |
| 162 | * @entry: Entry point function for the cpus |
| 163 | * @cpus: The cpumask of cpus that will use the entry point |
| 164 | * |
| 165 | * Set the cold boot address of the cpus. Any cpu outside the supported |
| 166 | * range would be removed from the cpu present mask. |
| 167 | */ |
| 168 | int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) |
| 169 | { |
| 170 | return -ENOTSUPP; |
| 171 | } |
| 172 | |
| 173 | /** |
| 174 | * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 175 | * @dev: Device pointer |
Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 176 | * @entry: Entry point function for the cpus |
| 177 | * @cpus: The cpumask of cpus that will use the entry point |
| 178 | * |
| 179 | * Set the Linux entry point for the SCM to transfer control to when coming |
| 180 | * out of a power down. CPU power down may be executed on cpuidle or hotplug. |
| 181 | */ |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 182 | int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, |
| 183 | const cpumask_t *cpus) |
Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 184 | { |
| 185 | return -ENOTSUPP; |
| 186 | } |
| 187 | |
| 188 | /** |
| 189 | * qcom_scm_cpu_power_down() - Power down the cpu |
| 190 | * @flags - Flags to flush cache |
| 191 | * |
| 192 | * This is an end point to power down cpu. If there was a pending interrupt, |
| 193 | * the control would return from this function, otherwise, the cpu jumps to the |
| 194 | * warm boot entry point set for this cpu upon reset. |
| 195 | */ |
| 196 | void __qcom_scm_cpu_power_down(u32 flags) |
| 197 | { |
| 198 | } |
| 199 | |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 200 | int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) |
Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 201 | { |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 202 | int ret; |
| 203 | struct qcom_scm_desc desc = {0}; |
| 204 | struct arm_smccc_res res; |
| 205 | |
| 206 | desc.arginfo = QCOM_SCM_ARGS(1); |
| 207 | desc.args[0] = QCOM_SCM_FNID(svc_id, cmd_id) | |
| 208 | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); |
| 209 | |
| 210 | ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD, |
| 211 | &desc, &res); |
| 212 | |
| 213 | return ret ? : res.a1; |
Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 214 | } |
| 215 | |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 216 | int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, |
| 217 | u32 req_cnt, u32 *resp) |
Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 218 | { |
Kumar Gala | 6b1751a | 2016-06-03 18:25:26 -0500 | [diff] [blame] | 219 | int ret; |
| 220 | struct qcom_scm_desc desc = {0}; |
| 221 | struct arm_smccc_res res; |
| 222 | |
| 223 | if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) |
| 224 | return -ERANGE; |
| 225 | |
| 226 | desc.args[0] = req[0].addr; |
| 227 | desc.args[1] = req[0].val; |
| 228 | desc.args[2] = req[1].addr; |
| 229 | desc.args[3] = req[1].val; |
| 230 | desc.args[4] = req[2].addr; |
| 231 | desc.args[5] = req[2].val; |
| 232 | desc.args[6] = req[3].addr; |
| 233 | desc.args[7] = req[3].val; |
| 234 | desc.args[8] = req[4].addr; |
| 235 | desc.args[9] = req[4].val; |
| 236 | desc.arginfo = QCOM_SCM_ARGS(10); |
| 237 | |
| 238 | ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP, &desc, |
| 239 | &res); |
| 240 | *resp = res.a1; |
| 241 | |
| 242 | return ret; |
| 243 | } |
| 244 | |
| 245 | void __qcom_scm_init(void) |
| 246 | { |
| 247 | u64 cmd; |
| 248 | struct arm_smccc_res res; |
| 249 | u32 function = QCOM_SCM_FNID(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD); |
| 250 | |
| 251 | /* First try a SMC64 call */ |
| 252 | cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, |
| 253 | ARM_SMCCC_OWNER_SIP, function); |
| 254 | |
| 255 | arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)), |
| 256 | 0, 0, 0, 0, 0, &res); |
| 257 | |
| 258 | if (!res.a0 && res.a1) |
| 259 | qcom_smccc_convention = ARM_SMCCC_SMC_64; |
| 260 | else |
| 261 | qcom_smccc_convention = ARM_SMCCC_SMC_32; |
Andy Gross | 50b956f | 2015-09-11 16:01:16 -0500 | [diff] [blame] | 262 | } |
Bjorn Andersson | f01e90f | 2015-09-23 12:56:12 -0700 | [diff] [blame] | 263 | |
| 264 | bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) |
| 265 | { |
| 266 | int ret; |
| 267 | struct qcom_scm_desc desc = {0}; |
| 268 | struct arm_smccc_res res; |
| 269 | |
| 270 | desc.args[0] = peripheral; |
| 271 | desc.arginfo = QCOM_SCM_ARGS(1); |
| 272 | |
| 273 | ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, |
| 274 | QCOM_SCM_PAS_IS_SUPPORTED_CMD, |
| 275 | &desc, &res); |
| 276 | |
| 277 | return ret ? false : !!res.a1; |
| 278 | } |
| 279 | |
| 280 | int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, |
| 281 | dma_addr_t metadata_phys) |
| 282 | { |
| 283 | int ret; |
| 284 | struct qcom_scm_desc desc = {0}; |
| 285 | struct arm_smccc_res res; |
| 286 | |
| 287 | desc.args[0] = peripheral; |
| 288 | desc.args[1] = metadata_phys; |
| 289 | desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); |
| 290 | |
| 291 | ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_INIT_IMAGE_CMD, |
| 292 | &desc, &res); |
| 293 | |
| 294 | return ret ? : res.a1; |
| 295 | } |
| 296 | |
| 297 | int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, |
| 298 | phys_addr_t addr, phys_addr_t size) |
| 299 | { |
| 300 | int ret; |
| 301 | struct qcom_scm_desc desc = {0}; |
| 302 | struct arm_smccc_res res; |
| 303 | |
| 304 | desc.args[0] = peripheral; |
| 305 | desc.args[1] = addr; |
| 306 | desc.args[2] = size; |
| 307 | desc.arginfo = QCOM_SCM_ARGS(3); |
| 308 | |
| 309 | ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MEM_SETUP_CMD, |
| 310 | &desc, &res); |
| 311 | |
| 312 | return ret ? : res.a1; |
| 313 | } |
| 314 | |
| 315 | int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) |
| 316 | { |
| 317 | int ret; |
| 318 | struct qcom_scm_desc desc = {0}; |
| 319 | struct arm_smccc_res res; |
| 320 | |
| 321 | desc.args[0] = peripheral; |
| 322 | desc.arginfo = QCOM_SCM_ARGS(1); |
| 323 | |
| 324 | ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, |
| 325 | QCOM_SCM_PAS_AUTH_AND_RESET_CMD, |
| 326 | &desc, &res); |
| 327 | |
| 328 | return ret ? : res.a1; |
| 329 | } |
| 330 | |
| 331 | int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) |
| 332 | { |
| 333 | int ret; |
| 334 | struct qcom_scm_desc desc = {0}; |
| 335 | struct arm_smccc_res res; |
| 336 | |
| 337 | desc.args[0] = peripheral; |
| 338 | desc.arginfo = QCOM_SCM_ARGS(1); |
| 339 | |
| 340 | ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_SHUTDOWN_CMD, |
| 341 | &desc, &res); |
| 342 | |
| 343 | return ret ? : res.a1; |
| 344 | } |
Bjorn Andersson | dd4fe5b | 2016-06-17 10:40:43 -0700 | [diff] [blame^] | 345 | |
| 346 | int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) |
| 347 | { |
| 348 | struct qcom_scm_desc desc = {0}; |
| 349 | struct arm_smccc_res res; |
| 350 | int ret; |
| 351 | |
| 352 | desc.args[0] = reset; |
| 353 | desc.args[1] = 0; |
| 354 | desc.arginfo = QCOM_SCM_ARGS(2); |
| 355 | |
| 356 | ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET, &desc, |
| 357 | &res); |
| 358 | |
| 359 | return ret ? : res.a1; |
| 360 | } |