| Daniel J Blueman | f9726bf | 2012-12-07 14:24:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Numascale NumaConnect-specific PCI code |
| 7 | * |
| 8 | * Copyright (C) 2012 Numascale AS. All rights reserved. |
| 9 | * |
| 10 | * Send feedback to <support@numascale.com> |
| 11 | * |
| 12 | * PCI accessor functions derived from mmconfig_64.c |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #include <linux/pci.h> |
| 17 | #include <asm/pci_x86.h> |
| 18 | |
| 19 | static u8 limit __read_mostly; |
| 20 | |
| 21 | static inline char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn) |
| 22 | { |
| 23 | struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); |
| 24 | |
| 25 | if (cfg && cfg->virt) |
| 26 | return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); |
| 27 | return NULL; |
| 28 | } |
| 29 | |
| 30 | static int pci_mmcfg_read_numachip(unsigned int seg, unsigned int bus, |
| 31 | unsigned int devfn, int reg, int len, u32 *value) |
| 32 | { |
| 33 | char __iomem *addr; |
| 34 | |
| 35 | /* Why do we have this when nobody checks it. How about a BUG()!? -AK */ |
| 36 | if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) { |
| 37 | err: *value = -1; |
| 38 | return -EINVAL; |
| 39 | } |
| 40 | |
| 41 | /* Ensure AMD Northbridges don't decode reads to other devices */ |
| 42 | if (unlikely(bus == 0 && devfn >= limit)) { |
| 43 | *value = -1; |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | rcu_read_lock(); |
| 48 | addr = pci_dev_base(seg, bus, devfn); |
| 49 | if (!addr) { |
| 50 | rcu_read_unlock(); |
| 51 | goto err; |
| 52 | } |
| 53 | |
| 54 | switch (len) { |
| 55 | case 1: |
| 56 | *value = mmio_config_readb(addr + reg); |
| 57 | break; |
| 58 | case 2: |
| 59 | *value = mmio_config_readw(addr + reg); |
| 60 | break; |
| 61 | case 4: |
| 62 | *value = mmio_config_readl(addr + reg); |
| 63 | break; |
| 64 | } |
| 65 | rcu_read_unlock(); |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus, |
| 71 | unsigned int devfn, int reg, int len, u32 value) |
| 72 | { |
| 73 | char __iomem *addr; |
| 74 | |
| 75 | /* Why do we have this when nobody checks it. How about a BUG()!? -AK */ |
| 76 | if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) |
| 77 | return -EINVAL; |
| 78 | |
| 79 | /* Ensure AMD Northbridges don't decode writes to other devices */ |
| 80 | if (unlikely(bus == 0 && devfn >= limit)) |
| 81 | return 0; |
| 82 | |
| 83 | rcu_read_lock(); |
| 84 | addr = pci_dev_base(seg, bus, devfn); |
| 85 | if (!addr) { |
| 86 | rcu_read_unlock(); |
| 87 | return -EINVAL; |
| 88 | } |
| 89 | |
| 90 | switch (len) { |
| 91 | case 1: |
| 92 | mmio_config_writeb(addr + reg, value); |
| 93 | break; |
| 94 | case 2: |
| 95 | mmio_config_writew(addr + reg, value); |
| 96 | break; |
| 97 | case 4: |
| 98 | mmio_config_writel(addr + reg, value); |
| 99 | break; |
| 100 | } |
| 101 | rcu_read_unlock(); |
| 102 | |
| 103 | return 0; |
| 104 | } |
| 105 | |
| 106 | const struct pci_raw_ops pci_mmcfg_numachip = { |
| 107 | .read = pci_mmcfg_read_numachip, |
| 108 | .write = pci_mmcfg_write_numachip, |
| 109 | }; |
| 110 | |
| 111 | int __init pci_numachip_init(void) |
| 112 | { |
| 113 | int ret = 0; |
| 114 | u32 val; |
| 115 | |
| 116 | /* For remote I/O, restrict bus 0 access to the actual number of AMD |
| 117 | Northbridges, which starts at device number 0x18 */ |
| 118 | ret = raw_pci_read(0, 0, PCI_DEVFN(0x18, 0), 0x60, sizeof(val), &val); |
| 119 | if (ret) |
| 120 | goto out; |
| 121 | |
| 122 | /* HyperTransport fabric size in bits 6:4 */ |
| 123 | limit = PCI_DEVFN(0x18 + ((val >> 4) & 7) + 1, 0); |
| 124 | |
| 125 | /* Use NumaChip PCI accessors for non-extended and extended access */ |
| 126 | raw_pci_ops = raw_pci_ext_ops = &pci_mmcfg_numachip; |
| 127 | out: |
| 128 | return ret; |
| 129 | } |