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Stephen Warren774fec32011-07-05 10:55:27 -06001/*
Stephen Warrenef280d32012-04-05 15:54:53 -06002 * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
Stephen Warren774fec32011-07-05 10:55:27 -06003 *
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2011 - NVIDIA, Inc.
6 *
7 * Based on code copyright/by:
8 * Copyright (c) 2008-2009, NVIDIA Corporation
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
23 *
24 */
25
Stephen Warren896637a2012-04-06 10:30:52 -060026#ifndef __TEGRA20_SPDIF_H__
27#define __TEGRA20_SPDIF_H__
Stephen Warren774fec32011-07-05 10:55:27 -060028
29#include "tegra_pcm.h"
30
Stephen Warren896637a2012-04-06 10:30:52 -060031/* Offsets from TEGRA20_SPDIF_BASE */
Stephen Warren774fec32011-07-05 10:55:27 -060032
Stephen Warren896637a2012-04-06 10:30:52 -060033#define TEGRA20_SPDIF_CTRL 0x0
34#define TEGRA20_SPDIF_STATUS 0x4
35#define TEGRA20_SPDIF_STROBE_CTRL 0x8
36#define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C
37#define TEGRA20_SPDIF_DATA_OUT 0x40
38#define TEGRA20_SPDIF_DATA_IN 0x80
39#define TEGRA20_SPDIF_CH_STA_RX_A 0x100
40#define TEGRA20_SPDIF_CH_STA_RX_B 0x104
41#define TEGRA20_SPDIF_CH_STA_RX_C 0x108
42#define TEGRA20_SPDIF_CH_STA_RX_D 0x10C
43#define TEGRA20_SPDIF_CH_STA_RX_E 0x110
44#define TEGRA20_SPDIF_CH_STA_RX_F 0x114
45#define TEGRA20_SPDIF_CH_STA_TX_A 0x140
46#define TEGRA20_SPDIF_CH_STA_TX_B 0x144
47#define TEGRA20_SPDIF_CH_STA_TX_C 0x148
48#define TEGRA20_SPDIF_CH_STA_TX_D 0x14C
49#define TEGRA20_SPDIF_CH_STA_TX_E 0x150
50#define TEGRA20_SPDIF_CH_STA_TX_F 0x154
51#define TEGRA20_SPDIF_USR_STA_RX_A 0x180
52#define TEGRA20_SPDIF_USR_DAT_TX_A 0x1C0
Stephen Warren774fec32011-07-05 10:55:27 -060053
Stephen Warren896637a2012-04-06 10:30:52 -060054/* Fields in TEGRA20_SPDIF_CTRL */
Stephen Warren774fec32011-07-05 10:55:27 -060055
56/* Start capturing from 0=right, 1=left channel */
Stephen Warren896637a2012-04-06 10:30:52 -060057#define TEGRA20_SPDIF_CTRL_CAP_LC (1 << 30)
Stephen Warren774fec32011-07-05 10:55:27 -060058
59/* SPDIF receiver(RX) enable */
Stephen Warren896637a2012-04-06 10:30:52 -060060#define TEGRA20_SPDIF_CTRL_RX_EN (1 << 29)
Stephen Warren774fec32011-07-05 10:55:27 -060061
62/* SPDIF Transmitter(TX) enable */
Stephen Warren896637a2012-04-06 10:30:52 -060063#define TEGRA20_SPDIF_CTRL_TX_EN (1 << 28)
Stephen Warren774fec32011-07-05 10:55:27 -060064
65/* Transmit Channel status */
Stephen Warren896637a2012-04-06 10:30:52 -060066#define TEGRA20_SPDIF_CTRL_TC_EN (1 << 27)
Stephen Warren774fec32011-07-05 10:55:27 -060067
68/* Transmit user Data */
Stephen Warren896637a2012-04-06 10:30:52 -060069#define TEGRA20_SPDIF_CTRL_TU_EN (1 << 26)
Stephen Warren774fec32011-07-05 10:55:27 -060070
71/* Interrupt on transmit error */
Stephen Warren896637a2012-04-06 10:30:52 -060072#define TEGRA20_SPDIF_CTRL_IE_TXE (1 << 25)
Stephen Warren774fec32011-07-05 10:55:27 -060073
74/* Interrupt on receive error */
Stephen Warren896637a2012-04-06 10:30:52 -060075#define TEGRA20_SPDIF_CTRL_IE_RXE (1 << 24)
Stephen Warren774fec32011-07-05 10:55:27 -060076
77/* Interrupt on invalid preamble */
Stephen Warren896637a2012-04-06 10:30:52 -060078#define TEGRA20_SPDIF_CTRL_IE_P (1 << 23)
Stephen Warren774fec32011-07-05 10:55:27 -060079
80/* Interrupt on "B" preamble */
Stephen Warren896637a2012-04-06 10:30:52 -060081#define TEGRA20_SPDIF_CTRL_IE_B (1 << 22)
Stephen Warren774fec32011-07-05 10:55:27 -060082
83/* Interrupt when block of channel status received */
Stephen Warren896637a2012-04-06 10:30:52 -060084#define TEGRA20_SPDIF_CTRL_IE_C (1 << 21)
Stephen Warren774fec32011-07-05 10:55:27 -060085
86/* Interrupt when a valid information unit (IU) is received */
Stephen Warren896637a2012-04-06 10:30:52 -060087#define TEGRA20_SPDIF_CTRL_IE_U (1 << 20)
Stephen Warren774fec32011-07-05 10:55:27 -060088
89/* Interrupt when RX user FIFO attention level is reached */
Stephen Warren896637a2012-04-06 10:30:52 -060090#define TEGRA20_SPDIF_CTRL_QE_RU (1 << 19)
Stephen Warren774fec32011-07-05 10:55:27 -060091
92/* Interrupt when TX user FIFO attention level is reached */
Stephen Warren896637a2012-04-06 10:30:52 -060093#define TEGRA20_SPDIF_CTRL_QE_TU (1 << 18)
Stephen Warren774fec32011-07-05 10:55:27 -060094
95/* Interrupt when RX data FIFO attention level is reached */
Stephen Warren896637a2012-04-06 10:30:52 -060096#define TEGRA20_SPDIF_CTRL_QE_RX (1 << 17)
Stephen Warren774fec32011-07-05 10:55:27 -060097
98/* Interrupt when TX data FIFO attention level is reached */
Stephen Warren896637a2012-04-06 10:30:52 -060099#define TEGRA20_SPDIF_CTRL_QE_TX (1 << 16)
Stephen Warren774fec32011-07-05 10:55:27 -0600100
101/* Loopback test mode enable */
Stephen Warren896637a2012-04-06 10:30:52 -0600102#define TEGRA20_SPDIF_CTRL_LBK_EN (1 << 15)
Stephen Warren774fec32011-07-05 10:55:27 -0600103
104/*
105 * Pack data mode:
106 * 0 = Single data (16 bit needs to be padded to match the
107 * interface data bit size).
108 * 1 = Packeted left/right channel data into a single word.
109 */
Stephen Warren896637a2012-04-06 10:30:52 -0600110#define TEGRA20_SPDIF_CTRL_PACK (1 << 14)
Stephen Warren774fec32011-07-05 10:55:27 -0600111
112/*
113 * 00 = 16bit data
114 * 01 = 20bit data
115 * 10 = 24bit data
116 * 11 = raw data
117 */
Stephen Warren896637a2012-04-06 10:30:52 -0600118#define TEGRA20_SPDIF_BIT_MODE_16BIT 0
119#define TEGRA20_SPDIF_BIT_MODE_20BIT 1
120#define TEGRA20_SPDIF_BIT_MODE_24BIT 2
121#define TEGRA20_SPDIF_BIT_MODE_RAW 3
Stephen Warren774fec32011-07-05 10:55:27 -0600122
Stephen Warren896637a2012-04-06 10:30:52 -0600123#define TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT 12
124#define TEGRA20_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
125#define TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA20_SPDIF_BIT_MODE_16BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
126#define TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA20_SPDIF_BIT_MODE_20BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
127#define TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA20_SPDIF_BIT_MODE_24BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
128#define TEGRA20_SPDIF_CTRL_BIT_MODE_RAW (TEGRA20_SPDIF_BIT_MODE_RAW << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600129
Stephen Warren896637a2012-04-06 10:30:52 -0600130/* Fields in TEGRA20_SPDIF_STATUS */
Stephen Warren774fec32011-07-05 10:55:27 -0600131
132/*
133 * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must
134 * write a 1 to the corresponding bit location to clear the status.
135 */
136
137/*
138 * Receiver(RX) shifter is busy receiving data.
139 * This bit is asserted when the receiver first locked onto the
140 * preamble of the data stream after RX_EN is asserted. This bit is
141 * deasserted when either,
142 * (a) the end of a frame is reached after RX_EN is deeasserted, or
143 * (b) the SPDIF data stream becomes inactive.
144 */
Stephen Warren896637a2012-04-06 10:30:52 -0600145#define TEGRA20_SPDIF_STATUS_RX_BSY (1 << 29)
Stephen Warren774fec32011-07-05 10:55:27 -0600146
147/*
148 * Transmitter(TX) shifter is busy transmitting data.
149 * This bit is asserted when TX_EN is asserted.
150 * This bit is deasserted when the end of a frame is reached after
151 * TX_EN is deasserted.
152 */
Stephen Warren896637a2012-04-06 10:30:52 -0600153#define TEGRA20_SPDIF_STATUS_TX_BSY (1 << 28)
Stephen Warren774fec32011-07-05 10:55:27 -0600154
155/*
156 * TX is busy shifting out channel status.
157 * This bit is asserted when both TX_EN and TC_EN are asserted and
158 * data from CH_STA_TX_A register is loaded into the internal shifter.
159 * This bit is deasserted when either,
160 * (a) the end of a frame is reached after TX_EN is deasserted, or
161 * (b) CH_STA_TX_F register is loaded into the internal shifter.
162 */
Stephen Warren896637a2012-04-06 10:30:52 -0600163#define TEGRA20_SPDIF_STATUS_TC_BSY (1 << 27)
Stephen Warren774fec32011-07-05 10:55:27 -0600164
165/*
166 * TX User data FIFO busy.
167 * This bit is asserted when TX_EN and TXU_EN are asserted and
168 * there's data in the TX user FIFO. This bit is deassert when either,
169 * (a) the end of a frame is reached after TX_EN is deasserted, or
170 * (b) there's no data left in the TX user FIFO.
171 */
Stephen Warren896637a2012-04-06 10:30:52 -0600172#define TEGRA20_SPDIF_STATUS_TU_BSY (1 << 26)
Stephen Warren774fec32011-07-05 10:55:27 -0600173
174/* TX FIFO Underrun error status */
Stephen Warren896637a2012-04-06 10:30:52 -0600175#define TEGRA20_SPDIF_STATUS_TX_ERR (1 << 25)
Stephen Warren774fec32011-07-05 10:55:27 -0600176
177/* RX FIFO Overrun error status */
Stephen Warren896637a2012-04-06 10:30:52 -0600178#define TEGRA20_SPDIF_STATUS_RX_ERR (1 << 24)
Stephen Warren774fec32011-07-05 10:55:27 -0600179
180/* Preamble status: 0=Preamble OK, 1=bad/missing preamble */
Stephen Warren896637a2012-04-06 10:30:52 -0600181#define TEGRA20_SPDIF_STATUS_IS_P (1 << 23)
Stephen Warren774fec32011-07-05 10:55:27 -0600182
183/* B-preamble detection status: 0=not detected, 1=B-preamble detected */
Stephen Warren896637a2012-04-06 10:30:52 -0600184#define TEGRA20_SPDIF_STATUS_IS_B (1 << 22)
Stephen Warren774fec32011-07-05 10:55:27 -0600185
186/*
187 * RX channel block data receive status:
188 * 0=entire block not recieved yet.
189 * 1=received entire block of channel status,
190 */
Stephen Warren896637a2012-04-06 10:30:52 -0600191#define TEGRA20_SPDIF_STATUS_IS_C (1 << 21)
Stephen Warren774fec32011-07-05 10:55:27 -0600192
193/* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
Stephen Warren896637a2012-04-06 10:30:52 -0600194#define TEGRA20_SPDIF_STATUS_IS_U (1 << 20)
Stephen Warren774fec32011-07-05 10:55:27 -0600195
196/*
197 * RX User FIFO Status:
198 * 1=attention level reached, 0=attention level not reached.
199 */
Stephen Warren896637a2012-04-06 10:30:52 -0600200#define TEGRA20_SPDIF_STATUS_QS_RU (1 << 19)
Stephen Warren774fec32011-07-05 10:55:27 -0600201
202/*
203 * TX User FIFO Status:
204 * 1=attention level reached, 0=attention level not reached.
205 */
Stephen Warren896637a2012-04-06 10:30:52 -0600206#define TEGRA20_SPDIF_STATUS_QS_TU (1 << 18)
Stephen Warren774fec32011-07-05 10:55:27 -0600207
208/*
209 * RX Data FIFO Status:
210 * 1=attention level reached, 0=attention level not reached.
211 */
Stephen Warren896637a2012-04-06 10:30:52 -0600212#define TEGRA20_SPDIF_STATUS_QS_RX (1 << 17)
Stephen Warren774fec32011-07-05 10:55:27 -0600213
214/*
215 * TX Data FIFO Status:
216 * 1=attention level reached, 0=attention level not reached.
217 */
Stephen Warren896637a2012-04-06 10:30:52 -0600218#define TEGRA20_SPDIF_STATUS_QS_TX (1 << 16)
Stephen Warren774fec32011-07-05 10:55:27 -0600219
Stephen Warren896637a2012-04-06 10:30:52 -0600220/* Fields in TEGRA20_SPDIF_STROBE_CTRL */
Stephen Warren774fec32011-07-05 10:55:27 -0600221
222/*
223 * Indicates the approximate number of detected SPDIFIN clocks within a
224 * bi-phase period.
225 */
Stephen Warren896637a2012-04-06 10:30:52 -0600226#define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16
227#define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600228
229/* Data strobe mode: 0=Auto-locked 1=Manual locked */
Stephen Warren896637a2012-04-06 10:30:52 -0600230#define TEGRA20_SPDIF_STROBE_CTRL_STROBE (1 << 15)
Stephen Warren774fec32011-07-05 10:55:27 -0600231
232/*
233 * Manual data strobe time within the bi-phase clock period (in terms of
234 * the number of over-sampling clocks).
235 */
Stephen Warren896637a2012-04-06 10:30:52 -0600236#define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8
237#define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600238
239/*
240 * Manual SPDIFIN bi-phase clock period (in terms of the number of
241 * over-sampling clocks).
242 */
Stephen Warren896637a2012-04-06 10:30:52 -0600243#define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0
244#define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600245
246/* Fields in SPDIF_DATA_FIFO_CSR */
247
248/* Clear Receiver User FIFO (RX USR.FIFO) */
Stephen Warren896637a2012-04-06 10:30:52 -0600249#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31)
Stephen Warren774fec32011-07-05 10:55:27 -0600250
Stephen Warren896637a2012-04-06 10:30:52 -0600251#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0
252#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1
253#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2
254#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3
Stephen Warren774fec32011-07-05 10:55:27 -0600255
256/* RU FIFO attention level */
Stephen Warren896637a2012-04-06 10:30:52 -0600257#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29
258#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \
259 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
260#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \
261 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
262#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \
263 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
264#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \
265 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
266#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \
267 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600268
269/* Number of RX USR.FIFO levels with valid data. */
Stephen Warren896637a2012-04-06 10:30:52 -0600270#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24
271#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600272
273/* Clear Transmitter User FIFO (TX USR.FIFO) */
Stephen Warren896637a2012-04-06 10:30:52 -0600274#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23)
Stephen Warren774fec32011-07-05 10:55:27 -0600275
276/* TU FIFO attention level */
Stephen Warren896637a2012-04-06 10:30:52 -0600277#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21
278#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \
279 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
280#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \
281 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
282#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \
283 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
284#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \
285 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
286#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \
287 (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600288
289/* Number of TX USR.FIFO levels that could be filled. */
Stephen Warren896637a2012-04-06 10:30:52 -0600290#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16
291#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600292
293/* Clear Receiver Data FIFO (RX DATA.FIFO) */
Stephen Warren896637a2012-04-06 10:30:52 -0600294#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15)
Stephen Warren774fec32011-07-05 10:55:27 -0600295
Stephen Warren896637a2012-04-06 10:30:52 -0600296#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0
297#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1
298#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2
299#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3
Stephen Warren774fec32011-07-05 10:55:27 -0600300
301/* RU FIFO attention level */
Stephen Warren896637a2012-04-06 10:30:52 -0600302#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13
303#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \
304 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
305#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \
306 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
307#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \
308 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
309#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \
310 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
311#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \
312 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600313
314/* Number of RX DATA.FIFO levels with valid data. */
Stephen Warren896637a2012-04-06 10:30:52 -0600315#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8
316#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600317
318/* Clear Transmitter Data FIFO (TX DATA.FIFO) */
Stephen Warren896637a2012-04-06 10:30:52 -0600319#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7)
Stephen Warren774fec32011-07-05 10:55:27 -0600320
321/* TU FIFO attention level */
Stephen Warren896637a2012-04-06 10:30:52 -0600322#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5
323#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \
324 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
325#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \
326 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
327#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \
328 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
329#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \
330 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
331#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \
332 (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600333
334/* Number of TX DATA.FIFO levels that could be filled. */
Stephen Warren896637a2012-04-06 10:30:52 -0600335#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0
336#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600337
Stephen Warren896637a2012-04-06 10:30:52 -0600338/* Fields in TEGRA20_SPDIF_DATA_OUT */
Stephen Warren774fec32011-07-05 10:55:27 -0600339
340/*
341 * This register has 5 different formats:
342 * 16-bit (BIT_MODE=00, PACK=0)
343 * 20-bit (BIT_MODE=01, PACK=0)
344 * 24-bit (BIT_MODE=10, PACK=0)
345 * raw (BIT_MODE=11, PACK=0)
346 * 16-bit packed (BIT_MODE=00, PACK=1)
347 */
348
Stephen Warren896637a2012-04-06 10:30:52 -0600349#define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT 0
350#define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600351
Stephen Warren896637a2012-04-06 10:30:52 -0600352#define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT 0
353#define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600354
Stephen Warren896637a2012-04-06 10:30:52 -0600355#define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT 0
356#define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600357
Stephen Warren896637a2012-04-06 10:30:52 -0600358#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31)
359#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30)
360#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29)
361#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28)
Stephen Warren774fec32011-07-05 10:55:27 -0600362
Stephen Warren896637a2012-04-06 10:30:52 -0600363#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8
364#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600365
Stephen Warren896637a2012-04-06 10:30:52 -0600366#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4
367#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600368
Stephen Warren896637a2012-04-06 10:30:52 -0600369#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0
370#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600371
Stephen Warren896637a2012-04-06 10:30:52 -0600372#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16
373#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600374
Stephen Warren896637a2012-04-06 10:30:52 -0600375#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0
376#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600377
Stephen Warren896637a2012-04-06 10:30:52 -0600378/* Fields in TEGRA20_SPDIF_DATA_IN */
Stephen Warren774fec32011-07-05 10:55:27 -0600379
380/*
381 * This register has 5 different formats:
382 * 16-bit (BIT_MODE=00, PACK=0)
383 * 20-bit (BIT_MODE=01, PACK=0)
384 * 24-bit (BIT_MODE=10, PACK=0)
385 * raw (BIT_MODE=11, PACK=0)
386 * 16-bit packed (BIT_MODE=00, PACK=1)
387 *
388 * Bits 31:24 are common to all modes except 16-bit packed
389 */
390
Stephen Warren896637a2012-04-06 10:30:52 -0600391#define TEGRA20_SPDIF_DATA_IN_DATA_P (1 << 31)
392#define TEGRA20_SPDIF_DATA_IN_DATA_C (1 << 30)
393#define TEGRA20_SPDIF_DATA_IN_DATA_U (1 << 29)
394#define TEGRA20_SPDIF_DATA_IN_DATA_V (1 << 28)
Stephen Warren774fec32011-07-05 10:55:27 -0600395
Stephen Warren896637a2012-04-06 10:30:52 -0600396#define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24
397#define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600398
Stephen Warren896637a2012-04-06 10:30:52 -0600399#define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT 0
400#define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600401
Stephen Warren896637a2012-04-06 10:30:52 -0600402#define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT 0
403#define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600404
Stephen Warren896637a2012-04-06 10:30:52 -0600405#define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT 0
406#define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600407
Stephen Warren896637a2012-04-06 10:30:52 -0600408#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8
409#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600410
Stephen Warren896637a2012-04-06 10:30:52 -0600411#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4
412#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600413
Stephen Warren896637a2012-04-06 10:30:52 -0600414#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0
415#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600416
Stephen Warren896637a2012-04-06 10:30:52 -0600417#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16
418#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600419
Stephen Warren896637a2012-04-06 10:30:52 -0600420#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0
421#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT)
Stephen Warren774fec32011-07-05 10:55:27 -0600422
Stephen Warren896637a2012-04-06 10:30:52 -0600423/* Fields in TEGRA20_SPDIF_CH_STA_RX_A */
424/* Fields in TEGRA20_SPDIF_CH_STA_RX_B */
425/* Fields in TEGRA20_SPDIF_CH_STA_RX_C */
426/* Fields in TEGRA20_SPDIF_CH_STA_RX_D */
427/* Fields in TEGRA20_SPDIF_CH_STA_RX_E */
428/* Fields in TEGRA20_SPDIF_CH_STA_RX_F */
Stephen Warren774fec32011-07-05 10:55:27 -0600429
430/*
431 * The 6-word receive channel data page buffer holds a block (192 frames) of
432 * channel status information. The order of receive is from LSB to MSB
433 * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
434 */
435
Stephen Warren896637a2012-04-06 10:30:52 -0600436/* Fields in TEGRA20_SPDIF_CH_STA_TX_A */
437/* Fields in TEGRA20_SPDIF_CH_STA_TX_B */
438/* Fields in TEGRA20_SPDIF_CH_STA_TX_C */
439/* Fields in TEGRA20_SPDIF_CH_STA_TX_D */
440/* Fields in TEGRA20_SPDIF_CH_STA_TX_E */
441/* Fields in TEGRA20_SPDIF_CH_STA_TX_F */
Stephen Warren774fec32011-07-05 10:55:27 -0600442
443/*
444 * The 6-word transmit channel data page buffer holds a block (192 frames) of
445 * channel status information. The order of transmission is from LSB to MSB
446 * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A.
447 */
448
Stephen Warren896637a2012-04-06 10:30:52 -0600449/* Fields in TEGRA20_SPDIF_USR_STA_RX_A */
Stephen Warren774fec32011-07-05 10:55:27 -0600450
451/*
452 * This 4-word deep FIFO receives user FIFO field information. The order of
453 * receive is from LSB to MSB bit.
454 */
455
Stephen Warren896637a2012-04-06 10:30:52 -0600456/* Fields in TEGRA20_SPDIF_USR_DAT_TX_A */
Stephen Warren774fec32011-07-05 10:55:27 -0600457
458/*
459 * This 4-word deep FIFO transmits user FIFO field information. The order of
460 * transmission is from LSB to MSB bit.
461 */
462
Stephen Warren896637a2012-04-06 10:30:52 -0600463struct tegra20_spdif {
Stephen Warren774fec32011-07-05 10:55:27 -0600464 struct clk *clk_spdif_out;
Lars-Peter Clausen3489d502013-04-03 11:06:03 +0200465 struct snd_dmaengine_dai_dma_data capture_dma_data;
466 struct snd_dmaengine_dai_dma_data playback_dma_data;
Stephen Warren5939ae72012-04-13 12:14:07 -0600467 struct regmap *regmap;
Stephen Warren774fec32011-07-05 10:55:27 -0600468};
469
470#endif