Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/clk.h> |
| 19 | #include <linux/clk-provider.h> |
| 20 | #include <linux/clkdev.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_address.h> |
| 23 | #include <linux/delay.h> |
Paul Walmsley | 25c9ded | 2013-06-07 06:18:58 -0600 | [diff] [blame] | 24 | #include <linux/export.h> |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 25 | #include <linux/clk/tegra.h> |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 26 | #include <dt-bindings/clock/tegra114-car.h> |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 27 | |
| 28 | #include "clk.h" |
Peter De Schrijver | 6609dbe | 2013-09-17 15:42:24 +0300 | [diff] [blame] | 29 | #include "clk-id.h" |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 30 | |
Paul Walmsley | 1c472d8 | 2013-06-07 06:19:09 -0600 | [diff] [blame] | 31 | #define RST_DFLL_DVCO 0x2F4 |
Paul Walmsley | 25c9ded | 2013-06-07 06:18:58 -0600 | [diff] [blame] | 32 | #define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ |
| 33 | #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ |
| 34 | #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 35 | |
Paul Walmsley | 1c472d8 | 2013-06-07 06:19:09 -0600 | [diff] [blame] | 36 | /* RST_DFLL_DVCO bitfields */ |
| 37 | #define DVFS_DFLL_RESET_SHIFT 0 |
| 38 | |
Paul Walmsley | 25c9ded | 2013-06-07 06:18:58 -0600 | [diff] [blame] | 39 | /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */ |
| 40 | #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */ |
| 41 | #define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */ |
| 42 | #define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */ |
| 43 | #define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */ |
| 44 | #define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */ |
| 45 | #define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */ |
| 46 | |
| 47 | /* CPU_FINETRIM_R bitfields */ |
| 48 | #define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */ |
| 49 | #define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT) |
| 50 | #define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */ |
| 51 | #define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT) |
| 52 | #define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */ |
| 53 | #define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT) |
| 54 | #define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */ |
| 55 | #define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT) |
| 56 | #define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */ |
| 57 | #define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT) |
| 58 | #define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ |
| 59 | #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) |
| 60 | |
Peter De Schrijver | d5ff89a | 2013-08-22 18:44:06 +0300 | [diff] [blame] | 61 | #define TEGRA114_CLK_PERIPH_BANKS 5 |
| 62 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 63 | #define PLLC_BASE 0x80 |
| 64 | #define PLLC_MISC2 0x88 |
| 65 | #define PLLC_MISC 0x8c |
| 66 | #define PLLC2_BASE 0x4e8 |
| 67 | #define PLLC2_MISC 0x4ec |
| 68 | #define PLLC3_BASE 0x4fc |
| 69 | #define PLLC3_MISC 0x500 |
| 70 | #define PLLM_BASE 0x90 |
| 71 | #define PLLM_MISC 0x9c |
| 72 | #define PLLP_BASE 0xa0 |
| 73 | #define PLLP_MISC 0xac |
| 74 | #define PLLX_BASE 0xe0 |
| 75 | #define PLLX_MISC 0xe4 |
| 76 | #define PLLX_MISC2 0x514 |
| 77 | #define PLLX_MISC3 0x518 |
| 78 | #define PLLD_BASE 0xd0 |
| 79 | #define PLLD_MISC 0xdc |
| 80 | #define PLLD2_BASE 0x4b8 |
| 81 | #define PLLD2_MISC 0x4bc |
| 82 | #define PLLE_BASE 0xe8 |
| 83 | #define PLLE_MISC 0xec |
| 84 | #define PLLA_BASE 0xb0 |
| 85 | #define PLLA_MISC 0xbc |
| 86 | #define PLLU_BASE 0xc0 |
| 87 | #define PLLU_MISC 0xcc |
| 88 | #define PLLRE_BASE 0x4c4 |
| 89 | #define PLLRE_MISC 0x4c8 |
| 90 | |
| 91 | #define PLL_MISC_LOCK_ENABLE 18 |
| 92 | #define PLLC_MISC_LOCK_ENABLE 24 |
| 93 | #define PLLDU_MISC_LOCK_ENABLE 22 |
| 94 | #define PLLE_MISC_LOCK_ENABLE 9 |
| 95 | #define PLLRE_MISC_LOCK_ENABLE 30 |
| 96 | |
| 97 | #define PLLC_IDDQ_BIT 26 |
| 98 | #define PLLX_IDDQ_BIT 3 |
| 99 | #define PLLRE_IDDQ_BIT 16 |
| 100 | |
| 101 | #define PLL_BASE_LOCK BIT(27) |
| 102 | #define PLLE_MISC_LOCK BIT(11) |
| 103 | #define PLLRE_MISC_LOCK BIT(24) |
| 104 | #define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) |
| 105 | |
| 106 | #define PLLE_AUX 0x48c |
| 107 | #define PLLC_OUT 0x84 |
| 108 | #define PLLM_OUT 0x94 |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 109 | |
| 110 | #define PMC_CLK_OUT_CNTRL 0x1a8 |
| 111 | #define PMC_DPD_PADS_ORIDE 0x1c |
| 112 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 |
| 113 | #define PMC_CTRL 0 |
| 114 | #define PMC_CTRL_BLINK_ENB 7 |
Alexandre Courbot | 9139227 | 2013-05-26 11:56:31 +0900 | [diff] [blame] | 115 | #define PMC_BLINK_TIMER 0x40 |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 116 | |
| 117 | #define OSC_CTRL 0x50 |
| 118 | #define OSC_CTRL_OSC_FREQ_SHIFT 28 |
| 119 | #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 |
| 120 | |
| 121 | #define PLLXC_SW_MAX_P 6 |
| 122 | |
| 123 | #define CCLKG_BURST_POLICY 0x368 |
| 124 | #define CCLKLP_BURST_POLICY 0x370 |
| 125 | #define SCLK_BURST_POLICY 0x028 |
| 126 | #define SYSTEM_CLK_RATE 0x030 |
| 127 | |
| 128 | #define UTMIP_PLL_CFG2 0x488 |
| 129 | #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) |
| 130 | #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) |
| 131 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) |
| 132 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) |
| 133 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) |
| 134 | |
| 135 | #define UTMIP_PLL_CFG1 0x484 |
| 136 | #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) |
| 137 | #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) |
| 138 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) |
| 139 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) |
| 140 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) |
| 141 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) |
| 142 | #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) |
| 143 | |
| 144 | #define UTMIPLL_HW_PWRDN_CFG0 0x52c |
| 145 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) |
| 146 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) |
| 147 | #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) |
| 148 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) |
| 149 | #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) |
| 150 | #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) |
| 151 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) |
| 152 | #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) |
| 153 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 154 | #define CLK_SOURCE_CSITE 0x1d4 |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 155 | #define CLK_SOURCE_XUSB_SS_SRC 0x610 |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 156 | #define CLK_SOURCE_EMC 0x19c |
| 157 | |
Peter De Schrijver | d53442e | 2013-06-06 13:47:29 +0300 | [diff] [blame] | 158 | /* PLLM override registers */ |
| 159 | #define PMC_PLLM_WB0_OVERRIDE 0x1dc |
| 160 | #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 |
| 161 | |
Joseph Lo | 31972fd | 2013-05-20 18:39:28 +0800 | [diff] [blame] | 162 | /* Tegra CPU clock and reset control regs */ |
| 163 | #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 |
| 164 | |
Joseph Lo | ad7d114 | 2013-07-03 17:50:44 +0800 | [diff] [blame] | 165 | #ifdef CONFIG_PM_SLEEP |
| 166 | static struct cpu_clk_suspend_context { |
| 167 | u32 clk_csite_src; |
Joseph Lo | 0017f44 | 2013-08-12 17:40:02 +0800 | [diff] [blame] | 168 | u32 cclkg_burst; |
| 169 | u32 cclkg_divider; |
Joseph Lo | ad7d114 | 2013-07-03 17:50:44 +0800 | [diff] [blame] | 170 | } tegra114_cpu_clk_sctx; |
| 171 | #endif |
| 172 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 173 | static void __iomem *clk_base; |
| 174 | static void __iomem *pmc_base; |
| 175 | |
| 176 | static DEFINE_SPINLOCK(pll_d_lock); |
| 177 | static DEFINE_SPINLOCK(pll_d2_lock); |
| 178 | static DEFINE_SPINLOCK(pll_u_lock); |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 179 | static DEFINE_SPINLOCK(pll_re_lock); |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 180 | static DEFINE_SPINLOCK(clk_out_lock); |
| 181 | static DEFINE_SPINLOCK(sysrate_lock); |
| 182 | |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 183 | static struct div_nmp pllxc_nmp = { |
| 184 | .divm_shift = 0, |
| 185 | .divm_width = 8, |
| 186 | .divn_shift = 8, |
| 187 | .divn_width = 8, |
| 188 | .divp_shift = 20, |
| 189 | .divp_width = 4, |
| 190 | }; |
| 191 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 192 | static struct pdiv_map pllxc_p[] = { |
| 193 | { .pdiv = 1, .hw_val = 0 }, |
| 194 | { .pdiv = 2, .hw_val = 1 }, |
| 195 | { .pdiv = 3, .hw_val = 2 }, |
| 196 | { .pdiv = 4, .hw_val = 3 }, |
| 197 | { .pdiv = 5, .hw_val = 4 }, |
| 198 | { .pdiv = 6, .hw_val = 5 }, |
| 199 | { .pdiv = 8, .hw_val = 6 }, |
| 200 | { .pdiv = 10, .hw_val = 7 }, |
| 201 | { .pdiv = 12, .hw_val = 8 }, |
| 202 | { .pdiv = 16, .hw_val = 9 }, |
| 203 | { .pdiv = 12, .hw_val = 10 }, |
| 204 | { .pdiv = 16, .hw_val = 11 }, |
| 205 | { .pdiv = 20, .hw_val = 12 }, |
| 206 | { .pdiv = 24, .hw_val = 13 }, |
| 207 | { .pdiv = 32, .hw_val = 14 }, |
| 208 | { .pdiv = 0, .hw_val = 0 }, |
| 209 | }; |
| 210 | |
| 211 | static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { |
| 212 | { 12000000, 624000000, 104, 0, 2}, |
| 213 | { 12000000, 600000000, 100, 0, 2}, |
| 214 | { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ |
| 215 | { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ |
| 216 | { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ |
| 217 | { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ |
| 218 | { 0, 0, 0, 0, 0, 0 }, |
| 219 | }; |
| 220 | |
| 221 | static struct tegra_clk_pll_params pll_c_params = { |
| 222 | .input_min = 12000000, |
| 223 | .input_max = 800000000, |
| 224 | .cf_min = 12000000, |
| 225 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ |
| 226 | .vco_min = 600000000, |
| 227 | .vco_max = 1400000000, |
| 228 | .base_reg = PLLC_BASE, |
| 229 | .misc_reg = PLLC_MISC, |
| 230 | .lock_mask = PLL_BASE_LOCK, |
| 231 | .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, |
| 232 | .lock_delay = 300, |
| 233 | .iddq_reg = PLLC_MISC, |
| 234 | .iddq_bit_idx = PLLC_IDDQ_BIT, |
| 235 | .max_p = PLLXC_SW_MAX_P, |
| 236 | .dyn_ramp_reg = PLLC_MISC2, |
| 237 | .stepa_shift = 17, |
| 238 | .stepb_shift = 9, |
| 239 | .pdiv_tohw = pllxc_p, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 240 | .div_nmp = &pllxc_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 241 | .freq_table = pll_c_freq_table, |
| 242 | .flags = TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 243 | }; |
| 244 | |
| 245 | static struct div_nmp pllcx_nmp = { |
| 246 | .divm_shift = 0, |
| 247 | .divm_width = 2, |
| 248 | .divn_shift = 8, |
| 249 | .divn_width = 8, |
| 250 | .divp_shift = 20, |
| 251 | .divp_width = 3, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | static struct pdiv_map pllc_p[] = { |
| 255 | { .pdiv = 1, .hw_val = 0 }, |
| 256 | { .pdiv = 2, .hw_val = 1 }, |
| 257 | { .pdiv = 4, .hw_val = 3 }, |
| 258 | { .pdiv = 8, .hw_val = 5 }, |
| 259 | { .pdiv = 16, .hw_val = 7 }, |
| 260 | { .pdiv = 0, .hw_val = 0 }, |
| 261 | }; |
| 262 | |
| 263 | static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { |
| 264 | {12000000, 600000000, 100, 0, 2}, |
| 265 | {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ |
| 266 | {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ |
| 267 | {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ |
| 268 | {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ |
| 269 | {0, 0, 0, 0, 0, 0}, |
| 270 | }; |
| 271 | |
| 272 | static struct tegra_clk_pll_params pll_c2_params = { |
| 273 | .input_min = 12000000, |
| 274 | .input_max = 48000000, |
| 275 | .cf_min = 12000000, |
| 276 | .cf_max = 19200000, |
| 277 | .vco_min = 600000000, |
| 278 | .vco_max = 1200000000, |
| 279 | .base_reg = PLLC2_BASE, |
| 280 | .misc_reg = PLLC2_MISC, |
| 281 | .lock_mask = PLL_BASE_LOCK, |
| 282 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
| 283 | .lock_delay = 300, |
| 284 | .pdiv_tohw = pllc_p, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 285 | .div_nmp = &pllcx_nmp, |
| 286 | .max_p = 7, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 287 | .ext_misc_reg[0] = 0x4f0, |
| 288 | .ext_misc_reg[1] = 0x4f4, |
| 289 | .ext_misc_reg[2] = 0x4f8, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 290 | .freq_table = pll_cx_freq_table, |
| 291 | .flags = TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 292 | }; |
| 293 | |
| 294 | static struct tegra_clk_pll_params pll_c3_params = { |
| 295 | .input_min = 12000000, |
| 296 | .input_max = 48000000, |
| 297 | .cf_min = 12000000, |
| 298 | .cf_max = 19200000, |
| 299 | .vco_min = 600000000, |
| 300 | .vco_max = 1200000000, |
| 301 | .base_reg = PLLC3_BASE, |
| 302 | .misc_reg = PLLC3_MISC, |
| 303 | .lock_mask = PLL_BASE_LOCK, |
| 304 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
| 305 | .lock_delay = 300, |
| 306 | .pdiv_tohw = pllc_p, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 307 | .div_nmp = &pllcx_nmp, |
| 308 | .max_p = 7, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 309 | .ext_misc_reg[0] = 0x504, |
| 310 | .ext_misc_reg[1] = 0x508, |
| 311 | .ext_misc_reg[2] = 0x50c, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 312 | .freq_table = pll_cx_freq_table, |
| 313 | .flags = TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 314 | }; |
| 315 | |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 316 | static struct div_nmp pllm_nmp = { |
| 317 | .divm_shift = 0, |
| 318 | .divm_width = 8, |
Peter De Schrijver | d53442e | 2013-06-06 13:47:29 +0300 | [diff] [blame] | 319 | .override_divm_shift = 0, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 320 | .divn_shift = 8, |
| 321 | .divn_width = 8, |
Peter De Schrijver | d53442e | 2013-06-06 13:47:29 +0300 | [diff] [blame] | 322 | .override_divn_shift = 8, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 323 | .divp_shift = 20, |
| 324 | .divp_width = 1, |
Peter De Schrijver | d53442e | 2013-06-06 13:47:29 +0300 | [diff] [blame] | 325 | .override_divp_shift = 27, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 326 | }; |
| 327 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 328 | static struct pdiv_map pllm_p[] = { |
| 329 | { .pdiv = 1, .hw_val = 0 }, |
| 330 | { .pdiv = 2, .hw_val = 1 }, |
| 331 | { .pdiv = 0, .hw_val = 0 }, |
| 332 | }; |
| 333 | |
| 334 | static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { |
| 335 | {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ |
| 336 | {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ |
| 337 | {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ |
| 338 | {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ |
| 339 | {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ |
| 340 | {0, 0, 0, 0, 0, 0}, |
| 341 | }; |
| 342 | |
| 343 | static struct tegra_clk_pll_params pll_m_params = { |
| 344 | .input_min = 12000000, |
| 345 | .input_max = 500000000, |
| 346 | .cf_min = 12000000, |
| 347 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ |
| 348 | .vco_min = 400000000, |
| 349 | .vco_max = 1066000000, |
| 350 | .base_reg = PLLM_BASE, |
| 351 | .misc_reg = PLLM_MISC, |
| 352 | .lock_mask = PLL_BASE_LOCK, |
| 353 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
| 354 | .lock_delay = 300, |
| 355 | .max_p = 2, |
| 356 | .pdiv_tohw = pllm_p, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 357 | .div_nmp = &pllm_nmp, |
Peter De Schrijver | d53442e | 2013-06-06 13:47:29 +0300 | [diff] [blame] | 358 | .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, |
| 359 | .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 360 | .freq_table = pll_m_freq_table, |
| 361 | .flags = TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 362 | }; |
| 363 | |
| 364 | static struct div_nmp pllp_nmp = { |
| 365 | .divm_shift = 0, |
| 366 | .divm_width = 5, |
| 367 | .divn_shift = 8, |
| 368 | .divn_width = 10, |
| 369 | .divp_shift = 20, |
| 370 | .divp_width = 3, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 371 | }; |
| 372 | |
| 373 | static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { |
| 374 | {12000000, 216000000, 432, 12, 1, 8}, |
| 375 | {13000000, 216000000, 432, 13, 1, 8}, |
| 376 | {16800000, 216000000, 360, 14, 1, 8}, |
| 377 | {19200000, 216000000, 360, 16, 1, 8}, |
| 378 | {26000000, 216000000, 432, 26, 1, 8}, |
| 379 | {0, 0, 0, 0, 0, 0}, |
| 380 | }; |
| 381 | |
| 382 | static struct tegra_clk_pll_params pll_p_params = { |
| 383 | .input_min = 2000000, |
| 384 | .input_max = 31000000, |
| 385 | .cf_min = 1000000, |
| 386 | .cf_max = 6000000, |
| 387 | .vco_min = 200000000, |
| 388 | .vco_max = 700000000, |
| 389 | .base_reg = PLLP_BASE, |
| 390 | .misc_reg = PLLP_MISC, |
| 391 | .lock_mask = PLL_BASE_LOCK, |
| 392 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
| 393 | .lock_delay = 300, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 394 | .div_nmp = &pllp_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 395 | .freq_table = pll_p_freq_table, |
| 396 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, |
| 397 | .fixed_rate = 408000000, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 398 | }; |
| 399 | |
| 400 | static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { |
| 401 | {9600000, 282240000, 147, 5, 0, 4}, |
| 402 | {9600000, 368640000, 192, 5, 0, 4}, |
| 403 | {9600000, 240000000, 200, 8, 0, 8}, |
| 404 | |
| 405 | {28800000, 282240000, 245, 25, 0, 8}, |
| 406 | {28800000, 368640000, 320, 25, 0, 8}, |
| 407 | {28800000, 240000000, 200, 24, 0, 8}, |
| 408 | {0, 0, 0, 0, 0, 0}, |
| 409 | }; |
| 410 | |
| 411 | |
| 412 | static struct tegra_clk_pll_params pll_a_params = { |
| 413 | .input_min = 2000000, |
| 414 | .input_max = 31000000, |
| 415 | .cf_min = 1000000, |
| 416 | .cf_max = 6000000, |
| 417 | .vco_min = 200000000, |
| 418 | .vco_max = 700000000, |
| 419 | .base_reg = PLLA_BASE, |
| 420 | .misc_reg = PLLA_MISC, |
| 421 | .lock_mask = PLL_BASE_LOCK, |
| 422 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
| 423 | .lock_delay = 300, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 424 | .div_nmp = &pllp_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 425 | .freq_table = pll_a_freq_table, |
| 426 | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 427 | }; |
| 428 | |
| 429 | static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { |
| 430 | {12000000, 216000000, 864, 12, 2, 12}, |
| 431 | {13000000, 216000000, 864, 13, 2, 12}, |
| 432 | {16800000, 216000000, 720, 14, 2, 12}, |
| 433 | {19200000, 216000000, 720, 16, 2, 12}, |
| 434 | {26000000, 216000000, 864, 26, 2, 12}, |
| 435 | |
| 436 | {12000000, 594000000, 594, 12, 0, 12}, |
| 437 | {13000000, 594000000, 594, 13, 0, 12}, |
| 438 | {16800000, 594000000, 495, 14, 0, 12}, |
| 439 | {19200000, 594000000, 495, 16, 0, 12}, |
| 440 | {26000000, 594000000, 594, 26, 0, 12}, |
| 441 | |
| 442 | {12000000, 1000000000, 1000, 12, 0, 12}, |
| 443 | {13000000, 1000000000, 1000, 13, 0, 12}, |
| 444 | {19200000, 1000000000, 625, 12, 0, 12}, |
| 445 | {26000000, 1000000000, 1000, 26, 0, 12}, |
| 446 | |
| 447 | {0, 0, 0, 0, 0, 0}, |
| 448 | }; |
| 449 | |
| 450 | static struct tegra_clk_pll_params pll_d_params = { |
| 451 | .input_min = 2000000, |
| 452 | .input_max = 40000000, |
| 453 | .cf_min = 1000000, |
| 454 | .cf_max = 6000000, |
| 455 | .vco_min = 500000000, |
| 456 | .vco_max = 1000000000, |
| 457 | .base_reg = PLLD_BASE, |
| 458 | .misc_reg = PLLD_MISC, |
| 459 | .lock_mask = PLL_BASE_LOCK, |
| 460 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, |
| 461 | .lock_delay = 1000, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 462 | .div_nmp = &pllp_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 463 | .freq_table = pll_d_freq_table, |
| 464 | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | |
| 465 | TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 466 | }; |
| 467 | |
| 468 | static struct tegra_clk_pll_params pll_d2_params = { |
| 469 | .input_min = 2000000, |
| 470 | .input_max = 40000000, |
| 471 | .cf_min = 1000000, |
| 472 | .cf_max = 6000000, |
| 473 | .vco_min = 500000000, |
| 474 | .vco_max = 1000000000, |
| 475 | .base_reg = PLLD2_BASE, |
| 476 | .misc_reg = PLLD2_MISC, |
| 477 | .lock_mask = PLL_BASE_LOCK, |
| 478 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, |
| 479 | .lock_delay = 1000, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 480 | .div_nmp = &pllp_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 481 | .freq_table = pll_d_freq_table, |
| 482 | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | |
| 483 | TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 484 | }; |
| 485 | |
| 486 | static struct pdiv_map pllu_p[] = { |
| 487 | { .pdiv = 1, .hw_val = 1 }, |
| 488 | { .pdiv = 2, .hw_val = 0 }, |
| 489 | { .pdiv = 0, .hw_val = 0 }, |
| 490 | }; |
| 491 | |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 492 | static struct div_nmp pllu_nmp = { |
| 493 | .divm_shift = 0, |
| 494 | .divm_width = 5, |
| 495 | .divn_shift = 8, |
| 496 | .divn_width = 10, |
| 497 | .divp_shift = 20, |
| 498 | .divp_width = 1, |
| 499 | }; |
| 500 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 501 | static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { |
| 502 | {12000000, 480000000, 960, 12, 0, 12}, |
| 503 | {13000000, 480000000, 960, 13, 0, 12}, |
| 504 | {16800000, 480000000, 400, 7, 0, 5}, |
| 505 | {19200000, 480000000, 200, 4, 0, 3}, |
| 506 | {26000000, 480000000, 960, 26, 0, 12}, |
| 507 | {0, 0, 0, 0, 0, 0}, |
| 508 | }; |
| 509 | |
| 510 | static struct tegra_clk_pll_params pll_u_params = { |
| 511 | .input_min = 2000000, |
| 512 | .input_max = 40000000, |
| 513 | .cf_min = 1000000, |
| 514 | .cf_max = 6000000, |
| 515 | .vco_min = 480000000, |
| 516 | .vco_max = 960000000, |
| 517 | .base_reg = PLLU_BASE, |
| 518 | .misc_reg = PLLU_MISC, |
| 519 | .lock_mask = PLL_BASE_LOCK, |
| 520 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, |
| 521 | .lock_delay = 1000, |
| 522 | .pdiv_tohw = pllu_p, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 523 | .div_nmp = &pllu_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 524 | .freq_table = pll_u_freq_table, |
| 525 | .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | |
| 526 | TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 527 | }; |
| 528 | |
| 529 | static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { |
| 530 | /* 1 GHz */ |
| 531 | {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ |
| 532 | {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ |
| 533 | {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ |
| 534 | {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ |
| 535 | {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ |
| 536 | |
| 537 | {0, 0, 0, 0, 0, 0}, |
| 538 | }; |
| 539 | |
| 540 | static struct tegra_clk_pll_params pll_x_params = { |
| 541 | .input_min = 12000000, |
| 542 | .input_max = 800000000, |
| 543 | .cf_min = 12000000, |
| 544 | .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ |
| 545 | .vco_min = 700000000, |
| 546 | .vco_max = 2400000000U, |
| 547 | .base_reg = PLLX_BASE, |
| 548 | .misc_reg = PLLX_MISC, |
| 549 | .lock_mask = PLL_BASE_LOCK, |
| 550 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
| 551 | .lock_delay = 300, |
| 552 | .iddq_reg = PLLX_MISC3, |
| 553 | .iddq_bit_idx = PLLX_IDDQ_BIT, |
| 554 | .max_p = PLLXC_SW_MAX_P, |
| 555 | .dyn_ramp_reg = PLLX_MISC2, |
| 556 | .stepa_shift = 16, |
| 557 | .stepb_shift = 24, |
| 558 | .pdiv_tohw = pllxc_p, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 559 | .div_nmp = &pllxc_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 560 | .freq_table = pll_x_freq_table, |
| 561 | .flags = TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 562 | }; |
| 563 | |
| 564 | static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { |
| 565 | /* PLLE special case: use cpcon field to store cml divider value */ |
| 566 | {336000000, 100000000, 100, 21, 16, 11}, |
| 567 | {312000000, 100000000, 200, 26, 24, 13}, |
Peter De Schrijver | 8e9cc80 | 2013-11-25 14:44:13 +0200 | [diff] [blame] | 568 | {12000000, 100000000, 200, 1, 24, 13}, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 569 | {0, 0, 0, 0, 0, 0}, |
| 570 | }; |
| 571 | |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 572 | static struct div_nmp plle_nmp = { |
| 573 | .divm_shift = 0, |
| 574 | .divm_width = 8, |
| 575 | .divn_shift = 8, |
| 576 | .divn_width = 8, |
| 577 | .divp_shift = 24, |
| 578 | .divp_width = 4, |
| 579 | }; |
| 580 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 581 | static struct tegra_clk_pll_params pll_e_params = { |
| 582 | .input_min = 12000000, |
| 583 | .input_max = 1000000000, |
| 584 | .cf_min = 12000000, |
| 585 | .cf_max = 75000000, |
| 586 | .vco_min = 1600000000, |
| 587 | .vco_max = 2400000000U, |
| 588 | .base_reg = PLLE_BASE, |
| 589 | .misc_reg = PLLE_MISC, |
| 590 | .aux_reg = PLLE_AUX, |
| 591 | .lock_mask = PLLE_MISC_LOCK, |
| 592 | .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, |
| 593 | .lock_delay = 300, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 594 | .div_nmp = &plle_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 595 | .freq_table = pll_e_freq_table, |
| 596 | .flags = TEGRA_PLL_FIXED, |
| 597 | .fixed_rate = 100000000, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 598 | }; |
| 599 | |
| 600 | static struct div_nmp pllre_nmp = { |
| 601 | .divm_shift = 0, |
| 602 | .divm_width = 8, |
| 603 | .divn_shift = 8, |
| 604 | .divn_width = 8, |
| 605 | .divp_shift = 16, |
| 606 | .divp_width = 4, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 607 | }; |
| 608 | |
| 609 | static struct tegra_clk_pll_params pll_re_vco_params = { |
| 610 | .input_min = 12000000, |
| 611 | .input_max = 1000000000, |
| 612 | .cf_min = 12000000, |
| 613 | .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ |
| 614 | .vco_min = 300000000, |
| 615 | .vco_max = 600000000, |
| 616 | .base_reg = PLLRE_BASE, |
| 617 | .misc_reg = PLLRE_MISC, |
| 618 | .lock_mask = PLLRE_MISC_LOCK, |
| 619 | .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, |
| 620 | .lock_delay = 300, |
| 621 | .iddq_reg = PLLRE_MISC, |
| 622 | .iddq_bit_idx = PLLRE_IDDQ_BIT, |
Peter De Schrijver | fd428ad | 2013-06-05 16:51:26 +0300 | [diff] [blame] | 623 | .div_nmp = &pllre_nmp, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 624 | .flags = TEGRA_PLL_USE_LOCK, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 625 | }; |
| 626 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 627 | /* possible OSC frequencies in Hz */ |
| 628 | static unsigned long tegra114_input_freq[] = { |
| 629 | [0] = 13000000, |
| 630 | [1] = 16800000, |
| 631 | [4] = 19200000, |
| 632 | [5] = 38400000, |
| 633 | [8] = 12000000, |
| 634 | [9] = 48000000, |
| 635 | [12] = 260000000, |
| 636 | }; |
| 637 | |
| 638 | #define MASK(x) (BIT(x) - 1) |
| 639 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 640 | struct utmi_clk_param { |
| 641 | /* Oscillator Frequency in KHz */ |
| 642 | u32 osc_frequency; |
| 643 | /* UTMIP PLL Enable Delay Count */ |
| 644 | u8 enable_delay_count; |
| 645 | /* UTMIP PLL Stable count */ |
| 646 | u8 stable_count; |
| 647 | /* UTMIP PLL Active delay count */ |
| 648 | u8 active_delay_count; |
| 649 | /* UTMIP PLL Xtal frequency count */ |
| 650 | u8 xtal_freq_count; |
| 651 | }; |
| 652 | |
| 653 | static const struct utmi_clk_param utmi_parameters[] = { |
| 654 | {.osc_frequency = 13000000, .enable_delay_count = 0x02, |
| 655 | .stable_count = 0x33, .active_delay_count = 0x05, |
| 656 | .xtal_freq_count = 0x7F}, |
| 657 | {.osc_frequency = 19200000, .enable_delay_count = 0x03, |
| 658 | .stable_count = 0x4B, .active_delay_count = 0x06, |
| 659 | .xtal_freq_count = 0xBB}, |
| 660 | {.osc_frequency = 12000000, .enable_delay_count = 0x02, |
| 661 | .stable_count = 0x2F, .active_delay_count = 0x04, |
| 662 | .xtal_freq_count = 0x76}, |
| 663 | {.osc_frequency = 26000000, .enable_delay_count = 0x04, |
| 664 | .stable_count = 0x66, .active_delay_count = 0x09, |
| 665 | .xtal_freq_count = 0xFE}, |
| 666 | {.osc_frequency = 16800000, .enable_delay_count = 0x03, |
| 667 | .stable_count = 0x41, .active_delay_count = 0x0A, |
| 668 | .xtal_freq_count = 0xA4}, |
| 669 | }; |
| 670 | |
| 671 | /* peripheral mux definitions */ |
| 672 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 673 | static const char *mux_plld_out0_plld2_out0[] = { |
| 674 | "pll_d_out0", "pll_d2_out0", |
| 675 | }; |
| 676 | #define mux_plld_out0_plld2_out0_idx NULL |
| 677 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 678 | static const char *mux_pllmcp_clkm[] = { |
| 679 | "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", |
| 680 | }; |
| 681 | |
| 682 | static const struct clk_div_table pll_re_div_table[] = { |
| 683 | { .val = 0, .div = 1 }, |
| 684 | { .val = 1, .div = 2 }, |
| 685 | { .val = 2, .div = 3 }, |
| 686 | { .val = 3, .div = 4 }, |
| 687 | { .val = 4, .div = 5 }, |
| 688 | { .val = 5, .div = 6 }, |
| 689 | { .val = 0, .div = 0 }, |
| 690 | }; |
| 691 | |
Peter De Schrijver | 6609dbe | 2013-09-17 15:42:24 +0300 | [diff] [blame] | 692 | static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { |
| 693 | [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true }, |
| 694 | [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true }, |
| 695 | [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true }, |
| 696 | [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true }, |
| 697 | [tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true }, |
| 698 | [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true }, |
| 699 | [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true }, |
| 700 | [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true }, |
| 701 | [tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true }, |
| 702 | [tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true }, |
| 703 | [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true }, |
| 704 | [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true }, |
| 705 | [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true }, |
| 706 | [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true }, |
| 707 | [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true }, |
| 708 | [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true }, |
| 709 | [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true }, |
| 710 | [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true }, |
| 711 | [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true }, |
| 712 | [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true }, |
| 713 | [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true }, |
| 714 | [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true }, |
| 715 | [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true }, |
| 716 | [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true }, |
| 717 | [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true }, |
| 718 | [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true }, |
| 719 | [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true }, |
| 720 | [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true }, |
| 721 | [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true }, |
| 722 | [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true }, |
| 723 | [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true }, |
| 724 | [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true }, |
| 725 | [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true }, |
| 726 | [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true }, |
| 727 | [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true }, |
| 728 | [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true }, |
| 729 | [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true }, |
| 730 | [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true }, |
| 731 | [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true }, |
| 732 | [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true }, |
| 733 | [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true }, |
| 734 | [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true }, |
| 735 | [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true }, |
| 736 | [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true }, |
| 737 | [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true }, |
| 738 | [tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true }, |
| 739 | [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true }, |
| 740 | [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true }, |
| 741 | [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true }, |
| 742 | [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true }, |
| 743 | [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true }, |
| 744 | [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true }, |
| 745 | [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true }, |
| 746 | [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true }, |
| 747 | [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true }, |
| 748 | [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true }, |
| 749 | [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true }, |
| 750 | [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true }, |
| 751 | [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true }, |
| 752 | [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true }, |
| 753 | [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true }, |
| 754 | [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true }, |
| 755 | [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true }, |
| 756 | [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true }, |
| 757 | [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true }, |
| 758 | [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true }, |
| 759 | [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true }, |
| 760 | [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true }, |
| 761 | [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true }, |
| 762 | [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true }, |
| 763 | [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true }, |
| 764 | [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true }, |
| 765 | [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true }, |
| 766 | [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true }, |
| 767 | [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true }, |
| 768 | [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true }, |
| 769 | [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true }, |
| 770 | [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true }, |
| 771 | [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true }, |
| 772 | [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true }, |
| 773 | [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true }, |
| 774 | [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true }, |
| 775 | [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true }, |
| 776 | [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true }, |
| 777 | [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true }, |
| 778 | [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true }, |
| 779 | [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true }, |
| 780 | [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true }, |
| 781 | [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true }, |
| 782 | [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true }, |
| 783 | [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true }, |
| 784 | [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true }, |
| 785 | [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true }, |
| 786 | [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true }, |
| 787 | [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true }, |
| 788 | [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true }, |
| 789 | [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true }, |
| 790 | [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true }, |
| 791 | [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true }, |
| 792 | [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true }, |
| 793 | [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA114_CLK_VI_SENSOR, .present = true }, |
| 794 | [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true }, |
| 795 | [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true }, |
| 796 | [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true }, |
| 797 | [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true }, |
| 798 | [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true }, |
| 799 | [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true }, |
| 800 | [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true }, |
| 801 | [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true }, |
| 802 | [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true }, |
| 803 | [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true }, |
| 804 | [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true }, |
| 805 | [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true }, |
| 806 | [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true }, |
| 807 | [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true }, |
| 808 | [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true }, |
| 809 | [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true }, |
| 810 | [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true }, |
| 811 | [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true }, |
| 812 | [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true }, |
| 813 | [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true }, |
| 814 | [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true }, |
| 815 | [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true }, |
| 816 | [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true }, |
| 817 | [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true }, |
| 818 | [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true }, |
| 819 | [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true }, |
| 820 | [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true }, |
| 821 | [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true }, |
| 822 | [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true }, |
| 823 | [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true }, |
| 824 | [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true }, |
| 825 | [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true }, |
| 826 | [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true }, |
| 827 | [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true }, |
| 828 | [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true }, |
| 829 | [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true }, |
| 830 | [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true }, |
| 831 | [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true }, |
| 832 | [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true }, |
| 833 | [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true }, |
| 834 | [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true }, |
| 835 | [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true }, |
| 836 | [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true }, |
| 837 | [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true }, |
| 838 | [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true }, |
| 839 | [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true }, |
| 840 | [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true }, |
| 841 | [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true }, |
| 842 | [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true }, |
| 843 | [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true }, |
| 844 | [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true }, |
| 845 | [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true }, |
| 846 | [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true }, |
| 847 | [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true }, |
| 848 | [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true }, |
| 849 | [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true }, |
| 850 | [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true }, |
| 851 | [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true }, |
| 852 | [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true }, |
| 853 | [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true }, |
| 854 | [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true }, |
| 855 | [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true }, |
| 856 | [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true }, |
| 857 | [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true }, |
| 858 | [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true }, |
| 859 | [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true }, |
| 860 | [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true }, |
| 861 | [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true }, |
| 862 | [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true }, |
| 863 | [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true }, |
| 864 | [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true }, |
| 865 | [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true }, |
| 866 | [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true }, |
| 867 | [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true }, |
| 868 | [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true }, |
| 869 | [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true }, |
| 870 | }; |
| 871 | |
Peter De Schrijver | 73d37e4 | 2013-10-09 14:47:57 +0300 | [diff] [blame] | 872 | static struct tegra_devclk devclks[] __initdata = { |
| 873 | { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M }, |
| 874 | { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF }, |
| 875 | { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K }, |
| 876 | { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 }, |
| 877 | { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 }, |
| 878 | { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C }, |
| 879 | { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 }, |
| 880 | { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 }, |
| 881 | { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 }, |
| 882 | { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P }, |
| 883 | { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 }, |
| 884 | { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 }, |
| 885 | { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 }, |
| 886 | { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 }, |
| 887 | { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M }, |
| 888 | { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 }, |
| 889 | { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X }, |
| 890 | { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 }, |
| 891 | { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U }, |
| 892 | { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M }, |
| 893 | { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M }, |
| 894 | { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M }, |
| 895 | { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M }, |
| 896 | { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D }, |
| 897 | { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 }, |
| 898 | { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 }, |
| 899 | { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 }, |
| 900 | { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A }, |
| 901 | { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 }, |
| 902 | { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO }, |
| 903 | { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT }, |
| 904 | { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 }, |
| 905 | { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC }, |
| 906 | { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC }, |
| 907 | { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC }, |
| 908 | { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC }, |
| 909 | { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC }, |
| 910 | { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC }, |
| 911 | { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC }, |
| 912 | { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 }, |
| 913 | { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 }, |
| 914 | { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 }, |
| 915 | { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 }, |
| 916 | { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 }, |
| 917 | { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF }, |
| 918 | { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X }, |
| 919 | { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X }, |
| 920 | { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X }, |
| 921 | { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X }, |
| 922 | { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X }, |
| 923 | { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X }, |
| 924 | { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 }, |
| 925 | { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 }, |
| 926 | { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 }, |
| 927 | { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK }, |
| 928 | { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G }, |
| 929 | { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP }, |
| 930 | { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK }, |
| 931 | { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK }, |
| 932 | { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK }, |
| 933 | { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC }, |
| 934 | { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER }, |
| 935 | }; |
| 936 | |
Peter De Schrijver | 343a607 | 2013-09-02 15:22:02 +0300 | [diff] [blame] | 937 | static struct clk **clks; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 938 | |
| 939 | static unsigned long osc_freq; |
| 940 | static unsigned long pll_ref_freq; |
| 941 | |
| 942 | static int __init tegra114_osc_clk_init(void __iomem *clk_base) |
| 943 | { |
| 944 | struct clk *clk; |
| 945 | u32 val, pll_ref_div; |
| 946 | |
| 947 | val = readl_relaxed(clk_base + OSC_CTRL); |
| 948 | |
| 949 | osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; |
| 950 | if (!osc_freq) { |
| 951 | WARN_ON(1); |
| 952 | return -EINVAL; |
| 953 | } |
| 954 | |
| 955 | /* clk_m */ |
| 956 | clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, |
| 957 | osc_freq); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 958 | clks[TEGRA114_CLK_CLK_M] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 959 | |
| 960 | /* pll_ref */ |
| 961 | val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; |
| 962 | pll_ref_div = 1 << val; |
| 963 | clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", |
| 964 | CLK_SET_RATE_PARENT, 1, pll_ref_div); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 965 | clks[TEGRA114_CLK_PLL_REF] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 966 | |
| 967 | pll_ref_freq = osc_freq / pll_ref_div; |
| 968 | |
| 969 | return 0; |
| 970 | } |
| 971 | |
| 972 | static void __init tegra114_fixed_clk_init(void __iomem *clk_base) |
| 973 | { |
| 974 | struct clk *clk; |
| 975 | |
| 976 | /* clk_32k */ |
| 977 | clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, |
| 978 | 32768); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 979 | clks[TEGRA114_CLK_CLK_32K] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 980 | |
| 981 | /* clk_m_div2 */ |
| 982 | clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", |
| 983 | CLK_SET_RATE_PARENT, 1, 2); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 984 | clks[TEGRA114_CLK_CLK_M_DIV2] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 985 | |
| 986 | /* clk_m_div4 */ |
| 987 | clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", |
| 988 | CLK_SET_RATE_PARENT, 1, 4); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 989 | clks[TEGRA114_CLK_CLK_M_DIV4] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 990 | |
| 991 | } |
| 992 | |
| 993 | static __init void tegra114_utmi_param_configure(void __iomem *clk_base) |
| 994 | { |
| 995 | u32 reg; |
| 996 | int i; |
| 997 | |
| 998 | for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { |
| 999 | if (osc_freq == utmi_parameters[i].osc_frequency) |
| 1000 | break; |
| 1001 | } |
| 1002 | |
| 1003 | if (i >= ARRAY_SIZE(utmi_parameters)) { |
| 1004 | pr_err("%s: Unexpected oscillator freq %lu\n", __func__, |
| 1005 | osc_freq); |
| 1006 | return; |
| 1007 | } |
| 1008 | |
| 1009 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); |
| 1010 | |
| 1011 | /* Program UTMIP PLL stable and active counts */ |
| 1012 | /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ |
| 1013 | reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); |
| 1014 | reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); |
| 1015 | |
| 1016 | reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); |
| 1017 | |
| 1018 | reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. |
| 1019 | active_delay_count); |
| 1020 | |
| 1021 | /* Remove power downs from UTMIP PLL control bits */ |
| 1022 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; |
| 1023 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; |
| 1024 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; |
| 1025 | |
| 1026 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); |
| 1027 | |
| 1028 | /* Program UTMIP PLL delay and oscillator frequency counts */ |
| 1029 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); |
| 1030 | reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); |
| 1031 | |
| 1032 | reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. |
| 1033 | enable_delay_count); |
| 1034 | |
| 1035 | reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); |
| 1036 | reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. |
| 1037 | xtal_freq_count); |
| 1038 | |
| 1039 | /* Remove power downs from UTMIP PLL control bits */ |
| 1040 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; |
| 1041 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; |
| 1042 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; |
| 1043 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; |
| 1044 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); |
| 1045 | |
| 1046 | /* Setup HW control of UTMIPLL */ |
| 1047 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); |
| 1048 | reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; |
| 1049 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; |
| 1050 | reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; |
| 1051 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); |
| 1052 | |
| 1053 | reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); |
| 1054 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; |
| 1055 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; |
| 1056 | writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); |
| 1057 | |
| 1058 | udelay(1); |
| 1059 | |
| 1060 | /* Setup SW override of UTMIPLL assuming USB2.0 |
| 1061 | ports are assigned to USB2 */ |
| 1062 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); |
| 1063 | reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; |
| 1064 | reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; |
| 1065 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); |
| 1066 | |
| 1067 | udelay(1); |
| 1068 | |
| 1069 | /* Enable HW control UTMIPLL */ |
| 1070 | reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); |
| 1071 | reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; |
| 1072 | writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); |
| 1073 | } |
| 1074 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1075 | static void __init tegra114_pll_init(void __iomem *clk_base, |
| 1076 | void __iomem *pmc) |
| 1077 | { |
| 1078 | u32 val; |
| 1079 | struct clk *clk; |
| 1080 | |
| 1081 | /* PLLC */ |
Peter De Schrijver | 04edb09 | 2013-09-06 14:37:37 +0300 | [diff] [blame] | 1082 | clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1083 | pmc, 0, &pll_c_params, NULL); |
Peter De Schrijver | 04edb09 | 2013-09-06 14:37:37 +0300 | [diff] [blame] | 1084 | clks[TEGRA114_CLK_PLL_C] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1085 | |
Peter De Schrijver | 04edb09 | 2013-09-06 14:37:37 +0300 | [diff] [blame] | 1086 | /* PLLC_OUT1 */ |
| 1087 | clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", |
| 1088 | clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, |
| 1089 | 8, 8, 1, NULL); |
| 1090 | clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", |
| 1091 | clk_base + PLLC_OUT, 1, 0, |
| 1092 | CLK_SET_RATE_PARENT, 0, NULL); |
Peter De Schrijver | 04edb09 | 2013-09-06 14:37:37 +0300 | [diff] [blame] | 1093 | clks[TEGRA114_CLK_PLL_C_OUT1] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1094 | |
| 1095 | /* PLLC2 */ |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1096 | clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, |
| 1097 | &pll_c2_params, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1098 | clks[TEGRA114_CLK_PLL_C2] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1099 | |
| 1100 | /* PLLC3 */ |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1101 | clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, |
| 1102 | &pll_c3_params, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1103 | clks[TEGRA114_CLK_PLL_C3] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1104 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1105 | /* PLLM */ |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1106 | clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1107 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, |
| 1108 | &pll_m_params, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1109 | clks[TEGRA114_CLK_PLL_M] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1110 | |
| 1111 | /* PLLM_OUT1 */ |
| 1112 | clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", |
| 1113 | clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, |
| 1114 | 8, 8, 1, NULL); |
| 1115 | clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", |
| 1116 | clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | |
| 1117 | CLK_SET_RATE_PARENT, 0, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1118 | clks[TEGRA114_CLK_PLL_M_OUT1] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1119 | |
| 1120 | /* PLLM_UD */ |
| 1121 | clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", |
| 1122 | CLK_SET_RATE_PARENT, 1, 1); |
| 1123 | |
| 1124 | /* PLLX */ |
Peter De Schrijver | 04edb09 | 2013-09-06 14:37:37 +0300 | [diff] [blame] | 1125 | clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1126 | pmc, CLK_IGNORE_UNUSED, &pll_x_params, NULL); |
Peter De Schrijver | 04edb09 | 2013-09-06 14:37:37 +0300 | [diff] [blame] | 1127 | clks[TEGRA114_CLK_PLL_X] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1128 | |
| 1129 | /* PLLX_OUT0 */ |
| 1130 | clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", |
| 1131 | CLK_SET_RATE_PARENT, 1, 2); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1132 | clks[TEGRA114_CLK_PLL_X_OUT0] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1133 | |
| 1134 | /* PLLU */ |
| 1135 | val = readl(clk_base + pll_u_params.base_reg); |
| 1136 | val &= ~BIT(24); /* disable PLLU_OVERRIDE */ |
| 1137 | writel(val, clk_base + pll_u_params.base_reg); |
| 1138 | |
| 1139 | clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1140 | &pll_u_params, &pll_u_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1141 | clks[TEGRA114_CLK_PLL_U] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1142 | |
| 1143 | tegra114_utmi_param_configure(clk_base); |
| 1144 | |
| 1145 | /* PLLU_480M */ |
| 1146 | clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", |
| 1147 | CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, |
| 1148 | 22, 0, &pll_u_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1149 | clks[TEGRA114_CLK_PLL_U_480M] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1150 | |
| 1151 | /* PLLU_60M */ |
| 1152 | clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", |
| 1153 | CLK_SET_RATE_PARENT, 1, 8); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1154 | clks[TEGRA114_CLK_PLL_U_60M] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1155 | |
| 1156 | /* PLLU_48M */ |
| 1157 | clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", |
| 1158 | CLK_SET_RATE_PARENT, 1, 10); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1159 | clks[TEGRA114_CLK_PLL_U_48M] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1160 | |
| 1161 | /* PLLU_12M */ |
| 1162 | clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", |
| 1163 | CLK_SET_RATE_PARENT, 1, 40); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1164 | clks[TEGRA114_CLK_PLL_U_12M] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1165 | |
| 1166 | /* PLLD */ |
| 1167 | clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1168 | &pll_d_params, &pll_d_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1169 | clks[TEGRA114_CLK_PLL_D] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1170 | |
| 1171 | /* PLLD_OUT0 */ |
| 1172 | clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", |
| 1173 | CLK_SET_RATE_PARENT, 1, 2); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1174 | clks[TEGRA114_CLK_PLL_D_OUT0] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1175 | |
| 1176 | /* PLLD2 */ |
| 1177 | clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1178 | &pll_d2_params, &pll_d2_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1179 | clks[TEGRA114_CLK_PLL_D2] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1180 | |
| 1181 | /* PLLD2_OUT0 */ |
| 1182 | clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", |
| 1183 | CLK_SET_RATE_PARENT, 1, 2); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1184 | clks[TEGRA114_CLK_PLL_D2_OUT0] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1185 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1186 | /* PLLRE */ |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1187 | clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1188 | 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1189 | clks[TEGRA114_CLK_PLL_RE_VCO] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1190 | |
| 1191 | clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, |
| 1192 | clk_base + PLLRE_BASE, 16, 4, 0, |
| 1193 | pll_re_div_table, &pll_re_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1194 | clks[TEGRA114_CLK_PLL_RE_OUT] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1195 | |
| 1196 | /* PLLE */ |
Peter De Schrijver | 8e9cc80 | 2013-11-25 14:44:13 +0200 | [diff] [blame] | 1197 | clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref", |
Peter De Schrijver | ebe142b | 2013-10-04 17:28:34 +0300 | [diff] [blame] | 1198 | clk_base, 0, &pll_e_params, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1199 | clks[TEGRA114_CLK_PLL_E_OUT0] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1200 | } |
| 1201 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1202 | static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", |
| 1203 | "clk_m_div4", "extern1", |
| 1204 | }; |
| 1205 | |
| 1206 | static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", |
| 1207 | "clk_m_div4", "extern2", |
| 1208 | }; |
| 1209 | |
| 1210 | static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", |
| 1211 | "clk_m_div4", "extern3", |
| 1212 | }; |
| 1213 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1214 | static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) |
| 1215 | { |
| 1216 | struct clk *clk; |
| 1217 | |
| 1218 | /* clk_out_1 */ |
| 1219 | clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 1220 | ARRAY_SIZE(clk_out1_parents), |
| 1221 | CLK_SET_RATE_NO_REPARENT, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1222 | pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, |
| 1223 | &clk_out_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1224 | clks[TEGRA114_CLK_CLK_OUT_1_MUX] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1225 | clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, |
| 1226 | pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, |
| 1227 | &clk_out_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1228 | clks[TEGRA114_CLK_CLK_OUT_1] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1229 | |
| 1230 | /* clk_out_2 */ |
| 1231 | clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 1232 | ARRAY_SIZE(clk_out2_parents), |
| 1233 | CLK_SET_RATE_NO_REPARENT, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1234 | pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, |
| 1235 | &clk_out_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1236 | clks[TEGRA114_CLK_CLK_OUT_2_MUX] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1237 | clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, |
| 1238 | pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, |
| 1239 | &clk_out_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1240 | clks[TEGRA114_CLK_CLK_OUT_2] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1241 | |
| 1242 | /* clk_out_3 */ |
| 1243 | clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 1244 | ARRAY_SIZE(clk_out3_parents), |
| 1245 | CLK_SET_RATE_NO_REPARENT, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1246 | pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, |
| 1247 | &clk_out_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1248 | clks[TEGRA114_CLK_CLK_OUT_3_MUX] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1249 | clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, |
| 1250 | pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, |
| 1251 | &clk_out_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1252 | clks[TEGRA114_CLK_CLK_OUT_3] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1253 | |
| 1254 | /* blink */ |
Alexandre Courbot | 9139227 | 2013-05-26 11:56:31 +0900 | [diff] [blame] | 1255 | /* clear the blink timer register to directly output clk_32k */ |
| 1256 | writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1257 | clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, |
| 1258 | pmc_base + PMC_DPD_PADS_ORIDE, |
| 1259 | PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); |
| 1260 | clk = clk_register_gate(NULL, "blink", "blink_override", 0, |
| 1261 | pmc_base + PMC_CTRL, |
| 1262 | PMC_CTRL_BLINK_ENB, 0, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1263 | clks[TEGRA114_CLK_BLINK] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1264 | |
| 1265 | } |
| 1266 | |
| 1267 | static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", |
Peter De Schrijver | 29b0944 | 2013-06-05 17:29:28 +0300 | [diff] [blame] | 1268 | "pll_p", "pll_p_out2", "unused", |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1269 | "clk_32k", "pll_m_out1" }; |
| 1270 | |
| 1271 | static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", |
| 1272 | "pll_p", "pll_p_out4", "unused", |
| 1273 | "unused", "pll_x" }; |
| 1274 | |
| 1275 | static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", |
| 1276 | "pll_p", "pll_p_out4", "unused", |
| 1277 | "unused", "pll_x", "pll_x_out0" }; |
| 1278 | |
| 1279 | static void __init tegra114_super_clk_init(void __iomem *clk_base) |
| 1280 | { |
| 1281 | struct clk *clk; |
| 1282 | |
| 1283 | /* CCLKG */ |
| 1284 | clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, |
| 1285 | ARRAY_SIZE(cclk_g_parents), |
| 1286 | CLK_SET_RATE_PARENT, |
| 1287 | clk_base + CCLKG_BURST_POLICY, |
| 1288 | 0, 4, 0, 0, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1289 | clks[TEGRA114_CLK_CCLK_G] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1290 | |
| 1291 | /* CCLKLP */ |
| 1292 | clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, |
| 1293 | ARRAY_SIZE(cclk_lp_parents), |
| 1294 | CLK_SET_RATE_PARENT, |
| 1295 | clk_base + CCLKLP_BURST_POLICY, |
| 1296 | 0, 4, 8, 9, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1297 | clks[TEGRA114_CLK_CCLK_LP] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1298 | |
| 1299 | /* SCLK */ |
| 1300 | clk = tegra_clk_register_super_mux("sclk", sclk_parents, |
| 1301 | ARRAY_SIZE(sclk_parents), |
| 1302 | CLK_SET_RATE_PARENT, |
| 1303 | clk_base + SCLK_BURST_POLICY, |
| 1304 | 0, 4, 0, 0, NULL); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1305 | clks[TEGRA114_CLK_SCLK] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1306 | |
| 1307 | /* HCLK */ |
| 1308 | clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, |
| 1309 | clk_base + SYSTEM_CLK_RATE, 4, 2, 0, |
| 1310 | &sysrate_lock); |
| 1311 | clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | |
| 1312 | CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, |
| 1313 | 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1314 | clks[TEGRA114_CLK_HCLK] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1315 | |
| 1316 | /* PCLK */ |
| 1317 | clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, |
| 1318 | clk_base + SYSTEM_CLK_RATE, 0, 2, 0, |
| 1319 | &sysrate_lock); |
| 1320 | clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | |
| 1321 | CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, |
| 1322 | 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1323 | clks[TEGRA114_CLK_PCLK] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1324 | } |
| 1325 | |
Peter De Schrijver | 76ebc13 | 2013-09-04 17:04:19 +0300 | [diff] [blame^] | 1326 | static __init void tegra114_periph_clk_init(void __iomem *clk_base, |
| 1327 | void __iomem *pmc_base) |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1328 | { |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1329 | struct clk *clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1330 | u32 val; |
| 1331 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1332 | /* xusb_hs_src */ |
| 1333 | val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); |
| 1334 | val |= BIT(25); /* always select PLLU_60M */ |
| 1335 | writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); |
| 1336 | |
| 1337 | clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, |
| 1338 | 1, 1); |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1339 | clks[TEGRA114_CLK_XUSB_HS_SRC] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1340 | |
Peter De Schrijver | 76ebc13 | 2013-09-04 17:04:19 +0300 | [diff] [blame^] | 1341 | /* dsia mux */ |
| 1342 | clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, |
| 1343 | ARRAY_SIZE(mux_plld_out0_plld2_out0), |
| 1344 | CLK_SET_RATE_NO_REPARENT, |
| 1345 | clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); |
| 1346 | clks[TEGRA114_CLK_DSIA_MUX] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1347 | |
Peter De Schrijver | 76ebc13 | 2013-09-04 17:04:19 +0300 | [diff] [blame^] | 1348 | /* dsib mux */ |
| 1349 | clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, |
| 1350 | ARRAY_SIZE(mux_plld_out0_plld2_out0), |
| 1351 | CLK_SET_RATE_NO_REPARENT, |
| 1352 | clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); |
| 1353 | clks[TEGRA114_CLK_DSIB_MUX] = clk; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1354 | |
Peter De Schrijver | 76ebc13 | 2013-09-04 17:04:19 +0300 | [diff] [blame^] | 1355 | /* emc mux */ |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1356 | clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 1357 | ARRAY_SIZE(mux_pllmcp_clkm), |
| 1358 | CLK_SET_RATE_NO_REPARENT, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1359 | clk_base + CLK_SOURCE_EMC, |
| 1360 | 29, 3, 0, NULL); |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1361 | |
Peter De Schrijver | 76ebc13 | 2013-09-04 17:04:19 +0300 | [diff] [blame^] | 1362 | tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks, |
| 1363 | &pll_p_params); |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1364 | } |
| 1365 | |
Joseph Lo | 31972fd | 2013-05-20 18:39:28 +0800 | [diff] [blame] | 1366 | /* Tegra114 CPU clock and reset control functions */ |
| 1367 | static void tegra114_wait_cpu_in_reset(u32 cpu) |
| 1368 | { |
| 1369 | unsigned int reg; |
| 1370 | |
| 1371 | do { |
| 1372 | reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); |
| 1373 | cpu_relax(); |
| 1374 | } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ |
| 1375 | } |
| 1376 | static void tegra114_disable_cpu_clock(u32 cpu) |
| 1377 | { |
| 1378 | /* flow controller would take care in the power sequence. */ |
| 1379 | } |
| 1380 | |
Joseph Lo | ad7d114 | 2013-07-03 17:50:44 +0800 | [diff] [blame] | 1381 | #ifdef CONFIG_PM_SLEEP |
| 1382 | static void tegra114_cpu_clock_suspend(void) |
| 1383 | { |
| 1384 | /* switch coresite to clk_m, save off original source */ |
| 1385 | tegra114_cpu_clk_sctx.clk_csite_src = |
| 1386 | readl(clk_base + CLK_SOURCE_CSITE); |
| 1387 | writel(3 << 30, clk_base + CLK_SOURCE_CSITE); |
Joseph Lo | 0017f44 | 2013-08-12 17:40:02 +0800 | [diff] [blame] | 1388 | |
| 1389 | tegra114_cpu_clk_sctx.cclkg_burst = |
| 1390 | readl(clk_base + CCLKG_BURST_POLICY); |
| 1391 | tegra114_cpu_clk_sctx.cclkg_divider = |
| 1392 | readl(clk_base + CCLKG_BURST_POLICY + 4); |
Joseph Lo | ad7d114 | 2013-07-03 17:50:44 +0800 | [diff] [blame] | 1393 | } |
| 1394 | |
| 1395 | static void tegra114_cpu_clock_resume(void) |
| 1396 | { |
| 1397 | writel(tegra114_cpu_clk_sctx.clk_csite_src, |
| 1398 | clk_base + CLK_SOURCE_CSITE); |
Joseph Lo | 0017f44 | 2013-08-12 17:40:02 +0800 | [diff] [blame] | 1399 | |
| 1400 | writel(tegra114_cpu_clk_sctx.cclkg_burst, |
| 1401 | clk_base + CCLKG_BURST_POLICY); |
| 1402 | writel(tegra114_cpu_clk_sctx.cclkg_divider, |
| 1403 | clk_base + CCLKG_BURST_POLICY + 4); |
Joseph Lo | ad7d114 | 2013-07-03 17:50:44 +0800 | [diff] [blame] | 1404 | } |
| 1405 | #endif |
| 1406 | |
Joseph Lo | 31972fd | 2013-05-20 18:39:28 +0800 | [diff] [blame] | 1407 | static struct tegra_cpu_car_ops tegra114_cpu_car_ops = { |
| 1408 | .wait_for_reset = tegra114_wait_cpu_in_reset, |
| 1409 | .disable_clock = tegra114_disable_cpu_clock, |
Joseph Lo | ad7d114 | 2013-07-03 17:50:44 +0800 | [diff] [blame] | 1410 | #ifdef CONFIG_PM_SLEEP |
| 1411 | .suspend = tegra114_cpu_clock_suspend, |
| 1412 | .resume = tegra114_cpu_clock_resume, |
| 1413 | #endif |
Joseph Lo | 31972fd | 2013-05-20 18:39:28 +0800 | [diff] [blame] | 1414 | }; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1415 | |
| 1416 | static const struct of_device_id pmc_match[] __initconst = { |
| 1417 | { .compatible = "nvidia,tegra114-pmc" }, |
| 1418 | {}, |
| 1419 | }; |
| 1420 | |
Paul Walmsley | 9e60121 | 2013-06-07 06:19:01 -0600 | [diff] [blame] | 1421 | /* |
| 1422 | * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5 |
| 1423 | * breaks |
| 1424 | */ |
Sachin Kamat | 056dfcf | 2013-08-08 09:55:47 +0530 | [diff] [blame] | 1425 | static struct tegra_clk_init_table init_table[] __initdata = { |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1426 | {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0}, |
| 1427 | {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0}, |
| 1428 | {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0}, |
| 1429 | {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0}, |
| 1430 | {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1}, |
| 1431 | {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1}, |
| 1432 | {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1}, |
| 1433 | {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1}, |
| 1434 | {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1}, |
| 1435 | {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, |
| 1436 | {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, |
| 1437 | {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, |
| 1438 | {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, |
| 1439 | {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, |
Andrew Chew | 897e1dd | 2013-08-07 19:25:09 +0800 | [diff] [blame] | 1440 | {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1441 | {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, |
| 1442 | {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, |
Thierry Reding | f67a8d2 | 2013-10-02 23:12:40 +0200 | [diff] [blame] | 1443 | {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, |
| 1444 | {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, |
Mark Zhang | fc20eef | 2013-08-07 19:25:08 +0800 | [diff] [blame] | 1445 | |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1446 | /* This MUST be the last entry. */ |
| 1447 | {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1448 | }; |
| 1449 | |
| 1450 | static void __init tegra114_clock_apply_init_table(void) |
| 1451 | { |
Peter De Schrijver | c9e2d69 | 2013-08-22 15:27:46 +0300 | [diff] [blame] | 1452 | tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX); |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1453 | } |
| 1454 | |
Paul Walmsley | 25c9ded | 2013-06-07 06:18:58 -0600 | [diff] [blame] | 1455 | |
| 1456 | /** |
| 1457 | * tegra114_car_barrier - wait for pending writes to the CAR to complete |
| 1458 | * |
| 1459 | * Wait for any outstanding writes to the CAR MMIO space from this CPU |
| 1460 | * to complete before continuing execution. No return value. |
| 1461 | */ |
| 1462 | static void tegra114_car_barrier(void) |
| 1463 | { |
| 1464 | wmb(); /* probably unnecessary */ |
| 1465 | readl_relaxed(clk_base + CPU_FINETRIM_SELECT); |
| 1466 | } |
| 1467 | |
| 1468 | /** |
| 1469 | * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays |
| 1470 | * |
| 1471 | * When the CPU rail voltage is in the high-voltage range, use the |
| 1472 | * built-in hardwired clock propagation delays in the CPU clock |
| 1473 | * shaper. No return value. |
| 1474 | */ |
| 1475 | void tegra114_clock_tune_cpu_trimmers_high(void) |
| 1476 | { |
| 1477 | u32 select = 0; |
| 1478 | |
| 1479 | /* Use hardwired rise->rise & fall->fall clock propagation delays */ |
| 1480 | select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | |
| 1481 | CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | |
| 1482 | CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); |
| 1483 | writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); |
| 1484 | |
| 1485 | tegra114_car_barrier(); |
| 1486 | } |
| 1487 | EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high); |
| 1488 | |
| 1489 | /** |
| 1490 | * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays |
| 1491 | * |
| 1492 | * When the CPU rail voltage is in the low-voltage range, use the |
| 1493 | * extended clock propagation delays set by |
| 1494 | * tegra114_clock_tune_cpu_trimmers_init(). The intention is to |
| 1495 | * maintain the input clock duty cycle that the FCPU subsystem |
| 1496 | * expects. No return value. |
| 1497 | */ |
| 1498 | void tegra114_clock_tune_cpu_trimmers_low(void) |
| 1499 | { |
| 1500 | u32 select = 0; |
| 1501 | |
| 1502 | /* |
| 1503 | * Use software-specified rise->rise & fall->fall clock |
| 1504 | * propagation delays (from |
| 1505 | * tegra114_clock_tune_cpu_trimmers_init() |
| 1506 | */ |
| 1507 | select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | |
| 1508 | CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | |
| 1509 | CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); |
| 1510 | writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); |
| 1511 | |
| 1512 | tegra114_car_barrier(); |
| 1513 | } |
| 1514 | EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low); |
| 1515 | |
| 1516 | /** |
| 1517 | * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays |
| 1518 | * |
| 1519 | * Program extended clock propagation delays into the FCPU clock |
| 1520 | * shaper and enable them. XXX Define the purpose - peak current |
| 1521 | * reduction? No return value. |
| 1522 | */ |
| 1523 | /* XXX Initial voltage rail state assumption issues? */ |
| 1524 | void tegra114_clock_tune_cpu_trimmers_init(void) |
| 1525 | { |
| 1526 | u32 dr = 0, r = 0; |
| 1527 | |
| 1528 | /* Increment the rise->rise clock delay by four steps */ |
| 1529 | r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK | |
| 1530 | CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK | |
| 1531 | CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK); |
| 1532 | writel_relaxed(r, clk_base + CPU_FINETRIM_R); |
| 1533 | |
| 1534 | /* |
| 1535 | * Use the rise->rise clock propagation delay specified in the |
| 1536 | * r field |
| 1537 | */ |
| 1538 | dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | |
| 1539 | CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | |
| 1540 | CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); |
| 1541 | writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); |
| 1542 | |
| 1543 | tegra114_clock_tune_cpu_trimmers_low(); |
| 1544 | } |
| 1545 | EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); |
| 1546 | |
Paul Walmsley | 1c472d8 | 2013-06-07 06:19:09 -0600 | [diff] [blame] | 1547 | /** |
| 1548 | * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset |
| 1549 | * |
| 1550 | * Assert the reset line of the DFLL's DVCO. No return value. |
| 1551 | */ |
| 1552 | void tegra114_clock_assert_dfll_dvco_reset(void) |
| 1553 | { |
| 1554 | u32 v; |
| 1555 | |
| 1556 | v = readl_relaxed(clk_base + RST_DFLL_DVCO); |
| 1557 | v |= (1 << DVFS_DFLL_RESET_SHIFT); |
| 1558 | writel_relaxed(v, clk_base + RST_DFLL_DVCO); |
| 1559 | tegra114_car_barrier(); |
| 1560 | } |
| 1561 | EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); |
| 1562 | |
| 1563 | /** |
| 1564 | * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset |
| 1565 | * |
| 1566 | * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to |
| 1567 | * operate. No return value. |
| 1568 | */ |
| 1569 | void tegra114_clock_deassert_dfll_dvco_reset(void) |
| 1570 | { |
| 1571 | u32 v; |
| 1572 | |
| 1573 | v = readl_relaxed(clk_base + RST_DFLL_DVCO); |
| 1574 | v &= ~(1 << DVFS_DFLL_RESET_SHIFT); |
| 1575 | writel_relaxed(v, clk_base + RST_DFLL_DVCO); |
| 1576 | tegra114_car_barrier(); |
| 1577 | } |
| 1578 | EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); |
| 1579 | |
Prashant Gaikwad | 061cec9 | 2013-05-27 13:10:09 +0530 | [diff] [blame] | 1580 | static void __init tegra114_clock_init(struct device_node *np) |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1581 | { |
| 1582 | struct device_node *node; |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1583 | |
| 1584 | clk_base = of_iomap(np, 0); |
| 1585 | if (!clk_base) { |
| 1586 | pr_err("ioremap tegra114 CAR failed\n"); |
| 1587 | return; |
| 1588 | } |
| 1589 | |
| 1590 | node = of_find_matching_node(NULL, pmc_match); |
| 1591 | if (!node) { |
| 1592 | pr_err("Failed to find pmc node\n"); |
| 1593 | WARN_ON(1); |
| 1594 | return; |
| 1595 | } |
| 1596 | |
| 1597 | pmc_base = of_iomap(node, 0); |
| 1598 | if (!pmc_base) { |
| 1599 | pr_err("Can't map pmc registers\n"); |
| 1600 | WARN_ON(1); |
| 1601 | return; |
| 1602 | } |
| 1603 | |
Peter De Schrijver | 343a607 | 2013-09-02 15:22:02 +0300 | [diff] [blame] | 1604 | clks = tegra_clk_init(TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_PERIPH_BANKS); |
| 1605 | if (!clks) |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1606 | return; |
| 1607 | |
Peter De Schrijver | 343a607 | 2013-09-02 15:22:02 +0300 | [diff] [blame] | 1608 | if (tegra114_osc_clk_init(clk_base) < 0) |
Peter De Schrijver | d5ff89a | 2013-08-22 18:44:06 +0300 | [diff] [blame] | 1609 | return; |
| 1610 | |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1611 | tegra114_fixed_clk_init(clk_base); |
| 1612 | tegra114_pll_init(clk_base, pmc_base); |
Peter De Schrijver | 76ebc13 | 2013-09-04 17:04:19 +0300 | [diff] [blame^] | 1613 | tegra114_periph_clk_init(clk_base, pmc_base); |
Peter De Schrijver | 6609dbe | 2013-09-17 15:42:24 +0300 | [diff] [blame] | 1614 | tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params); |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1615 | tegra114_pmc_clk_init(pmc_base); |
| 1616 | tegra114_super_clk_init(clk_base); |
| 1617 | |
Peter De Schrijver | 343a607 | 2013-09-02 15:22:02 +0300 | [diff] [blame] | 1618 | tegra_add_of_provider(np); |
Peter De Schrijver | 73d37e4 | 2013-10-09 14:47:57 +0300 | [diff] [blame] | 1619 | tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); |
Peter De Schrijver | 2cb5efe | 2013-04-03 17:40:45 +0300 | [diff] [blame] | 1620 | |
| 1621 | tegra_clk_apply_init_table = tegra114_clock_apply_init_table; |
| 1622 | |
| 1623 | tegra_cpu_car_ops = &tegra114_cpu_car_ops; |
| 1624 | } |
Prashant Gaikwad | 061cec9 | 2013-05-27 13:10:09 +0530 | [diff] [blame] | 1625 | CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init); |