Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 28 | #include <linux/cpufreq.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 29 | #include "i915_drv.h" |
| 30 | #include "intel_drv.h" |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 31 | #include "../../../platform/x86/intel_ips.h" |
| 32 | #include <linux/module.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 33 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 34 | /** |
| 35 | * RC6 is a special power stage which allows the GPU to enter an very |
| 36 | * low-voltage mode when idle, using down to 0V while at this stage. This |
| 37 | * stage is entered automatically when the GPU is idle when RC6 support is |
| 38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
| 39 | * |
| 40 | * There are different RC6 modes available in Intel GPU, which differentiate |
| 41 | * among each other with the latency required to enter and leave RC6 and |
| 42 | * voltage consumed by the GPU in different states. |
| 43 | * |
| 44 | * The combination of the following flags define which states GPU is allowed |
| 45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
| 46 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
| 47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
| 48 | * which brings the most power savings; deeper states save more power, but |
| 49 | * require higher latency to switch to and wake up. |
| 50 | */ |
| 51 | #define INTEL_RC6_ENABLE (1<<0) |
| 52 | #define INTEL_RC6p_ENABLE (1<<1) |
| 53 | #define INTEL_RC6pp_ENABLE (1<<2) |
| 54 | |
Damien Lespiau | da2078c | 2013-02-13 15:27:27 +0000 | [diff] [blame] | 55 | static void gen9_init_clock_gating(struct drm_device *dev) |
| 56 | { |
Damien Lespiau | acd5c34 | 2014-03-26 16:55:46 +0000 | [diff] [blame] | 57 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 58 | |
Damien Lespiau | 77719d2 | 2015-02-09 19:33:13 +0000 | [diff] [blame] | 59 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
| 60 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
| 61 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); |
Nick Hoath | 6381b55 | 2015-07-14 14:41:15 +0100 | [diff] [blame] | 62 | |
| 63 | /* WaDisableKillLogic:bxt,skl */ |
| 64 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
| 65 | ECOCHK_DIS_TLB); |
Damien Lespiau | 77719d2 | 2015-02-09 19:33:13 +0000 | [diff] [blame] | 66 | } |
Damien Lespiau | 91e41d1 | 2014-03-26 17:42:50 +0000 | [diff] [blame] | 67 | |
Damien Lespiau | 45db219 | 2015-02-09 19:33:09 +0000 | [diff] [blame] | 68 | static void skl_init_clock_gating(struct drm_device *dev) |
Damien Lespiau | da2078c | 2013-02-13 15:27:27 +0000 | [diff] [blame] | 69 | { |
Damien Lespiau | acd5c34 | 2014-03-26 16:55:46 +0000 | [diff] [blame] | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 3ca5da4 | 2014-03-26 18:18:01 +0000 | [diff] [blame] | 71 | |
Damien Lespiau | 77719d2 | 2015-02-09 19:33:13 +0000 | [diff] [blame] | 72 | gen9_init_clock_gating(dev); |
| 73 | |
Damien Lespiau | 2caa3b2 | 2015-02-09 19:33:20 +0000 | [diff] [blame] | 74 | if (INTEL_REVID(dev) <= SKL_REVID_D0) { |
Damien Lespiau | 81e231a | 2015-02-09 19:33:19 +0000 | [diff] [blame] | 75 | /* WaDisableHDCInvalidation:skl */ |
| 76 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
| 77 | BDW_DISABLE_HDC_INVALIDATION); |
| 78 | |
Damien Lespiau | 2caa3b2 | 2015-02-09 19:33:20 +0000 | [diff] [blame] | 79 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
| 80 | I915_WRITE(FF_SLICE_CS_CHICKEN2, |
Damien Lespiau | f1d3d34 | 2015-05-06 14:36:27 +0100 | [diff] [blame] | 81 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); |
Damien Lespiau | 2caa3b2 | 2015-02-09 19:33:20 +0000 | [diff] [blame] | 82 | } |
Damien Lespiau | 81e231a | 2015-02-09 19:33:19 +0000 | [diff] [blame] | 83 | |
Arun Siluvery | a4106a7 | 2015-07-14 15:01:29 +0100 | [diff] [blame] | 84 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
| 85 | * involving this register should also be added to WA batch as required. |
| 86 | */ |
Damien Lespiau | 8bc0ccf | 2015-02-09 19:33:18 +0000 | [diff] [blame] | 87 | if (INTEL_REVID(dev) <= SKL_REVID_E0) |
| 88 | /* WaDisableLSQCROPERFforOCL:skl */ |
| 89 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | |
| 90 | GEN8_LQSC_RO_PERF_DIS); |
Arun Siluvery | 245d966 | 2015-08-03 20:24:56 +0100 | [diff] [blame] | 91 | |
| 92 | /* WaEnableGapsTsvCreditFix:skl */ |
| 93 | if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) { |
| 94 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
| 95 | GEN9_GAPS_TSV_CREDIT_DISABLE)); |
| 96 | } |
Damien Lespiau | da2078c | 2013-02-13 15:27:27 +0000 | [diff] [blame] | 97 | } |
| 98 | |
Imre Deak | a82abe4 | 2015-03-27 14:00:04 +0200 | [diff] [blame] | 99 | static void bxt_init_clock_gating(struct drm_device *dev) |
| 100 | { |
Imre Deak | 32608ca | 2015-03-11 11:10:27 +0200 | [diff] [blame] | 101 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 102 | |
Imre Deak | a82abe4 | 2015-03-27 14:00:04 +0200 | [diff] [blame] | 103 | gen9_init_clock_gating(dev); |
Imre Deak | 32608ca | 2015-03-11 11:10:27 +0200 | [diff] [blame] | 104 | |
Nick Hoath | a754615 | 2015-06-29 14:07:32 +0100 | [diff] [blame] | 105 | /* WaDisableSDEUnitClockGating:bxt */ |
| 106 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 107 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
| 108 | |
Imre Deak | 32608ca | 2015-03-11 11:10:27 +0200 | [diff] [blame] | 109 | /* |
| 110 | * FIXME: |
Ben Widawsky | 868434c | 2015-03-11 10:49:32 +0200 | [diff] [blame] | 111 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
Imre Deak | 32608ca | 2015-03-11 11:10:27 +0200 | [diff] [blame] | 112 | */ |
Imre Deak | 32608ca | 2015-03-11 11:10:27 +0200 | [diff] [blame] | 113 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
Ben Widawsky | 868434c | 2015-03-11 10:49:32 +0200 | [diff] [blame] | 114 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
Imre Deak | 32608ca | 2015-03-11 11:10:27 +0200 | [diff] [blame] | 115 | |
Arun Siluvery | aa66c50 | 2015-09-25 14:33:40 +0100 | [diff] [blame] | 116 | /* WaStoreMultiplePTEenable:bxt */ |
| 117 | /* This is a requirement according to Hardware specification */ |
| 118 | if (INTEL_REVID(dev) == BXT_REVID_A0) |
Nick Hoath | a754615 | 2015-06-29 14:07:32 +0100 | [diff] [blame] | 119 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
Arun Siluvery | 5b88aba | 2015-09-08 10:31:49 +0100 | [diff] [blame] | 120 | |
| 121 | /* WaSetClckGatingDisableMedia:bxt */ |
| 122 | if (INTEL_REVID(dev) == BXT_REVID_A0) { |
| 123 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
| 124 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); |
| 125 | } |
Imre Deak | a82abe4 | 2015-03-27 14:00:04 +0200 | [diff] [blame] | 126 | } |
| 127 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 128 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
| 129 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 130 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 131 | u32 tmp; |
| 132 | |
| 133 | tmp = I915_READ(CLKCFG); |
| 134 | |
| 135 | switch (tmp & CLKCFG_FSB_MASK) { |
| 136 | case CLKCFG_FSB_533: |
| 137 | dev_priv->fsb_freq = 533; /* 133*4 */ |
| 138 | break; |
| 139 | case CLKCFG_FSB_800: |
| 140 | dev_priv->fsb_freq = 800; /* 200*4 */ |
| 141 | break; |
| 142 | case CLKCFG_FSB_667: |
| 143 | dev_priv->fsb_freq = 667; /* 167*4 */ |
| 144 | break; |
| 145 | case CLKCFG_FSB_400: |
| 146 | dev_priv->fsb_freq = 400; /* 100*4 */ |
| 147 | break; |
| 148 | } |
| 149 | |
| 150 | switch (tmp & CLKCFG_MEM_MASK) { |
| 151 | case CLKCFG_MEM_533: |
| 152 | dev_priv->mem_freq = 533; |
| 153 | break; |
| 154 | case CLKCFG_MEM_667: |
| 155 | dev_priv->mem_freq = 667; |
| 156 | break; |
| 157 | case CLKCFG_MEM_800: |
| 158 | dev_priv->mem_freq = 800; |
| 159 | break; |
| 160 | } |
| 161 | |
| 162 | /* detect pineview DDR3 setting */ |
| 163 | tmp = I915_READ(CSHRDDR3CTL); |
| 164 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
| 165 | } |
| 166 | |
| 167 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
| 168 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 169 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 170 | u16 ddrpll, csipll; |
| 171 | |
| 172 | ddrpll = I915_READ16(DDRMPLL1); |
| 173 | csipll = I915_READ16(CSIPLL0); |
| 174 | |
| 175 | switch (ddrpll & 0xff) { |
| 176 | case 0xc: |
| 177 | dev_priv->mem_freq = 800; |
| 178 | break; |
| 179 | case 0x10: |
| 180 | dev_priv->mem_freq = 1066; |
| 181 | break; |
| 182 | case 0x14: |
| 183 | dev_priv->mem_freq = 1333; |
| 184 | break; |
| 185 | case 0x18: |
| 186 | dev_priv->mem_freq = 1600; |
| 187 | break; |
| 188 | default: |
| 189 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
| 190 | ddrpll & 0xff); |
| 191 | dev_priv->mem_freq = 0; |
| 192 | break; |
| 193 | } |
| 194 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 195 | dev_priv->ips.r_t = dev_priv->mem_freq; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 196 | |
| 197 | switch (csipll & 0x3ff) { |
| 198 | case 0x00c: |
| 199 | dev_priv->fsb_freq = 3200; |
| 200 | break; |
| 201 | case 0x00e: |
| 202 | dev_priv->fsb_freq = 3733; |
| 203 | break; |
| 204 | case 0x010: |
| 205 | dev_priv->fsb_freq = 4266; |
| 206 | break; |
| 207 | case 0x012: |
| 208 | dev_priv->fsb_freq = 4800; |
| 209 | break; |
| 210 | case 0x014: |
| 211 | dev_priv->fsb_freq = 5333; |
| 212 | break; |
| 213 | case 0x016: |
| 214 | dev_priv->fsb_freq = 5866; |
| 215 | break; |
| 216 | case 0x018: |
| 217 | dev_priv->fsb_freq = 6400; |
| 218 | break; |
| 219 | default: |
| 220 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
| 221 | csipll & 0x3ff); |
| 222 | dev_priv->fsb_freq = 0; |
| 223 | break; |
| 224 | } |
| 225 | |
| 226 | if (dev_priv->fsb_freq == 3200) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 227 | dev_priv->ips.c_m = 0; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 228 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 229 | dev_priv->ips.c_m = 1; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 230 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 231 | dev_priv->ips.c_m = 2; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 232 | } |
| 233 | } |
| 234 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 235 | static const struct cxsr_latency cxsr_latency_table[] = { |
| 236 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 237 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 238 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 239 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 240 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
| 241 | |
| 242 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 243 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 244 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 245 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 246 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
| 247 | |
| 248 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 249 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 250 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 251 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 252 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
| 253 | |
| 254 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 255 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 256 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 257 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 258 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
| 259 | |
| 260 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 261 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 262 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 263 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 264 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
| 265 | |
| 266 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 267 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 268 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 269 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 270 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
| 271 | }; |
| 272 | |
Daniel Vetter | 63c6227 | 2012-04-21 23:17:55 +0200 | [diff] [blame] | 273 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 274 | int is_ddr3, |
| 275 | int fsb, |
| 276 | int mem) |
| 277 | { |
| 278 | const struct cxsr_latency *latency; |
| 279 | int i; |
| 280 | |
| 281 | if (fsb == 0 || mem == 0) |
| 282 | return NULL; |
| 283 | |
| 284 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 285 | latency = &cxsr_latency_table[i]; |
| 286 | if (is_desktop == latency->is_desktop && |
| 287 | is_ddr3 == latency->is_ddr3 && |
| 288 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 289 | return latency; |
| 290 | } |
| 291 | |
| 292 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 293 | |
| 294 | return NULL; |
| 295 | } |
| 296 | |
Ville Syrjälä | fc1ac8d | 2015-03-05 21:19:52 +0200 | [diff] [blame] | 297 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
| 298 | { |
| 299 | u32 val; |
| 300 | |
| 301 | mutex_lock(&dev_priv->rps.hw_lock); |
| 302 | |
| 303 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
| 304 | if (enable) |
| 305 | val &= ~FORCE_DDR_HIGH_FREQ; |
| 306 | else |
| 307 | val |= FORCE_DDR_HIGH_FREQ; |
| 308 | val &= ~FORCE_DDR_LOW_FREQ; |
| 309 | val |= FORCE_DDR_FREQ_REQ_ACK; |
| 310 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); |
| 311 | |
| 312 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & |
| 313 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) |
| 314 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); |
| 315 | |
| 316 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 317 | } |
| 318 | |
Ville Syrjälä | cfb4141 | 2015-03-05 21:19:51 +0200 | [diff] [blame] | 319 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
| 320 | { |
| 321 | u32 val; |
| 322 | |
| 323 | mutex_lock(&dev_priv->rps.hw_lock); |
| 324 | |
| 325 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 326 | if (enable) |
| 327 | val |= DSP_MAXFIFO_PM5_ENABLE; |
| 328 | else |
| 329 | val &= ~DSP_MAXFIFO_PM5_ENABLE; |
| 330 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 331 | |
| 332 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 333 | } |
| 334 | |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 335 | #define FW_WM(value, plane) \ |
| 336 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) |
| 337 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 338 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 339 | { |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 340 | struct drm_device *dev = dev_priv->dev; |
| 341 | u32 val; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 342 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 343 | if (IS_VALLEYVIEW(dev)) { |
| 344 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
Ville Syrjälä | a7a6c49 | 2015-06-24 22:00:01 +0300 | [diff] [blame] | 345 | POSTING_READ(FW_BLC_SELF_VLV); |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 346 | dev_priv->wm.vlv.cxsr = enable; |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 347 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
| 348 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
Ville Syrjälä | a7a6c49 | 2015-06-24 22:00:01 +0300 | [diff] [blame] | 349 | POSTING_READ(FW_BLC_SELF); |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 350 | } else if (IS_PINEVIEW(dev)) { |
| 351 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; |
| 352 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; |
| 353 | I915_WRITE(DSPFW3, val); |
Ville Syrjälä | a7a6c49 | 2015-06-24 22:00:01 +0300 | [diff] [blame] | 354 | POSTING_READ(DSPFW3); |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 355 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 356 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
| 357 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); |
| 358 | I915_WRITE(FW_BLC_SELF, val); |
Ville Syrjälä | a7a6c49 | 2015-06-24 22:00:01 +0300 | [diff] [blame] | 359 | POSTING_READ(FW_BLC_SELF); |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 360 | } else if (IS_I915GM(dev)) { |
| 361 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
| 362 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); |
| 363 | I915_WRITE(INSTPM, val); |
Ville Syrjälä | a7a6c49 | 2015-06-24 22:00:01 +0300 | [diff] [blame] | 364 | POSTING_READ(INSTPM); |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 365 | } else { |
| 366 | return; |
| 367 | } |
| 368 | |
| 369 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
| 370 | enable ? "enabled" : "disabled"); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 371 | } |
| 372 | |
Ville Syrjälä | fc1ac8d | 2015-03-05 21:19:52 +0200 | [diff] [blame] | 373 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 374 | /* |
| 375 | * Latency for FIFO fetches is dependent on several factors: |
| 376 | * - memory configuration (speed, channels) |
| 377 | * - chipset |
| 378 | * - current MCH state |
| 379 | * It can be fairly high in some situations, so here we assume a fairly |
| 380 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 381 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 382 | * and power consumption (set it too low to save power and we might see |
| 383 | * FIFO underruns and display "flicker"). |
| 384 | * |
| 385 | * A value of 5us seems to be a good balance; safe for very low end |
| 386 | * platforms but not overly aggressive on lower latency configs. |
| 387 | */ |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 388 | static const int pessimal_latency_ns = 5000; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 389 | |
Ville Syrjälä | b500472 | 2015-03-05 21:19:47 +0200 | [diff] [blame] | 390 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
| 391 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) |
| 392 | |
| 393 | static int vlv_get_fifo_size(struct drm_device *dev, |
| 394 | enum pipe pipe, int plane) |
| 395 | { |
| 396 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 397 | int sprite0_start, sprite1_start, size; |
| 398 | |
| 399 | switch (pipe) { |
| 400 | uint32_t dsparb, dsparb2, dsparb3; |
| 401 | case PIPE_A: |
| 402 | dsparb = I915_READ(DSPARB); |
| 403 | dsparb2 = I915_READ(DSPARB2); |
| 404 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); |
| 405 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); |
| 406 | break; |
| 407 | case PIPE_B: |
| 408 | dsparb = I915_READ(DSPARB); |
| 409 | dsparb2 = I915_READ(DSPARB2); |
| 410 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); |
| 411 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); |
| 412 | break; |
| 413 | case PIPE_C: |
| 414 | dsparb2 = I915_READ(DSPARB2); |
| 415 | dsparb3 = I915_READ(DSPARB3); |
| 416 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); |
| 417 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); |
| 418 | break; |
| 419 | default: |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | switch (plane) { |
| 424 | case 0: |
| 425 | size = sprite0_start; |
| 426 | break; |
| 427 | case 1: |
| 428 | size = sprite1_start - sprite0_start; |
| 429 | break; |
| 430 | case 2: |
| 431 | size = 512 - 1 - sprite1_start; |
| 432 | break; |
| 433 | default: |
| 434 | return 0; |
| 435 | } |
| 436 | |
| 437 | DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", |
| 438 | pipe_name(pipe), plane == 0 ? "primary" : "sprite", |
| 439 | plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), |
| 440 | size); |
| 441 | |
| 442 | return size; |
| 443 | } |
| 444 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 445 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 446 | { |
| 447 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 448 | uint32_t dsparb = I915_READ(DSPARB); |
| 449 | int size; |
| 450 | |
| 451 | size = dsparb & 0x7f; |
| 452 | if (plane) |
| 453 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
| 454 | |
| 455 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 456 | plane ? "B" : "A", size); |
| 457 | |
| 458 | return size; |
| 459 | } |
| 460 | |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 461 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 462 | { |
| 463 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 464 | uint32_t dsparb = I915_READ(DSPARB); |
| 465 | int size; |
| 466 | |
| 467 | size = dsparb & 0x1ff; |
| 468 | if (plane) |
| 469 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
| 470 | size >>= 1; /* Convert to cachelines */ |
| 471 | |
| 472 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 473 | plane ? "B" : "A", size); |
| 474 | |
| 475 | return size; |
| 476 | } |
| 477 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 478 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 479 | { |
| 480 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 481 | uint32_t dsparb = I915_READ(DSPARB); |
| 482 | int size; |
| 483 | |
| 484 | size = dsparb & 0x7f; |
| 485 | size >>= 2; /* Convert to cachelines */ |
| 486 | |
| 487 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 488 | plane ? "B" : "A", |
| 489 | size); |
| 490 | |
| 491 | return size; |
| 492 | } |
| 493 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 494 | /* Pineview has different values for various configs */ |
| 495 | static const struct intel_watermark_params pineview_display_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 496 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
| 497 | .max_wm = PINEVIEW_MAX_WM, |
| 498 | .default_wm = PINEVIEW_DFT_WM, |
| 499 | .guard_size = PINEVIEW_GUARD_WM, |
| 500 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 501 | }; |
| 502 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 503 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
| 504 | .max_wm = PINEVIEW_MAX_WM, |
| 505 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, |
| 506 | .guard_size = PINEVIEW_GUARD_WM, |
| 507 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 508 | }; |
| 509 | static const struct intel_watermark_params pineview_cursor_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 510 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
| 511 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
| 512 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
| 513 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
| 514 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 515 | }; |
| 516 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 517 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
| 518 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
| 519 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
| 520 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
| 521 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 522 | }; |
| 523 | static const struct intel_watermark_params g4x_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 524 | .fifo_size = G4X_FIFO_SIZE, |
| 525 | .max_wm = G4X_MAX_WM, |
| 526 | .default_wm = G4X_MAX_WM, |
| 527 | .guard_size = 2, |
| 528 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 529 | }; |
| 530 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 531 | .fifo_size = I965_CURSOR_FIFO, |
| 532 | .max_wm = I965_CURSOR_MAX_WM, |
| 533 | .default_wm = I965_CURSOR_DFT_WM, |
| 534 | .guard_size = 2, |
| 535 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 536 | }; |
| 537 | static const struct intel_watermark_params valleyview_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 538 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
| 539 | .max_wm = VALLEYVIEW_MAX_WM, |
| 540 | .default_wm = VALLEYVIEW_MAX_WM, |
| 541 | .guard_size = 2, |
| 542 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 543 | }; |
| 544 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 545 | .fifo_size = I965_CURSOR_FIFO, |
| 546 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, |
| 547 | .default_wm = I965_CURSOR_DFT_WM, |
| 548 | .guard_size = 2, |
| 549 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 550 | }; |
| 551 | static const struct intel_watermark_params i965_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 552 | .fifo_size = I965_CURSOR_FIFO, |
| 553 | .max_wm = I965_CURSOR_MAX_WM, |
| 554 | .default_wm = I965_CURSOR_DFT_WM, |
| 555 | .guard_size = 2, |
| 556 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 557 | }; |
| 558 | static const struct intel_watermark_params i945_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 559 | .fifo_size = I945_FIFO_SIZE, |
| 560 | .max_wm = I915_MAX_WM, |
| 561 | .default_wm = 1, |
| 562 | .guard_size = 2, |
| 563 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 564 | }; |
| 565 | static const struct intel_watermark_params i915_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 566 | .fifo_size = I915_FIFO_SIZE, |
| 567 | .max_wm = I915_MAX_WM, |
| 568 | .default_wm = 1, |
| 569 | .guard_size = 2, |
| 570 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 571 | }; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 572 | static const struct intel_watermark_params i830_a_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 573 | .fifo_size = I855GM_FIFO_SIZE, |
| 574 | .max_wm = I915_MAX_WM, |
| 575 | .default_wm = 1, |
| 576 | .guard_size = 2, |
| 577 | .cacheline_size = I830_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 578 | }; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 579 | static const struct intel_watermark_params i830_bc_wm_info = { |
| 580 | .fifo_size = I855GM_FIFO_SIZE, |
| 581 | .max_wm = I915_MAX_WM/2, |
| 582 | .default_wm = 1, |
| 583 | .guard_size = 2, |
| 584 | .cacheline_size = I830_FIFO_LINE_SIZE, |
| 585 | }; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 586 | static const struct intel_watermark_params i845_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 587 | .fifo_size = I830_FIFO_SIZE, |
| 588 | .max_wm = I915_MAX_WM, |
| 589 | .default_wm = 1, |
| 590 | .guard_size = 2, |
| 591 | .cacheline_size = I830_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 592 | }; |
| 593 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 594 | /** |
| 595 | * intel_calculate_wm - calculate watermark level |
| 596 | * @clock_in_khz: pixel clock |
| 597 | * @wm: chip FIFO params |
| 598 | * @pixel_size: display pixel size |
| 599 | * @latency_ns: memory latency for the platform |
| 600 | * |
| 601 | * Calculate the watermark level (the level at which the display plane will |
| 602 | * start fetching from memory again). Each chip has a different display |
| 603 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 604 | * in the correct intel_watermark_params structure. |
| 605 | * |
| 606 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 607 | * on the pixel size. When it reaches the watermark level, it'll start |
| 608 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 609 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 610 | * will occur, and a display engine hang could result. |
| 611 | */ |
| 612 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 613 | const struct intel_watermark_params *wm, |
| 614 | int fifo_size, |
| 615 | int pixel_size, |
| 616 | unsigned long latency_ns) |
| 617 | { |
| 618 | long entries_required, wm_size; |
| 619 | |
| 620 | /* |
| 621 | * Note: we need to make sure we don't overflow for various clock & |
| 622 | * latency values. |
| 623 | * clocks go from a few thousand to several hundred thousand. |
| 624 | * latency is usually a few thousand |
| 625 | */ |
| 626 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 627 | 1000; |
| 628 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
| 629 | |
| 630 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
| 631 | |
| 632 | wm_size = fifo_size - (entries_required + wm->guard_size); |
| 633 | |
| 634 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
| 635 | |
| 636 | /* Don't promote wm_size to unsigned... */ |
| 637 | if (wm_size > (long)wm->max_wm) |
| 638 | wm_size = wm->max_wm; |
| 639 | if (wm_size <= 0) |
| 640 | wm_size = wm->default_wm; |
Ville Syrjälä | d6feb19 | 2014-09-05 21:54:13 +0300 | [diff] [blame] | 641 | |
| 642 | /* |
| 643 | * Bspec seems to indicate that the value shouldn't be lower than |
| 644 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. |
| 645 | * Lets go for 8 which is the burst size since certain platforms |
| 646 | * already use a hardcoded 8 (which is what the spec says should be |
| 647 | * done). |
| 648 | */ |
| 649 | if (wm_size <= 8) |
| 650 | wm_size = 8; |
| 651 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 652 | return wm_size; |
| 653 | } |
| 654 | |
| 655 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
| 656 | { |
| 657 | struct drm_crtc *crtc, *enabled = NULL; |
| 658 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 659 | for_each_crtc(dev, crtc) { |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 660 | if (intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 661 | if (enabled) |
| 662 | return NULL; |
| 663 | enabled = crtc; |
| 664 | } |
| 665 | } |
| 666 | |
| 667 | return enabled; |
| 668 | } |
| 669 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 670 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 671 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 672 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 673 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 674 | struct drm_crtc *crtc; |
| 675 | const struct cxsr_latency *latency; |
| 676 | u32 reg; |
| 677 | unsigned long wm; |
| 678 | |
| 679 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
| 680 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 681 | if (!latency) { |
| 682 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 683 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 684 | return; |
| 685 | } |
| 686 | |
| 687 | crtc = single_enabled_crtc(dev); |
| 688 | if (crtc) { |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 689 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Matt Roper | 59bea88 | 2015-02-27 10:12:01 -0800 | [diff] [blame] | 690 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 691 | int clock = adjusted_mode->crtc_clock; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 692 | |
| 693 | /* Display SR */ |
| 694 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
| 695 | pineview_display_wm.fifo_size, |
| 696 | pixel_size, latency->display_sr); |
| 697 | reg = I915_READ(DSPFW1); |
| 698 | reg &= ~DSPFW_SR_MASK; |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 699 | reg |= FW_WM(wm, SR); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 700 | I915_WRITE(DSPFW1, reg); |
| 701 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 702 | |
| 703 | /* cursor SR */ |
| 704 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
| 705 | pineview_display_wm.fifo_size, |
| 706 | pixel_size, latency->cursor_sr); |
| 707 | reg = I915_READ(DSPFW3); |
| 708 | reg &= ~DSPFW_CURSOR_SR_MASK; |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 709 | reg |= FW_WM(wm, CURSOR_SR); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 710 | I915_WRITE(DSPFW3, reg); |
| 711 | |
| 712 | /* Display HPLL off SR */ |
| 713 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
| 714 | pineview_display_hplloff_wm.fifo_size, |
| 715 | pixel_size, latency->display_hpll_disable); |
| 716 | reg = I915_READ(DSPFW3); |
| 717 | reg &= ~DSPFW_HPLL_SR_MASK; |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 718 | reg |= FW_WM(wm, HPLL_SR); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 719 | I915_WRITE(DSPFW3, reg); |
| 720 | |
| 721 | /* cursor HPLL off SR */ |
| 722 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
| 723 | pineview_display_hplloff_wm.fifo_size, |
| 724 | pixel_size, latency->cursor_hpll_disable); |
| 725 | reg = I915_READ(DSPFW3); |
| 726 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 727 | reg |= FW_WM(wm, HPLL_CURSOR); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 728 | I915_WRITE(DSPFW3, reg); |
| 729 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 730 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 731 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 732 | } else { |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 733 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 734 | } |
| 735 | } |
| 736 | |
| 737 | static bool g4x_compute_wm0(struct drm_device *dev, |
| 738 | int plane, |
| 739 | const struct intel_watermark_params *display, |
| 740 | int display_latency_ns, |
| 741 | const struct intel_watermark_params *cursor, |
| 742 | int cursor_latency_ns, |
| 743 | int *plane_wm, |
| 744 | int *cursor_wm) |
| 745 | { |
| 746 | struct drm_crtc *crtc; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 747 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 748 | int htotal, hdisplay, clock, pixel_size; |
| 749 | int line_time_us, line_count; |
| 750 | int entries, tlb_miss; |
| 751 | |
| 752 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 753 | if (!intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 754 | *cursor_wm = cursor->guard_size; |
| 755 | *plane_wm = display->guard_size; |
| 756 | return false; |
| 757 | } |
| 758 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 759 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 760 | clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 761 | htotal = adjusted_mode->crtc_htotal; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 762 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
Matt Roper | 59bea88 | 2015-02-27 10:12:01 -0800 | [diff] [blame] | 763 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 764 | |
| 765 | /* Use the small buffer method to calculate plane watermark */ |
| 766 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 767 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
| 768 | if (tlb_miss > 0) |
| 769 | entries += tlb_miss; |
| 770 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 771 | *plane_wm = entries + display->guard_size; |
| 772 | if (*plane_wm > (int)display->max_wm) |
| 773 | *plane_wm = display->max_wm; |
| 774 | |
| 775 | /* Use the large buffer method to calculate cursor watermark */ |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 776 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 777 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
Matt Roper | 3dd512f | 2015-02-27 10:12:00 -0800 | [diff] [blame] | 778 | entries = line_count * crtc->cursor->state->crtc_w * pixel_size; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 779 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
| 780 | if (tlb_miss > 0) |
| 781 | entries += tlb_miss; |
| 782 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 783 | *cursor_wm = entries + cursor->guard_size; |
| 784 | if (*cursor_wm > (int)cursor->max_wm) |
| 785 | *cursor_wm = (int)cursor->max_wm; |
| 786 | |
| 787 | return true; |
| 788 | } |
| 789 | |
| 790 | /* |
| 791 | * Check the wm result. |
| 792 | * |
| 793 | * If any calculated watermark values is larger than the maximum value that |
| 794 | * can be programmed into the associated watermark register, that watermark |
| 795 | * must be disabled. |
| 796 | */ |
| 797 | static bool g4x_check_srwm(struct drm_device *dev, |
| 798 | int display_wm, int cursor_wm, |
| 799 | const struct intel_watermark_params *display, |
| 800 | const struct intel_watermark_params *cursor) |
| 801 | { |
| 802 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
| 803 | display_wm, cursor_wm); |
| 804 | |
| 805 | if (display_wm > display->max_wm) { |
| 806 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
| 807 | display_wm, display->max_wm); |
| 808 | return false; |
| 809 | } |
| 810 | |
| 811 | if (cursor_wm > cursor->max_wm) { |
| 812 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
| 813 | cursor_wm, cursor->max_wm); |
| 814 | return false; |
| 815 | } |
| 816 | |
| 817 | if (!(display_wm || cursor_wm)) { |
| 818 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
| 819 | return false; |
| 820 | } |
| 821 | |
| 822 | return true; |
| 823 | } |
| 824 | |
| 825 | static bool g4x_compute_srwm(struct drm_device *dev, |
| 826 | int plane, |
| 827 | int latency_ns, |
| 828 | const struct intel_watermark_params *display, |
| 829 | const struct intel_watermark_params *cursor, |
| 830 | int *display_wm, int *cursor_wm) |
| 831 | { |
| 832 | struct drm_crtc *crtc; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 833 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 834 | int hdisplay, htotal, pixel_size, clock; |
| 835 | unsigned long line_time_us; |
| 836 | int line_count, line_size; |
| 837 | int small, large; |
| 838 | int entries; |
| 839 | |
| 840 | if (!latency_ns) { |
| 841 | *display_wm = *cursor_wm = 0; |
| 842 | return false; |
| 843 | } |
| 844 | |
| 845 | crtc = intel_get_crtc_for_plane(dev, plane); |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 846 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 847 | clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 848 | htotal = adjusted_mode->crtc_htotal; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 849 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
Matt Roper | 59bea88 | 2015-02-27 10:12:01 -0800 | [diff] [blame] | 850 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 851 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 852 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 853 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 854 | line_size = hdisplay * pixel_size; |
| 855 | |
| 856 | /* Use the minimum of the small and large buffer method for primary */ |
| 857 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 858 | large = line_count * line_size; |
| 859 | |
| 860 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 861 | *display_wm = entries + display->guard_size; |
| 862 | |
| 863 | /* calculate the self-refresh watermark for display cursor */ |
Matt Roper | 3dd512f | 2015-02-27 10:12:00 -0800 | [diff] [blame] | 864 | entries = line_count * pixel_size * crtc->cursor->state->crtc_w; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 865 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 866 | *cursor_wm = entries + cursor->guard_size; |
| 867 | |
| 868 | return g4x_check_srwm(dev, |
| 869 | *display_wm, *cursor_wm, |
| 870 | display, cursor); |
| 871 | } |
| 872 | |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 873 | #define FW_WM_VLV(value, plane) \ |
| 874 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) |
| 875 | |
Ville Syrjälä | 0018fda | 2015-03-05 21:19:45 +0200 | [diff] [blame] | 876 | static void vlv_write_wm_values(struct intel_crtc *crtc, |
| 877 | const struct vlv_wm_values *wm) |
| 878 | { |
| 879 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 880 | enum pipe pipe = crtc->pipe; |
| 881 | |
| 882 | I915_WRITE(VLV_DDL(pipe), |
| 883 | (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | |
| 884 | (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | |
| 885 | (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | |
| 886 | (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); |
| 887 | |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 888 | I915_WRITE(DSPFW1, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 889 | FW_WM(wm->sr.plane, SR) | |
| 890 | FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | |
| 891 | FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | |
| 892 | FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 893 | I915_WRITE(DSPFW2, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 894 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | |
| 895 | FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | |
| 896 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 897 | I915_WRITE(DSPFW3, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 898 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 899 | |
| 900 | if (IS_CHERRYVIEW(dev_priv)) { |
| 901 | I915_WRITE(DSPFW7_CHV, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 902 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
| 903 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 904 | I915_WRITE(DSPFW8_CHV, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 905 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | |
| 906 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 907 | I915_WRITE(DSPFW9_CHV, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 908 | FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | |
| 909 | FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 910 | I915_WRITE(DSPHOWM, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 911 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
| 912 | FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | |
| 913 | FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | |
| 914 | FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | |
| 915 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | |
| 916 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | |
| 917 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | |
| 918 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | |
| 919 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | |
| 920 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 921 | } else { |
| 922 | I915_WRITE(DSPFW7, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 923 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
| 924 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 925 | I915_WRITE(DSPHOWM, |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 926 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
| 927 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | |
| 928 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | |
| 929 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | |
| 930 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | |
| 931 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | |
| 932 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 933 | } |
| 934 | |
Ville Syrjälä | 2cb389b | 2015-06-24 22:00:10 +0300 | [diff] [blame] | 935 | /* zero (unused) WM1 watermarks */ |
| 936 | I915_WRITE(DSPFW4, 0); |
| 937 | I915_WRITE(DSPFW5, 0); |
| 938 | I915_WRITE(DSPFW6, 0); |
| 939 | I915_WRITE(DSPHOWM1, 0); |
| 940 | |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 941 | POSTING_READ(DSPFW1); |
Ville Syrjälä | 0018fda | 2015-03-05 21:19:45 +0200 | [diff] [blame] | 942 | } |
| 943 | |
Ville Syrjälä | 1566597 | 2015-03-10 16:16:28 +0200 | [diff] [blame] | 944 | #undef FW_WM_VLV |
| 945 | |
Ville Syrjälä | 6eb1a68 | 2015-06-24 22:00:03 +0300 | [diff] [blame] | 946 | enum vlv_wm_level { |
| 947 | VLV_WM_LEVEL_PM2, |
| 948 | VLV_WM_LEVEL_PM5, |
| 949 | VLV_WM_LEVEL_DDR_DVFS, |
Ville Syrjälä | 6eb1a68 | 2015-06-24 22:00:03 +0300 | [diff] [blame] | 950 | }; |
| 951 | |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 952 | /* latency must be in 0.1us units. */ |
| 953 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, |
| 954 | unsigned int pipe_htotal, |
| 955 | unsigned int horiz_pixels, |
| 956 | unsigned int bytes_per_pixel, |
| 957 | unsigned int latency) |
| 958 | { |
| 959 | unsigned int ret; |
| 960 | |
| 961 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
| 962 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
| 963 | ret = DIV_ROUND_UP(ret, 64); |
| 964 | |
| 965 | return ret; |
| 966 | } |
| 967 | |
| 968 | static void vlv_setup_wm_latency(struct drm_device *dev) |
| 969 | { |
| 970 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 971 | |
| 972 | /* all latencies in usec */ |
| 973 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; |
| 974 | |
Ville Syrjälä | 58590c1 | 2015-09-08 21:05:12 +0300 | [diff] [blame] | 975 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
| 976 | |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 977 | if (IS_CHERRYVIEW(dev_priv)) { |
| 978 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; |
| 979 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; |
Ville Syrjälä | 58590c1 | 2015-09-08 21:05:12 +0300 | [diff] [blame] | 980 | |
| 981 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 982 | } |
| 983 | } |
| 984 | |
| 985 | static uint16_t vlv_compute_wm_level(struct intel_plane *plane, |
| 986 | struct intel_crtc *crtc, |
| 987 | const struct intel_plane_state *state, |
| 988 | int level) |
| 989 | { |
| 990 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
| 991 | int clock, htotal, pixel_size, width, wm; |
| 992 | |
| 993 | if (dev_priv->wm.pri_latency[level] == 0) |
| 994 | return USHRT_MAX; |
| 995 | |
| 996 | if (!state->visible) |
| 997 | return 0; |
| 998 | |
| 999 | pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
| 1000 | clock = crtc->config->base.adjusted_mode.crtc_clock; |
| 1001 | htotal = crtc->config->base.adjusted_mode.crtc_htotal; |
| 1002 | width = crtc->config->pipe_src_w; |
| 1003 | if (WARN_ON(htotal == 0)) |
| 1004 | htotal = 1; |
| 1005 | |
| 1006 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
| 1007 | /* |
| 1008 | * FIXME the formula gives values that are |
| 1009 | * too big for the cursor FIFO, and hence we |
| 1010 | * would never be able to use cursors. For |
| 1011 | * now just hardcode the watermark. |
| 1012 | */ |
| 1013 | wm = 63; |
| 1014 | } else { |
| 1015 | wm = vlv_wm_method2(clock, htotal, width, pixel_size, |
| 1016 | dev_priv->wm.pri_latency[level] * 10); |
| 1017 | } |
| 1018 | |
| 1019 | return min_t(int, wm, USHRT_MAX); |
| 1020 | } |
| 1021 | |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 1022 | static void vlv_compute_fifo(struct intel_crtc *crtc) |
| 1023 | { |
| 1024 | struct drm_device *dev = crtc->base.dev; |
| 1025 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
| 1026 | struct intel_plane *plane; |
| 1027 | unsigned int total_rate = 0; |
| 1028 | const int fifo_size = 512 - 1; |
| 1029 | int fifo_extra, fifo_left = fifo_size; |
| 1030 | |
| 1031 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 1032 | struct intel_plane_state *state = |
| 1033 | to_intel_plane_state(plane->base.state); |
| 1034 | |
| 1035 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) |
| 1036 | continue; |
| 1037 | |
| 1038 | if (state->visible) { |
| 1039 | wm_state->num_active_planes++; |
| 1040 | total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
| 1041 | } |
| 1042 | } |
| 1043 | |
| 1044 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 1045 | struct intel_plane_state *state = |
| 1046 | to_intel_plane_state(plane->base.state); |
| 1047 | unsigned int rate; |
| 1048 | |
| 1049 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
| 1050 | plane->wm.fifo_size = 63; |
| 1051 | continue; |
| 1052 | } |
| 1053 | |
| 1054 | if (!state->visible) { |
| 1055 | plane->wm.fifo_size = 0; |
| 1056 | continue; |
| 1057 | } |
| 1058 | |
| 1059 | rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); |
| 1060 | plane->wm.fifo_size = fifo_size * rate / total_rate; |
| 1061 | fifo_left -= plane->wm.fifo_size; |
| 1062 | } |
| 1063 | |
| 1064 | fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); |
| 1065 | |
| 1066 | /* spread the remainder evenly */ |
| 1067 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 1068 | int plane_extra; |
| 1069 | |
| 1070 | if (fifo_left == 0) |
| 1071 | break; |
| 1072 | |
| 1073 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) |
| 1074 | continue; |
| 1075 | |
| 1076 | /* give it all to the first plane if none are active */ |
| 1077 | if (plane->wm.fifo_size == 0 && |
| 1078 | wm_state->num_active_planes) |
| 1079 | continue; |
| 1080 | |
| 1081 | plane_extra = min(fifo_extra, fifo_left); |
| 1082 | plane->wm.fifo_size += plane_extra; |
| 1083 | fifo_left -= plane_extra; |
| 1084 | } |
| 1085 | |
| 1086 | WARN_ON(fifo_left != 0); |
| 1087 | } |
| 1088 | |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1089 | static void vlv_invert_wms(struct intel_crtc *crtc) |
| 1090 | { |
| 1091 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
| 1092 | int level; |
| 1093 | |
| 1094 | for (level = 0; level < wm_state->num_levels; level++) { |
| 1095 | struct drm_device *dev = crtc->base.dev; |
| 1096 | const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; |
| 1097 | struct intel_plane *plane; |
| 1098 | |
| 1099 | wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; |
| 1100 | wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; |
| 1101 | |
| 1102 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 1103 | switch (plane->base.type) { |
| 1104 | int sprite; |
| 1105 | case DRM_PLANE_TYPE_CURSOR: |
| 1106 | wm_state->wm[level].cursor = plane->wm.fifo_size - |
| 1107 | wm_state->wm[level].cursor; |
| 1108 | break; |
| 1109 | case DRM_PLANE_TYPE_PRIMARY: |
| 1110 | wm_state->wm[level].primary = plane->wm.fifo_size - |
| 1111 | wm_state->wm[level].primary; |
| 1112 | break; |
| 1113 | case DRM_PLANE_TYPE_OVERLAY: |
| 1114 | sprite = plane->plane; |
| 1115 | wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - |
| 1116 | wm_state->wm[level].sprite[sprite]; |
| 1117 | break; |
| 1118 | } |
| 1119 | } |
| 1120 | } |
| 1121 | } |
| 1122 | |
Ville Syrjälä | 26e1fe4 | 2015-06-24 22:00:06 +0300 | [diff] [blame] | 1123 | static void vlv_compute_wm(struct intel_crtc *crtc) |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1124 | { |
| 1125 | struct drm_device *dev = crtc->base.dev; |
| 1126 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
| 1127 | struct intel_plane *plane; |
| 1128 | int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; |
| 1129 | int level; |
| 1130 | |
| 1131 | memset(wm_state, 0, sizeof(*wm_state)); |
| 1132 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 1133 | wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; |
Ville Syrjälä | 58590c1 | 2015-09-08 21:05:12 +0300 | [diff] [blame] | 1134 | wm_state->num_levels = to_i915(dev)->wm.max_level + 1; |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1135 | |
| 1136 | wm_state->num_active_planes = 0; |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1137 | |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 1138 | vlv_compute_fifo(crtc); |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1139 | |
| 1140 | if (wm_state->num_active_planes != 1) |
| 1141 | wm_state->cxsr = false; |
| 1142 | |
| 1143 | if (wm_state->cxsr) { |
| 1144 | for (level = 0; level < wm_state->num_levels; level++) { |
| 1145 | wm_state->sr[level].plane = sr_fifo_size; |
| 1146 | wm_state->sr[level].cursor = 63; |
| 1147 | } |
| 1148 | } |
| 1149 | |
| 1150 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 1151 | struct intel_plane_state *state = |
| 1152 | to_intel_plane_state(plane->base.state); |
| 1153 | |
| 1154 | if (!state->visible) |
| 1155 | continue; |
| 1156 | |
| 1157 | /* normal watermarks */ |
| 1158 | for (level = 0; level < wm_state->num_levels; level++) { |
| 1159 | int wm = vlv_compute_wm_level(plane, crtc, state, level); |
| 1160 | int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; |
| 1161 | |
| 1162 | /* hack */ |
| 1163 | if (WARN_ON(level == 0 && wm > max_wm)) |
| 1164 | wm = max_wm; |
| 1165 | |
| 1166 | if (wm > plane->wm.fifo_size) |
| 1167 | break; |
| 1168 | |
| 1169 | switch (plane->base.type) { |
| 1170 | int sprite; |
| 1171 | case DRM_PLANE_TYPE_CURSOR: |
| 1172 | wm_state->wm[level].cursor = wm; |
| 1173 | break; |
| 1174 | case DRM_PLANE_TYPE_PRIMARY: |
| 1175 | wm_state->wm[level].primary = wm; |
| 1176 | break; |
| 1177 | case DRM_PLANE_TYPE_OVERLAY: |
| 1178 | sprite = plane->plane; |
| 1179 | wm_state->wm[level].sprite[sprite] = wm; |
| 1180 | break; |
| 1181 | } |
| 1182 | } |
| 1183 | |
| 1184 | wm_state->num_levels = level; |
| 1185 | |
| 1186 | if (!wm_state->cxsr) |
| 1187 | continue; |
| 1188 | |
| 1189 | /* maxfifo watermarks */ |
| 1190 | switch (plane->base.type) { |
| 1191 | int sprite, level; |
| 1192 | case DRM_PLANE_TYPE_CURSOR: |
| 1193 | for (level = 0; level < wm_state->num_levels; level++) |
| 1194 | wm_state->sr[level].cursor = |
| 1195 | wm_state->sr[level].cursor; |
| 1196 | break; |
| 1197 | case DRM_PLANE_TYPE_PRIMARY: |
| 1198 | for (level = 0; level < wm_state->num_levels; level++) |
| 1199 | wm_state->sr[level].plane = |
| 1200 | min(wm_state->sr[level].plane, |
| 1201 | wm_state->wm[level].primary); |
| 1202 | break; |
| 1203 | case DRM_PLANE_TYPE_OVERLAY: |
| 1204 | sprite = plane->plane; |
| 1205 | for (level = 0; level < wm_state->num_levels; level++) |
| 1206 | wm_state->sr[level].plane = |
| 1207 | min(wm_state->sr[level].plane, |
| 1208 | wm_state->wm[level].sprite[sprite]); |
| 1209 | break; |
| 1210 | } |
| 1211 | } |
| 1212 | |
| 1213 | /* clear any (partially) filled invalid levels */ |
Ville Syrjälä | 58590c1 | 2015-09-08 21:05:12 +0300 | [diff] [blame] | 1214 | for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1215 | memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); |
| 1216 | memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); |
| 1217 | } |
| 1218 | |
| 1219 | vlv_invert_wms(crtc); |
| 1220 | } |
| 1221 | |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 1222 | #define VLV_FIFO(plane, value) \ |
| 1223 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) |
| 1224 | |
| 1225 | static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) |
| 1226 | { |
| 1227 | struct drm_device *dev = crtc->base.dev; |
| 1228 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1229 | struct intel_plane *plane; |
| 1230 | int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; |
| 1231 | |
| 1232 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 1233 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { |
| 1234 | WARN_ON(plane->wm.fifo_size != 63); |
| 1235 | continue; |
| 1236 | } |
| 1237 | |
| 1238 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) |
| 1239 | sprite0_start = plane->wm.fifo_size; |
| 1240 | else if (plane->plane == 0) |
| 1241 | sprite1_start = sprite0_start + plane->wm.fifo_size; |
| 1242 | else |
| 1243 | fifo_size = sprite1_start + plane->wm.fifo_size; |
| 1244 | } |
| 1245 | |
| 1246 | WARN_ON(fifo_size != 512 - 1); |
| 1247 | |
| 1248 | DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", |
| 1249 | pipe_name(crtc->pipe), sprite0_start, |
| 1250 | sprite1_start, fifo_size); |
| 1251 | |
| 1252 | switch (crtc->pipe) { |
| 1253 | uint32_t dsparb, dsparb2, dsparb3; |
| 1254 | case PIPE_A: |
| 1255 | dsparb = I915_READ(DSPARB); |
| 1256 | dsparb2 = I915_READ(DSPARB2); |
| 1257 | |
| 1258 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | |
| 1259 | VLV_FIFO(SPRITEB, 0xff)); |
| 1260 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | |
| 1261 | VLV_FIFO(SPRITEB, sprite1_start)); |
| 1262 | |
| 1263 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | |
| 1264 | VLV_FIFO(SPRITEB_HI, 0x1)); |
| 1265 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | |
| 1266 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); |
| 1267 | |
| 1268 | I915_WRITE(DSPARB, dsparb); |
| 1269 | I915_WRITE(DSPARB2, dsparb2); |
| 1270 | break; |
| 1271 | case PIPE_B: |
| 1272 | dsparb = I915_READ(DSPARB); |
| 1273 | dsparb2 = I915_READ(DSPARB2); |
| 1274 | |
| 1275 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | |
| 1276 | VLV_FIFO(SPRITED, 0xff)); |
| 1277 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | |
| 1278 | VLV_FIFO(SPRITED, sprite1_start)); |
| 1279 | |
| 1280 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | |
| 1281 | VLV_FIFO(SPRITED_HI, 0xff)); |
| 1282 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | |
| 1283 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); |
| 1284 | |
| 1285 | I915_WRITE(DSPARB, dsparb); |
| 1286 | I915_WRITE(DSPARB2, dsparb2); |
| 1287 | break; |
| 1288 | case PIPE_C: |
| 1289 | dsparb3 = I915_READ(DSPARB3); |
| 1290 | dsparb2 = I915_READ(DSPARB2); |
| 1291 | |
| 1292 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | |
| 1293 | VLV_FIFO(SPRITEF, 0xff)); |
| 1294 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | |
| 1295 | VLV_FIFO(SPRITEF, sprite1_start)); |
| 1296 | |
| 1297 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | |
| 1298 | VLV_FIFO(SPRITEF_HI, 0xff)); |
| 1299 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | |
| 1300 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); |
| 1301 | |
| 1302 | I915_WRITE(DSPARB3, dsparb3); |
| 1303 | I915_WRITE(DSPARB2, dsparb2); |
| 1304 | break; |
| 1305 | default: |
| 1306 | break; |
| 1307 | } |
| 1308 | } |
| 1309 | |
| 1310 | #undef VLV_FIFO |
| 1311 | |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1312 | static void vlv_merge_wm(struct drm_device *dev, |
| 1313 | struct vlv_wm_values *wm) |
| 1314 | { |
| 1315 | struct intel_crtc *crtc; |
| 1316 | int num_active_crtcs = 0; |
| 1317 | |
Ville Syrjälä | 58590c1 | 2015-09-08 21:05:12 +0300 | [diff] [blame] | 1318 | wm->level = to_i915(dev)->wm.max_level; |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1319 | wm->cxsr = true; |
| 1320 | |
| 1321 | for_each_intel_crtc(dev, crtc) { |
| 1322 | const struct vlv_wm_state *wm_state = &crtc->wm_state; |
| 1323 | |
| 1324 | if (!crtc->active) |
| 1325 | continue; |
| 1326 | |
| 1327 | if (!wm_state->cxsr) |
| 1328 | wm->cxsr = false; |
| 1329 | |
| 1330 | num_active_crtcs++; |
| 1331 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); |
| 1332 | } |
| 1333 | |
| 1334 | if (num_active_crtcs != 1) |
| 1335 | wm->cxsr = false; |
| 1336 | |
Ville Syrjälä | 6f9c784 | 2015-06-24 22:00:08 +0300 | [diff] [blame] | 1337 | if (num_active_crtcs > 1) |
| 1338 | wm->level = VLV_WM_LEVEL_PM2; |
| 1339 | |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1340 | for_each_intel_crtc(dev, crtc) { |
| 1341 | struct vlv_wm_state *wm_state = &crtc->wm_state; |
| 1342 | enum pipe pipe = crtc->pipe; |
| 1343 | |
| 1344 | if (!crtc->active) |
| 1345 | continue; |
| 1346 | |
| 1347 | wm->pipe[pipe] = wm_state->wm[wm->level]; |
| 1348 | if (wm->cxsr) |
| 1349 | wm->sr = wm_state->sr[wm->level]; |
| 1350 | |
| 1351 | wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; |
| 1352 | wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; |
| 1353 | wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; |
| 1354 | wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; |
| 1355 | } |
| 1356 | } |
| 1357 | |
| 1358 | static void vlv_update_wm(struct drm_crtc *crtc) |
| 1359 | { |
| 1360 | struct drm_device *dev = crtc->dev; |
| 1361 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1362 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1363 | enum pipe pipe = intel_crtc->pipe; |
| 1364 | struct vlv_wm_values wm = {}; |
| 1365 | |
Ville Syrjälä | 26e1fe4 | 2015-06-24 22:00:06 +0300 | [diff] [blame] | 1366 | vlv_compute_wm(intel_crtc); |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1367 | vlv_merge_wm(dev, &wm); |
| 1368 | |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 1369 | if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { |
| 1370 | /* FIXME should be part of crtc atomic commit */ |
| 1371 | vlv_pipe_set_fifo_size(intel_crtc); |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1372 | return; |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 1373 | } |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1374 | |
| 1375 | if (wm.level < VLV_WM_LEVEL_DDR_DVFS && |
| 1376 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) |
| 1377 | chv_set_memory_dvfs(dev_priv, false); |
| 1378 | |
| 1379 | if (wm.level < VLV_WM_LEVEL_PM5 && |
| 1380 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) |
| 1381 | chv_set_memory_pm5(dev_priv, false); |
| 1382 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 1383 | if (!wm.cxsr && dev_priv->wm.vlv.cxsr) |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1384 | intel_set_memory_cxsr(dev_priv, false); |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1385 | |
Ville Syrjälä | 54f1b6e | 2015-06-24 22:00:05 +0300 | [diff] [blame] | 1386 | /* FIXME should be part of crtc atomic commit */ |
| 1387 | vlv_pipe_set_fifo_size(intel_crtc); |
| 1388 | |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1389 | vlv_write_wm_values(intel_crtc, &wm); |
| 1390 | |
| 1391 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " |
| 1392 | "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", |
| 1393 | pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, |
| 1394 | wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], |
| 1395 | wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); |
| 1396 | |
Ville Syrjälä | 852eb00 | 2015-06-24 22:00:07 +0300 | [diff] [blame] | 1397 | if (wm.cxsr && !dev_priv->wm.vlv.cxsr) |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1398 | intel_set_memory_cxsr(dev_priv, true); |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 1399 | |
| 1400 | if (wm.level >= VLV_WM_LEVEL_PM5 && |
| 1401 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) |
| 1402 | chv_set_memory_pm5(dev_priv, true); |
| 1403 | |
| 1404 | if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && |
| 1405 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) |
| 1406 | chv_set_memory_dvfs(dev_priv, true); |
| 1407 | |
| 1408 | dev_priv->wm.vlv = wm; |
Ville Syrjälä | 3c2777f | 2014-06-26 17:03:06 +0300 | [diff] [blame] | 1409 | } |
| 1410 | |
Ville Syrjälä | ae80152 | 2015-03-05 21:19:49 +0200 | [diff] [blame] | 1411 | #define single_plane_enabled(mask) is_power_of_2(mask) |
| 1412 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1413 | static void g4x_update_wm(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1414 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1415 | struct drm_device *dev = crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1416 | static const int sr_latency_ns = 12000; |
| 1417 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1418 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1419 | int plane_sr, cursor_sr; |
| 1420 | unsigned int enabled = 0; |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1421 | bool cxsr_enabled; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1422 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1423 | if (g4x_compute_wm0(dev, PIPE_A, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1424 | &g4x_wm_info, pessimal_latency_ns, |
| 1425 | &g4x_cursor_wm_info, pessimal_latency_ns, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1426 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1427 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1428 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1429 | if (g4x_compute_wm0(dev, PIPE_B, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1430 | &g4x_wm_info, pessimal_latency_ns, |
| 1431 | &g4x_cursor_wm_info, pessimal_latency_ns, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1432 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1433 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1434 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1435 | if (single_plane_enabled(enabled) && |
| 1436 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1437 | sr_latency_ns, |
| 1438 | &g4x_wm_info, |
| 1439 | &g4x_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1440 | &plane_sr, &cursor_sr)) { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1441 | cxsr_enabled = true; |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1442 | } else { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1443 | cxsr_enabled = false; |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1444 | intel_set_memory_cxsr(dev_priv, false); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1445 | plane_sr = cursor_sr = 0; |
| 1446 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1447 | |
Ville Syrjälä | a504345 | 2014-06-28 02:04:18 +0300 | [diff] [blame] | 1448 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
| 1449 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1450 | planea_wm, cursora_wm, |
| 1451 | planeb_wm, cursorb_wm, |
| 1452 | plane_sr, cursor_sr); |
| 1453 | |
| 1454 | I915_WRITE(DSPFW1, |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 1455 | FW_WM(plane_sr, SR) | |
| 1456 | FW_WM(cursorb_wm, CURSORB) | |
| 1457 | FW_WM(planeb_wm, PLANEB) | |
| 1458 | FW_WM(planea_wm, PLANEA)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1459 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1460 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 1461 | FW_WM(cursora_wm, CURSORA)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1462 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 1463 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1464 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 1465 | FW_WM(cursor_sr, CURSOR_SR)); |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1466 | |
| 1467 | if (cxsr_enabled) |
| 1468 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1469 | } |
| 1470 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1471 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1472 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1473 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1474 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1475 | struct drm_crtc *crtc; |
| 1476 | int srwm = 1; |
| 1477 | int cursor_sr = 16; |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1478 | bool cxsr_enabled; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1479 | |
| 1480 | /* Calc sr entries for one plane configs */ |
| 1481 | crtc = single_enabled_crtc(dev); |
| 1482 | if (crtc) { |
| 1483 | /* self-refresh has much higher latency */ |
| 1484 | static const int sr_latency_ns = 12000; |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 1485 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1486 | int clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1487 | int htotal = adjusted_mode->crtc_htotal; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1488 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
Matt Roper | 59bea88 | 2015-02-27 10:12:01 -0800 | [diff] [blame] | 1489 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1490 | unsigned long line_time_us; |
| 1491 | int entries; |
| 1492 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1493 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1494 | |
| 1495 | /* Use ns/us then divide to preserve precision */ |
| 1496 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1497 | pixel_size * hdisplay; |
| 1498 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
| 1499 | srwm = I965_FIFO_SIZE - entries; |
| 1500 | if (srwm < 0) |
| 1501 | srwm = 1; |
| 1502 | srwm &= 0x1ff; |
| 1503 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
| 1504 | entries, srwm); |
| 1505 | |
| 1506 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Matt Roper | 3dd512f | 2015-02-27 10:12:00 -0800 | [diff] [blame] | 1507 | pixel_size * crtc->cursor->state->crtc_w; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1508 | entries = DIV_ROUND_UP(entries, |
| 1509 | i965_cursor_wm_info.cacheline_size); |
| 1510 | cursor_sr = i965_cursor_wm_info.fifo_size - |
| 1511 | (entries + i965_cursor_wm_info.guard_size); |
| 1512 | |
| 1513 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 1514 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 1515 | |
| 1516 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 1517 | "cursor %d\n", srwm, cursor_sr); |
| 1518 | |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1519 | cxsr_enabled = true; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1520 | } else { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1521 | cxsr_enabled = false; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1522 | /* Turn off self refresh if both pipes are enabled */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1523 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1524 | } |
| 1525 | |
| 1526 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 1527 | srwm); |
| 1528 | |
| 1529 | /* 965 has limitations... */ |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 1530 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
| 1531 | FW_WM(8, CURSORB) | |
| 1532 | FW_WM(8, PLANEB) | |
| 1533 | FW_WM(8, PLANEA)); |
| 1534 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | |
| 1535 | FW_WM(8, PLANEC_OLD)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1536 | /* update cursor SR watermark */ |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 1537 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1538 | |
| 1539 | if (cxsr_enabled) |
| 1540 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1541 | } |
| 1542 | |
Ville Syrjälä | f499896 | 2015-03-10 17:02:21 +0200 | [diff] [blame] | 1543 | #undef FW_WM |
| 1544 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1545 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1546 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1547 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1548 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1549 | const struct intel_watermark_params *wm_info; |
| 1550 | uint32_t fwater_lo; |
| 1551 | uint32_t fwater_hi; |
| 1552 | int cwm, srwm = 1; |
| 1553 | int fifo_size; |
| 1554 | int planea_wm, planeb_wm; |
| 1555 | struct drm_crtc *crtc, *enabled = NULL; |
| 1556 | |
| 1557 | if (IS_I945GM(dev)) |
| 1558 | wm_info = &i945_wm_info; |
| 1559 | else if (!IS_GEN2(dev)) |
| 1560 | wm_info = &i915_wm_info; |
| 1561 | else |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1562 | wm_info = &i830_a_wm_info; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1563 | |
| 1564 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 1565 | crtc = intel_get_crtc_for_plane(dev, 0); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1566 | if (intel_crtc_active(crtc)) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1567 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | 59bea88 | 2015-02-27 10:12:01 -0800 | [diff] [blame] | 1568 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1569 | if (IS_GEN2(dev)) |
| 1570 | cpp = 4; |
| 1571 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1572 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1573 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1574 | wm_info, fifo_size, cpp, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1575 | pessimal_latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1576 | enabled = crtc; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1577 | } else { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1578 | planea_wm = fifo_size - wm_info->guard_size; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1579 | if (planea_wm > (long)wm_info->max_wm) |
| 1580 | planea_wm = wm_info->max_wm; |
| 1581 | } |
| 1582 | |
| 1583 | if (IS_GEN2(dev)) |
| 1584 | wm_info = &i830_bc_wm_info; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1585 | |
| 1586 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
| 1587 | crtc = intel_get_crtc_for_plane(dev, 1); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1588 | if (intel_crtc_active(crtc)) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1589 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | 59bea88 | 2015-02-27 10:12:01 -0800 | [diff] [blame] | 1590 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1591 | if (IS_GEN2(dev)) |
| 1592 | cpp = 4; |
| 1593 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1594 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1595 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1596 | wm_info, fifo_size, cpp, |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1597 | pessimal_latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1598 | if (enabled == NULL) |
| 1599 | enabled = crtc; |
| 1600 | else |
| 1601 | enabled = NULL; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1602 | } else { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1603 | planeb_wm = fifo_size - wm_info->guard_size; |
Ville Syrjälä | 9d53910 | 2014-08-15 01:21:53 +0300 | [diff] [blame] | 1604 | if (planeb_wm > (long)wm_info->max_wm) |
| 1605 | planeb_wm = wm_info->max_wm; |
| 1606 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1607 | |
| 1608 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 1609 | |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1610 | if (IS_I915GM(dev) && enabled) { |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 1611 | struct drm_i915_gem_object *obj; |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1612 | |
Matt Roper | 59bea88 | 2015-02-27 10:12:01 -0800 | [diff] [blame] | 1613 | obj = intel_fb_obj(enabled->primary->state->fb); |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1614 | |
| 1615 | /* self-refresh seems busted with untiled */ |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 1616 | if (obj->tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1617 | enabled = NULL; |
| 1618 | } |
| 1619 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1620 | /* |
| 1621 | * Overlay gets an aggressive default since video jitter is bad. |
| 1622 | */ |
| 1623 | cwm = 2; |
| 1624 | |
| 1625 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1626 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1627 | |
| 1628 | /* Calc sr entries for one plane configs */ |
| 1629 | if (HAS_FW_BLC(dev) && enabled) { |
| 1630 | /* self-refresh has much higher latency */ |
| 1631 | static const int sr_latency_ns = 6000; |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 1632 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1633 | int clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1634 | int htotal = adjusted_mode->crtc_htotal; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1635 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
Matt Roper | 59bea88 | 2015-02-27 10:12:01 -0800 | [diff] [blame] | 1636 | int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1637 | unsigned long line_time_us; |
| 1638 | int entries; |
| 1639 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1640 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1641 | |
| 1642 | /* Use ns/us then divide to preserve precision */ |
| 1643 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1644 | pixel_size * hdisplay; |
| 1645 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
| 1646 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
| 1647 | srwm = wm_info->fifo_size - entries; |
| 1648 | if (srwm < 0) |
| 1649 | srwm = 1; |
| 1650 | |
| 1651 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1652 | I915_WRITE(FW_BLC_SELF, |
| 1653 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 1654 | else if (IS_I915GM(dev)) |
| 1655 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
| 1656 | } |
| 1657 | |
| 1658 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
| 1659 | planea_wm, planeb_wm, cwm, srwm); |
| 1660 | |
| 1661 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 1662 | fwater_hi = (cwm & 0x1f); |
| 1663 | |
| 1664 | /* Set request length to 8 cachelines per fetch */ |
| 1665 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 1666 | fwater_hi = fwater_hi | (1 << 8); |
| 1667 | |
| 1668 | I915_WRITE(FW_BLC, fwater_lo); |
| 1669 | I915_WRITE(FW_BLC2, fwater_hi); |
| 1670 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1671 | if (enabled) |
| 1672 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1673 | } |
| 1674 | |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1675 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1676 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1677 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1678 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1679 | struct drm_crtc *crtc; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1680 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1681 | uint32_t fwater_lo; |
| 1682 | int planea_wm; |
| 1683 | |
| 1684 | crtc = single_enabled_crtc(dev); |
| 1685 | if (crtc == NULL) |
| 1686 | return; |
| 1687 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 1688 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1689 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1690 | &i845_wm_info, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1691 | dev_priv->display.get_fifo_size(dev, 0), |
Chris Wilson | 5aef600 | 2014-09-03 11:56:07 +0100 | [diff] [blame] | 1692 | 4, pessimal_latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1693 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
| 1694 | fwater_lo |= (3<<8) | planea_wm; |
| 1695 | |
| 1696 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
| 1697 | |
| 1698 | I915_WRITE(FW_BLC, fwater_lo); |
| 1699 | } |
| 1700 | |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 1701 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1702 | { |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 1703 | uint32_t pixel_rate; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1704 | |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 1705 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1706 | |
| 1707 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to |
| 1708 | * adjust the pixel_rate here. */ |
| 1709 | |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 1710 | if (pipe_config->pch_pfit.enabled) { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1711 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 1712 | uint32_t pfit_size = pipe_config->pch_pfit.size; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1713 | |
Ville Syrjälä | 8cfb340 | 2015-06-03 15:45:11 +0300 | [diff] [blame] | 1714 | pipe_w = pipe_config->pipe_src_w; |
| 1715 | pipe_h = pipe_config->pipe_src_h; |
| 1716 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1717 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
| 1718 | pfit_h = pfit_size & 0xFFFF; |
| 1719 | if (pipe_w < pfit_w) |
| 1720 | pipe_w = pfit_w; |
| 1721 | if (pipe_h < pfit_h) |
| 1722 | pipe_h = pfit_h; |
| 1723 | |
| 1724 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
| 1725 | pfit_w * pfit_h); |
| 1726 | } |
| 1727 | |
| 1728 | return pixel_rate; |
| 1729 | } |
| 1730 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1731 | /* latency must be in 0.1us units. */ |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1732 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1733 | uint32_t latency) |
| 1734 | { |
| 1735 | uint64_t ret; |
| 1736 | |
Ville Syrjälä | 3312ba6 | 2013-08-01 16:18:53 +0300 | [diff] [blame] | 1737 | if (WARN(latency == 0, "Latency value missing\n")) |
| 1738 | return UINT_MAX; |
| 1739 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1740 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
| 1741 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
| 1742 | |
| 1743 | return ret; |
| 1744 | } |
| 1745 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1746 | /* latency must be in 0.1us units. */ |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1747 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1748 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
| 1749 | uint32_t latency) |
| 1750 | { |
| 1751 | uint32_t ret; |
| 1752 | |
Ville Syrjälä | 3312ba6 | 2013-08-01 16:18:53 +0300 | [diff] [blame] | 1753 | if (WARN(latency == 0, "Latency value missing\n")) |
| 1754 | return UINT_MAX; |
| 1755 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1756 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
| 1757 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
| 1758 | ret = DIV_ROUND_UP(ret, 64) + 2; |
| 1759 | return ret; |
| 1760 | } |
| 1761 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1762 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1763 | uint8_t bytes_per_pixel) |
| 1764 | { |
| 1765 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; |
| 1766 | } |
| 1767 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1768 | struct ilk_wm_maximums { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1769 | uint16_t pri; |
| 1770 | uint16_t spr; |
| 1771 | uint16_t cur; |
| 1772 | uint16_t fbc; |
| 1773 | }; |
| 1774 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 1775 | /* used in computing the new watermarks state */ |
| 1776 | struct intel_wm_config { |
| 1777 | unsigned int num_pipes_active; |
| 1778 | bool sprites_enabled; |
| 1779 | bool sprites_scaled; |
| 1780 | }; |
| 1781 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1782 | /* |
| 1783 | * For both WM_PIPE and WM_LP. |
| 1784 | * mem_value must be in 0.1us units. |
| 1785 | */ |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1786 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1787 | const struct intel_plane_state *pstate, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1788 | uint32_t mem_value, |
| 1789 | bool is_lp) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1790 | { |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1791 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1792 | uint32_t method1, method2; |
| 1793 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1794 | if (!cstate->base.active || !pstate->visible) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1795 | return 0; |
| 1796 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1797 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1798 | |
| 1799 | if (!is_lp) |
| 1800 | return method1; |
| 1801 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1802 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
| 1803 | cstate->base.adjusted_mode.crtc_htotal, |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1804 | drm_rect_width(&pstate->dst), |
| 1805 | bpp, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1806 | mem_value); |
| 1807 | |
| 1808 | return min(method1, method2); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1809 | } |
| 1810 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1811 | /* |
| 1812 | * For both WM_PIPE and WM_LP. |
| 1813 | * mem_value must be in 0.1us units. |
| 1814 | */ |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1815 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1816 | const struct intel_plane_state *pstate, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1817 | uint32_t mem_value) |
| 1818 | { |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1819 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1820 | uint32_t method1, method2; |
| 1821 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1822 | if (!cstate->base.active || !pstate->visible) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1823 | return 0; |
| 1824 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1825 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
| 1826 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
| 1827 | cstate->base.adjusted_mode.crtc_htotal, |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1828 | drm_rect_width(&pstate->dst), |
| 1829 | bpp, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1830 | mem_value); |
| 1831 | return min(method1, method2); |
| 1832 | } |
| 1833 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1834 | /* |
| 1835 | * For both WM_PIPE and WM_LP. |
| 1836 | * mem_value must be in 0.1us units. |
| 1837 | */ |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1838 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1839 | const struct intel_plane_state *pstate, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1840 | uint32_t mem_value) |
| 1841 | { |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1842 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
| 1843 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1844 | if (!cstate->base.active || !pstate->visible) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1845 | return 0; |
| 1846 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1847 | return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
| 1848 | cstate->base.adjusted_mode.crtc_htotal, |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1849 | drm_rect_width(&pstate->dst), |
| 1850 | bpp, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1851 | mem_value); |
| 1852 | } |
| 1853 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1854 | /* Only for WM_LP. */ |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1855 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1856 | const struct intel_plane_state *pstate, |
Ville Syrjälä | 1fda988 | 2013-07-05 11:57:19 +0300 | [diff] [blame] | 1857 | uint32_t pri_val) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1858 | { |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1859 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
| 1860 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 1861 | if (!cstate->base.active || !pstate->visible) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1862 | return 0; |
| 1863 | |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 1864 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1865 | } |
| 1866 | |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1867 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
| 1868 | { |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 1869 | if (INTEL_INFO(dev)->gen >= 8) |
| 1870 | return 3072; |
| 1871 | else if (INTEL_INFO(dev)->gen >= 7) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1872 | return 768; |
| 1873 | else |
| 1874 | return 512; |
| 1875 | } |
| 1876 | |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1877 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
| 1878 | int level, bool is_sprite) |
| 1879 | { |
| 1880 | if (INTEL_INFO(dev)->gen >= 8) |
| 1881 | /* BDW primary/sprite plane watermarks */ |
| 1882 | return level == 0 ? 255 : 2047; |
| 1883 | else if (INTEL_INFO(dev)->gen >= 7) |
| 1884 | /* IVB/HSW primary/sprite plane watermarks */ |
| 1885 | return level == 0 ? 127 : 1023; |
| 1886 | else if (!is_sprite) |
| 1887 | /* ILK/SNB primary plane watermarks */ |
| 1888 | return level == 0 ? 127 : 511; |
| 1889 | else |
| 1890 | /* ILK/SNB sprite plane watermarks */ |
| 1891 | return level == 0 ? 63 : 255; |
| 1892 | } |
| 1893 | |
| 1894 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, |
| 1895 | int level) |
| 1896 | { |
| 1897 | if (INTEL_INFO(dev)->gen >= 7) |
| 1898 | return level == 0 ? 63 : 255; |
| 1899 | else |
| 1900 | return level == 0 ? 31 : 63; |
| 1901 | } |
| 1902 | |
| 1903 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) |
| 1904 | { |
| 1905 | if (INTEL_INFO(dev)->gen >= 8) |
| 1906 | return 31; |
| 1907 | else |
| 1908 | return 15; |
| 1909 | } |
| 1910 | |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1911 | /* Calculate the maximum primary/sprite plane watermark */ |
| 1912 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, |
| 1913 | int level, |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1914 | const struct intel_wm_config *config, |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1915 | enum intel_ddb_partitioning ddb_partitioning, |
| 1916 | bool is_sprite) |
| 1917 | { |
| 1918 | unsigned int fifo_size = ilk_display_fifo_size(dev); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1919 | |
| 1920 | /* if sprites aren't enabled, sprites get nothing */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1921 | if (is_sprite && !config->sprites_enabled) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1922 | return 0; |
| 1923 | |
| 1924 | /* HSW allows LP1+ watermarks even with multiple pipes */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1925 | if (level == 0 || config->num_pipes_active > 1) { |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1926 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
| 1927 | |
| 1928 | /* |
| 1929 | * For some reason the non self refresh |
| 1930 | * FIFO size is only half of the self |
| 1931 | * refresh FIFO size on ILK/SNB. |
| 1932 | */ |
| 1933 | if (INTEL_INFO(dev)->gen <= 6) |
| 1934 | fifo_size /= 2; |
| 1935 | } |
| 1936 | |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1937 | if (config->sprites_enabled) { |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1938 | /* level 0 is always calculated with 1:1 split */ |
| 1939 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { |
| 1940 | if (is_sprite) |
| 1941 | fifo_size *= 5; |
| 1942 | fifo_size /= 6; |
| 1943 | } else { |
| 1944 | fifo_size /= 2; |
| 1945 | } |
| 1946 | } |
| 1947 | |
| 1948 | /* clamp to max that the registers can hold */ |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1949 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1950 | } |
| 1951 | |
| 1952 | /* Calculate the maximum cursor plane watermark */ |
| 1953 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1954 | int level, |
| 1955 | const struct intel_wm_config *config) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1956 | { |
| 1957 | /* HSW LP1+ watermarks w/ multiple pipes */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1958 | if (level > 0 && config->num_pipes_active > 1) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1959 | return 64; |
| 1960 | |
| 1961 | /* otherwise just report max that registers can hold */ |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1962 | return ilk_cursor_wm_reg_max(dev, level); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1963 | } |
| 1964 | |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 1965 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 1966 | int level, |
| 1967 | const struct intel_wm_config *config, |
| 1968 | enum intel_ddb_partitioning ddb_partitioning, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1969 | struct ilk_wm_maximums *max) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1970 | { |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1971 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
| 1972 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); |
| 1973 | max->cur = ilk_cursor_wm_max(dev, level, config); |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1974 | max->fbc = ilk_fbc_wm_reg_max(dev); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1975 | } |
| 1976 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 1977 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
| 1978 | int level, |
| 1979 | struct ilk_wm_maximums *max) |
| 1980 | { |
| 1981 | max->pri = ilk_plane_wm_reg_max(dev, level, false); |
| 1982 | max->spr = ilk_plane_wm_reg_max(dev, level, true); |
| 1983 | max->cur = ilk_cursor_wm_reg_max(dev, level); |
| 1984 | max->fbc = ilk_fbc_wm_reg_max(dev); |
| 1985 | } |
| 1986 | |
Ville Syrjälä | d939565 | 2013-10-09 19:18:10 +0300 | [diff] [blame] | 1987 | static bool ilk_validate_wm_level(int level, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1988 | const struct ilk_wm_maximums *max, |
Ville Syrjälä | d939565 | 2013-10-09 19:18:10 +0300 | [diff] [blame] | 1989 | struct intel_wm_level *result) |
Ville Syrjälä | a9786a1 | 2013-08-07 13:24:47 +0300 | [diff] [blame] | 1990 | { |
| 1991 | bool ret; |
| 1992 | |
| 1993 | /* already determined to be invalid? */ |
| 1994 | if (!result->enable) |
| 1995 | return false; |
| 1996 | |
| 1997 | result->enable = result->pri_val <= max->pri && |
| 1998 | result->spr_val <= max->spr && |
| 1999 | result->cur_val <= max->cur; |
| 2000 | |
| 2001 | ret = result->enable; |
| 2002 | |
| 2003 | /* |
| 2004 | * HACK until we can pre-compute everything, |
| 2005 | * and thus fail gracefully if LP0 watermarks |
| 2006 | * are exceeded... |
| 2007 | */ |
| 2008 | if (level == 0 && !result->enable) { |
| 2009 | if (result->pri_val > max->pri) |
| 2010 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", |
| 2011 | level, result->pri_val, max->pri); |
| 2012 | if (result->spr_val > max->spr) |
| 2013 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", |
| 2014 | level, result->spr_val, max->spr); |
| 2015 | if (result->cur_val > max->cur) |
| 2016 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", |
| 2017 | level, result->cur_val, max->cur); |
| 2018 | |
| 2019 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); |
| 2020 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); |
| 2021 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); |
| 2022 | result->enable = true; |
| 2023 | } |
| 2024 | |
Ville Syrjälä | a9786a1 | 2013-08-07 13:24:47 +0300 | [diff] [blame] | 2025 | return ret; |
| 2026 | } |
| 2027 | |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 2028 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 2029 | const struct intel_crtc *intel_crtc, |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 2030 | int level, |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 2031 | struct intel_crtc_state *cstate, |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 2032 | struct intel_wm_level *result) |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 2033 | { |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2034 | struct intel_plane *intel_plane; |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 2035 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; |
| 2036 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; |
| 2037 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; |
| 2038 | |
| 2039 | /* WM1+ latency values stored in 0.5us units */ |
| 2040 | if (level > 0) { |
| 2041 | pri_latency *= 5; |
| 2042 | spr_latency *= 5; |
| 2043 | cur_latency *= 5; |
| 2044 | } |
| 2045 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2046 | for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) { |
| 2047 | struct intel_plane_state *pstate = |
| 2048 | to_intel_plane_state(intel_plane->base.state); |
| 2049 | |
| 2050 | switch (intel_plane->base.type) { |
| 2051 | case DRM_PLANE_TYPE_PRIMARY: |
| 2052 | result->pri_val = ilk_compute_pri_wm(cstate, pstate, |
| 2053 | pri_latency, |
| 2054 | level); |
| 2055 | result->fbc_val = ilk_compute_fbc_wm(cstate, pstate, |
| 2056 | result->pri_val); |
| 2057 | break; |
| 2058 | case DRM_PLANE_TYPE_OVERLAY: |
| 2059 | result->spr_val = ilk_compute_spr_wm(cstate, pstate, |
| 2060 | spr_latency); |
| 2061 | break; |
| 2062 | case DRM_PLANE_TYPE_CURSOR: |
| 2063 | result->cur_val = ilk_compute_cur_wm(cstate, pstate, |
| 2064 | cur_latency); |
| 2065 | break; |
| 2066 | } |
| 2067 | } |
| 2068 | |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 2069 | result->enable = true; |
| 2070 | } |
| 2071 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2072 | static uint32_t |
| 2073 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2074 | { |
| 2075 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2076 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 2077 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 2078 | u32 linetime, ips_linetime; |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2079 | |
Matt Roper | 3ef0028 | 2015-03-09 10:19:24 -0700 | [diff] [blame] | 2080 | if (!intel_crtc->active) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2081 | return 0; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2082 | |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2083 | /* The WM are computed with base on how long it takes to fill a single |
| 2084 | * row at the given clock rate, multiplied by 8. |
| 2085 | * */ |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 2086 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
| 2087 | adjusted_mode->crtc_clock); |
| 2088 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
Ville Syrjälä | 05024da | 2015-06-03 15:45:08 +0300 | [diff] [blame] | 2089 | dev_priv->cdclk_freq); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2090 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2091 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
| 2092 | PIPE_WM_LINETIME_TIME(linetime); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2093 | } |
| 2094 | |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 2095 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2096 | { |
| 2097 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2098 | |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 2099 | if (IS_GEN9(dev)) { |
| 2100 | uint32_t val; |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 2101 | int ret, i; |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 2102 | int level, max_level = ilk_wm_max_level(dev); |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 2103 | |
| 2104 | /* read the first set of memory latencies[0:3] */ |
| 2105 | val = 0; /* data0 to be programmed to 0 for first set */ |
| 2106 | mutex_lock(&dev_priv->rps.hw_lock); |
| 2107 | ret = sandybridge_pcode_read(dev_priv, |
| 2108 | GEN9_PCODE_READ_MEM_LATENCY, |
| 2109 | &val); |
| 2110 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 2111 | |
| 2112 | if (ret) { |
| 2113 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); |
| 2114 | return; |
| 2115 | } |
| 2116 | |
| 2117 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; |
| 2118 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & |
| 2119 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 2120 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & |
| 2121 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 2122 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & |
| 2123 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 2124 | |
| 2125 | /* read the second set of memory latencies[4:7] */ |
| 2126 | val = 1; /* data0 to be programmed to 1 for second set */ |
| 2127 | mutex_lock(&dev_priv->rps.hw_lock); |
| 2128 | ret = sandybridge_pcode_read(dev_priv, |
| 2129 | GEN9_PCODE_READ_MEM_LATENCY, |
| 2130 | &val); |
| 2131 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 2132 | if (ret) { |
| 2133 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); |
| 2134 | return; |
| 2135 | } |
| 2136 | |
| 2137 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; |
| 2138 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & |
| 2139 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 2140 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & |
| 2141 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 2142 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & |
| 2143 | GEN9_MEM_LATENCY_LEVEL_MASK; |
| 2144 | |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 2145 | /* |
Damien Lespiau | 6f97235 | 2015-02-09 19:33:07 +0000 | [diff] [blame] | 2146 | * WaWmMemoryReadLatency:skl |
| 2147 | * |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 2148 | * punit doesn't take into account the read latency so we need |
| 2149 | * to add 2us to the various latency levels we retrieve from |
| 2150 | * the punit. |
| 2151 | * - W0 is a bit special in that it's the only level that |
| 2152 | * can't be disabled if we want to have display working, so |
| 2153 | * we always add 2us there. |
| 2154 | * - For levels >=1, punit returns 0us latency when they are |
| 2155 | * disabled, so we respect that and don't add 2us then |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 2156 | * |
| 2157 | * Additionally, if a level n (n > 1) has a 0us latency, all |
| 2158 | * levels m (m >= n) need to be disabled. We make sure to |
| 2159 | * sanitize the values out of the punit to satisfy this |
| 2160 | * requirement. |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 2161 | */ |
| 2162 | wm[0] += 2; |
| 2163 | for (level = 1; level <= max_level; level++) |
| 2164 | if (wm[level] != 0) |
| 2165 | wm[level] += 2; |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 2166 | else { |
| 2167 | for (i = level + 1; i <= max_level; i++) |
| 2168 | wm[i] = 0; |
Vandana Kannan | 367294b | 2014-11-04 17:06:46 +0000 | [diff] [blame] | 2169 | |
Vandana Kannan | 4f94738 | 2014-11-04 17:06:47 +0000 | [diff] [blame] | 2170 | break; |
| 2171 | } |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 2172 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2173 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
| 2174 | |
| 2175 | wm[0] = (sskpd >> 56) & 0xFF; |
| 2176 | if (wm[0] == 0) |
| 2177 | wm[0] = sskpd & 0xF; |
Ville Syrjälä | e5d5019 | 2013-07-05 11:57:22 +0300 | [diff] [blame] | 2178 | wm[1] = (sskpd >> 4) & 0xFF; |
| 2179 | wm[2] = (sskpd >> 12) & 0xFF; |
| 2180 | wm[3] = (sskpd >> 20) & 0x1FF; |
| 2181 | wm[4] = (sskpd >> 32) & 0x1FF; |
Ville Syrjälä | 63cf9a1 | 2013-07-05 11:57:23 +0300 | [diff] [blame] | 2182 | } else if (INTEL_INFO(dev)->gen >= 6) { |
| 2183 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
| 2184 | |
| 2185 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; |
| 2186 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; |
| 2187 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; |
| 2188 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; |
Ville Syrjälä | 3a88d0a | 2013-08-01 16:18:49 +0300 | [diff] [blame] | 2189 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 2190 | uint32_t mltr = I915_READ(MLTR_ILK); |
| 2191 | |
| 2192 | /* ILK primary LP0 latency is 700 ns */ |
| 2193 | wm[0] = 7; |
| 2194 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; |
| 2195 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2196 | } |
| 2197 | } |
| 2198 | |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2199 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 2200 | { |
| 2201 | /* ILK sprite LP0 latency is 1300 ns */ |
| 2202 | if (INTEL_INFO(dev)->gen == 5) |
| 2203 | wm[0] = 13; |
| 2204 | } |
| 2205 | |
| 2206 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 2207 | { |
| 2208 | /* ILK cursor LP0 latency is 1300 ns */ |
| 2209 | if (INTEL_INFO(dev)->gen == 5) |
| 2210 | wm[0] = 13; |
| 2211 | |
| 2212 | /* WaDoubleCursorLP3Latency:ivb */ |
| 2213 | if (IS_IVYBRIDGE(dev)) |
| 2214 | wm[3] *= 2; |
| 2215 | } |
| 2216 | |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 2217 | int ilk_wm_max_level(const struct drm_device *dev) |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2218 | { |
| 2219 | /* how many WM levels are we expecting */ |
Damien Lespiau | b6e742f | 2015-05-09 02:05:55 +0100 | [diff] [blame] | 2220 | if (INTEL_INFO(dev)->gen >= 9) |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 2221 | return 7; |
| 2222 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2223 | return 4; |
| 2224 | else if (INTEL_INFO(dev)->gen >= 6) |
| 2225 | return 3; |
| 2226 | else |
| 2227 | return 2; |
| 2228 | } |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 2229 | |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2230 | static void intel_print_wm_latency(struct drm_device *dev, |
| 2231 | const char *name, |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 2232 | const uint16_t wm[8]) |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2233 | { |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2234 | int level, max_level = ilk_wm_max_level(dev); |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2235 | |
| 2236 | for (level = 0; level <= max_level; level++) { |
| 2237 | unsigned int latency = wm[level]; |
| 2238 | |
| 2239 | if (latency == 0) { |
| 2240 | DRM_ERROR("%s WM%d latency not provided\n", |
| 2241 | name, level); |
| 2242 | continue; |
| 2243 | } |
| 2244 | |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 2245 | /* |
| 2246 | * - latencies are in us on gen9. |
| 2247 | * - before then, WM1+ latency values are in 0.5us units |
| 2248 | */ |
| 2249 | if (IS_GEN9(dev)) |
| 2250 | latency *= 10; |
| 2251 | else if (level > 0) |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2252 | latency *= 5; |
| 2253 | |
| 2254 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", |
| 2255 | name, level, wm[level], |
| 2256 | latency / 10, latency % 10); |
| 2257 | } |
| 2258 | } |
| 2259 | |
Ville Syrjälä | e95a2f7 | 2014-05-08 15:09:19 +0300 | [diff] [blame] | 2260 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
| 2261 | uint16_t wm[5], uint16_t min) |
| 2262 | { |
| 2263 | int level, max_level = ilk_wm_max_level(dev_priv->dev); |
| 2264 | |
| 2265 | if (wm[0] >= min) |
| 2266 | return false; |
| 2267 | |
| 2268 | wm[0] = max(wm[0], min); |
| 2269 | for (level = 1; level <= max_level; level++) |
| 2270 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); |
| 2271 | |
| 2272 | return true; |
| 2273 | } |
| 2274 | |
| 2275 | static void snb_wm_latency_quirk(struct drm_device *dev) |
| 2276 | { |
| 2277 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2278 | bool changed; |
| 2279 | |
| 2280 | /* |
| 2281 | * The BIOS provided WM memory latency values are often |
| 2282 | * inadequate for high resolution displays. Adjust them. |
| 2283 | */ |
| 2284 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | |
| 2285 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | |
| 2286 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); |
| 2287 | |
| 2288 | if (!changed) |
| 2289 | return; |
| 2290 | |
| 2291 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); |
| 2292 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
| 2293 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
| 2294 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
| 2295 | } |
| 2296 | |
Damien Lespiau | fa50ad6 | 2014-03-17 18:01:16 +0000 | [diff] [blame] | 2297 | static void ilk_setup_wm_latency(struct drm_device *dev) |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2298 | { |
| 2299 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2300 | |
| 2301 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); |
| 2302 | |
| 2303 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, |
| 2304 | sizeof(dev_priv->wm.pri_latency)); |
| 2305 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, |
| 2306 | sizeof(dev_priv->wm.pri_latency)); |
| 2307 | |
| 2308 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); |
| 2309 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2310 | |
| 2311 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
| 2312 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
| 2313 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
Ville Syrjälä | e95a2f7 | 2014-05-08 15:09:19 +0300 | [diff] [blame] | 2314 | |
| 2315 | if (IS_GEN6(dev)) |
| 2316 | snb_wm_latency_quirk(dev); |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2317 | } |
| 2318 | |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 2319 | static void skl_setup_wm_latency(struct drm_device *dev) |
| 2320 | { |
| 2321 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2322 | |
| 2323 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); |
| 2324 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); |
| 2325 | } |
| 2326 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2327 | static void ilk_compute_wm_config(struct drm_device *dev, |
| 2328 | struct intel_wm_config *config) |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2329 | { |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2330 | struct intel_crtc *intel_crtc; |
| 2331 | |
| 2332 | /* Compute the currently _active_ config */ |
| 2333 | for_each_intel_crtc(dev, intel_crtc) { |
| 2334 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
| 2335 | |
| 2336 | if (!wm->pipe_enabled) |
| 2337 | continue; |
| 2338 | |
| 2339 | config->sprites_enabled |= wm->sprites_enabled; |
| 2340 | config->sprites_scaled |= wm->sprites_scaled; |
| 2341 | config->num_pipes_active++; |
| 2342 | } |
| 2343 | } |
| 2344 | |
| 2345 | /* Compute new watermarks for the pipe */ |
| 2346 | static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, |
| 2347 | struct intel_pipe_wm *pipe_wm) |
| 2348 | { |
| 2349 | struct drm_crtc *crtc = cstate->base.crtc; |
| 2350 | struct drm_device *dev = crtc->dev; |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 2351 | const struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2352 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 2353 | struct intel_plane *intel_plane; |
| 2354 | struct intel_plane_state *sprstate = NULL; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2355 | int level, max_level = ilk_wm_max_level(dev); |
| 2356 | /* LP0 watermark maximums depend on this pipe alone */ |
| 2357 | struct intel_wm_config config = { |
| 2358 | .num_pipes_active = 1, |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2359 | }; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2360 | struct ilk_wm_maximums max; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2361 | |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 2362 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2363 | if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) { |
| 2364 | sprstate = to_intel_plane_state(intel_plane->base.state); |
| 2365 | break; |
| 2366 | } |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 2367 | } |
| 2368 | |
| 2369 | config.sprites_enabled = sprstate->visible; |
| 2370 | config.sprites_scaled = sprstate->visible && |
| 2371 | (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || |
| 2372 | drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); |
| 2373 | |
Matt Roper | 7221fc3 | 2015-09-24 15:53:08 -0700 | [diff] [blame] | 2374 | pipe_wm->pipe_enabled = cstate->base.active; |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2375 | pipe_wm->sprites_enabled = sprstate->visible; |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 2376 | pipe_wm->sprites_scaled = config.sprites_scaled; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2377 | |
Ville Syrjälä | 7b39a0b | 2013-12-05 15:51:30 +0200 | [diff] [blame] | 2378 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 2379 | if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) |
Ville Syrjälä | 7b39a0b | 2013-12-05 15:51:30 +0200 | [diff] [blame] | 2380 | max_level = 1; |
| 2381 | |
| 2382 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ |
Matt Roper | 43d59ed | 2015-09-24 15:53:07 -0700 | [diff] [blame] | 2383 | if (config.sprites_scaled) |
Ville Syrjälä | 7b39a0b | 2013-12-05 15:51:30 +0200 | [diff] [blame] | 2384 | max_level = 0; |
| 2385 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2386 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2387 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2388 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2389 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2390 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2391 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
| 2392 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); |
| 2393 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2394 | /* At least LP0 must be valid */ |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2395 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2396 | return false; |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2397 | |
| 2398 | ilk_compute_wm_reg_maximums(dev, 1, &max); |
| 2399 | |
| 2400 | for (level = 1; level <= max_level; level++) { |
| 2401 | struct intel_wm_level wm = {}; |
| 2402 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2403 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm); |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2404 | |
| 2405 | /* |
| 2406 | * Disable any watermark level that exceeds the |
| 2407 | * register maximums since such watermarks are |
| 2408 | * always invalid. |
| 2409 | */ |
| 2410 | if (!ilk_validate_wm_level(level, &max, &wm)) |
| 2411 | break; |
| 2412 | |
| 2413 | pipe_wm->wm[level] = wm; |
| 2414 | } |
| 2415 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2416 | return true; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2417 | } |
| 2418 | |
| 2419 | /* |
| 2420 | * Merge the watermarks from all active pipes for a specific level. |
| 2421 | */ |
| 2422 | static void ilk_merge_wm_level(struct drm_device *dev, |
| 2423 | int level, |
| 2424 | struct intel_wm_level *ret_wm) |
| 2425 | { |
| 2426 | const struct intel_crtc *intel_crtc; |
| 2427 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2428 | ret_wm->enable = true; |
| 2429 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2430 | for_each_intel_crtc(dev, intel_crtc) { |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2431 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
Ville Syrjälä | fe392ef | 2014-03-07 18:32:10 +0200 | [diff] [blame] | 2432 | const struct intel_wm_level *wm = &active->wm[level]; |
| 2433 | |
| 2434 | if (!active->pipe_enabled) |
| 2435 | continue; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2436 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2437 | /* |
| 2438 | * The watermark values may have been used in the past, |
| 2439 | * so we must maintain them in the registers for some |
| 2440 | * time even if the level is now disabled. |
| 2441 | */ |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2442 | if (!wm->enable) |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2443 | ret_wm->enable = false; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2444 | |
| 2445 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); |
| 2446 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); |
| 2447 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); |
| 2448 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); |
| 2449 | } |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2450 | } |
| 2451 | |
| 2452 | /* |
| 2453 | * Merge all low power watermarks for all active pipes. |
| 2454 | */ |
| 2455 | static void ilk_wm_merge(struct drm_device *dev, |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2456 | const struct intel_wm_config *config, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2457 | const struct ilk_wm_maximums *max, |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2458 | struct intel_pipe_wm *merged) |
| 2459 | { |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 2460 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2461 | int level, max_level = ilk_wm_max_level(dev); |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2462 | int last_enabled_level = max_level; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2463 | |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2464 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
| 2465 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && |
| 2466 | config->num_pipes_active > 1) |
| 2467 | return; |
| 2468 | |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2469 | /* ILK: FBC WM must be disabled always */ |
| 2470 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2471 | |
| 2472 | /* merge each WM1+ level */ |
| 2473 | for (level = 1; level <= max_level; level++) { |
| 2474 | struct intel_wm_level *wm = &merged->wm[level]; |
| 2475 | |
| 2476 | ilk_merge_wm_level(dev, level, wm); |
| 2477 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2478 | if (level > last_enabled_level) |
| 2479 | wm->enable = false; |
| 2480 | else if (!ilk_validate_wm_level(level, max, wm)) |
| 2481 | /* make sure all following levels get disabled */ |
| 2482 | last_enabled_level = level - 1; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2483 | |
| 2484 | /* |
| 2485 | * The spec says it is preferred to disable |
| 2486 | * FBC WMs instead of disabling a WM level. |
| 2487 | */ |
| 2488 | if (wm->fbc_val > max->fbc) { |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2489 | if (wm->enable) |
| 2490 | merged->fbc_wm_enabled = false; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2491 | wm->fbc_val = 0; |
| 2492 | } |
| 2493 | } |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2494 | |
| 2495 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ |
| 2496 | /* |
| 2497 | * FIXME this is racy. FBC might get enabled later. |
| 2498 | * What we should check here is whether FBC can be |
| 2499 | * enabled sometime later. |
| 2500 | */ |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 2501 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && |
| 2502 | intel_fbc_enabled(dev_priv)) { |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2503 | for (level = 2; level <= max_level; level++) { |
| 2504 | struct intel_wm_level *wm = &merged->wm[level]; |
| 2505 | |
| 2506 | wm->enable = false; |
| 2507 | } |
| 2508 | } |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2509 | } |
| 2510 | |
Ville Syrjälä | b380ca3 | 2013-10-09 19:18:01 +0300 | [diff] [blame] | 2511 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
| 2512 | { |
| 2513 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ |
| 2514 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); |
| 2515 | } |
| 2516 | |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2517 | /* The value we need to program into the WM_LPx latency field */ |
| 2518 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) |
| 2519 | { |
| 2520 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2521 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2522 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2523 | return 2 * level; |
| 2524 | else |
| 2525 | return dev_priv->wm.pri_latency[level]; |
| 2526 | } |
| 2527 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2528 | static void ilk_compute_wm_results(struct drm_device *dev, |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2529 | const struct intel_pipe_wm *merged, |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2530 | enum intel_ddb_partitioning partitioning, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2531 | struct ilk_wm_values *results) |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2532 | { |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2533 | struct intel_crtc *intel_crtc; |
| 2534 | int level, wm_lp; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2535 | |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2536 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2537 | results->partitioning = partitioning; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2538 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2539 | /* LP1+ register values */ |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2540 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 2541 | const struct intel_wm_level *r; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2542 | |
Ville Syrjälä | b380ca3 | 2013-10-09 19:18:01 +0300 | [diff] [blame] | 2543 | level = ilk_wm_lp_to_level(wm_lp, merged); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2544 | |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2545 | r = &merged->wm[level]; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2546 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2547 | /* |
| 2548 | * Maintain the watermark values even if the level is |
| 2549 | * disabled. Doing otherwise could cause underruns. |
| 2550 | */ |
| 2551 | results->wm_lp[wm_lp - 1] = |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2552 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 2553 | (r->pri_val << WM1_LP_SR_SHIFT) | |
| 2554 | r->cur_val; |
| 2555 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2556 | if (r->enable) |
| 2557 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; |
| 2558 | |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 2559 | if (INTEL_INFO(dev)->gen >= 8) |
| 2560 | results->wm_lp[wm_lp - 1] |= |
| 2561 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; |
| 2562 | else |
| 2563 | results->wm_lp[wm_lp - 1] |= |
| 2564 | r->fbc_val << WM1_LP_FBC_SHIFT; |
| 2565 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2566 | /* |
| 2567 | * Always set WM1S_LP_EN when spr_val != 0, even if the |
| 2568 | * level is disabled. Doing otherwise could cause underruns. |
| 2569 | */ |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2570 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
| 2571 | WARN_ON(wm_lp != 1); |
| 2572 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; |
| 2573 | } else |
| 2574 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2575 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2576 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2577 | /* LP0 register values */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2578 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2579 | enum pipe pipe = intel_crtc->pipe; |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2580 | const struct intel_wm_level *r = |
| 2581 | &intel_crtc->wm.active.wm[0]; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2582 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2583 | if (WARN_ON(!r->enable)) |
| 2584 | continue; |
| 2585 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2586 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2587 | |
| 2588 | results->wm_pipe[pipe] = |
| 2589 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | |
| 2590 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | |
| 2591 | r->cur_val; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2592 | } |
| 2593 | } |
| 2594 | |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2595 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
| 2596 | * case both are at the same level. Prefer r1 in case they're the same. */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2597 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2598 | struct intel_pipe_wm *r1, |
| 2599 | struct intel_pipe_wm *r2) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2600 | { |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2601 | int level, max_level = ilk_wm_max_level(dev); |
| 2602 | int level1 = 0, level2 = 0; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2603 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2604 | for (level = 1; level <= max_level; level++) { |
| 2605 | if (r1->wm[level].enable) |
| 2606 | level1 = level; |
| 2607 | if (r2->wm[level].enable) |
| 2608 | level2 = level; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2609 | } |
| 2610 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2611 | if (level1 == level2) { |
| 2612 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2613 | return r2; |
| 2614 | else |
| 2615 | return r1; |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2616 | } else if (level1 > level2) { |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2617 | return r1; |
| 2618 | } else { |
| 2619 | return r2; |
| 2620 | } |
| 2621 | } |
| 2622 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2623 | /* dirty bits used to track which watermarks need changes */ |
| 2624 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) |
| 2625 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) |
| 2626 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) |
| 2627 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) |
| 2628 | #define WM_DIRTY_FBC (1 << 24) |
| 2629 | #define WM_DIRTY_DDB (1 << 25) |
| 2630 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2631 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2632 | const struct ilk_wm_values *old, |
| 2633 | const struct ilk_wm_values *new) |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2634 | { |
| 2635 | unsigned int dirty = 0; |
| 2636 | enum pipe pipe; |
| 2637 | int wm_lp; |
| 2638 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2639 | for_each_pipe(dev_priv, pipe) { |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2640 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
| 2641 | dirty |= WM_DIRTY_LINETIME(pipe); |
| 2642 | /* Must disable LP1+ watermarks too */ |
| 2643 | dirty |= WM_DIRTY_LP_ALL; |
| 2644 | } |
| 2645 | |
| 2646 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { |
| 2647 | dirty |= WM_DIRTY_PIPE(pipe); |
| 2648 | /* Must disable LP1+ watermarks too */ |
| 2649 | dirty |= WM_DIRTY_LP_ALL; |
| 2650 | } |
| 2651 | } |
| 2652 | |
| 2653 | if (old->enable_fbc_wm != new->enable_fbc_wm) { |
| 2654 | dirty |= WM_DIRTY_FBC; |
| 2655 | /* Must disable LP1+ watermarks too */ |
| 2656 | dirty |= WM_DIRTY_LP_ALL; |
| 2657 | } |
| 2658 | |
| 2659 | if (old->partitioning != new->partitioning) { |
| 2660 | dirty |= WM_DIRTY_DDB; |
| 2661 | /* Must disable LP1+ watermarks too */ |
| 2662 | dirty |= WM_DIRTY_LP_ALL; |
| 2663 | } |
| 2664 | |
| 2665 | /* LP1+ watermarks already deemed dirty, no need to continue */ |
| 2666 | if (dirty & WM_DIRTY_LP_ALL) |
| 2667 | return dirty; |
| 2668 | |
| 2669 | /* Find the lowest numbered LP1+ watermark in need of an update... */ |
| 2670 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
| 2671 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || |
| 2672 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) |
| 2673 | break; |
| 2674 | } |
| 2675 | |
| 2676 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ |
| 2677 | for (; wm_lp <= 3; wm_lp++) |
| 2678 | dirty |= WM_DIRTY_LP(wm_lp); |
| 2679 | |
| 2680 | return dirty; |
| 2681 | } |
| 2682 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2683 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
| 2684 | unsigned int dirty) |
| 2685 | { |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2686 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2687 | bool changed = false; |
| 2688 | |
| 2689 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
| 2690 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; |
| 2691 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); |
| 2692 | changed = true; |
| 2693 | } |
| 2694 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { |
| 2695 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; |
| 2696 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); |
| 2697 | changed = true; |
| 2698 | } |
| 2699 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { |
| 2700 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; |
| 2701 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); |
| 2702 | changed = true; |
| 2703 | } |
| 2704 | |
| 2705 | /* |
| 2706 | * Don't touch WM1S_LP_EN here. |
| 2707 | * Doing so could cause underruns. |
| 2708 | */ |
| 2709 | |
| 2710 | return changed; |
| 2711 | } |
| 2712 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2713 | /* |
| 2714 | * The spec says we shouldn't write when we don't need, because every write |
| 2715 | * causes WMs to be re-evaluated, expending some power. |
| 2716 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2717 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
| 2718 | struct ilk_wm_values *results) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2719 | { |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2720 | struct drm_device *dev = dev_priv->dev; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2721 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2722 | unsigned int dirty; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2723 | uint32_t val; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2724 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2725 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2726 | if (!dirty) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2727 | return; |
| 2728 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2729 | _ilk_disable_lp_wm(dev_priv, dirty); |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2730 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2731 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2732 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2733 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2734 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2735 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2736 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
| 2737 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2738 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2739 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2740 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2741 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2742 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2743 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
| 2744 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2745 | if (dirty & WM_DIRTY_DDB) { |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2746 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2747 | val = I915_READ(WM_MISC); |
| 2748 | if (results->partitioning == INTEL_DDB_PART_1_2) |
| 2749 | val &= ~WM_MISC_DATA_PARTITION_5_6; |
| 2750 | else |
| 2751 | val |= WM_MISC_DATA_PARTITION_5_6; |
| 2752 | I915_WRITE(WM_MISC, val); |
| 2753 | } else { |
| 2754 | val = I915_READ(DISP_ARB_CTL2); |
| 2755 | if (results->partitioning == INTEL_DDB_PART_1_2) |
| 2756 | val &= ~DISP_DATA_PARTITION_5_6; |
| 2757 | else |
| 2758 | val |= DISP_DATA_PARTITION_5_6; |
| 2759 | I915_WRITE(DISP_ARB_CTL2, val); |
| 2760 | } |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2761 | } |
| 2762 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2763 | if (dirty & WM_DIRTY_FBC) { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2764 | val = I915_READ(DISP_ARB_CTL); |
| 2765 | if (results->enable_fbc_wm) |
| 2766 | val &= ~DISP_FBC_WM_DIS; |
| 2767 | else |
| 2768 | val |= DISP_FBC_WM_DIS; |
| 2769 | I915_WRITE(DISP_ARB_CTL, val); |
| 2770 | } |
| 2771 | |
Imre Deak | 954911e | 2013-12-17 14:46:34 +0200 | [diff] [blame] | 2772 | if (dirty & WM_DIRTY_LP(1) && |
| 2773 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) |
| 2774 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); |
| 2775 | |
| 2776 | if (INTEL_INFO(dev)->gen >= 7) { |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2777 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
| 2778 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); |
| 2779 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) |
| 2780 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); |
| 2781 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2782 | |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2783 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2784 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2785 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2786 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2787 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2788 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2789 | |
| 2790 | dev_priv->wm.hw = *results; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2791 | } |
| 2792 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2793 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
| 2794 | { |
| 2795 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2796 | |
| 2797 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); |
| 2798 | } |
| 2799 | |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2800 | /* |
| 2801 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the |
| 2802 | * different active planes. |
| 2803 | */ |
| 2804 | |
| 2805 | #define SKL_DDB_SIZE 896 /* in blocks */ |
Damien Lespiau | 43d735a | 2015-03-17 11:39:34 +0200 | [diff] [blame] | 2806 | #define BXT_DDB_SIZE 512 |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2807 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2808 | /* |
| 2809 | * Return the index of a plane in the SKL DDB and wm result arrays. Primary |
| 2810 | * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and |
| 2811 | * other universal planes are in indices 1..n. Note that this may leave unused |
| 2812 | * indices between the top "sprite" plane and the cursor. |
| 2813 | */ |
| 2814 | static int |
| 2815 | skl_wm_plane_id(const struct intel_plane *plane) |
| 2816 | { |
| 2817 | switch (plane->base.type) { |
| 2818 | case DRM_PLANE_TYPE_PRIMARY: |
| 2819 | return 0; |
| 2820 | case DRM_PLANE_TYPE_CURSOR: |
| 2821 | return PLANE_CURSOR; |
| 2822 | case DRM_PLANE_TYPE_OVERLAY: |
| 2823 | return plane->plane + 1; |
| 2824 | default: |
| 2825 | MISSING_CASE(plane->base.type); |
| 2826 | return plane->plane; |
| 2827 | } |
| 2828 | } |
| 2829 | |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2830 | static void |
| 2831 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2832 | const struct intel_crtc_state *cstate, |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2833 | const struct intel_wm_config *config, |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2834 | struct skl_ddb_entry *alloc /* out */) |
| 2835 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2836 | struct drm_crtc *for_crtc = cstate->base.crtc; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2837 | struct drm_crtc *crtc; |
| 2838 | unsigned int pipe_size, ddb_size; |
| 2839 | int nth_active_pipe; |
| 2840 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2841 | if (!cstate->base.active) { |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2842 | alloc->start = 0; |
| 2843 | alloc->end = 0; |
| 2844 | return; |
| 2845 | } |
| 2846 | |
Damien Lespiau | 43d735a | 2015-03-17 11:39:34 +0200 | [diff] [blame] | 2847 | if (IS_BROXTON(dev)) |
| 2848 | ddb_size = BXT_DDB_SIZE; |
| 2849 | else |
| 2850 | ddb_size = SKL_DDB_SIZE; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2851 | |
| 2852 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ |
| 2853 | |
| 2854 | nth_active_pipe = 0; |
| 2855 | for_each_crtc(dev, crtc) { |
Matt Roper | 3ef0028 | 2015-03-09 10:19:24 -0700 | [diff] [blame] | 2856 | if (!to_intel_crtc(crtc)->active) |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2857 | continue; |
| 2858 | |
| 2859 | if (crtc == for_crtc) |
| 2860 | break; |
| 2861 | |
| 2862 | nth_active_pipe++; |
| 2863 | } |
| 2864 | |
| 2865 | pipe_size = ddb_size / config->num_pipes_active; |
| 2866 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 2867 | alloc->end = alloc->start + pipe_size; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2868 | } |
| 2869 | |
| 2870 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) |
| 2871 | { |
| 2872 | if (config->num_pipes_active == 1) |
| 2873 | return 32; |
| 2874 | |
| 2875 | return 8; |
| 2876 | } |
| 2877 | |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2878 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
| 2879 | { |
| 2880 | entry->start = reg & 0x3ff; |
| 2881 | entry->end = (reg >> 16) & 0x3ff; |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 2882 | if (entry->end) |
| 2883 | entry->end += 1; |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2884 | } |
| 2885 | |
Damien Lespiau | 08db665 | 2014-11-04 17:06:52 +0000 | [diff] [blame] | 2886 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
| 2887 | struct skl_ddb_allocation *ddb /* out */) |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2888 | { |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2889 | enum pipe pipe; |
| 2890 | int plane; |
| 2891 | u32 val; |
| 2892 | |
| 2893 | for_each_pipe(dev_priv, pipe) { |
Damien Lespiau | dd74078 | 2015-02-28 14:54:08 +0000 | [diff] [blame] | 2894 | for_each_plane(dev_priv, pipe, plane) { |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2895 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); |
| 2896 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], |
| 2897 | val); |
| 2898 | } |
| 2899 | |
| 2900 | val = I915_READ(CUR_BUF_CFG(pipe)); |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 2901 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], |
| 2902 | val); |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 2903 | } |
| 2904 | } |
| 2905 | |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2906 | static unsigned int |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2907 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
| 2908 | const struct drm_plane_state *pstate, |
| 2909 | int y) |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2910 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2911 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
| 2912 | struct drm_framebuffer *fb = pstate->fb; |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 2913 | |
| 2914 | /* for planar format */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2915 | if (fb->pixel_format == DRM_FORMAT_NV12) { |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 2916 | if (y) /* y-plane data rate */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2917 | return intel_crtc->config->pipe_src_w * |
| 2918 | intel_crtc->config->pipe_src_h * |
| 2919 | drm_format_plane_cpp(fb->pixel_format, 0); |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 2920 | else /* uv-plane data rate */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2921 | return (intel_crtc->config->pipe_src_w/2) * |
| 2922 | (intel_crtc->config->pipe_src_h/2) * |
| 2923 | drm_format_plane_cpp(fb->pixel_format, 1); |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 2924 | } |
| 2925 | |
| 2926 | /* for packed formats */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2927 | return intel_crtc->config->pipe_src_w * |
| 2928 | intel_crtc->config->pipe_src_h * |
| 2929 | drm_format_plane_cpp(fb->pixel_format, 0); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2930 | } |
| 2931 | |
| 2932 | /* |
| 2933 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching |
| 2934 | * a 8192x4096@32bpp framebuffer: |
| 2935 | * 3 * 4096 * 8192 * 4 < 2^32 |
| 2936 | */ |
| 2937 | static unsigned int |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2938 | skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate) |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2939 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2940 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
| 2941 | struct drm_device *dev = intel_crtc->base.dev; |
| 2942 | const struct intel_plane *intel_plane; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2943 | unsigned int total_data_rate = 0; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2944 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2945 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
| 2946 | const struct drm_plane_state *pstate = intel_plane->base.state; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2947 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2948 | if (pstate->fb == NULL) |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2949 | continue; |
| 2950 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2951 | /* packed/uv */ |
| 2952 | total_data_rate += skl_plane_relative_data_rate(cstate, |
| 2953 | pstate, |
| 2954 | 0); |
| 2955 | |
| 2956 | if (pstate->fb->pixel_format == DRM_FORMAT_NV12) |
| 2957 | /* y-plane */ |
| 2958 | total_data_rate += skl_plane_relative_data_rate(cstate, |
| 2959 | pstate, |
| 2960 | 1); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2961 | } |
| 2962 | |
| 2963 | return total_data_rate; |
| 2964 | } |
| 2965 | |
| 2966 | static void |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2967 | skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 2968 | const struct intel_wm_config *config, |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2969 | struct skl_ddb_allocation *ddb /* out */) |
| 2970 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2971 | struct drm_crtc *crtc = cstate->base.crtc; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2972 | struct drm_device *dev = crtc->dev; |
| 2973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2974 | struct intel_plane *intel_plane; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2975 | enum pipe pipe = intel_crtc->pipe; |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 2976 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2977 | uint16_t alloc_size, start, cursor_blocks; |
Damien Lespiau | 8095815 | 2015-02-09 13:35:10 +0000 | [diff] [blame] | 2978 | uint16_t minimum[I915_MAX_PLANES]; |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 2979 | uint16_t y_minimum[I915_MAX_PLANES]; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2980 | unsigned int total_data_rate; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2981 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2982 | skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc); |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 2983 | alloc_size = skl_ddb_entry_size(alloc); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2984 | if (alloc_size == 0) { |
| 2985 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 2986 | memset(&ddb->plane[pipe][PLANE_CURSOR], 0, |
| 2987 | sizeof(ddb->plane[pipe][PLANE_CURSOR])); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2988 | return; |
| 2989 | } |
| 2990 | |
| 2991 | cursor_blocks = skl_cursor_allocation(config); |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 2992 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; |
| 2993 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2994 | |
| 2995 | alloc_size -= cursor_blocks; |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 2996 | alloc->end -= cursor_blocks; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 2997 | |
Damien Lespiau | 8095815 | 2015-02-09 13:35:10 +0000 | [diff] [blame] | 2998 | /* 1. Allocate the mininum required blocks for each active plane */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 2999 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
| 3000 | struct drm_plane *plane = &intel_plane->base; |
| 3001 | struct drm_framebuffer *fb = plane->fb; |
| 3002 | int id = skl_wm_plane_id(intel_plane); |
Damien Lespiau | 8095815 | 2015-02-09 13:35:10 +0000 | [diff] [blame] | 3003 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3004 | if (fb == NULL) |
| 3005 | continue; |
| 3006 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
Damien Lespiau | 8095815 | 2015-02-09 13:35:10 +0000 | [diff] [blame] | 3007 | continue; |
| 3008 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3009 | minimum[id] = 8; |
| 3010 | alloc_size -= minimum[id]; |
| 3011 | y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0; |
| 3012 | alloc_size -= y_minimum[id]; |
Damien Lespiau | 8095815 | 2015-02-09 13:35:10 +0000 | [diff] [blame] | 3013 | } |
| 3014 | |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3015 | /* |
Damien Lespiau | 8095815 | 2015-02-09 13:35:10 +0000 | [diff] [blame] | 3016 | * 2. Distribute the remaining space in proportion to the amount of |
| 3017 | * data each plane needs to fetch from memory. |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3018 | * |
| 3019 | * FIXME: we may not allocate every single block here. |
| 3020 | */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3021 | total_data_rate = skl_get_total_relative_data_rate(cstate); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3022 | |
Damien Lespiau | 34bb56a | 2014-11-04 17:07:01 +0000 | [diff] [blame] | 3023 | start = alloc->start; |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3024 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
| 3025 | struct drm_plane *plane = &intel_plane->base; |
| 3026 | struct drm_plane_state *pstate = intel_plane->base.state; |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3027 | unsigned int data_rate, y_data_rate; |
| 3028 | uint16_t plane_blocks, y_plane_blocks = 0; |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3029 | int id = skl_wm_plane_id(intel_plane); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3030 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3031 | if (pstate->fb == NULL) |
| 3032 | continue; |
| 3033 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3034 | continue; |
| 3035 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3036 | data_rate = skl_plane_relative_data_rate(cstate, pstate, 0); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3037 | |
| 3038 | /* |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3039 | * allocation for (packed formats) or (uv-plane part of planar format): |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3040 | * promote the expression to 64 bits to avoid overflowing, the |
| 3041 | * result is < available as data_rate / total_data_rate < 1 |
| 3042 | */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3043 | plane_blocks = minimum[id]; |
Damien Lespiau | 8095815 | 2015-02-09 13:35:10 +0000 | [diff] [blame] | 3044 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, |
| 3045 | total_data_rate); |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3046 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3047 | ddb->plane[pipe][id].start = start; |
| 3048 | ddb->plane[pipe][id].end = start + plane_blocks; |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3049 | |
| 3050 | start += plane_blocks; |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3051 | |
| 3052 | /* |
| 3053 | * allocation for y_plane part of planar format: |
| 3054 | */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3055 | if (pstate->fb->pixel_format == DRM_FORMAT_NV12) { |
| 3056 | y_data_rate = skl_plane_relative_data_rate(cstate, |
| 3057 | pstate, |
| 3058 | 1); |
| 3059 | y_plane_blocks = y_minimum[id]; |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3060 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, |
| 3061 | total_data_rate); |
| 3062 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3063 | ddb->y_plane[pipe][id].start = start; |
| 3064 | ddb->y_plane[pipe][id].end = start + y_plane_blocks; |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3065 | |
| 3066 | start += y_plane_blocks; |
| 3067 | } |
| 3068 | |
Damien Lespiau | b9cec07 | 2014-11-04 17:06:43 +0000 | [diff] [blame] | 3069 | } |
| 3070 | |
| 3071 | } |
| 3072 | |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 3073 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3074 | { |
| 3075 | /* TODO: Take into account the scalers once we support them */ |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 3076 | return config->base.adjusted_mode.crtc_clock; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3077 | } |
| 3078 | |
| 3079 | /* |
| 3080 | * The max latency should be 257 (max the punit can code is 255 and we add 2us |
| 3081 | * for the read latency) and bytes_per_pixel should always be <= 8, so that |
| 3082 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
| 3083 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. |
| 3084 | */ |
| 3085 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
| 3086 | uint32_t latency) |
| 3087 | { |
| 3088 | uint32_t wm_intermediate_val, ret; |
| 3089 | |
| 3090 | if (latency == 0) |
| 3091 | return UINT_MAX; |
| 3092 | |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3093 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3094 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
| 3095 | |
| 3096 | return ret; |
| 3097 | } |
| 3098 | |
| 3099 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
| 3100 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
Tvrtko Ursulin | 0fda656 | 2015-02-27 15:12:35 +0000 | [diff] [blame] | 3101 | uint64_t tiling, uint32_t latency) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3102 | { |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3103 | uint32_t ret; |
| 3104 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
| 3105 | uint32_t wm_intermediate_val; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3106 | |
| 3107 | if (latency == 0) |
| 3108 | return UINT_MAX; |
| 3109 | |
| 3110 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; |
Tvrtko Ursulin | 0fda656 | 2015-02-27 15:12:35 +0000 | [diff] [blame] | 3111 | |
| 3112 | if (tiling == I915_FORMAT_MOD_Y_TILED || |
| 3113 | tiling == I915_FORMAT_MOD_Yf_TILED) { |
| 3114 | plane_bytes_per_line *= 4; |
| 3115 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
| 3116 | plane_blocks_per_line /= 4; |
| 3117 | } else { |
| 3118 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
| 3119 | } |
| 3120 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3121 | wm_intermediate_val = latency * pixel_rate; |
| 3122 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3123 | plane_blocks_per_line; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3124 | |
| 3125 | return ret; |
| 3126 | } |
| 3127 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3128 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
| 3129 | const struct intel_crtc *intel_crtc) |
| 3130 | { |
| 3131 | struct drm_device *dev = intel_crtc->base.dev; |
| 3132 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3133 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; |
| 3134 | enum pipe pipe = intel_crtc->pipe; |
| 3135 | |
| 3136 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], |
| 3137 | sizeof(new_ddb->plane[pipe]))) |
| 3138 | return true; |
| 3139 | |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3140 | if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], |
| 3141 | sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3142 | return true; |
| 3143 | |
| 3144 | return false; |
| 3145 | } |
| 3146 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3147 | static void skl_compute_wm_global_parameters(struct drm_device *dev, |
| 3148 | struct intel_wm_config *config) |
| 3149 | { |
| 3150 | struct drm_crtc *crtc; |
| 3151 | |
| 3152 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
| 3153 | config->num_pipes_active += to_intel_crtc(crtc)->active; |
| 3154 | } |
| 3155 | |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3156 | static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3157 | struct intel_crtc_state *cstate, |
| 3158 | struct intel_plane *intel_plane, |
Damien Lespiau | afb024a | 2014-11-04 17:06:59 +0000 | [diff] [blame] | 3159 | uint16_t ddb_allocation, |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3160 | int level, |
Damien Lespiau | afb024a | 2014-11-04 17:06:59 +0000 | [diff] [blame] | 3161 | uint16_t *out_blocks, /* out */ |
| 3162 | uint8_t *out_lines /* out */) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3163 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3164 | struct drm_plane *plane = &intel_plane->base; |
| 3165 | struct drm_framebuffer *fb = plane->state->fb; |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3166 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
| 3167 | uint32_t method1, method2; |
| 3168 | uint32_t plane_bytes_per_line, plane_blocks_per_line; |
| 3169 | uint32_t res_blocks, res_lines; |
| 3170 | uint32_t selected_result; |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3171 | uint8_t bytes_per_pixel; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3172 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3173 | if (latency == 0 || !cstate->base.active || !fb) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3174 | return false; |
| 3175 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3176 | bytes_per_pixel = (fb->pixel_format == DRM_FORMAT_NV12) ? |
| 3177 | drm_format_plane_cpp(DRM_FORMAT_NV12, 0) : |
| 3178 | drm_format_plane_cpp(DRM_FORMAT_NV12, 1); |
| 3179 | method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate), |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3180 | bytes_per_pixel, |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3181 | latency); |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3182 | method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate), |
| 3183 | cstate->base.adjusted_mode.crtc_htotal, |
| 3184 | cstate->pipe_src_w, |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3185 | bytes_per_pixel, |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3186 | fb->modifier[0], |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3187 | latency); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3188 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3189 | plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel; |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3190 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3191 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3192 | if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || |
| 3193 | fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { |
Tvrtko Ursulin | 1fc0a8f | 2015-03-23 11:10:38 +0000 | [diff] [blame] | 3194 | uint32_t min_scanlines = 4; |
| 3195 | uint32_t y_tile_minimum; |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3196 | if (intel_rotation_90_or_270(plane->state->rotation)) { |
| 3197 | int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ? |
| 3198 | drm_format_plane_cpp(fb->pixel_format, 1) : |
| 3199 | drm_format_plane_cpp(fb->pixel_format, 0); |
| 3200 | |
| 3201 | switch (bpp) { |
Tvrtko Ursulin | 1fc0a8f | 2015-03-23 11:10:38 +0000 | [diff] [blame] | 3202 | case 1: |
| 3203 | min_scanlines = 16; |
| 3204 | break; |
| 3205 | case 2: |
| 3206 | min_scanlines = 8; |
| 3207 | break; |
| 3208 | case 8: |
| 3209 | WARN(1, "Unsupported pixel depth for rotation"); |
kbuild test robot | 2f0b579 | 2015-03-26 22:30:21 +0800 | [diff] [blame] | 3210 | } |
Tvrtko Ursulin | 1fc0a8f | 2015-03-23 11:10:38 +0000 | [diff] [blame] | 3211 | } |
| 3212 | y_tile_minimum = plane_blocks_per_line * min_scanlines; |
Tvrtko Ursulin | 0fda656 | 2015-02-27 15:12:35 +0000 | [diff] [blame] | 3213 | selected_result = max(method2, y_tile_minimum); |
| 3214 | } else { |
| 3215 | if ((ddb_allocation / plane_blocks_per_line) >= 1) |
| 3216 | selected_result = min(method1, method2); |
| 3217 | else |
| 3218 | selected_result = method1; |
| 3219 | } |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3220 | |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3221 | res_blocks = selected_result + 1; |
| 3222 | res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); |
Damien Lespiau | e6d6617 | 2014-11-04 17:06:55 +0000 | [diff] [blame] | 3223 | |
Tvrtko Ursulin | 0fda656 | 2015-02-27 15:12:35 +0000 | [diff] [blame] | 3224 | if (level >= 1 && level <= 7) { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3225 | if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || |
| 3226 | fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) |
Tvrtko Ursulin | 0fda656 | 2015-02-27 15:12:35 +0000 | [diff] [blame] | 3227 | res_lines += 4; |
| 3228 | else |
| 3229 | res_blocks++; |
| 3230 | } |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3231 | |
| 3232 | if (res_blocks >= ddb_allocation || res_lines > 31) |
Damien Lespiau | e6d6617 | 2014-11-04 17:06:55 +0000 | [diff] [blame] | 3233 | return false; |
| 3234 | |
| 3235 | *out_blocks = res_blocks; |
| 3236 | *out_lines = res_lines; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3237 | |
| 3238 | return true; |
| 3239 | } |
| 3240 | |
| 3241 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, |
| 3242 | struct skl_ddb_allocation *ddb, |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3243 | struct intel_crtc_state *cstate, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3244 | int level, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3245 | struct skl_wm_level *result) |
| 3246 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3247 | struct drm_device *dev = dev_priv->dev; |
| 3248 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
| 3249 | struct intel_plane *intel_plane; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3250 | uint16_t ddb_blocks; |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3251 | enum pipe pipe = intel_crtc->pipe; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3252 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3253 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
| 3254 | int i = skl_wm_plane_id(intel_plane); |
| 3255 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3256 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); |
| 3257 | |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3258 | result->plane_en[i] = skl_compute_plane_wm(dev_priv, |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3259 | cstate, |
| 3260 | intel_plane, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3261 | ddb_blocks, |
Tvrtko Ursulin | d4c2aa6 | 2015-02-27 11:15:22 +0000 | [diff] [blame] | 3262 | level, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3263 | &result->plane_res_b[i], |
| 3264 | &result->plane_res_l[i]); |
| 3265 | } |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3266 | } |
| 3267 | |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 3268 | static uint32_t |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3269 | skl_compute_linetime_wm(struct intel_crtc_state *cstate) |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 3270 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3271 | if (!cstate->base.active) |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 3272 | return 0; |
| 3273 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3274 | if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0)) |
Mika Kuoppala | 661abfc | 2015-07-16 19:36:51 +0300 | [diff] [blame] | 3275 | return 0; |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 3276 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3277 | return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, |
| 3278 | skl_pipe_pixel_rate(cstate)); |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 3279 | } |
| 3280 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3281 | static void skl_compute_transition_wm(struct intel_crtc_state *cstate, |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3282 | struct skl_wm_level *trans_wm /* out */) |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 3283 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3284 | struct drm_crtc *crtc = cstate->base.crtc; |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3286 | struct intel_plane *intel_plane; |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3287 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3288 | if (!cstate->base.active) |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 3289 | return; |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3290 | |
| 3291 | /* Until we know more, just disable transition WMs */ |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3292 | for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) { |
| 3293 | int i = skl_wm_plane_id(intel_plane); |
| 3294 | |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3295 | trans_wm->plane_en[i] = false; |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3296 | } |
Damien Lespiau | 407b50f | 2014-11-04 17:06:57 +0000 | [diff] [blame] | 3297 | } |
| 3298 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3299 | static void skl_compute_pipe_wm(struct intel_crtc_state *cstate, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3300 | struct skl_ddb_allocation *ddb, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3301 | struct skl_pipe_wm *pipe_wm) |
| 3302 | { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3303 | struct drm_device *dev = cstate->base.crtc->dev; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3304 | const struct drm_i915_private *dev_priv = dev->dev_private; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3305 | int level, max_level = ilk_wm_max_level(dev); |
| 3306 | |
| 3307 | for (level = 0; level <= max_level; level++) { |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3308 | skl_compute_wm_level(dev_priv, ddb, cstate, |
| 3309 | level, &pipe_wm->wm[level]); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3310 | } |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3311 | pipe_wm->linetime = skl_compute_linetime_wm(cstate); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3312 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3313 | skl_compute_transition_wm(cstate, &pipe_wm->trans_wm); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3314 | } |
| 3315 | |
| 3316 | static void skl_compute_wm_results(struct drm_device *dev, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3317 | struct skl_pipe_wm *p_wm, |
| 3318 | struct skl_wm_values *r, |
| 3319 | struct intel_crtc *intel_crtc) |
| 3320 | { |
| 3321 | int level, max_level = ilk_wm_max_level(dev); |
| 3322 | enum pipe pipe = intel_crtc->pipe; |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3323 | uint32_t temp; |
| 3324 | int i; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3325 | |
| 3326 | for (level = 0; level <= max_level; level++) { |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3327 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
| 3328 | temp = 0; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3329 | |
| 3330 | temp |= p_wm->wm[level].plane_res_l[i] << |
| 3331 | PLANE_WM_LINES_SHIFT; |
| 3332 | temp |= p_wm->wm[level].plane_res_b[i]; |
| 3333 | if (p_wm->wm[level].plane_en[i]) |
| 3334 | temp |= PLANE_WM_EN; |
| 3335 | |
| 3336 | r->plane[pipe][i][level] = temp; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3337 | } |
| 3338 | |
| 3339 | temp = 0; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3340 | |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3341 | temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
| 3342 | temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3343 | |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3344 | if (p_wm->wm[level].plane_en[PLANE_CURSOR]) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3345 | temp |= PLANE_WM_EN; |
| 3346 | |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3347 | r->plane[pipe][PLANE_CURSOR][level] = temp; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3348 | |
| 3349 | } |
| 3350 | |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3351 | /* transition WMs */ |
| 3352 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
| 3353 | temp = 0; |
| 3354 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; |
| 3355 | temp |= p_wm->trans_wm.plane_res_b[i]; |
| 3356 | if (p_wm->trans_wm.plane_en[i]) |
| 3357 | temp |= PLANE_WM_EN; |
| 3358 | |
| 3359 | r->plane_trans[pipe][i] = temp; |
| 3360 | } |
| 3361 | |
| 3362 | temp = 0; |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3363 | temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
| 3364 | temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; |
| 3365 | if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3366 | temp |= PLANE_WM_EN; |
| 3367 | |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3368 | r->plane_trans[pipe][PLANE_CURSOR] = temp; |
Damien Lespiau | 9414f56 | 2014-11-04 17:06:58 +0000 | [diff] [blame] | 3369 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3370 | r->wm_linetime[pipe] = p_wm->linetime; |
| 3371 | } |
| 3372 | |
Damien Lespiau | 16160e3 | 2014-11-04 17:06:53 +0000 | [diff] [blame] | 3373 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, |
| 3374 | const struct skl_ddb_entry *entry) |
| 3375 | { |
| 3376 | if (entry->end) |
| 3377 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); |
| 3378 | else |
| 3379 | I915_WRITE(reg, 0); |
| 3380 | } |
| 3381 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3382 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
| 3383 | const struct skl_wm_values *new) |
| 3384 | { |
| 3385 | struct drm_device *dev = dev_priv->dev; |
| 3386 | struct intel_crtc *crtc; |
| 3387 | |
| 3388 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
| 3389 | int i, level, max_level = ilk_wm_max_level(dev); |
| 3390 | enum pipe pipe = crtc->pipe; |
| 3391 | |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 3392 | if (!new->dirty[pipe]) |
| 3393 | continue; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3394 | |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 3395 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
| 3396 | |
| 3397 | for (level = 0; level <= max_level; level++) { |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3398 | for (i = 0; i < intel_num_planes(crtc); i++) |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 3399 | I915_WRITE(PLANE_WM(pipe, i, level), |
| 3400 | new->plane[pipe][i][level]); |
| 3401 | I915_WRITE(CUR_WM(pipe, level), |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3402 | new->plane[pipe][PLANE_CURSOR][level]); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3403 | } |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 3404 | for (i = 0; i < intel_num_planes(crtc); i++) |
| 3405 | I915_WRITE(PLANE_WM_TRANS(pipe, i), |
| 3406 | new->plane_trans[pipe][i]); |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3407 | I915_WRITE(CUR_WM_TRANS(pipe), |
| 3408 | new->plane_trans[pipe][PLANE_CURSOR]); |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 3409 | |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3410 | for (i = 0; i < intel_num_planes(crtc); i++) { |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 3411 | skl_ddb_entry_write(dev_priv, |
| 3412 | PLANE_BUF_CFG(pipe, i), |
| 3413 | &new->ddb.plane[pipe][i]); |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3414 | skl_ddb_entry_write(dev_priv, |
| 3415 | PLANE_NV12_BUF_CFG(pipe, i), |
| 3416 | &new->ddb.y_plane[pipe][i]); |
| 3417 | } |
Damien Lespiau | 5d374d9 | 2014-11-04 17:07:00 +0000 | [diff] [blame] | 3418 | |
| 3419 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3420 | &new->ddb.plane[pipe][PLANE_CURSOR]); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3421 | } |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3422 | } |
| 3423 | |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3424 | /* |
| 3425 | * When setting up a new DDB allocation arrangement, we need to correctly |
| 3426 | * sequence the times at which the new allocations for the pipes are taken into |
| 3427 | * account or we'll have pipes fetching from space previously allocated to |
| 3428 | * another pipe. |
| 3429 | * |
| 3430 | * Roughly the sequence looks like: |
| 3431 | * 1. re-allocate the pipe(s) with the allocation being reduced and not |
| 3432 | * overlapping with a previous light-up pipe (another way to put it is: |
| 3433 | * pipes with their new allocation strickly included into their old ones). |
| 3434 | * 2. re-allocate the other pipes that get their allocation reduced |
| 3435 | * 3. allocate the pipes having their allocation increased |
| 3436 | * |
| 3437 | * Steps 1. and 2. are here to take care of the following case: |
| 3438 | * - Initially DDB looks like this: |
| 3439 | * | B | C | |
| 3440 | * - enable pipe A. |
| 3441 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C |
| 3442 | * allocation |
| 3443 | * | A | B | C | |
| 3444 | * |
| 3445 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). |
| 3446 | */ |
| 3447 | |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 3448 | static void |
| 3449 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3450 | { |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3451 | int plane; |
| 3452 | |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 3453 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
| 3454 | |
Damien Lespiau | dd74078 | 2015-02-28 14:54:08 +0000 | [diff] [blame] | 3455 | for_each_plane(dev_priv, pipe, plane) { |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3456 | I915_WRITE(PLANE_SURF(pipe, plane), |
| 3457 | I915_READ(PLANE_SURF(pipe, plane))); |
| 3458 | } |
| 3459 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
| 3460 | } |
| 3461 | |
| 3462 | static bool |
| 3463 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, |
| 3464 | const struct skl_ddb_allocation *new, |
| 3465 | enum pipe pipe) |
| 3466 | { |
| 3467 | uint16_t old_size, new_size; |
| 3468 | |
| 3469 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); |
| 3470 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); |
| 3471 | |
| 3472 | return old_size != new_size && |
| 3473 | new->pipe[pipe].start >= old->pipe[pipe].start && |
| 3474 | new->pipe[pipe].end <= old->pipe[pipe].end; |
| 3475 | } |
| 3476 | |
| 3477 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, |
| 3478 | struct skl_wm_values *new_values) |
| 3479 | { |
| 3480 | struct drm_device *dev = dev_priv->dev; |
| 3481 | struct skl_ddb_allocation *cur_ddb, *new_ddb; |
Ville Syrjälä | c929cb4 | 2015-04-02 18:28:07 +0300 | [diff] [blame] | 3482 | bool reallocated[I915_MAX_PIPES] = {}; |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3483 | struct intel_crtc *crtc; |
| 3484 | enum pipe pipe; |
| 3485 | |
| 3486 | new_ddb = &new_values->ddb; |
| 3487 | cur_ddb = &dev_priv->wm.skl_hw.ddb; |
| 3488 | |
| 3489 | /* |
| 3490 | * First pass: flush the pipes with the new allocation contained into |
| 3491 | * the old space. |
| 3492 | * |
| 3493 | * We'll wait for the vblank on those pipes to ensure we can safely |
| 3494 | * re-allocate the freed space without this pipe fetching from it. |
| 3495 | */ |
| 3496 | for_each_intel_crtc(dev, crtc) { |
| 3497 | if (!crtc->active) |
| 3498 | continue; |
| 3499 | |
| 3500 | pipe = crtc->pipe; |
| 3501 | |
| 3502 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) |
| 3503 | continue; |
| 3504 | |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 3505 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3506 | intel_wait_for_vblank(dev, pipe); |
| 3507 | |
| 3508 | reallocated[pipe] = true; |
| 3509 | } |
| 3510 | |
| 3511 | |
| 3512 | /* |
| 3513 | * Second pass: flush the pipes that are having their allocation |
| 3514 | * reduced, but overlapping with a previous allocation. |
| 3515 | * |
| 3516 | * Here as well we need to wait for the vblank to make sure the freed |
| 3517 | * space is not used anymore. |
| 3518 | */ |
| 3519 | for_each_intel_crtc(dev, crtc) { |
| 3520 | if (!crtc->active) |
| 3521 | continue; |
| 3522 | |
| 3523 | pipe = crtc->pipe; |
| 3524 | |
| 3525 | if (reallocated[pipe]) |
| 3526 | continue; |
| 3527 | |
| 3528 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < |
| 3529 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 3530 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3531 | intel_wait_for_vblank(dev, pipe); |
Sonika Jindal | d9d8e6b | 2014-12-11 17:58:15 +0530 | [diff] [blame] | 3532 | reallocated[pipe] = true; |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3533 | } |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3534 | } |
| 3535 | |
| 3536 | /* |
| 3537 | * Third pass: flush the pipes that got more space allocated. |
| 3538 | * |
| 3539 | * We don't need to actively wait for the update here, next vblank |
| 3540 | * will just get more DDB space with the correct WM values. |
| 3541 | */ |
| 3542 | for_each_intel_crtc(dev, crtc) { |
| 3543 | if (!crtc->active) |
| 3544 | continue; |
| 3545 | |
| 3546 | pipe = crtc->pipe; |
| 3547 | |
| 3548 | /* |
| 3549 | * At this point, only the pipes more space than before are |
| 3550 | * left to re-allocate. |
| 3551 | */ |
| 3552 | if (reallocated[pipe]) |
| 3553 | continue; |
| 3554 | |
Damien Lespiau | d21b795 | 2014-11-04 17:07:03 +0000 | [diff] [blame] | 3555 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3556 | } |
| 3557 | } |
| 3558 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3559 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3560 | struct intel_wm_config *config, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3561 | struct skl_ddb_allocation *ddb, /* out */ |
| 3562 | struct skl_pipe_wm *pipe_wm /* out */) |
| 3563 | { |
| 3564 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3565 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3566 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3567 | skl_allocate_pipe_ddb(cstate, config, ddb); |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3568 | skl_compute_pipe_wm(cstate, ddb, pipe_wm); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3569 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3570 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3571 | return false; |
| 3572 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3573 | intel_crtc->wm.skl_active = *pipe_wm; |
Chandra Konduru | 2cd601c | 2015-04-27 15:47:37 -0700 | [diff] [blame] | 3574 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3575 | return true; |
| 3576 | } |
| 3577 | |
| 3578 | static void skl_update_other_pipe_wm(struct drm_device *dev, |
| 3579 | struct drm_crtc *crtc, |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3580 | struct intel_wm_config *config, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3581 | struct skl_wm_values *r) |
| 3582 | { |
| 3583 | struct intel_crtc *intel_crtc; |
| 3584 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); |
| 3585 | |
| 3586 | /* |
| 3587 | * If the WM update hasn't changed the allocation for this_crtc (the |
| 3588 | * crtc we are currently computing the new WM values for), other |
| 3589 | * enabled crtcs will keep the same allocation and we don't need to |
| 3590 | * recompute anything for them. |
| 3591 | */ |
| 3592 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) |
| 3593 | return; |
| 3594 | |
| 3595 | /* |
| 3596 | * Otherwise, because of this_crtc being freshly enabled/disabled, the |
| 3597 | * other active pipes need new DDB allocation and WM values. |
| 3598 | */ |
| 3599 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
| 3600 | base.head) { |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3601 | struct skl_pipe_wm pipe_wm = {}; |
| 3602 | bool wm_changed; |
| 3603 | |
| 3604 | if (this_crtc->pipe == intel_crtc->pipe) |
| 3605 | continue; |
| 3606 | |
| 3607 | if (!intel_crtc->active) |
| 3608 | continue; |
| 3609 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3610 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, config, |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3611 | &r->ddb, &pipe_wm); |
| 3612 | |
| 3613 | /* |
| 3614 | * If we end up re-computing the other pipe WM values, it's |
| 3615 | * because it was really needed, so we expect the WM values to |
| 3616 | * be different. |
| 3617 | */ |
| 3618 | WARN_ON(!wm_changed); |
| 3619 | |
Matt Roper | 3a05f5e | 2015-09-24 15:53:11 -0700 | [diff] [blame] | 3620 | skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3621 | r->dirty[intel_crtc->pipe] = true; |
| 3622 | } |
| 3623 | } |
| 3624 | |
Bob Paauwe | adda50b | 2015-07-21 10:42:53 -0700 | [diff] [blame] | 3625 | static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) |
| 3626 | { |
| 3627 | watermarks->wm_linetime[pipe] = 0; |
| 3628 | memset(watermarks->plane[pipe], 0, |
| 3629 | sizeof(uint32_t) * 8 * I915_MAX_PLANES); |
Bob Paauwe | adda50b | 2015-07-21 10:42:53 -0700 | [diff] [blame] | 3630 | memset(watermarks->plane_trans[pipe], |
| 3631 | 0, sizeof(uint32_t) * I915_MAX_PLANES); |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3632 | watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; |
Bob Paauwe | adda50b | 2015-07-21 10:42:53 -0700 | [diff] [blame] | 3633 | |
| 3634 | /* Clear ddb entries for pipe */ |
| 3635 | memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); |
| 3636 | memset(&watermarks->ddb.plane[pipe], 0, |
| 3637 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); |
| 3638 | memset(&watermarks->ddb.y_plane[pipe], 0, |
| 3639 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3640 | memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, |
| 3641 | sizeof(struct skl_ddb_entry)); |
Bob Paauwe | adda50b | 2015-07-21 10:42:53 -0700 | [diff] [blame] | 3642 | |
| 3643 | } |
| 3644 | |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3645 | static void skl_update_wm(struct drm_crtc *crtc) |
| 3646 | { |
| 3647 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3648 | struct drm_device *dev = crtc->dev; |
| 3649 | struct drm_i915_private *dev_priv = dev->dev_private; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3650 | struct skl_wm_values *results = &dev_priv->wm.skl_results; |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3651 | struct skl_pipe_wm pipe_wm = {}; |
| 3652 | struct intel_wm_config config = {}; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3653 | |
Bob Paauwe | adda50b | 2015-07-21 10:42:53 -0700 | [diff] [blame] | 3654 | |
| 3655 | /* Clear all dirty flags */ |
| 3656 | memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); |
| 3657 | |
| 3658 | skl_clear_wm(results, intel_crtc->pipe); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3659 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3660 | skl_compute_wm_global_parameters(dev, &config); |
| 3661 | |
| 3662 | if (!skl_update_pipe_wm(crtc, &config, &results->ddb, &pipe_wm)) |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3663 | return; |
| 3664 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3665 | skl_compute_wm_results(dev, &pipe_wm, results, intel_crtc); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3666 | results->dirty[intel_crtc->pipe] = true; |
| 3667 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3668 | skl_update_other_pipe_wm(dev, crtc, &config, results); |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3669 | skl_write_wm_values(dev_priv, results); |
Damien Lespiau | 0e8fb7b | 2014-11-04 17:07:02 +0000 | [diff] [blame] | 3670 | skl_flush_wm_values(dev_priv, results); |
Damien Lespiau | 53b0deb | 2014-11-04 17:06:48 +0000 | [diff] [blame] | 3671 | |
| 3672 | /* store the new configuration */ |
| 3673 | dev_priv->wm.skl_hw = *results; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 3674 | } |
| 3675 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3676 | static void ilk_update_wm(struct drm_crtc *crtc) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 3677 | { |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3679 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
| 3680 | struct drm_device *dev = crtc->dev; |
| 3681 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3682 | struct ilk_wm_maximums max; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3683 | struct ilk_wm_values results = {}; |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 3684 | enum intel_ddb_partitioning partitioning; |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3685 | struct intel_pipe_wm pipe_wm = {}; |
| 3686 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
| 3687 | struct intel_wm_config config = {}; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 3688 | |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3689 | WARN_ON(cstate->base.active != intel_crtc->active); |
| 3690 | |
| 3691 | /* |
| 3692 | * IVB workaround: must disable low power watermarks for at least |
| 3693 | * one frame before enabling scaling. LP watermarks can be re-enabled |
| 3694 | * when scaling is disabled. |
| 3695 | * |
| 3696 | * WaCxSRDisabledForSpriteScaling:ivb |
| 3697 | */ |
| 3698 | if (cstate->disable_lp_wm) { |
| 3699 | ilk_disable_lp_wm(dev); |
| 3700 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3701 | } |
| 3702 | |
| 3703 | intel_compute_pipe_wm(cstate, &pipe_wm); |
| 3704 | |
| 3705 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) |
| 3706 | return; |
| 3707 | |
| 3708 | intel_crtc->wm.active = pipe_wm; |
| 3709 | |
| 3710 | ilk_compute_wm_config(dev, &config); |
| 3711 | |
| 3712 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
| 3713 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 3714 | |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 3715 | /* 5/6 split only in single pipe config on IVB+ */ |
Ville Syrjälä | ec98c8d | 2013-10-11 15:26:26 +0300 | [diff] [blame] | 3716 | if (INTEL_INFO(dev)->gen >= 7 && |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3717 | config.num_pipes_active == 1 && config.sprites_enabled) { |
| 3718 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
| 3719 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 3720 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3721 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 3722 | } else { |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 3723 | best_lp_wm = &lp_wm_1_2; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 3724 | } |
| 3725 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 3726 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 3727 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 3728 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3729 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 3730 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3731 | ilk_write_wm_values(dev_priv, &results); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 3732 | } |
| 3733 | |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3734 | static void skl_pipe_wm_active_state(uint32_t val, |
| 3735 | struct skl_pipe_wm *active, |
| 3736 | bool is_transwm, |
| 3737 | bool is_cursor, |
| 3738 | int i, |
| 3739 | int level) |
| 3740 | { |
| 3741 | bool is_enabled = (val & PLANE_WM_EN) != 0; |
| 3742 | |
| 3743 | if (!is_transwm) { |
| 3744 | if (!is_cursor) { |
| 3745 | active->wm[level].plane_en[i] = is_enabled; |
| 3746 | active->wm[level].plane_res_b[i] = |
| 3747 | val & PLANE_WM_BLOCKS_MASK; |
| 3748 | active->wm[level].plane_res_l[i] = |
| 3749 | (val >> PLANE_WM_LINES_SHIFT) & |
| 3750 | PLANE_WM_LINES_MASK; |
| 3751 | } else { |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3752 | active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; |
| 3753 | active->wm[level].plane_res_b[PLANE_CURSOR] = |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3754 | val & PLANE_WM_BLOCKS_MASK; |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3755 | active->wm[level].plane_res_l[PLANE_CURSOR] = |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3756 | (val >> PLANE_WM_LINES_SHIFT) & |
| 3757 | PLANE_WM_LINES_MASK; |
| 3758 | } |
| 3759 | } else { |
| 3760 | if (!is_cursor) { |
| 3761 | active->trans_wm.plane_en[i] = is_enabled; |
| 3762 | active->trans_wm.plane_res_b[i] = |
| 3763 | val & PLANE_WM_BLOCKS_MASK; |
| 3764 | active->trans_wm.plane_res_l[i] = |
| 3765 | (val >> PLANE_WM_LINES_SHIFT) & |
| 3766 | PLANE_WM_LINES_MASK; |
| 3767 | } else { |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3768 | active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; |
| 3769 | active->trans_wm.plane_res_b[PLANE_CURSOR] = |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3770 | val & PLANE_WM_BLOCKS_MASK; |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3771 | active->trans_wm.plane_res_l[PLANE_CURSOR] = |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3772 | (val >> PLANE_WM_LINES_SHIFT) & |
| 3773 | PLANE_WM_LINES_MASK; |
| 3774 | } |
| 3775 | } |
| 3776 | } |
| 3777 | |
| 3778 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
| 3779 | { |
| 3780 | struct drm_device *dev = crtc->dev; |
| 3781 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3782 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; |
| 3783 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3784 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3785 | enum pipe pipe = intel_crtc->pipe; |
| 3786 | int level, i, max_level; |
| 3787 | uint32_t temp; |
| 3788 | |
| 3789 | max_level = ilk_wm_max_level(dev); |
| 3790 | |
| 3791 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
| 3792 | |
| 3793 | for (level = 0; level <= max_level; level++) { |
| 3794 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
| 3795 | hw->plane[pipe][i][level] = |
| 3796 | I915_READ(PLANE_WM(pipe, i, level)); |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3797 | hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3798 | } |
| 3799 | |
| 3800 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
| 3801 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3802 | hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3803 | |
Matt Roper | 3ef0028 | 2015-03-09 10:19:24 -0700 | [diff] [blame] | 3804 | if (!intel_crtc->active) |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3805 | return; |
| 3806 | |
| 3807 | hw->dirty[pipe] = true; |
| 3808 | |
| 3809 | active->linetime = hw->wm_linetime[pipe]; |
| 3810 | |
| 3811 | for (level = 0; level <= max_level; level++) { |
| 3812 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
| 3813 | temp = hw->plane[pipe][i][level]; |
| 3814 | skl_pipe_wm_active_state(temp, active, false, |
| 3815 | false, i, level); |
| 3816 | } |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3817 | temp = hw->plane[pipe][PLANE_CURSOR][level]; |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3818 | skl_pipe_wm_active_state(temp, active, false, true, i, level); |
| 3819 | } |
| 3820 | |
| 3821 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
| 3822 | temp = hw->plane_trans[pipe][i]; |
| 3823 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); |
| 3824 | } |
| 3825 | |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3826 | temp = hw->plane_trans[pipe][PLANE_CURSOR]; |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3827 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); |
| 3828 | } |
| 3829 | |
| 3830 | void skl_wm_get_hw_state(struct drm_device *dev) |
| 3831 | { |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 3832 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3833 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3834 | struct drm_crtc *crtc; |
| 3835 | |
Damien Lespiau | a269c58 | 2014-11-04 17:06:49 +0000 | [diff] [blame] | 3836 | skl_ddb_get_hw_state(dev_priv, ddb); |
Pradeep Bhat | 3078999 | 2014-11-04 17:06:45 +0000 | [diff] [blame] | 3837 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
| 3838 | skl_pipe_wm_get_hw_state(crtc); |
| 3839 | } |
| 3840 | |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3841 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
| 3842 | { |
| 3843 | struct drm_device *dev = crtc->dev; |
| 3844 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 3845 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3846 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | 261a27d | 2015-10-08 15:28:25 -0700 | [diff] [blame] | 3847 | struct intel_pipe_wm *active = &intel_crtc->wm.active; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3848 | enum pipe pipe = intel_crtc->pipe; |
| 3849 | static const unsigned int wm0_pipe_reg[] = { |
| 3850 | [PIPE_A] = WM0_PIPEA_ILK, |
| 3851 | [PIPE_B] = WM0_PIPEB_ILK, |
| 3852 | [PIPE_C] = WM0_PIPEC_IVB, |
| 3853 | }; |
| 3854 | |
| 3855 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 3856 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ce0e071 | 2013-12-05 15:51:36 +0200 | [diff] [blame] | 3857 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3858 | |
Matt Roper | 3ef0028 | 2015-03-09 10:19:24 -0700 | [diff] [blame] | 3859 | active->pipe_enabled = intel_crtc->active; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 3860 | |
| 3861 | if (active->pipe_enabled) { |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 3862 | u32 tmp = hw->wm_pipe[pipe]; |
| 3863 | |
| 3864 | /* |
| 3865 | * For active pipes LP0 watermark is marked as |
| 3866 | * enabled, and LP1+ watermaks as disabled since |
| 3867 | * we can't really reverse compute them in case |
| 3868 | * multiple pipes are active. |
| 3869 | */ |
| 3870 | active->wm[0].enable = true; |
| 3871 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; |
| 3872 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; |
| 3873 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; |
| 3874 | active->linetime = hw->wm_linetime[pipe]; |
| 3875 | } else { |
| 3876 | int level, max_level = ilk_wm_max_level(dev); |
| 3877 | |
| 3878 | /* |
| 3879 | * For inactive pipes, all watermark levels |
| 3880 | * should be marked as enabled but zeroed, |
| 3881 | * which is what we'd compute them to. |
| 3882 | */ |
| 3883 | for (level = 0; level <= max_level; level++) |
| 3884 | active->wm[level].enable = true; |
| 3885 | } |
| 3886 | } |
| 3887 | |
Ville Syrjälä | 6eb1a68 | 2015-06-24 22:00:03 +0300 | [diff] [blame] | 3888 | #define _FW_WM(value, plane) \ |
| 3889 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) |
| 3890 | #define _FW_WM_VLV(value, plane) \ |
| 3891 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) |
| 3892 | |
| 3893 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, |
| 3894 | struct vlv_wm_values *wm) |
| 3895 | { |
| 3896 | enum pipe pipe; |
| 3897 | uint32_t tmp; |
| 3898 | |
| 3899 | for_each_pipe(dev_priv, pipe) { |
| 3900 | tmp = I915_READ(VLV_DDL(pipe)); |
| 3901 | |
| 3902 | wm->ddl[pipe].primary = |
| 3903 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
| 3904 | wm->ddl[pipe].cursor = |
| 3905 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
| 3906 | wm->ddl[pipe].sprite[0] = |
| 3907 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
| 3908 | wm->ddl[pipe].sprite[1] = |
| 3909 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
| 3910 | } |
| 3911 | |
| 3912 | tmp = I915_READ(DSPFW1); |
| 3913 | wm->sr.plane = _FW_WM(tmp, SR); |
| 3914 | wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); |
| 3915 | wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); |
| 3916 | wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); |
| 3917 | |
| 3918 | tmp = I915_READ(DSPFW2); |
| 3919 | wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); |
| 3920 | wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); |
| 3921 | wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); |
| 3922 | |
| 3923 | tmp = I915_READ(DSPFW3); |
| 3924 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); |
| 3925 | |
| 3926 | if (IS_CHERRYVIEW(dev_priv)) { |
| 3927 | tmp = I915_READ(DSPFW7_CHV); |
| 3928 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); |
| 3929 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); |
| 3930 | |
| 3931 | tmp = I915_READ(DSPFW8_CHV); |
| 3932 | wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); |
| 3933 | wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); |
| 3934 | |
| 3935 | tmp = I915_READ(DSPFW9_CHV); |
| 3936 | wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); |
| 3937 | wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); |
| 3938 | |
| 3939 | tmp = I915_READ(DSPHOWM); |
| 3940 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; |
| 3941 | wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; |
| 3942 | wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; |
| 3943 | wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; |
| 3944 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
| 3945 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; |
| 3946 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; |
| 3947 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; |
| 3948 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; |
| 3949 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; |
| 3950 | } else { |
| 3951 | tmp = I915_READ(DSPFW7); |
| 3952 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); |
| 3953 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); |
| 3954 | |
| 3955 | tmp = I915_READ(DSPHOWM); |
| 3956 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; |
| 3957 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
| 3958 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; |
| 3959 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; |
| 3960 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; |
| 3961 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; |
| 3962 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; |
| 3963 | } |
| 3964 | } |
| 3965 | |
| 3966 | #undef _FW_WM |
| 3967 | #undef _FW_WM_VLV |
| 3968 | |
| 3969 | void vlv_wm_get_hw_state(struct drm_device *dev) |
| 3970 | { |
| 3971 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3972 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; |
| 3973 | struct intel_plane *plane; |
| 3974 | enum pipe pipe; |
| 3975 | u32 val; |
| 3976 | |
| 3977 | vlv_read_wm_values(dev_priv, wm); |
| 3978 | |
| 3979 | for_each_intel_plane(dev, plane) { |
| 3980 | switch (plane->base.type) { |
| 3981 | int sprite; |
| 3982 | case DRM_PLANE_TYPE_CURSOR: |
| 3983 | plane->wm.fifo_size = 63; |
| 3984 | break; |
| 3985 | case DRM_PLANE_TYPE_PRIMARY: |
| 3986 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); |
| 3987 | break; |
| 3988 | case DRM_PLANE_TYPE_OVERLAY: |
| 3989 | sprite = plane->plane; |
| 3990 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); |
| 3991 | break; |
| 3992 | } |
| 3993 | } |
| 3994 | |
| 3995 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
| 3996 | wm->level = VLV_WM_LEVEL_PM2; |
| 3997 | |
| 3998 | if (IS_CHERRYVIEW(dev_priv)) { |
| 3999 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4000 | |
| 4001 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 4002 | if (val & DSP_MAXFIFO_PM5_ENABLE) |
| 4003 | wm->level = VLV_WM_LEVEL_PM5; |
| 4004 | |
Ville Syrjälä | 58590c1 | 2015-09-08 21:05:12 +0300 | [diff] [blame] | 4005 | /* |
| 4006 | * If DDR DVFS is disabled in the BIOS, Punit |
| 4007 | * will never ack the request. So if that happens |
| 4008 | * assume we don't have to enable/disable DDR DVFS |
| 4009 | * dynamically. To test that just set the REQ_ACK |
| 4010 | * bit to poke the Punit, but don't change the |
| 4011 | * HIGH/LOW bits so that we don't actually change |
| 4012 | * the current state. |
| 4013 | */ |
Ville Syrjälä | 6eb1a68 | 2015-06-24 22:00:03 +0300 | [diff] [blame] | 4014 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
Ville Syrjälä | 58590c1 | 2015-09-08 21:05:12 +0300 | [diff] [blame] | 4015 | val |= FORCE_DDR_FREQ_REQ_ACK; |
| 4016 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); |
| 4017 | |
| 4018 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & |
| 4019 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { |
| 4020 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " |
| 4021 | "assuming DDR DVFS is disabled\n"); |
| 4022 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; |
| 4023 | } else { |
| 4024 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
| 4025 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) |
| 4026 | wm->level = VLV_WM_LEVEL_DDR_DVFS; |
| 4027 | } |
Ville Syrjälä | 6eb1a68 | 2015-06-24 22:00:03 +0300 | [diff] [blame] | 4028 | |
| 4029 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4030 | } |
| 4031 | |
| 4032 | for_each_pipe(dev_priv, pipe) |
| 4033 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", |
| 4034 | pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, |
| 4035 | wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); |
| 4036 | |
| 4037 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", |
| 4038 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); |
| 4039 | } |
| 4040 | |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 4041 | void ilk_wm_get_hw_state(struct drm_device *dev) |
| 4042 | { |
| 4043 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 4044 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 4045 | struct drm_crtc *crtc; |
| 4046 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 4047 | for_each_crtc(dev, crtc) |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 4048 | ilk_pipe_wm_get_hw_state(crtc); |
| 4049 | |
| 4050 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); |
| 4051 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); |
| 4052 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); |
| 4053 | |
| 4054 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); |
Ville Syrjälä | cfa7698 | 2014-03-07 18:32:08 +0200 | [diff] [blame] | 4055 | if (INTEL_INFO(dev)->gen >= 7) { |
| 4056 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
| 4057 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); |
| 4058 | } |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 4059 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 4060 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 4061 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
| 4062 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
| 4063 | else if (IS_IVYBRIDGE(dev)) |
| 4064 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
| 4065 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 4066 | |
| 4067 | hw->enable_fbc_wm = |
| 4068 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); |
| 4069 | } |
| 4070 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 4071 | /** |
| 4072 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 4073 | * |
| 4074 | * Calculate watermark values for the various WM regs based on current mode |
| 4075 | * and plane configuration. |
| 4076 | * |
| 4077 | * There are several cases to deal with here: |
| 4078 | * - normal (i.e. non-self-refresh) |
| 4079 | * - self-refresh (SR) mode |
| 4080 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 4081 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 4082 | * lines), so need to account for TLB latency |
| 4083 | * |
| 4084 | * The normal calculation is: |
| 4085 | * watermark = dotclock * bytes per pixel * latency |
| 4086 | * where latency is platform & configuration dependent (we assume pessimal |
| 4087 | * values here). |
| 4088 | * |
| 4089 | * The SR calculation is: |
| 4090 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 4091 | * bytes per pixel |
| 4092 | * where |
| 4093 | * line time = htotal / dotclock |
| 4094 | * surface width = hdisplay for normal plane and 64 for cursor |
| 4095 | * and latency is assumed to be high, as above. |
| 4096 | * |
| 4097 | * The final value programmed to the register should always be rounded up, |
| 4098 | * and include an extra 2 entries to account for clock crossings. |
| 4099 | * |
| 4100 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 4101 | * to set the non-SR watermarks to 8. |
| 4102 | */ |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 4103 | void intel_update_watermarks(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 4104 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 4105 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 4106 | |
| 4107 | if (dev_priv->display.update_wm) |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 4108 | dev_priv->display.update_wm(crtc); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 4109 | } |
| 4110 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4111 | /** |
| 4112 | * Lock protecting IPS related data structures |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4113 | */ |
| 4114 | DEFINE_SPINLOCK(mchdev_lock); |
| 4115 | |
| 4116 | /* Global for IPS driver to get at the current i915 device. Protected by |
| 4117 | * mchdev_lock. */ |
| 4118 | static struct drm_i915_private *i915_mch_dev; |
| 4119 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4120 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 4121 | { |
| 4122 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4123 | u16 rgvswctl; |
| 4124 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4125 | assert_spin_locked(&mchdev_lock); |
| 4126 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4127 | rgvswctl = I915_READ16(MEMSWCTL); |
| 4128 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 4129 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 4130 | return false; /* still busy with another command */ |
| 4131 | } |
| 4132 | |
| 4133 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 4134 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 4135 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 4136 | POSTING_READ16(MEMSWCTL); |
| 4137 | |
| 4138 | rgvswctl |= MEMCTL_CMD_STS; |
| 4139 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 4140 | |
| 4141 | return true; |
| 4142 | } |
| 4143 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4144 | static void ironlake_enable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4145 | { |
| 4146 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4147 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
| 4148 | u8 fmax, fmin, fstart, vstart; |
| 4149 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4150 | spin_lock_irq(&mchdev_lock); |
| 4151 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4152 | /* Enable temp reporting */ |
| 4153 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
| 4154 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
| 4155 | |
| 4156 | /* 100ms RC evaluation intervals */ |
| 4157 | I915_WRITE(RCUPEI, 100000); |
| 4158 | I915_WRITE(RCDNEI, 100000); |
| 4159 | |
| 4160 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 4161 | I915_WRITE(RCBMAXAVG, 90000); |
| 4162 | I915_WRITE(RCBMINAVG, 80000); |
| 4163 | |
| 4164 | I915_WRITE(MEMIHYST, 1); |
| 4165 | |
| 4166 | /* Set up min, max, and cur for interrupt handling */ |
| 4167 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 4168 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 4169 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 4170 | MEMMODE_FSTART_SHIFT; |
| 4171 | |
Ville Syrjälä | 616847e | 2015-09-18 20:03:19 +0300 | [diff] [blame] | 4172 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4173 | PXVFREQ_PX_SHIFT; |
| 4174 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4175 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
| 4176 | dev_priv->ips.fstart = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4177 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4178 | dev_priv->ips.max_delay = fstart; |
| 4179 | dev_priv->ips.min_delay = fmin; |
| 4180 | dev_priv->ips.cur_delay = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4181 | |
| 4182 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
| 4183 | fmax, fmin, fstart); |
| 4184 | |
| 4185 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 4186 | |
| 4187 | /* |
| 4188 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 4189 | */ |
| 4190 | |
| 4191 | I915_WRITE(VIDSTART, vstart); |
| 4192 | POSTING_READ(VIDSTART); |
| 4193 | |
| 4194 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 4195 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 4196 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4197 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4198 | DRM_ERROR("stuck trying to change perf mode\n"); |
Daniel Vetter | dd92d8d | 2015-07-20 10:58:21 +0200 | [diff] [blame] | 4199 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4200 | |
| 4201 | ironlake_set_drps(dev, fstart); |
| 4202 | |
Ville Syrjälä | 7d81c3e | 2015-09-18 20:03:20 +0300 | [diff] [blame] | 4203 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
| 4204 | I915_READ(DDREC) + I915_READ(CSIEC); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4205 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
Ville Syrjälä | 7d81c3e | 2015-09-18 20:03:20 +0300 | [diff] [blame] | 4206 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 4207 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4208 | |
| 4209 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4210 | } |
| 4211 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4212 | static void ironlake_disable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4213 | { |
| 4214 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4215 | u16 rgvswctl; |
| 4216 | |
| 4217 | spin_lock_irq(&mchdev_lock); |
| 4218 | |
| 4219 | rgvswctl = I915_READ16(MEMSWCTL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4220 | |
| 4221 | /* Ack interrupts, disable EFC interrupt */ |
| 4222 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 4223 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 4224 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 4225 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 4226 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 4227 | |
| 4228 | /* Go back to the starting frequency */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4229 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
Daniel Vetter | dd92d8d | 2015-07-20 10:58:21 +0200 | [diff] [blame] | 4230 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4231 | rgvswctl |= MEMCTL_CMD_STS; |
| 4232 | I915_WRITE(MEMSWCTL, rgvswctl); |
Daniel Vetter | dd92d8d | 2015-07-20 10:58:21 +0200 | [diff] [blame] | 4233 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4234 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4235 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4236 | } |
| 4237 | |
Daniel Vetter | acbe947 | 2012-07-26 11:50:05 +0200 | [diff] [blame] | 4238 | /* There's a funny hw issue where the hw returns all 0 when reading from |
| 4239 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
| 4240 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
| 4241 | * all limits and the gpu stuck at whatever frequency it is at atm). |
| 4242 | */ |
Akash Goel | 74ef117 | 2015-03-06 11:07:19 +0530 | [diff] [blame] | 4243 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4244 | { |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 4245 | u32 limits; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4246 | |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 4247 | /* Only set the down limit when we've reached the lowest level to avoid |
| 4248 | * getting more interrupts, otherwise leave this clear. This prevents a |
| 4249 | * race in the hw when coming out of rc6: There's a tiny window where |
| 4250 | * the hw runs at the minimal clock before selecting the desired |
| 4251 | * frequency, if the down threshold expires in that window we will not |
| 4252 | * receive a down interrupt. */ |
Akash Goel | 74ef117 | 2015-03-06 11:07:19 +0530 | [diff] [blame] | 4253 | if (IS_GEN9(dev_priv->dev)) { |
| 4254 | limits = (dev_priv->rps.max_freq_softlimit) << 23; |
| 4255 | if (val <= dev_priv->rps.min_freq_softlimit) |
| 4256 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; |
| 4257 | } else { |
| 4258 | limits = dev_priv->rps.max_freq_softlimit << 24; |
| 4259 | if (val <= dev_priv->rps.min_freq_softlimit) |
| 4260 | limits |= dev_priv->rps.min_freq_softlimit << 16; |
| 4261 | } |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 4262 | |
| 4263 | return limits; |
| 4264 | } |
| 4265 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4266 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
| 4267 | { |
| 4268 | int new_power; |
Akash Goel | 8a58643 | 2015-03-06 11:07:18 +0530 | [diff] [blame] | 4269 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
| 4270 | u32 ei_up = 0, ei_down = 0; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4271 | |
| 4272 | new_power = dev_priv->rps.power; |
| 4273 | switch (dev_priv->rps.power) { |
| 4274 | case LOW_POWER: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4275 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4276 | new_power = BETWEEN; |
| 4277 | break; |
| 4278 | |
| 4279 | case BETWEEN: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4280 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4281 | new_power = LOW_POWER; |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4282 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4283 | new_power = HIGH_POWER; |
| 4284 | break; |
| 4285 | |
| 4286 | case HIGH_POWER: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4287 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4288 | new_power = BETWEEN; |
| 4289 | break; |
| 4290 | } |
| 4291 | /* Max/min bins are special */ |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4292 | if (val <= dev_priv->rps.min_freq_softlimit) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4293 | new_power = LOW_POWER; |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4294 | if (val >= dev_priv->rps.max_freq_softlimit) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4295 | new_power = HIGH_POWER; |
| 4296 | if (new_power == dev_priv->rps.power) |
| 4297 | return; |
| 4298 | |
| 4299 | /* Note the units here are not exactly 1us, but 1280ns. */ |
| 4300 | switch (new_power) { |
| 4301 | case LOW_POWER: |
| 4302 | /* Upclock if more than 95% busy over 16ms */ |
Akash Goel | 8a58643 | 2015-03-06 11:07:18 +0530 | [diff] [blame] | 4303 | ei_up = 16000; |
| 4304 | threshold_up = 95; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4305 | |
| 4306 | /* Downclock if less than 85% busy over 32ms */ |
Akash Goel | 8a58643 | 2015-03-06 11:07:18 +0530 | [diff] [blame] | 4307 | ei_down = 32000; |
| 4308 | threshold_down = 85; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4309 | break; |
| 4310 | |
| 4311 | case BETWEEN: |
| 4312 | /* Upclock if more than 90% busy over 13ms */ |
Akash Goel | 8a58643 | 2015-03-06 11:07:18 +0530 | [diff] [blame] | 4313 | ei_up = 13000; |
| 4314 | threshold_up = 90; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4315 | |
| 4316 | /* Downclock if less than 75% busy over 32ms */ |
Akash Goel | 8a58643 | 2015-03-06 11:07:18 +0530 | [diff] [blame] | 4317 | ei_down = 32000; |
| 4318 | threshold_down = 75; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4319 | break; |
| 4320 | |
| 4321 | case HIGH_POWER: |
| 4322 | /* Upclock if more than 85% busy over 10ms */ |
Akash Goel | 8a58643 | 2015-03-06 11:07:18 +0530 | [diff] [blame] | 4323 | ei_up = 10000; |
| 4324 | threshold_up = 85; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4325 | |
| 4326 | /* Downclock if less than 60% busy over 32ms */ |
Akash Goel | 8a58643 | 2015-03-06 11:07:18 +0530 | [diff] [blame] | 4327 | ei_down = 32000; |
| 4328 | threshold_down = 60; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4329 | break; |
| 4330 | } |
| 4331 | |
Akash Goel | 8a58643 | 2015-03-06 11:07:18 +0530 | [diff] [blame] | 4332 | I915_WRITE(GEN6_RP_UP_EI, |
| 4333 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); |
| 4334 | I915_WRITE(GEN6_RP_UP_THRESHOLD, |
| 4335 | GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); |
| 4336 | |
| 4337 | I915_WRITE(GEN6_RP_DOWN_EI, |
| 4338 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); |
| 4339 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, |
| 4340 | GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); |
| 4341 | |
| 4342 | I915_WRITE(GEN6_RP_CONTROL, |
| 4343 | GEN6_RP_MEDIA_TURBO | |
| 4344 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 4345 | GEN6_RP_MEDIA_IS_GFX | |
| 4346 | GEN6_RP_ENABLE | |
| 4347 | GEN6_RP_UP_BUSY_AVG | |
| 4348 | GEN6_RP_DOWN_IDLE_AVG); |
| 4349 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4350 | dev_priv->rps.power = new_power; |
Chris Wilson | 8fb5519 | 2015-04-07 16:20:28 +0100 | [diff] [blame] | 4351 | dev_priv->rps.up_threshold = threshold_up; |
| 4352 | dev_priv->rps.down_threshold = threshold_down; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4353 | dev_priv->rps.last_adj = 0; |
| 4354 | } |
| 4355 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 4356 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
| 4357 | { |
| 4358 | u32 mask = 0; |
| 4359 | |
| 4360 | if (val > dev_priv->rps.min_freq_softlimit) |
Chris Wilson | 6f4b12f8 | 2015-03-18 09:48:23 +0000 | [diff] [blame] | 4361 | mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 4362 | if (val < dev_priv->rps.max_freq_softlimit) |
Chris Wilson | 6f4b12f8 | 2015-03-18 09:48:23 +0000 | [diff] [blame] | 4363 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 4364 | |
Chris Wilson | 7b3c29f | 2014-07-10 20:31:19 +0100 | [diff] [blame] | 4365 | mask &= dev_priv->pm_rps_events; |
| 4366 | |
Imre Deak | 59d02a1 | 2014-12-19 19:33:26 +0200 | [diff] [blame] | 4367 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 4368 | } |
| 4369 | |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 4370 | /* gen6_set_rps is called to update the frequency request, but should also be |
| 4371 | * called when the range (min_delay and max_delay) is modified so that we can |
| 4372 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 4373 | static void gen6_set_rps(struct drm_device *dev, u8 val) |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 4374 | { |
| 4375 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 4376 | |
Sagar Arun Kamble | 23eafea | 2015-08-23 17:52:48 +0530 | [diff] [blame] | 4377 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
| 4378 | if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
| 4379 | return; |
| 4380 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4381 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4382 | WARN_ON(val > dev_priv->rps.max_freq); |
| 4383 | WARN_ON(val < dev_priv->rps.min_freq); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4384 | |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 4385 | /* min/max delay may still have been modified so be sure to |
| 4386 | * write the limits value. |
| 4387 | */ |
| 4388 | if (val != dev_priv->rps.cur_freq) { |
| 4389 | gen6_set_rps_thresholds(dev_priv, val); |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 4390 | |
Akash Goel | 5704195 | 2015-03-06 11:07:17 +0530 | [diff] [blame] | 4391 | if (IS_GEN9(dev)) |
| 4392 | I915_WRITE(GEN6_RPNSWREQ, |
| 4393 | GEN9_FREQUENCY(val)); |
| 4394 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 4395 | I915_WRITE(GEN6_RPNSWREQ, |
| 4396 | HSW_FREQUENCY(val)); |
| 4397 | else |
| 4398 | I915_WRITE(GEN6_RPNSWREQ, |
| 4399 | GEN6_FREQUENCY(val) | |
| 4400 | GEN6_OFFSET(0) | |
| 4401 | GEN6_AGGRESSIVE_TURBO); |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 4402 | } |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 4403 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 4404 | /* Make sure we continue to get interrupts |
| 4405 | * until we hit the minimum or maximum frequencies. |
| 4406 | */ |
Akash Goel | 74ef117 | 2015-03-06 11:07:19 +0530 | [diff] [blame] | 4407 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 4408 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 4409 | |
Ben Widawsky | d5570a7 | 2012-09-07 19:43:41 -0700 | [diff] [blame] | 4410 | POSTING_READ(GEN6_RPNSWREQ); |
| 4411 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4412 | dev_priv->rps.cur_freq = val; |
Daniel Vetter | be2cde9 | 2012-08-30 13:26:48 +0200 | [diff] [blame] | 4413 | trace_intel_gpu_freq_change(val * 50); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4414 | } |
| 4415 | |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 4416 | static void valleyview_set_rps(struct drm_device *dev, u8 val) |
| 4417 | { |
| 4418 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4419 | |
| 4420 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4421 | WARN_ON(val > dev_priv->rps.max_freq); |
| 4422 | WARN_ON(val < dev_priv->rps.min_freq); |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 4423 | |
| 4424 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), |
| 4425 | "Odd GPU freq value\n")) |
| 4426 | val &= ~1; |
| 4427 | |
Deepak S | cd25dd5 | 2015-07-10 18:31:40 +0530 | [diff] [blame] | 4428 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
| 4429 | |
Chris Wilson | 8fb5519 | 2015-04-07 16:20:28 +0100 | [diff] [blame] | 4430 | if (val != dev_priv->rps.cur_freq) { |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 4431 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
Chris Wilson | 8fb5519 | 2015-04-07 16:20:28 +0100 | [diff] [blame] | 4432 | if (!IS_CHERRYVIEW(dev_priv)) |
| 4433 | gen6_set_rps_thresholds(dev_priv, val); |
| 4434 | } |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 4435 | |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 4436 | dev_priv->rps.cur_freq = val; |
| 4437 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
| 4438 | } |
| 4439 | |
Deepak S | a7f6e23 | 2015-05-09 18:04:44 +0530 | [diff] [blame] | 4440 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 4441 | * |
| 4442 | * * If Gfx is Idle, then |
Deepak S | a7f6e23 | 2015-05-09 18:04:44 +0530 | [diff] [blame] | 4443 | * 1. Forcewake Media well. |
| 4444 | * 2. Request idle freq. |
| 4445 | * 3. Release Forcewake of Media well. |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 4446 | */ |
| 4447 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) |
| 4448 | { |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4449 | u32 val = dev_priv->rps.idle_freq; |
Deepak S | 5549d25 | 2014-06-28 11:26:11 +0530 | [diff] [blame] | 4450 | |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4451 | if (dev_priv->rps.cur_freq <= val) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 4452 | return; |
| 4453 | |
Deepak S | a7f6e23 | 2015-05-09 18:04:44 +0530 | [diff] [blame] | 4454 | /* Wake up the media well, as that takes a lot less |
| 4455 | * power than the Render well. */ |
| 4456 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); |
| 4457 | valleyview_set_rps(dev_priv->dev, val); |
| 4458 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 4459 | } |
| 4460 | |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 4461 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
| 4462 | { |
| 4463 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4464 | if (dev_priv->rps.enabled) { |
| 4465 | if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) |
| 4466 | gen6_rps_reset_ei(dev_priv); |
| 4467 | I915_WRITE(GEN6_PMINTRMSK, |
| 4468 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); |
| 4469 | } |
| 4470 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4471 | } |
| 4472 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4473 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
| 4474 | { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 4475 | struct drm_device *dev = dev_priv->dev; |
| 4476 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4477 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 4478 | if (dev_priv->rps.enabled) { |
Ville Syrjälä | 21a11ff | 2015-01-27 16:36:15 +0200 | [diff] [blame] | 4479 | if (IS_VALLEYVIEW(dev)) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 4480 | vlv_set_rps_idle(dev_priv); |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4481 | else |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4482 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 4483 | dev_priv->rps.last_adj = 0; |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 4484 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 4485 | } |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 4486 | mutex_unlock(&dev_priv->rps.hw_lock); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 4487 | |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 4488 | spin_lock(&dev_priv->rps.client_lock); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 4489 | while (!list_empty(&dev_priv->rps.clients)) |
| 4490 | list_del_init(dev_priv->rps.clients.next); |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 4491 | spin_unlock(&dev_priv->rps.client_lock); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4492 | } |
| 4493 | |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 4494 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 4495 | struct intel_rps_client *rps, |
| 4496 | unsigned long submitted) |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4497 | { |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 4498 | /* This is intentionally racy! We peek at the state here, then |
| 4499 | * validate inside the RPS worker. |
| 4500 | */ |
| 4501 | if (!(dev_priv->mm.busy && |
| 4502 | dev_priv->rps.enabled && |
| 4503 | dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) |
| 4504 | return; |
Chris Wilson | 43cf3bf | 2015-03-18 09:48:22 +0000 | [diff] [blame] | 4505 | |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 4506 | /* Force a RPS boost (and don't count it against the client) if |
| 4507 | * the GPU is severely congested. |
| 4508 | */ |
Chris Wilson | d0bc54f | 2015-05-21 21:01:48 +0100 | [diff] [blame] | 4509 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 4510 | rps = NULL; |
| 4511 | |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 4512 | spin_lock(&dev_priv->rps.client_lock); |
| 4513 | if (rps == NULL || list_empty(&rps->link)) { |
| 4514 | spin_lock_irq(&dev_priv->irq_lock); |
| 4515 | if (dev_priv->rps.interrupts_enabled) { |
| 4516 | dev_priv->rps.client_boost = true; |
| 4517 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
| 4518 | } |
| 4519 | spin_unlock_irq(&dev_priv->irq_lock); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 4520 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 4521 | if (rps != NULL) { |
| 4522 | list_add(&rps->link, &dev_priv->rps.clients); |
| 4523 | rps->boosts++; |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 4524 | } else |
| 4525 | dev_priv->rps.boosts++; |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 4526 | } |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 4527 | spin_unlock(&dev_priv->rps.client_lock); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4528 | } |
| 4529 | |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 4530 | void intel_set_rps(struct drm_device *dev, u8 val) |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4531 | { |
Ville Syrjälä | ffe02b4 | 2015-02-02 19:09:50 +0200 | [diff] [blame] | 4532 | if (IS_VALLEYVIEW(dev)) |
| 4533 | valleyview_set_rps(dev, val); |
| 4534 | else |
| 4535 | gen6_set_rps(dev, val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4536 | } |
| 4537 | |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4538 | static void gen9_disable_rps(struct drm_device *dev) |
| 4539 | { |
| 4540 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4541 | |
| 4542 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Zhe Wang | 38c2352 | 2015-01-20 12:23:04 +0000 | [diff] [blame] | 4543 | I915_WRITE(GEN9_PG_ENABLE, 0); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4544 | } |
| 4545 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 4546 | static void gen6_disable_rps(struct drm_device *dev) |
| 4547 | { |
| 4548 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4549 | |
| 4550 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4551 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 4552 | } |
| 4553 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4554 | static void cherryview_disable_rps(struct drm_device *dev) |
| 4555 | { |
| 4556 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4557 | |
| 4558 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4559 | } |
| 4560 | |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 4561 | static void valleyview_disable_rps(struct drm_device *dev) |
| 4562 | { |
| 4563 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4564 | |
Deepak S | 98a2e5f | 2014-08-18 10:35:27 -0700 | [diff] [blame] | 4565 | /* we're doing forcewake before Disabling RC6, |
| 4566 | * This what the BIOS expects when going into suspend */ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4567 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Deepak S | 98a2e5f | 2014-08-18 10:35:27 -0700 | [diff] [blame] | 4568 | |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 4569 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 4570 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4571 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 4572 | } |
| 4573 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 4574 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
| 4575 | { |
Imre Deak | 91ca689 | 2014-04-14 20:24:25 +0300 | [diff] [blame] | 4576 | if (IS_VALLEYVIEW(dev)) { |
| 4577 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
| 4578 | mode = GEN6_RC_CTL_RC6_ENABLE; |
| 4579 | else |
| 4580 | mode = 0; |
| 4581 | } |
Rodrigo Vivi | 58abf1d | 2014-10-07 07:06:50 -0700 | [diff] [blame] | 4582 | if (HAS_RC6p(dev)) |
| 4583 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", |
| 4584 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
| 4585 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
| 4586 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
| 4587 | |
| 4588 | else |
| 4589 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", |
| 4590 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 4591 | } |
| 4592 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 4593 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4594 | { |
Daniel Vetter | e7d66d8 | 2015-06-15 23:23:54 +0200 | [diff] [blame] | 4595 | /* No RC6 before Ironlake and code is gone for ilk. */ |
| 4596 | if (INTEL_INFO(dev)->gen < 6) |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 4597 | return 0; |
| 4598 | |
Daniel Vetter | 456470e | 2012-08-08 23:35:40 +0200 | [diff] [blame] | 4599 | /* Respect the kernel parameter if it is set */ |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 4600 | if (enable_rc6 >= 0) { |
| 4601 | int mask; |
| 4602 | |
Rodrigo Vivi | 58abf1d | 2014-10-07 07:06:50 -0700 | [diff] [blame] | 4603 | if (HAS_RC6p(dev)) |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 4604 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
| 4605 | INTEL_RC6pp_ENABLE; |
| 4606 | else |
| 4607 | mask = INTEL_RC6_ENABLE; |
| 4608 | |
| 4609 | if ((enable_rc6 & mask) != enable_rc6) |
Daniel Vetter | 8dfd1f0 | 2014-08-04 11:15:56 +0200 | [diff] [blame] | 4610 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
| 4611 | enable_rc6 & mask, enable_rc6, mask); |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 4612 | |
| 4613 | return enable_rc6 & mask; |
| 4614 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4615 | |
Ben Widawsky | 8bade1a | 2014-01-28 20:25:39 -0800 | [diff] [blame] | 4616 | if (IS_IVYBRIDGE(dev)) |
Ben Widawsky | cca84a1 | 2014-01-28 20:25:38 -0800 | [diff] [blame] | 4617 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
Ben Widawsky | 8bade1a | 2014-01-28 20:25:39 -0800 | [diff] [blame] | 4618 | |
| 4619 | return INTEL_RC6_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4620 | } |
| 4621 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 4622 | int intel_enable_rc6(const struct drm_device *dev) |
| 4623 | { |
| 4624 | return i915.enable_rc6; |
| 4625 | } |
| 4626 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4627 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 4628 | { |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4629 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4630 | uint32_t rp_state_cap; |
| 4631 | u32 ddcc_status = 0; |
| 4632 | int ret; |
| 4633 | |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 4634 | /* All of these values are in units of 50MHz */ |
| 4635 | dev_priv->rps.cur_freq = 0; |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4636 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
Bob Paauwe | 3504056 | 2015-06-25 14:54:07 -0700 | [diff] [blame] | 4637 | if (IS_BROXTON(dev)) { |
| 4638 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
| 4639 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; |
| 4640 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
| 4641 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; |
| 4642 | } else { |
| 4643 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
| 4644 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
| 4645 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
| 4646 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; |
| 4647 | } |
| 4648 | |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 4649 | /* hw_max = RP0 until we check for overclocking */ |
| 4650 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
| 4651 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4652 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
Akash Goel | c5e0688 | 2015-06-29 14:50:19 +0530 | [diff] [blame] | 4653 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4654 | ret = sandybridge_pcode_read(dev_priv, |
| 4655 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, |
| 4656 | &ddcc_status); |
| 4657 | if (0 == ret) |
| 4658 | dev_priv->rps.efficient_freq = |
Tom O'Rourke | 46efa4a | 2015-02-10 23:06:46 -0800 | [diff] [blame] | 4659 | clamp_t(u8, |
| 4660 | ((ddcc_status >> 8) & 0xff), |
| 4661 | dev_priv->rps.min_freq, |
| 4662 | dev_priv->rps.max_freq); |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4663 | } |
| 4664 | |
Akash Goel | c5e0688 | 2015-06-29 14:50:19 +0530 | [diff] [blame] | 4665 | if (IS_SKYLAKE(dev)) { |
| 4666 | /* Store the frequency values in 16.66 MHZ units, which is |
| 4667 | the natural hardware unit for SKL */ |
| 4668 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; |
| 4669 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; |
| 4670 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; |
| 4671 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; |
| 4672 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; |
| 4673 | } |
| 4674 | |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4675 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
| 4676 | |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 4677 | /* Preserve min/max settings in case of re-init */ |
| 4678 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 4679 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 4680 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4681 | if (dev_priv->rps.min_freq_softlimit == 0) { |
| 4682 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 4683 | dev_priv->rps.min_freq_softlimit = |
Ville Syrjälä | 813b5e6 | 2015-03-25 19:27:16 +0200 | [diff] [blame] | 4684 | max_t(int, dev_priv->rps.efficient_freq, |
| 4685 | intel_freq_opcode(dev_priv, 450)); |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4686 | else |
| 4687 | dev_priv->rps.min_freq_softlimit = |
| 4688 | dev_priv->rps.min_freq; |
| 4689 | } |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 4690 | } |
| 4691 | |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4692 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4693 | static void gen9_enable_rps(struct drm_device *dev) |
| 4694 | { |
| 4695 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4696 | |
| 4697 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 4698 | |
Damien Lespiau | ba1c554 | 2015-01-16 18:07:26 +0000 | [diff] [blame] | 4699 | gen6_init_rps_frequencies(dev); |
| 4700 | |
Sagar Arun Kamble | 23eafea | 2015-08-23 17:52:48 +0530 | [diff] [blame] | 4701 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
| 4702 | if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { |
| 4703 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 4704 | return; |
| 4705 | } |
| 4706 | |
Akash Goel | 0beb059 | 2015-03-06 11:07:20 +0530 | [diff] [blame] | 4707 | /* Program defaults and thresholds for RPS*/ |
| 4708 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 4709 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4710 | |
Akash Goel | 0beb059 | 2015-03-06 11:07:20 +0530 | [diff] [blame] | 4711 | /* 1 second timeout*/ |
| 4712 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, |
| 4713 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); |
| 4714 | |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4715 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4716 | |
Akash Goel | 0beb059 | 2015-03-06 11:07:20 +0530 | [diff] [blame] | 4717 | /* Leaning on the below call to gen6_set_rps to program/setup the |
| 4718 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, |
| 4719 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ |
| 4720 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
| 4721 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 4722 | |
| 4723 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 4724 | } |
| 4725 | |
| 4726 | static void gen9_enable_rc6(struct drm_device *dev) |
| 4727 | { |
| 4728 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4729 | struct intel_engine_cs *ring; |
| 4730 | uint32_t rc6_mask = 0; |
| 4731 | int unused; |
| 4732 | |
| 4733 | /* 1a: Software RC state - RC0 */ |
| 4734 | I915_WRITE(GEN6_RC_STATE, 0); |
| 4735 | |
| 4736 | /* 1b: Get forcewake during program sequence. Although the driver |
| 4737 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4738 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4739 | |
| 4740 | /* 2a: Disable RC states. */ |
| 4741 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4742 | |
| 4743 | /* 2b: Program RC6 thresholds.*/ |
Sagar Arun Kamble | 63a4dec | 2015-09-12 10:17:53 +0530 | [diff] [blame] | 4744 | |
| 4745 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ |
| 4746 | if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && |
| 4747 | (INTEL_REVID(dev) <= SKL_REVID_E0))) |
| 4748 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); |
| 4749 | else |
| 4750 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4751 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 4752 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 4753 | for_each_ring(ring, dev_priv, unused) |
| 4754 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
Sagar Arun Kamble | 97c322e | 2015-09-12 10:17:54 +0530 | [diff] [blame] | 4755 | |
| 4756 | if (HAS_GUC_UCODE(dev)) |
| 4757 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); |
| 4758 | |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4759 | I915_WRITE(GEN6_RC_SLEEP, 0); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4760 | |
Zhe Wang | 38c2352 | 2015-01-20 12:23:04 +0000 | [diff] [blame] | 4761 | /* 2c: Program Coarse Power Gating Policies. */ |
| 4762 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); |
| 4763 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); |
| 4764 | |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4765 | /* 3a: Enable RC6 */ |
| 4766 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
| 4767 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
| 4768 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
| 4769 | "on" : "off"); |
Sagar Arun Kamble | 3e7732a | 2015-10-01 20:29:27 +0530 | [diff] [blame] | 4770 | /* WaRsUseTimeoutMode */ |
Sagar Arun Kamble | e3429cd | 2015-09-12 10:17:52 +0530 | [diff] [blame] | 4771 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || |
Sagar Arun Kamble | 3e7732a | 2015-10-01 20:29:27 +0530 | [diff] [blame] | 4772 | (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { |
| 4773 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ |
Sagar Arun Kamble | e3429cd | 2015-09-12 10:17:52 +0530 | [diff] [blame] | 4774 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 4775 | GEN7_RC_CTL_TO_MODE | |
| 4776 | rc6_mask); |
Sagar Arun Kamble | 3e7732a | 2015-10-01 20:29:27 +0530 | [diff] [blame] | 4777 | } else { |
| 4778 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ |
Sagar Arun Kamble | e3429cd | 2015-09-12 10:17:52 +0530 | [diff] [blame] | 4779 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 4780 | GEN6_RC_CTL_EI_MODE(1) | |
| 4781 | rc6_mask); |
Sagar Arun Kamble | 3e7732a | 2015-10-01 20:29:27 +0530 | [diff] [blame] | 4782 | } |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4783 | |
Sagar Kamble | cb07bae | 2015-04-12 11:28:14 +0530 | [diff] [blame] | 4784 | /* |
| 4785 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. |
Sagar Arun Kamble | f2d2fe9 | 2015-09-12 10:17:51 +0530 | [diff] [blame] | 4786 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
Sagar Kamble | cb07bae | 2015-04-12 11:28:14 +0530 | [diff] [blame] | 4787 | */ |
Sagar Arun Kamble | f2d2fe9 | 2015-09-12 10:17:51 +0530 | [diff] [blame] | 4788 | if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || |
| 4789 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) |
| 4790 | I915_WRITE(GEN9_PG_ENABLE, 0); |
| 4791 | else |
| 4792 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? |
| 4793 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); |
Zhe Wang | 38c2352 | 2015-01-20 12:23:04 +0000 | [diff] [blame] | 4794 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4795 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 4796 | |
| 4797 | } |
| 4798 | |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4799 | static void gen8_enable_rps(struct drm_device *dev) |
| 4800 | { |
| 4801 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4802 | struct intel_engine_cs *ring; |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4803 | uint32_t rc6_mask = 0; |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4804 | int unused; |
| 4805 | |
| 4806 | /* 1a: Software RC state - RC0 */ |
| 4807 | I915_WRITE(GEN6_RC_STATE, 0); |
| 4808 | |
| 4809 | /* 1c & 1d: Get forcewake during program sequence. Although the driver |
| 4810 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4811 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4812 | |
| 4813 | /* 2a: Disable RC states. */ |
| 4814 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4815 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4816 | /* Initialize rps frequencies */ |
| 4817 | gen6_init_rps_frequencies(dev); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4818 | |
| 4819 | /* 2b: Program RC6 thresholds.*/ |
| 4820 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
| 4821 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 4822 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 4823 | for_each_ring(ring, dev_priv, unused) |
| 4824 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 4825 | I915_WRITE(GEN6_RC_SLEEP, 0); |
Tom O'Rourke | 0d68b25 | 2014-04-09 11:44:06 -0700 | [diff] [blame] | 4826 | if (IS_BROADWELL(dev)) |
| 4827 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
| 4828 | else |
| 4829 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4830 | |
| 4831 | /* 3: Enable RC6 */ |
| 4832 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
| 4833 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
Ben Widawsky | abbf9d2 | 2014-01-28 20:25:41 -0800 | [diff] [blame] | 4834 | intel_print_rc6_info(dev, rc6_mask); |
Tom O'Rourke | 0d68b25 | 2014-04-09 11:44:06 -0700 | [diff] [blame] | 4835 | if (IS_BROADWELL(dev)) |
| 4836 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 4837 | GEN7_RC_CTL_TO_MODE | |
| 4838 | rc6_mask); |
| 4839 | else |
| 4840 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 4841 | GEN6_RC_CTL_EI_MODE(1) | |
| 4842 | rc6_mask); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4843 | |
| 4844 | /* 4 Program defaults and thresholds for RPS*/ |
Ben Widawsky | f9bdc58 | 2014-03-31 17:16:41 -0700 | [diff] [blame] | 4845 | I915_WRITE(GEN6_RPNSWREQ, |
| 4846 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
| 4847 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 4848 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4849 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
| 4850 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4851 | |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4852 | /* Docs recommend 900MHz, and 300 MHz respectively */ |
| 4853 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
| 4854 | dev_priv->rps.max_freq_softlimit << 24 | |
| 4855 | dev_priv->rps.min_freq_softlimit << 16); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4856 | |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4857 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ |
| 4858 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ |
| 4859 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ |
| 4860 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4861 | |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4862 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4863 | |
| 4864 | /* 5: Enable RPS */ |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4865 | I915_WRITE(GEN6_RP_CONTROL, |
| 4866 | GEN6_RP_MEDIA_TURBO | |
| 4867 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 4868 | GEN6_RP_MEDIA_IS_GFX | |
| 4869 | GEN6_RP_ENABLE | |
| 4870 | GEN6_RP_UP_BUSY_AVG | |
| 4871 | GEN6_RP_DOWN_IDLE_AVG); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4872 | |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4873 | /* 6: Ring frequency + overclocking (our driver does this later */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4874 | |
Tom O'Rourke | c7f3153 | 2014-11-19 14:21:54 -0800 | [diff] [blame] | 4875 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4876 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
Daniel Vetter | 7526ed7 | 2014-09-29 15:07:19 +0200 | [diff] [blame] | 4877 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4878 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4879 | } |
| 4880 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4881 | static void gen6_enable_rps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4882 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4883 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4884 | struct intel_engine_cs *ring; |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 4885 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4886 | u32 gtfifodbg; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4887 | int rc6_mode; |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 4888 | int i, ret; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4889 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4890 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4891 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4892 | /* Here begins a magic sequence of register writes to enable |
| 4893 | * auto-downclocking. |
| 4894 | * |
| 4895 | * Perhaps there might be some value in exposing these to |
| 4896 | * userspace... |
| 4897 | */ |
| 4898 | I915_WRITE(GEN6_RC_STATE, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4899 | |
| 4900 | /* Clear the DBG now so we don't confuse earlier errors */ |
| 4901 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
| 4902 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
| 4903 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 4904 | } |
| 4905 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4906 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4907 | |
Tom O'Rourke | 93ee292 | 2014-11-19 14:21:52 -0800 | [diff] [blame] | 4908 | /* Initialize rps frequencies */ |
| 4909 | gen6_init_rps_frequencies(dev); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4910 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4911 | /* disable the counters and set deterministic thresholds */ |
| 4912 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 4913 | |
| 4914 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
| 4915 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
| 4916 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
| 4917 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 4918 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 4919 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4920 | for_each_ring(ring, dev_priv, i) |
| 4921 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4922 | |
| 4923 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 4924 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
Daniel Vetter | 29c78f6 | 2013-11-16 16:04:26 +0100 | [diff] [blame] | 4925 | if (IS_IVYBRIDGE(dev)) |
Stéphane Marchesin | 351aa56 | 2013-08-13 11:55:17 -0700 | [diff] [blame] | 4926 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
| 4927 | else |
| 4928 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
Stéphane Marchesin | 0920a48 | 2013-01-29 19:41:59 -0800 | [diff] [blame] | 4929 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4930 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
| 4931 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 4932 | /* Check if we are enabling RC6 */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4933 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
| 4934 | if (rc6_mode & INTEL_RC6_ENABLE) |
| 4935 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
| 4936 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 4937 | /* We don't use those on Haswell */ |
| 4938 | if (!IS_HASWELL(dev)) { |
| 4939 | if (rc6_mode & INTEL_RC6p_ENABLE) |
| 4940 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4941 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 4942 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
| 4943 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
| 4944 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4945 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 4946 | intel_print_rc6_info(dev, rc6_mask); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4947 | |
| 4948 | I915_WRITE(GEN6_RC_CONTROL, |
| 4949 | rc6_mask | |
| 4950 | GEN6_RC_CTL_EI_MODE(1) | |
| 4951 | GEN6_RC_CTL_HW_ENABLE); |
| 4952 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4953 | /* Power down if completely idle for over 50ms */ |
| 4954 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4955 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4956 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 4957 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 4958 | if (ret) |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 4959 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 4960 | |
| 4961 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
| 4962 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ |
| 4963 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4964 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 4965 | (pcu_mbox & 0xff) * 50); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4966 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4967 | } |
| 4968 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 4969 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 4970 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4971 | |
Ben Widawsky | 31643d5 | 2012-09-26 10:34:01 -0700 | [diff] [blame] | 4972 | rc6vids = 0; |
| 4973 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 4974 | if (IS_GEN6(dev) && ret) { |
| 4975 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
| 4976 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
| 4977 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
| 4978 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
| 4979 | rc6vids &= 0xffff00; |
| 4980 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
| 4981 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
| 4982 | if (ret) |
| 4983 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
| 4984 | } |
| 4985 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4986 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4987 | } |
| 4988 | |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 4989 | static void __gen6_update_ring_freq(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4990 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4991 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4992 | int min_freq = 15; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 4993 | unsigned int gpu_freq; |
| 4994 | unsigned int max_ia_freq, min_ring_freq; |
Akash Goel | 4c8c774 | 2015-06-29 14:50:20 +0530 | [diff] [blame] | 4995 | unsigned int max_gpu_freq, min_gpu_freq; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4996 | int scaling_factor = 180; |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 4997 | struct cpufreq_policy *policy; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4998 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4999 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 5000 | |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 5001 | policy = cpufreq_cpu_get(0); |
| 5002 | if (policy) { |
| 5003 | max_ia_freq = policy->cpuinfo.max_freq; |
| 5004 | cpufreq_cpu_put(policy); |
| 5005 | } else { |
| 5006 | /* |
| 5007 | * Default to measured freq if none found, PCU will ensure we |
| 5008 | * don't go over |
| 5009 | */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5010 | max_ia_freq = tsc_khz; |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 5011 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5012 | |
| 5013 | /* Convert from kHz to MHz */ |
| 5014 | max_ia_freq /= 1000; |
| 5015 | |
Ben Widawsky | 153b4b95 | 2013-10-22 22:05:09 -0700 | [diff] [blame] | 5016 | min_ring_freq = I915_READ(DCLK) & 0xf; |
Ben Widawsky | f6aca45 | 2013-10-02 09:25:02 -0700 | [diff] [blame] | 5017 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
| 5018 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 5019 | |
Akash Goel | 4c8c774 | 2015-06-29 14:50:20 +0530 | [diff] [blame] | 5020 | if (IS_SKYLAKE(dev)) { |
| 5021 | /* Convert GT frequency to 50 HZ units */ |
| 5022 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; |
| 5023 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; |
| 5024 | } else { |
| 5025 | min_gpu_freq = dev_priv->rps.min_freq; |
| 5026 | max_gpu_freq = dev_priv->rps.max_freq; |
| 5027 | } |
| 5028 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5029 | /* |
| 5030 | * For each potential GPU frequency, load a ring frequency we'd like |
| 5031 | * to use for memory access. We do this by specifying the IA frequency |
| 5032 | * the PCU should use as a reference to determine the ring frequency. |
| 5033 | */ |
Akash Goel | 4c8c774 | 2015-06-29 14:50:20 +0530 | [diff] [blame] | 5034 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
| 5035 | int diff = max_gpu_freq - gpu_freq; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 5036 | unsigned int ia_freq = 0, ring_freq = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5037 | |
Akash Goel | 4c8c774 | 2015-06-29 14:50:20 +0530 | [diff] [blame] | 5038 | if (IS_SKYLAKE(dev)) { |
| 5039 | /* |
| 5040 | * ring_freq = 2 * GT. ring_freq is in 100MHz units |
| 5041 | * No floor required for ring frequency on SKL. |
| 5042 | */ |
| 5043 | ring_freq = gpu_freq; |
| 5044 | } else if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | 46c764d | 2013-11-02 21:07:49 -0700 | [diff] [blame] | 5045 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
| 5046 | ring_freq = max(min_ring_freq, gpu_freq); |
| 5047 | } else if (IS_HASWELL(dev)) { |
Ben Widawsky | f6aca45 | 2013-10-02 09:25:02 -0700 | [diff] [blame] | 5048 | ring_freq = mult_frac(gpu_freq, 5, 4); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 5049 | ring_freq = max(min_ring_freq, ring_freq); |
| 5050 | /* leave ia_freq as the default, chosen by cpufreq */ |
| 5051 | } else { |
| 5052 | /* On older processors, there is no separate ring |
| 5053 | * clock domain, so in order to boost the bandwidth |
| 5054 | * of the ring, we need to upclock the CPU (ia_freq). |
| 5055 | * |
| 5056 | * For GPU frequencies less than 750MHz, |
| 5057 | * just use the lowest ring freq. |
| 5058 | */ |
| 5059 | if (gpu_freq < min_freq) |
| 5060 | ia_freq = 800; |
| 5061 | else |
| 5062 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
| 5063 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
| 5064 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5065 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 5066 | sandybridge_pcode_write(dev_priv, |
| 5067 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 5068 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
| 5069 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | |
| 5070 | gpu_freq); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5071 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 5072 | } |
| 5073 | |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 5074 | void gen6_update_ring_freq(struct drm_device *dev) |
| 5075 | { |
| 5076 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5077 | |
Akash Goel | 97d3308 | 2015-06-29 14:50:23 +0530 | [diff] [blame] | 5078 | if (!HAS_CORE_RING_FREQ(dev)) |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 5079 | return; |
| 5080 | |
| 5081 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5082 | __gen6_update_ring_freq(dev); |
| 5083 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5084 | } |
| 5085 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 5086 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5087 | { |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 5088 | struct drm_device *dev = dev_priv->dev; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5089 | u32 val, rp0; |
| 5090 | |
Jani Nikula | 5b5929c | 2015-10-07 11:17:46 +0300 | [diff] [blame] | 5091 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5092 | |
Jani Nikula | 5b5929c | 2015-10-07 11:17:46 +0300 | [diff] [blame] | 5093 | switch (INTEL_INFO(dev)->eu_total) { |
| 5094 | case 8: |
| 5095 | /* (2 * 4) config */ |
| 5096 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); |
| 5097 | break; |
| 5098 | case 12: |
| 5099 | /* (2 * 6) config */ |
| 5100 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); |
| 5101 | break; |
| 5102 | case 16: |
| 5103 | /* (2 * 8) config */ |
| 5104 | default: |
| 5105 | /* Setting (2 * 8) Min RP0 for any other combination */ |
| 5106 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); |
| 5107 | break; |
Deepak S | 095acd5 | 2015-01-17 11:05:59 +0530 | [diff] [blame] | 5108 | } |
Jani Nikula | 5b5929c | 2015-10-07 11:17:46 +0300 | [diff] [blame] | 5109 | |
| 5110 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); |
| 5111 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5112 | return rp0; |
| 5113 | } |
| 5114 | |
| 5115 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
| 5116 | { |
| 5117 | u32 val, rpe; |
| 5118 | |
| 5119 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); |
| 5120 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; |
| 5121 | |
| 5122 | return rpe; |
| 5123 | } |
| 5124 | |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 5125 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
| 5126 | { |
| 5127 | u32 val, rp1; |
| 5128 | |
Jani Nikula | 5b5929c | 2015-10-07 11:17:46 +0300 | [diff] [blame] | 5129 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
| 5130 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); |
| 5131 | |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 5132 | return rp1; |
| 5133 | } |
| 5134 | |
Deepak S | f8f2b00 | 2014-07-10 13:16:21 +0530 | [diff] [blame] | 5135 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
| 5136 | { |
| 5137 | u32 val, rp1; |
| 5138 | |
| 5139 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
| 5140 | |
| 5141 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; |
| 5142 | |
| 5143 | return rp1; |
| 5144 | } |
| 5145 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 5146 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5147 | { |
| 5148 | u32 val, rp0; |
| 5149 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 5150 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5151 | |
| 5152 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; |
| 5153 | /* Clamp to max */ |
| 5154 | rp0 = min_t(u32, rp0, 0xea); |
| 5155 | |
| 5156 | return rp0; |
| 5157 | } |
| 5158 | |
| 5159 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
| 5160 | { |
| 5161 | u32 val, rpe; |
| 5162 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 5163 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5164 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 5165 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5166 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
| 5167 | |
| 5168 | return rpe; |
| 5169 | } |
| 5170 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 5171 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5172 | { |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 5173 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5174 | } |
| 5175 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5176 | /* Check that the pctx buffer wasn't move under us. */ |
| 5177 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) |
| 5178 | { |
| 5179 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
| 5180 | |
| 5181 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + |
| 5182 | dev_priv->vlv_pctx->stolen->start); |
| 5183 | } |
| 5184 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5185 | |
| 5186 | /* Check that the pcbr address is not empty. */ |
| 5187 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) |
| 5188 | { |
| 5189 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
| 5190 | |
| 5191 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); |
| 5192 | } |
| 5193 | |
| 5194 | static void cherryview_setup_pctx(struct drm_device *dev) |
| 5195 | { |
| 5196 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5197 | unsigned long pctx_paddr, paddr; |
| 5198 | struct i915_gtt *gtt = &dev_priv->gtt; |
| 5199 | u32 pcbr; |
| 5200 | int pctx_size = 32*1024; |
| 5201 | |
| 5202 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 5203 | |
| 5204 | pcbr = I915_READ(VLV_PCBR); |
| 5205 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { |
Ville Syrjälä | ce611ef | 2014-11-07 21:33:46 +0200 | [diff] [blame] | 5206 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5207 | paddr = (dev_priv->mm.stolen_base + |
| 5208 | (gtt->stolen_size - pctx_size)); |
| 5209 | |
| 5210 | pctx_paddr = (paddr & (~4095)); |
| 5211 | I915_WRITE(VLV_PCBR, pctx_paddr); |
| 5212 | } |
Ville Syrjälä | ce611ef | 2014-11-07 21:33:46 +0200 | [diff] [blame] | 5213 | |
| 5214 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5215 | } |
| 5216 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 5217 | static void valleyview_setup_pctx(struct drm_device *dev) |
| 5218 | { |
| 5219 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5220 | struct drm_i915_gem_object *pctx; |
| 5221 | unsigned long pctx_paddr; |
| 5222 | u32 pcbr; |
| 5223 | int pctx_size = 24*1024; |
| 5224 | |
Imre Deak | 17b0c1f | 2014-02-11 21:39:06 +0200 | [diff] [blame] | 5225 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 5226 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 5227 | pcbr = I915_READ(VLV_PCBR); |
| 5228 | if (pcbr) { |
| 5229 | /* BIOS set it up already, grab the pre-alloc'd space */ |
| 5230 | int pcbr_offset; |
| 5231 | |
| 5232 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; |
| 5233 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, |
| 5234 | pcbr_offset, |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 5235 | I915_GTT_OFFSET_NONE, |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 5236 | pctx_size); |
| 5237 | goto out; |
| 5238 | } |
| 5239 | |
Ville Syrjälä | ce611ef | 2014-11-07 21:33:46 +0200 | [diff] [blame] | 5240 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
| 5241 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 5242 | /* |
| 5243 | * From the Gunit register HAS: |
| 5244 | * The Gfx driver is expected to program this register and ensure |
| 5245 | * proper allocation within Gfx stolen memory. For example, this |
| 5246 | * register should be programmed such than the PCBR range does not |
| 5247 | * overlap with other ranges, such as the frame buffer, protected |
| 5248 | * memory, or any other relevant ranges. |
| 5249 | */ |
| 5250 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
| 5251 | if (!pctx) { |
| 5252 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
| 5253 | return; |
| 5254 | } |
| 5255 | |
| 5256 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
| 5257 | I915_WRITE(VLV_PCBR, pctx_paddr); |
| 5258 | |
| 5259 | out: |
Ville Syrjälä | ce611ef | 2014-11-07 21:33:46 +0200 | [diff] [blame] | 5260 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 5261 | dev_priv->vlv_pctx = pctx; |
| 5262 | } |
| 5263 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5264 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
| 5265 | { |
| 5266 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5267 | |
| 5268 | if (WARN_ON(!dev_priv->vlv_pctx)) |
| 5269 | return; |
| 5270 | |
| 5271 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); |
| 5272 | dev_priv->vlv_pctx = NULL; |
| 5273 | } |
| 5274 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5275 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
| 5276 | { |
| 5277 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5278 | u32 val; |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5279 | |
| 5280 | valleyview_setup_pctx(dev); |
| 5281 | |
| 5282 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5283 | |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5284 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 5285 | switch ((val >> 6) & 3) { |
| 5286 | case 0: |
| 5287 | case 1: |
| 5288 | dev_priv->mem_freq = 800; |
| 5289 | break; |
| 5290 | case 2: |
| 5291 | dev_priv->mem_freq = 1066; |
| 5292 | break; |
| 5293 | case 3: |
| 5294 | dev_priv->mem_freq = 1333; |
| 5295 | break; |
| 5296 | } |
Ville Syrjälä | 80b83b6 | 2014-11-10 22:55:14 +0200 | [diff] [blame] | 5297 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5298 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5299 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
| 5300 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
| 5301 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5302 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5303 | dev_priv->rps.max_freq); |
| 5304 | |
| 5305 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); |
| 5306 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5307 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5308 | dev_priv->rps.efficient_freq); |
| 5309 | |
Deepak S | f8f2b00 | 2014-07-10 13:16:21 +0530 | [diff] [blame] | 5310 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
| 5311 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5312 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
Deepak S | f8f2b00 | 2014-07-10 13:16:21 +0530 | [diff] [blame] | 5313 | dev_priv->rps.rp1_freq); |
| 5314 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5315 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
| 5316 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5317 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5318 | dev_priv->rps.min_freq); |
| 5319 | |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 5320 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
| 5321 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5322 | /* Preserve min/max settings in case of re-init */ |
| 5323 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 5324 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 5325 | |
| 5326 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 5327 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 5328 | |
| 5329 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5330 | } |
| 5331 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5332 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
| 5333 | { |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5334 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5335 | u32 val; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5336 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5337 | cherryview_setup_pctx(dev); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5338 | |
| 5339 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5340 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 5341 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | c6e8f39 | 2014-11-07 21:33:43 +0200 | [diff] [blame] | 5342 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 5343 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | c6e8f39 | 2014-11-07 21:33:43 +0200 | [diff] [blame] | 5344 | |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5345 | switch ((val >> 2) & 0x7) { |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5346 | case 3: |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5347 | dev_priv->mem_freq = 2000; |
| 5348 | break; |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 5349 | default: |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5350 | dev_priv->mem_freq = 1600; |
| 5351 | break; |
| 5352 | } |
Ville Syrjälä | 80b83b6 | 2014-11-10 22:55:14 +0200 | [diff] [blame] | 5353 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
Ville Syrjälä | 2bb25c1 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 5354 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5355 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
| 5356 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
| 5357 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5358 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5359 | dev_priv->rps.max_freq); |
| 5360 | |
| 5361 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); |
| 5362 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5363 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5364 | dev_priv->rps.efficient_freq); |
| 5365 | |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 5366 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
| 5367 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5368 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 5369 | dev_priv->rps.rp1_freq); |
| 5370 | |
Deepak S | 5b7c91b | 2015-05-09 18:15:46 +0530 | [diff] [blame] | 5371 | /* PUnit validated range is only [RPe, RP0] */ |
| 5372 | dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5373 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5374 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5375 | dev_priv->rps.min_freq); |
| 5376 | |
Ville Syrjälä | 1c14762 | 2014-08-18 14:42:43 +0300 | [diff] [blame] | 5377 | WARN_ONCE((dev_priv->rps.max_freq | |
| 5378 | dev_priv->rps.efficient_freq | |
| 5379 | dev_priv->rps.rp1_freq | |
| 5380 | dev_priv->rps.min_freq) & 1, |
| 5381 | "Odd GPU freq values\n"); |
| 5382 | |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 5383 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
| 5384 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5385 | /* Preserve min/max settings in case of re-init */ |
| 5386 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 5387 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 5388 | |
| 5389 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 5390 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 5391 | |
| 5392 | mutex_unlock(&dev_priv->rps.hw_lock); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5393 | } |
| 5394 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5395 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
| 5396 | { |
| 5397 | valleyview_cleanup_pctx(dev); |
| 5398 | } |
| 5399 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5400 | static void cherryview_enable_rps(struct drm_device *dev) |
| 5401 | { |
| 5402 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5403 | struct intel_engine_cs *ring; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5404 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5405 | int i; |
| 5406 | |
| 5407 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 5408 | |
| 5409 | gtfifodbg = I915_READ(GTFIFODBG); |
| 5410 | if (gtfifodbg) { |
| 5411 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
| 5412 | gtfifodbg); |
| 5413 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 5414 | } |
| 5415 | |
| 5416 | cherryview_check_pctx(dev_priv); |
| 5417 | |
| 5418 | /* 1a & 1b: Get forcewake during program sequence. Although the driver |
| 5419 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 5420 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5421 | |
Ville Syrjälä | 160614a | 2015-01-19 13:50:47 +0200 | [diff] [blame] | 5422 | /* Disable RC states. */ |
| 5423 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 5424 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5425 | /* 2a: Program RC6 thresholds.*/ |
| 5426 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
| 5427 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 5428 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 5429 | |
| 5430 | for_each_ring(ring, dev_priv, i) |
| 5431 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 5432 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 5433 | |
Deepak S | f4f71c7 | 2015-03-28 15:23:35 +0530 | [diff] [blame] | 5434 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
| 5435 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5436 | |
| 5437 | /* allows RC6 residency counter to work */ |
| 5438 | I915_WRITE(VLV_COUNTER_CONTROL, |
| 5439 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
| 5440 | VLV_MEDIA_RC6_COUNT_EN | |
| 5441 | VLV_RENDER_RC6_COUNT_EN)); |
| 5442 | |
| 5443 | /* For now we assume BIOS is allocating and populating the PCBR */ |
| 5444 | pcbr = I915_READ(VLV_PCBR); |
| 5445 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5446 | /* 3: Enable RC6 */ |
| 5447 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && |
| 5448 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) |
Ville Syrjälä | af5a75a | 2015-01-19 13:50:50 +0200 | [diff] [blame] | 5449 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5450 | |
| 5451 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
| 5452 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5453 | /* 4 Program defaults and thresholds for RPS*/ |
Ville Syrjälä | 3cbdb48 | 2015-01-19 13:50:49 +0200 | [diff] [blame] | 5454 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5455 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 5456 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 5457 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 5458 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 5459 | |
| 5460 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 5461 | |
| 5462 | /* 5: Enable RPS */ |
| 5463 | I915_WRITE(GEN6_RP_CONTROL, |
| 5464 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
Ville Syrjälä | eb973a5 | 2015-01-21 19:37:59 +0200 | [diff] [blame] | 5465 | GEN6_RP_MEDIA_IS_GFX | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5466 | GEN6_RP_ENABLE | |
| 5467 | GEN6_RP_UP_BUSY_AVG | |
| 5468 | GEN6_RP_DOWN_IDLE_AVG); |
| 5469 | |
Deepak S | 3ef6234 | 2015-04-29 08:36:24 +0530 | [diff] [blame] | 5470 | /* Setting Fixed Bias */ |
| 5471 | val = VLV_OVERRIDE_EN | |
| 5472 | VLV_SOC_TDP_EN | |
| 5473 | CHV_BIAS_CPU_50_SOC_50; |
| 5474 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); |
| 5475 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5476 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 5477 | |
Ville Syrjälä | 8d40c3a | 2014-11-07 21:33:45 +0200 | [diff] [blame] | 5478 | /* RPS code assumes GPLL is used */ |
| 5479 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); |
| 5480 | |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 5481 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5482 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
| 5483 | |
| 5484 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
| 5485 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5486 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5487 | dev_priv->rps.cur_freq); |
| 5488 | |
| 5489 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5490 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 5491 | dev_priv->rps.efficient_freq); |
| 5492 | |
| 5493 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
| 5494 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 5495 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5496 | } |
| 5497 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5498 | static void valleyview_enable_rps(struct drm_device *dev) |
| 5499 | { |
| 5500 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 5501 | struct intel_engine_cs *ring; |
Ben Widawsky | 2a5913a | 2014-03-19 18:31:13 -0700 | [diff] [blame] | 5502 | u32 gtfifodbg, val, rc6_mode = 0; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5503 | int i; |
| 5504 | |
| 5505 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 5506 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5507 | valleyview_check_pctx(dev_priv); |
| 5508 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5509 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
Jesse Barnes | f7d85c1 | 2013-09-27 10:40:54 -0700 | [diff] [blame] | 5510 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
| 5511 | gtfifodbg); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5512 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 5513 | } |
| 5514 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 5515 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 5516 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5517 | |
Ville Syrjälä | 160614a | 2015-01-19 13:50:47 +0200 | [diff] [blame] | 5518 | /* Disable RC states. */ |
| 5519 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 5520 | |
Ville Syrjälä | cad725f | 2015-01-19 13:50:48 +0200 | [diff] [blame] | 5521 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5522 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 5523 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 5524 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 5525 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 5526 | |
| 5527 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 5528 | |
| 5529 | I915_WRITE(GEN6_RP_CONTROL, |
| 5530 | GEN6_RP_MEDIA_TURBO | |
| 5531 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 5532 | GEN6_RP_MEDIA_IS_GFX | |
| 5533 | GEN6_RP_ENABLE | |
| 5534 | GEN6_RP_UP_BUSY_AVG | |
| 5535 | GEN6_RP_DOWN_IDLE_CONT); |
| 5536 | |
| 5537 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); |
| 5538 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 5539 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 5540 | |
| 5541 | for_each_ring(ring, dev_priv, i) |
| 5542 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 5543 | |
Jesse Barnes | 2f0aa304 | 2013-11-15 09:32:11 -0800 | [diff] [blame] | 5544 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5545 | |
| 5546 | /* allows RC6 residency counter to work */ |
Jesse Barnes | 49798eb | 2013-09-26 17:55:57 -0700 | [diff] [blame] | 5547 | I915_WRITE(VLV_COUNTER_CONTROL, |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 5548 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
| 5549 | VLV_RENDER_RC0_COUNT_EN | |
Jesse Barnes | 49798eb | 2013-09-26 17:55:57 -0700 | [diff] [blame] | 5550 | VLV_MEDIA_RC6_COUNT_EN | |
| 5551 | VLV_RENDER_RC6_COUNT_EN)); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 5552 | |
Jesse Barnes | a2b23fe | 2013-09-19 09:33:13 -0700 | [diff] [blame] | 5553 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
Jesse Barnes | 6b88f29 | 2013-11-15 09:32:12 -0800 | [diff] [blame] | 5554 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 5555 | |
| 5556 | intel_print_rc6_info(dev, rc6_mode); |
| 5557 | |
Jesse Barnes | a2b23fe | 2013-09-19 09:33:13 -0700 | [diff] [blame] | 5558 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5559 | |
Deepak S | 3ef6234 | 2015-04-29 08:36:24 +0530 | [diff] [blame] | 5560 | /* Setting Fixed Bias */ |
| 5561 | val = VLV_OVERRIDE_EN | |
| 5562 | VLV_SOC_TDP_EN | |
| 5563 | VLV_BIAS_CPU_125_SOC_875; |
| 5564 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); |
| 5565 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 5566 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5567 | |
Ville Syrjälä | 8d40c3a | 2014-11-07 21:33:45 +0200 | [diff] [blame] | 5568 | /* RPS code assumes GPLL is used */ |
| 5569 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); |
| 5570 | |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 5571 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5572 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
| 5573 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 5574 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 5575 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5576 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 5577 | dev_priv->rps.cur_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5578 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 5579 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5580 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 5581 | dev_priv->rps.efficient_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5582 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 5583 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5584 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 5585 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5586 | } |
| 5587 | |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 5588 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 5589 | { |
| 5590 | unsigned long freq; |
| 5591 | int div = (vidfreq & 0x3f0000) >> 16; |
| 5592 | int post = (vidfreq & 0x3000) >> 12; |
| 5593 | int pre = (vidfreq & 0x7); |
| 5594 | |
| 5595 | if (!pre) |
| 5596 | return 0; |
| 5597 | |
| 5598 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 5599 | |
| 5600 | return freq; |
| 5601 | } |
| 5602 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5603 | static const struct cparams { |
| 5604 | u16 i; |
| 5605 | u16 t; |
| 5606 | u16 m; |
| 5607 | u16 c; |
| 5608 | } cparams[] = { |
| 5609 | { 1, 1333, 301, 28664 }, |
| 5610 | { 1, 1066, 294, 24460 }, |
| 5611 | { 1, 800, 294, 25192 }, |
| 5612 | { 0, 1333, 276, 27605 }, |
| 5613 | { 0, 1066, 276, 27605 }, |
| 5614 | { 0, 800, 231, 23784 }, |
| 5615 | }; |
| 5616 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5617 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5618 | { |
| 5619 | u64 total_count, diff, ret; |
| 5620 | u32 count1, count2, count3, m = 0, c = 0; |
| 5621 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
| 5622 | int i; |
| 5623 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5624 | assert_spin_locked(&mchdev_lock); |
| 5625 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5626 | diff1 = now - dev_priv->ips.last_time1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5627 | |
| 5628 | /* Prevent division-by-zero if we are asking too fast. |
| 5629 | * Also, we don't get interesting results if we are polling |
| 5630 | * faster than once in 10ms, so just return the saved value |
| 5631 | * in such cases. |
| 5632 | */ |
| 5633 | if (diff1 <= 10) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5634 | return dev_priv->ips.chipset_power; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5635 | |
| 5636 | count1 = I915_READ(DMIEC); |
| 5637 | count2 = I915_READ(DDREC); |
| 5638 | count3 = I915_READ(CSIEC); |
| 5639 | |
| 5640 | total_count = count1 + count2 + count3; |
| 5641 | |
| 5642 | /* FIXME: handle per-counter overflow */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5643 | if (total_count < dev_priv->ips.last_count1) { |
| 5644 | diff = ~0UL - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5645 | diff += total_count; |
| 5646 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5647 | diff = total_count - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5648 | } |
| 5649 | |
| 5650 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5651 | if (cparams[i].i == dev_priv->ips.c_m && |
| 5652 | cparams[i].t == dev_priv->ips.r_t) { |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5653 | m = cparams[i].m; |
| 5654 | c = cparams[i].c; |
| 5655 | break; |
| 5656 | } |
| 5657 | } |
| 5658 | |
| 5659 | diff = div_u64(diff, diff1); |
| 5660 | ret = ((m * diff) + c); |
| 5661 | ret = div_u64(ret, 10); |
| 5662 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5663 | dev_priv->ips.last_count1 = total_count; |
| 5664 | dev_priv->ips.last_time1 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5665 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5666 | dev_priv->ips.chipset_power = ret; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5667 | |
| 5668 | return ret; |
| 5669 | } |
| 5670 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5671 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
| 5672 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5673 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5674 | unsigned long val; |
| 5675 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5676 | if (INTEL_INFO(dev)->gen != 5) |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5677 | return 0; |
| 5678 | |
| 5679 | spin_lock_irq(&mchdev_lock); |
| 5680 | |
| 5681 | val = __i915_chipset_val(dev_priv); |
| 5682 | |
| 5683 | spin_unlock_irq(&mchdev_lock); |
| 5684 | |
| 5685 | return val; |
| 5686 | } |
| 5687 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5688 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
| 5689 | { |
| 5690 | unsigned long m, x, b; |
| 5691 | u32 tsfs; |
| 5692 | |
| 5693 | tsfs = I915_READ(TSFS); |
| 5694 | |
| 5695 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
| 5696 | x = I915_READ8(TR1); |
| 5697 | |
| 5698 | b = tsfs & TSFS_INTR_MASK; |
| 5699 | |
| 5700 | return ((m * x) / 127) - b; |
| 5701 | } |
| 5702 | |
Mika Kuoppala | d972d6e | 2014-12-01 18:01:05 +0200 | [diff] [blame] | 5703 | static int _pxvid_to_vd(u8 pxvid) |
| 5704 | { |
| 5705 | if (pxvid == 0) |
| 5706 | return 0; |
| 5707 | |
| 5708 | if (pxvid >= 8 && pxvid < 31) |
| 5709 | pxvid = 31; |
| 5710 | |
| 5711 | return (pxvid + 2) * 125; |
| 5712 | } |
| 5713 | |
| 5714 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5715 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5716 | struct drm_device *dev = dev_priv->dev; |
Mika Kuoppala | d972d6e | 2014-12-01 18:01:05 +0200 | [diff] [blame] | 5717 | const int vd = _pxvid_to_vd(pxvid); |
| 5718 | const int vm = vd - 1125; |
| 5719 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5720 | if (INTEL_INFO(dev)->is_mobile) |
Mika Kuoppala | d972d6e | 2014-12-01 18:01:05 +0200 | [diff] [blame] | 5721 | return vm > 0 ? vm : 0; |
| 5722 | |
| 5723 | return vd; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5724 | } |
| 5725 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5726 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5727 | { |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 5728 | u64 now, diff, diffms; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5729 | u32 count; |
| 5730 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5731 | assert_spin_locked(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5732 | |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 5733 | now = ktime_get_raw_ns(); |
| 5734 | diffms = now - dev_priv->ips.last_time2; |
| 5735 | do_div(diffms, NSEC_PER_MSEC); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5736 | |
| 5737 | /* Don't divide by 0 */ |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5738 | if (!diffms) |
| 5739 | return; |
| 5740 | |
| 5741 | count = I915_READ(GFXEC); |
| 5742 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5743 | if (count < dev_priv->ips.last_count2) { |
| 5744 | diff = ~0UL - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5745 | diff += count; |
| 5746 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5747 | diff = count - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5748 | } |
| 5749 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5750 | dev_priv->ips.last_count2 = count; |
| 5751 | dev_priv->ips.last_time2 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5752 | |
| 5753 | /* More magic constants... */ |
| 5754 | diff = diff * 1181; |
| 5755 | diff = div_u64(diff, diffms * 10); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5756 | dev_priv->ips.gfx_power = diff; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5757 | } |
| 5758 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5759 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
| 5760 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5761 | struct drm_device *dev = dev_priv->dev; |
| 5762 | |
| 5763 | if (INTEL_INFO(dev)->gen != 5) |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5764 | return; |
| 5765 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5766 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5767 | |
| 5768 | __i915_update_gfx_val(dev_priv); |
| 5769 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5770 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5771 | } |
| 5772 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5773 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5774 | { |
| 5775 | unsigned long t, corr, state1, corr2, state2; |
| 5776 | u32 pxvid, ext_v; |
| 5777 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5778 | assert_spin_locked(&mchdev_lock); |
| 5779 | |
Ville Syrjälä | 616847e | 2015-09-18 20:03:19 +0300 | [diff] [blame] | 5780 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5781 | pxvid = (pxvid >> 24) & 0x7f; |
| 5782 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
| 5783 | |
| 5784 | state1 = ext_v; |
| 5785 | |
| 5786 | t = i915_mch_val(dev_priv); |
| 5787 | |
| 5788 | /* Revel in the empirically derived constants */ |
| 5789 | |
| 5790 | /* Correction factor in 1/100000 units */ |
| 5791 | if (t > 80) |
| 5792 | corr = ((t * 2349) + 135940); |
| 5793 | else if (t >= 50) |
| 5794 | corr = ((t * 964) + 29317); |
| 5795 | else /* < 50 */ |
| 5796 | corr = ((t * 301) + 1004); |
| 5797 | |
| 5798 | corr = corr * ((150142 * state1) / 10000 - 78642); |
| 5799 | corr /= 100000; |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5800 | corr2 = (corr * dev_priv->ips.corr); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5801 | |
| 5802 | state2 = (corr2 * state1) / 10000; |
| 5803 | state2 /= 100; /* convert to mW */ |
| 5804 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5805 | __i915_update_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5806 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5807 | return dev_priv->ips.gfx_power + state2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5808 | } |
| 5809 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5810 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
| 5811 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5812 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5813 | unsigned long val; |
| 5814 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 5815 | if (INTEL_INFO(dev)->gen != 5) |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5816 | return 0; |
| 5817 | |
| 5818 | spin_lock_irq(&mchdev_lock); |
| 5819 | |
| 5820 | val = __i915_gfx_val(dev_priv); |
| 5821 | |
| 5822 | spin_unlock_irq(&mchdev_lock); |
| 5823 | |
| 5824 | return val; |
| 5825 | } |
| 5826 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5827 | /** |
| 5828 | * i915_read_mch_val - return value for IPS use |
| 5829 | * |
| 5830 | * Calculate and return a value for the IPS driver to use when deciding whether |
| 5831 | * we have thermal and power headroom to increase CPU or GPU power budget. |
| 5832 | */ |
| 5833 | unsigned long i915_read_mch_val(void) |
| 5834 | { |
| 5835 | struct drm_i915_private *dev_priv; |
| 5836 | unsigned long chipset_val, graphics_val, ret = 0; |
| 5837 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5838 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5839 | if (!i915_mch_dev) |
| 5840 | goto out_unlock; |
| 5841 | dev_priv = i915_mch_dev; |
| 5842 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 5843 | chipset_val = __i915_chipset_val(dev_priv); |
| 5844 | graphics_val = __i915_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5845 | |
| 5846 | ret = chipset_val + graphics_val; |
| 5847 | |
| 5848 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5849 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5850 | |
| 5851 | return ret; |
| 5852 | } |
| 5853 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
| 5854 | |
| 5855 | /** |
| 5856 | * i915_gpu_raise - raise GPU frequency limit |
| 5857 | * |
| 5858 | * Raise the limit; IPS indicates we have thermal headroom. |
| 5859 | */ |
| 5860 | bool i915_gpu_raise(void) |
| 5861 | { |
| 5862 | struct drm_i915_private *dev_priv; |
| 5863 | bool ret = true; |
| 5864 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5865 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5866 | if (!i915_mch_dev) { |
| 5867 | ret = false; |
| 5868 | goto out_unlock; |
| 5869 | } |
| 5870 | dev_priv = i915_mch_dev; |
| 5871 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5872 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
| 5873 | dev_priv->ips.max_delay--; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5874 | |
| 5875 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5876 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5877 | |
| 5878 | return ret; |
| 5879 | } |
| 5880 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
| 5881 | |
| 5882 | /** |
| 5883 | * i915_gpu_lower - lower GPU frequency limit |
| 5884 | * |
| 5885 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
| 5886 | * frequency maximum. |
| 5887 | */ |
| 5888 | bool i915_gpu_lower(void) |
| 5889 | { |
| 5890 | struct drm_i915_private *dev_priv; |
| 5891 | bool ret = true; |
| 5892 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5893 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5894 | if (!i915_mch_dev) { |
| 5895 | ret = false; |
| 5896 | goto out_unlock; |
| 5897 | } |
| 5898 | dev_priv = i915_mch_dev; |
| 5899 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5900 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
| 5901 | dev_priv->ips.max_delay++; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5902 | |
| 5903 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5904 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5905 | |
| 5906 | return ret; |
| 5907 | } |
| 5908 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
| 5909 | |
| 5910 | /** |
| 5911 | * i915_gpu_busy - indicate GPU business to IPS |
| 5912 | * |
| 5913 | * Tell the IPS driver whether or not the GPU is busy. |
| 5914 | */ |
| 5915 | bool i915_gpu_busy(void) |
| 5916 | { |
| 5917 | struct drm_i915_private *dev_priv; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 5918 | struct intel_engine_cs *ring; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5919 | bool ret = false; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 5920 | int i; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5921 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5922 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5923 | if (!i915_mch_dev) |
| 5924 | goto out_unlock; |
| 5925 | dev_priv = i915_mch_dev; |
| 5926 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 5927 | for_each_ring(ring, dev_priv, i) |
| 5928 | ret |= !list_empty(&ring->request_list); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5929 | |
| 5930 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5931 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5932 | |
| 5933 | return ret; |
| 5934 | } |
| 5935 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
| 5936 | |
| 5937 | /** |
| 5938 | * i915_gpu_turbo_disable - disable graphics turbo |
| 5939 | * |
| 5940 | * Disable graphics turbo by resetting the max frequency and setting the |
| 5941 | * current frequency to the default. |
| 5942 | */ |
| 5943 | bool i915_gpu_turbo_disable(void) |
| 5944 | { |
| 5945 | struct drm_i915_private *dev_priv; |
| 5946 | bool ret = true; |
| 5947 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5948 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5949 | if (!i915_mch_dev) { |
| 5950 | ret = false; |
| 5951 | goto out_unlock; |
| 5952 | } |
| 5953 | dev_priv = i915_mch_dev; |
| 5954 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5955 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5956 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5957 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5958 | ret = false; |
| 5959 | |
| 5960 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5961 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5962 | |
| 5963 | return ret; |
| 5964 | } |
| 5965 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
| 5966 | |
| 5967 | /** |
| 5968 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
| 5969 | * IPS got loaded first. |
| 5970 | * |
| 5971 | * This awkward dance is so that neither module has to depend on the |
| 5972 | * other in order for IPS to do the appropriate communication of |
| 5973 | * GPU turbo limits to i915. |
| 5974 | */ |
| 5975 | static void |
| 5976 | ips_ping_for_i915_load(void) |
| 5977 | { |
| 5978 | void (*link)(void); |
| 5979 | |
| 5980 | link = symbol_get(ips_link_to_i915_driver); |
| 5981 | if (link) { |
| 5982 | link(); |
| 5983 | symbol_put(ips_link_to_i915_driver); |
| 5984 | } |
| 5985 | } |
| 5986 | |
| 5987 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
| 5988 | { |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 5989 | /* We only register the i915 ips part with intel-ips once everything is |
| 5990 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5991 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5992 | i915_mch_dev = dev_priv; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 5993 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 5994 | |
| 5995 | ips_ping_for_i915_load(); |
| 5996 | } |
| 5997 | |
| 5998 | void intel_gpu_ips_teardown(void) |
| 5999 | { |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 6000 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 6001 | i915_mch_dev = NULL; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 6002 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 6003 | } |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 6004 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6005 | static void intel_init_emon(struct drm_device *dev) |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 6006 | { |
| 6007 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6008 | u32 lcfuse; |
| 6009 | u8 pxw[16]; |
| 6010 | int i; |
| 6011 | |
| 6012 | /* Disable to program */ |
| 6013 | I915_WRITE(ECR, 0); |
| 6014 | POSTING_READ(ECR); |
| 6015 | |
| 6016 | /* Program energy weights for various events */ |
| 6017 | I915_WRITE(SDEW, 0x15040d00); |
| 6018 | I915_WRITE(CSIEW0, 0x007f0000); |
| 6019 | I915_WRITE(CSIEW1, 0x1e220004); |
| 6020 | I915_WRITE(CSIEW2, 0x04000004); |
| 6021 | |
| 6022 | for (i = 0; i < 5; i++) |
Ville Syrjälä | 616847e | 2015-09-18 20:03:19 +0300 | [diff] [blame] | 6023 | I915_WRITE(PEW(i), 0); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 6024 | for (i = 0; i < 3; i++) |
Ville Syrjälä | 616847e | 2015-09-18 20:03:19 +0300 | [diff] [blame] | 6025 | I915_WRITE(DEW(i), 0); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 6026 | |
| 6027 | /* Program P-state weights to account for frequency power adjustment */ |
| 6028 | for (i = 0; i < 16; i++) { |
Ville Syrjälä | 616847e | 2015-09-18 20:03:19 +0300 | [diff] [blame] | 6029 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 6030 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 6031 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 6032 | PXVFREQ_PX_SHIFT; |
| 6033 | unsigned long val; |
| 6034 | |
| 6035 | val = vid * vid; |
| 6036 | val *= (freq / 1000); |
| 6037 | val *= 255; |
| 6038 | val /= (127*127*900); |
| 6039 | if (val > 0xff) |
| 6040 | DRM_ERROR("bad pxval: %ld\n", val); |
| 6041 | pxw[i] = val; |
| 6042 | } |
| 6043 | /* Render standby states get 0 weight */ |
| 6044 | pxw[14] = 0; |
| 6045 | pxw[15] = 0; |
| 6046 | |
| 6047 | for (i = 0; i < 4; i++) { |
| 6048 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 6049 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
Ville Syrjälä | 616847e | 2015-09-18 20:03:19 +0300 | [diff] [blame] | 6050 | I915_WRITE(PXW(i), val); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 6051 | } |
| 6052 | |
| 6053 | /* Adjust magic regs to magic values (more experimental results) */ |
| 6054 | I915_WRITE(OGW0, 0); |
| 6055 | I915_WRITE(OGW1, 0); |
| 6056 | I915_WRITE(EG0, 0x00007f00); |
| 6057 | I915_WRITE(EG1, 0x0000000e); |
| 6058 | I915_WRITE(EG2, 0x000e0000); |
| 6059 | I915_WRITE(EG3, 0x68000300); |
| 6060 | I915_WRITE(EG4, 0x42000000); |
| 6061 | I915_WRITE(EG5, 0x00140031); |
| 6062 | I915_WRITE(EG6, 0); |
| 6063 | I915_WRITE(EG7, 0); |
| 6064 | |
| 6065 | for (i = 0; i < 8; i++) |
Ville Syrjälä | 616847e | 2015-09-18 20:03:19 +0300 | [diff] [blame] | 6066 | I915_WRITE(PXWL(i), 0); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 6067 | |
| 6068 | /* Enable PMON + select events */ |
| 6069 | I915_WRITE(ECR, 0x80000019); |
| 6070 | |
| 6071 | lcfuse = I915_READ(LCFUSE02); |
| 6072 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 6073 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 6074 | } |
| 6075 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 6076 | void intel_init_gt_powersave(struct drm_device *dev) |
| 6077 | { |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 6078 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
| 6079 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 6080 | if (IS_CHERRYVIEW(dev)) |
| 6081 | cherryview_init_gt_powersave(dev); |
| 6082 | else if (IS_VALLEYVIEW(dev)) |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 6083 | valleyview_init_gt_powersave(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 6084 | } |
| 6085 | |
| 6086 | void intel_cleanup_gt_powersave(struct drm_device *dev) |
| 6087 | { |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 6088 | if (IS_CHERRYVIEW(dev)) |
| 6089 | return; |
| 6090 | else if (IS_VALLEYVIEW(dev)) |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 6091 | valleyview_cleanup_gt_powersave(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 6092 | } |
| 6093 | |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 6094 | static void gen6_suspend_rps(struct drm_device *dev) |
| 6095 | { |
| 6096 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6097 | |
| 6098 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 6099 | |
Akash Goel | 4c2a889 | 2015-03-06 11:07:24 +0530 | [diff] [blame] | 6100 | gen6_disable_rps_interrupts(dev); |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 6101 | } |
| 6102 | |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 6103 | /** |
| 6104 | * intel_suspend_gt_powersave - suspend PM work and helper threads |
| 6105 | * @dev: drm device |
| 6106 | * |
| 6107 | * We don't want to disable RC6 or other features here, we just want |
| 6108 | * to make sure any work we've queued has finished and won't bother |
| 6109 | * us while we're suspended. |
| 6110 | */ |
| 6111 | void intel_suspend_gt_powersave(struct drm_device *dev) |
| 6112 | { |
| 6113 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6114 | |
Imre Deak | d4d70aa | 2014-11-19 15:30:04 +0200 | [diff] [blame] | 6115 | if (INTEL_INFO(dev)->gen < 6) |
| 6116 | return; |
| 6117 | |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 6118 | gen6_suspend_rps(dev); |
Deepak S | b47adc1 | 2014-06-20 20:03:02 +0530 | [diff] [blame] | 6119 | |
| 6120 | /* Force GPU to min freq during suspend */ |
| 6121 | gen6_rps_idle(dev_priv); |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 6122 | } |
| 6123 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6124 | void intel_disable_gt_powersave(struct drm_device *dev) |
| 6125 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 6126 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6127 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 6128 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6129 | ironlake_disable_drps(dev); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 6130 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 10d8d36 | 2014-06-12 17:48:52 +0200 | [diff] [blame] | 6131 | intel_suspend_gt_powersave(dev); |
Imre Deak | e494837 | 2014-05-12 18:35:04 +0300 | [diff] [blame] | 6132 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 6133 | mutex_lock(&dev_priv->rps.hw_lock); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 6134 | if (INTEL_INFO(dev)->gen >= 9) |
| 6135 | gen9_disable_rps(dev); |
| 6136 | else if (IS_CHERRYVIEW(dev)) |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 6137 | cherryview_disable_rps(dev); |
| 6138 | else if (IS_VALLEYVIEW(dev)) |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 6139 | valleyview_disable_rps(dev); |
| 6140 | else |
| 6141 | gen6_disable_rps(dev); |
Imre Deak | e534770 | 2014-11-19 15:30:02 +0200 | [diff] [blame] | 6142 | |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 6143 | dev_priv->rps.enabled = false; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 6144 | mutex_unlock(&dev_priv->rps.hw_lock); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 6145 | } |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6146 | } |
| 6147 | |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 6148 | static void intel_gen6_powersave_work(struct work_struct *work) |
| 6149 | { |
| 6150 | struct drm_i915_private *dev_priv = |
| 6151 | container_of(work, struct drm_i915_private, |
| 6152 | rps.delayed_resume_work.work); |
| 6153 | struct drm_device *dev = dev_priv->dev; |
| 6154 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 6155 | mutex_lock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 6156 | |
Akash Goel | 4c2a889 | 2015-03-06 11:07:24 +0530 | [diff] [blame] | 6157 | gen6_reset_rps_interrupts(dev); |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 6158 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 6159 | if (IS_CHERRYVIEW(dev)) { |
| 6160 | cherryview_enable_rps(dev); |
| 6161 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 6162 | valleyview_enable_rps(dev); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 6163 | } else if (INTEL_INFO(dev)->gen >= 9) { |
Jesse Barnes | b6fef0e | 2015-01-16 18:07:25 +0000 | [diff] [blame] | 6164 | gen9_enable_rc6(dev); |
Zhe Wang | 20e4936 | 2014-11-04 17:07:05 +0000 | [diff] [blame] | 6165 | gen9_enable_rps(dev); |
Akash Goel | cc017fb | 2015-06-29 14:50:21 +0530 | [diff] [blame] | 6166 | if (IS_SKYLAKE(dev)) |
| 6167 | __gen6_update_ring_freq(dev); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 6168 | } else if (IS_BROADWELL(dev)) { |
| 6169 | gen8_enable_rps(dev); |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 6170 | __gen6_update_ring_freq(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 6171 | } else { |
| 6172 | gen6_enable_rps(dev); |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 6173 | __gen6_update_ring_freq(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 6174 | } |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 6175 | |
| 6176 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); |
| 6177 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); |
| 6178 | |
| 6179 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); |
| 6180 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); |
| 6181 | |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 6182 | dev_priv->rps.enabled = true; |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 6183 | |
Akash Goel | 4c2a889 | 2015-03-06 11:07:24 +0530 | [diff] [blame] | 6184 | gen6_enable_rps_interrupts(dev); |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame] | 6185 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 6186 | mutex_unlock(&dev_priv->rps.hw_lock); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 6187 | |
| 6188 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 6189 | } |
| 6190 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6191 | void intel_enable_gt_powersave(struct drm_device *dev) |
| 6192 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 6193 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6194 | |
Yu Zhang | f61018b | 2015-02-10 19:05:52 +0800 | [diff] [blame] | 6195 | /* Powersaving is controlled by the host when inside a VM */ |
| 6196 | if (intel_vgpu_active(dev)) |
| 6197 | return; |
| 6198 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6199 | if (IS_IRONLAKE_M(dev)) { |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 6200 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6201 | ironlake_enable_drps(dev); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6202 | intel_init_emon(dev); |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 6203 | mutex_unlock(&dev->struct_mutex); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 6204 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 6205 | /* |
| 6206 | * PCU communication is slow and this doesn't need to be |
| 6207 | * done at any specific time, so do this out of our fast path |
| 6208 | * to make resume and init faster. |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 6209 | * |
| 6210 | * We depend on the HW RC6 power context save/restore |
| 6211 | * mechanism when entering D3 through runtime PM suspend. So |
| 6212 | * disable RPM until RPS/RC6 is properly setup. We can only |
| 6213 | * get here via the driver load/system resume/runtime resume |
| 6214 | * paths, so the _noresume version is enough (and in case of |
| 6215 | * runtime resume it's necessary). |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 6216 | */ |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 6217 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
| 6218 | round_jiffies_up_relative(HZ))) |
| 6219 | intel_runtime_pm_get_noresume(dev_priv); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 6220 | } |
| 6221 | } |
| 6222 | |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 6223 | void intel_reset_gt_powersave(struct drm_device *dev) |
| 6224 | { |
| 6225 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6226 | |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 6227 | if (INTEL_INFO(dev)->gen < 6) |
| 6228 | return; |
| 6229 | |
| 6230 | gen6_suspend_rps(dev); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 6231 | dev_priv->rps.enabled = false; |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 6232 | } |
| 6233 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6234 | static void ibx_init_clock_gating(struct drm_device *dev) |
| 6235 | { |
| 6236 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6237 | |
| 6238 | /* |
| 6239 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 6240 | * gating for the panel power sequencer or it will fail to |
| 6241 | * start up when no ports are active. |
| 6242 | */ |
| 6243 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 6244 | } |
| 6245 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6246 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
| 6247 | { |
| 6248 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | b12ce1d | 2015-05-26 20:27:23 +0300 | [diff] [blame] | 6249 | enum pipe pipe; |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6250 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 6251 | for_each_pipe(dev_priv, pipe) { |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6252 | I915_WRITE(DSPCNTR(pipe), |
| 6253 | I915_READ(DSPCNTR(pipe)) | |
| 6254 | DISPPLANE_TRICKLE_FEED_DISABLE); |
Ville Syrjälä | b12ce1d | 2015-05-26 20:27:23 +0300 | [diff] [blame] | 6255 | |
| 6256 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); |
| 6257 | POSTING_READ(DSPSURF(pipe)); |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6258 | } |
| 6259 | } |
| 6260 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 6261 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
| 6262 | { |
| 6263 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6264 | |
| 6265 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
| 6266 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); |
| 6267 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); |
| 6268 | |
| 6269 | /* |
| 6270 | * Don't touch WM1S_LP_EN here. |
| 6271 | * Doing so could cause underruns. |
| 6272 | */ |
| 6273 | } |
| 6274 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6275 | static void ironlake_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6276 | { |
| 6277 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 6278 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6279 | |
Damien Lespiau | f1e8fa5 | 2013-06-07 17:41:09 +0100 | [diff] [blame] | 6280 | /* |
| 6281 | * Required for FBC |
| 6282 | * WaFbcDisableDpfcClockGating:ilk |
| 6283 | */ |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 6284 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
| 6285 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
| 6286 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6287 | |
| 6288 | I915_WRITE(PCH_3DCGDIS0, |
| 6289 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 6290 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 6291 | I915_WRITE(PCH_3DCGDIS1, |
| 6292 | VFMUNIT_CLOCK_GATE_DISABLE); |
| 6293 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6294 | /* |
| 6295 | * According to the spec the following bits should be set in |
| 6296 | * order to enable memory self-refresh |
| 6297 | * The bit 22/21 of 0x42004 |
| 6298 | * The bit 5 of 0x42020 |
| 6299 | * The bit 15 of 0x45000 |
| 6300 | */ |
| 6301 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 6302 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 6303 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 6304 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6305 | I915_WRITE(DISP_ARB_CTL, |
| 6306 | (I915_READ(DISP_ARB_CTL) | |
| 6307 | DISP_FBC_WM_DIS)); |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 6308 | |
| 6309 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6310 | |
| 6311 | /* |
| 6312 | * Based on the document from hardware guys the following bits |
| 6313 | * should be set unconditionally in order to enable FBC. |
| 6314 | * The bit 22 of 0x42000 |
| 6315 | * The bit 22 of 0x42004 |
| 6316 | * The bit 7,8,9 of 0x42020. |
| 6317 | */ |
| 6318 | if (IS_IRONLAKE_M(dev)) { |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 6319 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6320 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 6321 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 6322 | ILK_FBCQ_DIS); |
| 6323 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 6324 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 6325 | ILK_DPARB_GATE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6326 | } |
| 6327 | |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 6328 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
| 6329 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6330 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 6331 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 6332 | ILK_ELPIN_409_SELECT); |
| 6333 | I915_WRITE(_3D_CHICKEN2, |
| 6334 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
| 6335 | _3D_CHICKEN2_WM_READ_PIPELINED); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 6336 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6337 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 6338 | I915_WRITE(CACHE_MODE_0, |
| 6339 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6340 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6341 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
| 6342 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6343 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6344 | g4x_disable_trickle_feed(dev); |
Ville Syrjälä | bdad2b2 | 2013-06-07 10:47:03 +0300 | [diff] [blame] | 6345 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6346 | ibx_init_clock_gating(dev); |
| 6347 | } |
| 6348 | |
| 6349 | static void cpt_init_clock_gating(struct drm_device *dev) |
| 6350 | { |
| 6351 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6352 | int pipe; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 6353 | uint32_t val; |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6354 | |
| 6355 | /* |
| 6356 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 6357 | * gating for the panel power sequencer or it will fail to |
| 6358 | * start up when no ports are active. |
| 6359 | */ |
Jesse Barnes | cd66407 | 2013-10-02 10:34:19 -0700 | [diff] [blame] | 6360 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
| 6361 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | |
| 6362 | PCH_CPUNIT_CLOCK_GATE_DISABLE); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6363 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
| 6364 | DPLS_EDP_PPS_FIX_DIS); |
Takashi Iwai | 335c07b | 2012-12-11 11:46:29 +0100 | [diff] [blame] | 6365 | /* The below fixes the weird display corruption, a few pixels shifted |
| 6366 | * downward, on (only) LVDS of some HP laptops with IVY. |
| 6367 | */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 6368 | for_each_pipe(dev_priv, pipe) { |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 6369 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
| 6370 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 6371 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 6372 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 6373 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 6374 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
| 6375 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; |
| 6376 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 6377 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
| 6378 | } |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6379 | /* WADP0ClockGatingDisable */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 6380 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6381 | I915_WRITE(TRANS_CHICKEN1(pipe), |
| 6382 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
| 6383 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6384 | } |
| 6385 | |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 6386 | static void gen6_check_mch_setup(struct drm_device *dev) |
| 6387 | { |
| 6388 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6389 | uint32_t tmp; |
| 6390 | |
| 6391 | tmp = I915_READ(MCH_SSKPD); |
Daniel Vetter | df662a2 | 2014-08-04 11:17:25 +0200 | [diff] [blame] | 6392 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
| 6393 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", |
| 6394 | tmp); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 6395 | } |
| 6396 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6397 | static void gen6_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6398 | { |
| 6399 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 6400 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6401 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 6402 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6403 | |
| 6404 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 6405 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 6406 | ILK_ELPIN_409_SELECT); |
| 6407 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6408 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
Daniel Vetter | 4283908 | 2012-12-14 23:38:28 +0100 | [diff] [blame] | 6409 | I915_WRITE(_3D_CHICKEN, |
| 6410 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
| 6411 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6412 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
| 6413 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6414 | |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 6415 | /* |
| 6416 | * BSpec recoomends 8x4 when MSAA is used, |
| 6417 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 6418 | * |
| 6419 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 6420 | * disable bit, which we don't touch here, but it's good |
| 6421 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 6422 | */ |
| 6423 | I915_WRITE(GEN6_GT_MODE, |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 6424 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 6425 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 6426 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6427 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6428 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 6429 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6430 | |
| 6431 | I915_WRITE(GEN6_UCGCTL1, |
| 6432 | I915_READ(GEN6_UCGCTL1) | |
| 6433 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
| 6434 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
| 6435 | |
| 6436 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 6437 | * gating disable must be set. Failure to set it results in |
| 6438 | * flickering pixels due to Z write ordering failures after |
| 6439 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 6440 | * Sanctuary and Tropics, and apparently anything else with |
| 6441 | * alpha test or pixel discard. |
| 6442 | * |
| 6443 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 6444 | * but we didn't debug actual testcases to find it out. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6445 | * |
Ville Syrjälä | ef59318 | 2014-01-22 21:32:47 +0200 | [diff] [blame] | 6446 | * WaDisableRCCUnitClockGating:snb |
| 6447 | * WaDisableRCPBUnitClockGating:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6448 | */ |
| 6449 | I915_WRITE(GEN6_UCGCTL2, |
| 6450 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 6451 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 6452 | |
Ville Syrjälä | 5eb146d | 2014-02-04 21:59:16 +0200 | [diff] [blame] | 6453 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
Ville Syrjälä | 743b57d | 2014-02-04 21:59:17 +0200 | [diff] [blame] | 6454 | I915_WRITE(_3D_CHICKEN3, |
| 6455 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6456 | |
| 6457 | /* |
Ville Syrjälä | e927ecd | 2014-02-04 21:59:18 +0200 | [diff] [blame] | 6458 | * Bspec says: |
| 6459 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and |
| 6460 | * 3DSTATE_SF number of SF output attributes is more than 16." |
| 6461 | */ |
| 6462 | I915_WRITE(_3D_CHICKEN3, |
| 6463 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); |
| 6464 | |
| 6465 | /* |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6466 | * According to the spec the following bits should be |
| 6467 | * set in order to enable memory self-refresh and fbc: |
| 6468 | * The bit21 and bit22 of 0x42000 |
| 6469 | * The bit21 and bit22 of 0x42004 |
| 6470 | * The bit5 and bit7 of 0x42020 |
| 6471 | * The bit14 of 0x70180 |
| 6472 | * The bit14 of 0x71180 |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 6473 | * |
| 6474 | * WaFbcAsynchFlipDisableFbcQueue:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6475 | */ |
| 6476 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 6477 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 6478 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
| 6479 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 6480 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 6481 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 6482 | I915_WRITE(ILK_DSPCLK_GATE_D, |
| 6483 | I915_READ(ILK_DSPCLK_GATE_D) | |
| 6484 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
| 6485 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6486 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6487 | g4x_disable_trickle_feed(dev); |
Ben Widawsky | f8f2ac9 | 2012-10-03 19:34:24 -0700 | [diff] [blame] | 6488 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6489 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 6490 | |
| 6491 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6492 | } |
| 6493 | |
| 6494 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
| 6495 | { |
| 6496 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
| 6497 | |
Ville Syrjälä | 3aad905 | 2014-01-22 21:32:59 +0200 | [diff] [blame] | 6498 | /* |
Ville Syrjälä | 46680e0 | 2014-01-22 21:33:01 +0200 | [diff] [blame] | 6499 | * WaVSThreadDispatchOverride:ivb,vlv |
Ville Syrjälä | 3aad905 | 2014-01-22 21:32:59 +0200 | [diff] [blame] | 6500 | * |
| 6501 | * This actually overrides the dispatch |
| 6502 | * mode for all thread types. |
| 6503 | */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6504 | reg &= ~GEN7_FF_SCHED_MASK; |
| 6505 | reg |= GEN7_FF_TS_SCHED_HW; |
| 6506 | reg |= GEN7_FF_VS_SCHED_HW; |
| 6507 | reg |= GEN7_FF_DS_SCHED_HW; |
| 6508 | |
| 6509 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
| 6510 | } |
| 6511 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 6512 | static void lpt_init_clock_gating(struct drm_device *dev) |
| 6513 | { |
| 6514 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6515 | |
| 6516 | /* |
| 6517 | * TODO: this bit should only be enabled when really needed, then |
| 6518 | * disabled when not needed anymore in order to save power. |
| 6519 | */ |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 6520 | if (HAS_PCH_LPT_LP(dev)) |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 6521 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
| 6522 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
| 6523 | PCH_LP_PARTITION_LEVEL_DISABLE); |
Paulo Zanoni | 0a790cd | 2013-04-17 18:15:49 -0300 | [diff] [blame] | 6524 | |
| 6525 | /* WADPOClockGatingDisable:hsw */ |
Ville Syrjälä | 36c0d0c | 2015-09-18 20:03:31 +0300 | [diff] [blame] | 6526 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
| 6527 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | |
Paulo Zanoni | 0a790cd | 2013-04-17 18:15:49 -0300 | [diff] [blame] | 6528 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 6529 | } |
| 6530 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 6531 | static void lpt_suspend_hw(struct drm_device *dev) |
| 6532 | { |
| 6533 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6534 | |
Ville Syrjälä | c269952 | 2015-08-27 23:55:59 +0300 | [diff] [blame] | 6535 | if (HAS_PCH_LPT_LP(dev)) { |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 6536 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 6537 | |
| 6538 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 6539 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 6540 | } |
| 6541 | } |
| 6542 | |
Paulo Zanoni | 47c2bd9 | 2014-08-21 17:09:37 -0300 | [diff] [blame] | 6543 | static void broadwell_init_clock_gating(struct drm_device *dev) |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 6544 | { |
| 6545 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 6546 | enum pipe pipe; |
Ville Syrjälä | 4d487cf | 2015-05-19 20:32:56 +0300 | [diff] [blame] | 6547 | uint32_t misccpctl; |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 6548 | |
Ville Syrjälä | 7ad0dba | 2015-05-19 20:32:55 +0300 | [diff] [blame] | 6549 | ilk_init_lp_watermarks(dev); |
Ben Widawsky | 50ed5fb | 2013-11-02 21:07:40 -0700 | [diff] [blame] | 6550 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 6551 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
Ben Widawsky | 50ed5fb | 2013-11-02 21:07:40 -0700 | [diff] [blame] | 6552 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 6553 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 6554 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 6555 | I915_WRITE(CHICKEN_PAR1_1, |
| 6556 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); |
| 6557 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 6558 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 6559 | for_each_pipe(dev_priv, pipe) { |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 6560 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
Ville Syrjälä | c7c6562 | 2014-03-05 13:05:45 +0200 | [diff] [blame] | 6561 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
Ville Syrjälä | 8f670bb | 2014-03-05 13:05:47 +0200 | [diff] [blame] | 6562 | BDW_DPRS_MASK_VBLANK_SRD); |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 6563 | } |
Ben Widawsky | 63801f2 | 2013-12-12 17:26:03 -0800 | [diff] [blame] | 6564 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 6565 | /* WaVSRefCountFullforceMissDisable:bdw */ |
| 6566 | /* WaDSRefCountFullforceMissDisable:bdw */ |
| 6567 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 6568 | I915_READ(GEN7_FF_THREAD_MODE) & |
| 6569 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
Ville Syrjälä | 36075a4 | 2014-02-04 21:59:21 +0200 | [diff] [blame] | 6570 | |
Ville Syrjälä | 295e8bb | 2014-02-27 21:59:01 +0200 | [diff] [blame] | 6571 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
| 6572 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
Ville Syrjälä | 4f1ca9e | 2014-02-27 21:59:02 +0200 | [diff] [blame] | 6573 | |
| 6574 | /* WaDisableSDEUnitClockGating:bdw */ |
| 6575 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 6576 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
Damien Lespiau | 5d70868 | 2014-03-26 18:41:51 +0000 | [diff] [blame] | 6577 | |
Ville Syrjälä | 4d487cf | 2015-05-19 20:32:56 +0300 | [diff] [blame] | 6578 | /* |
| 6579 | * WaProgramL3SqcReg1Default:bdw |
| 6580 | * WaTempDisableDOPClkGating:bdw |
| 6581 | */ |
| 6582 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 6583 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 6584 | I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); |
| 6585 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 6586 | |
Ville Syrjälä | 6d50b06 | 2015-05-19 20:32:57 +0300 | [diff] [blame] | 6587 | /* |
| 6588 | * WaGttCachingOffByDefault:bdw |
| 6589 | * GTT cache may not work with big pages, so if those |
| 6590 | * are ever enabled GTT cache may need to be disabled. |
| 6591 | */ |
| 6592 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); |
| 6593 | |
Paulo Zanoni | 89d6b2b | 2014-08-21 17:09:36 -0300 | [diff] [blame] | 6594 | lpt_init_clock_gating(dev); |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 6595 | } |
| 6596 | |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6597 | static void haswell_init_clock_gating(struct drm_device *dev) |
| 6598 | { |
| 6599 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6600 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 6601 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6602 | |
Francisco Jerez | f3fc488 | 2013-10-02 15:53:16 -0700 | [diff] [blame] | 6603 | /* L3 caching of data atomics doesn't work -- disable it. */ |
| 6604 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); |
| 6605 | I915_WRITE(HSW_ROW_CHICKEN3, |
| 6606 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); |
| 6607 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6608 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6609 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 6610 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 6611 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 6612 | |
Ville Syrjälä | e36ea7f | 2014-01-22 21:33:00 +0200 | [diff] [blame] | 6613 | /* WaVSRefCountFullforceMissDisable:hsw */ |
| 6614 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 6615 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6616 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6617 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
| 6618 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6619 | |
Chia-I Wu | fe27c60 | 2014-01-28 13:29:33 +0800 | [diff] [blame] | 6620 | /* enable HiZ Raw Stall Optimization */ |
| 6621 | I915_WRITE(CACHE_MODE_0_GEN7, |
| 6622 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
| 6623 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6624 | /* WaDisable4x2SubspanOptimization:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6625 | I915_WRITE(CACHE_MODE_1, |
| 6626 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 6627 | |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 6628 | /* |
| 6629 | * BSpec recommends 8x4 when MSAA is used, |
| 6630 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 6631 | * |
| 6632 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 6633 | * disable bit, which we don't touch here, but it's good |
| 6634 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 6635 | */ |
| 6636 | I915_WRITE(GEN7_GT_MODE, |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 6637 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 6638 | |
Kenneth Graunke | 9441159 | 2014-12-31 16:23:00 -0800 | [diff] [blame] | 6639 | /* WaSampleCChickenBitEnable:hsw */ |
| 6640 | I915_WRITE(HALF_SLICE_CHICKEN3, |
| 6641 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); |
| 6642 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6643 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
Ben Widawsky | e3dff58 | 2013-03-20 14:49:14 -0700 | [diff] [blame] | 6644 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
| 6645 | |
Paulo Zanoni | 90a8864 | 2013-05-03 17:23:45 -0300 | [diff] [blame] | 6646 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
| 6647 | I915_WRITE(CHICKEN_PAR1_1, |
| 6648 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 6649 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 6650 | lpt_init_clock_gating(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6651 | } |
| 6652 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6653 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6654 | { |
| 6655 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 6656 | uint32_t snpcr; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6657 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 6658 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6659 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 6660 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6661 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6662 | /* WaDisableEarlyCull:ivb */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 6663 | I915_WRITE(_3D_CHICKEN3, |
| 6664 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 6665 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6666 | /* WaDisableBackToBackFlipFix:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6667 | I915_WRITE(IVB_CHICKEN3, |
| 6668 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 6669 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 6670 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6671 | /* WaDisablePSDDualDispatchEnable:ivb */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 6672 | if (IS_IVB_GT1(dev)) |
| 6673 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
| 6674 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 6675 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6676 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
| 6677 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6678 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6679 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6680 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 6681 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 6682 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6683 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6684 | I915_WRITE(GEN7_L3CNTLREG1, |
| 6685 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 6686 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 6687 | GEN7_WA_L3_CHICKEN_MODE); |
| 6688 | if (IS_IVB_GT1(dev)) |
| 6689 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 6690 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Ville Syrjälä | 412236c | 2014-01-22 21:32:44 +0200 | [diff] [blame] | 6691 | else { |
| 6692 | /* must write both registers */ |
| 6693 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 6694 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 6695 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
| 6696 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Ville Syrjälä | 412236c | 2014-01-22 21:32:44 +0200 | [diff] [blame] | 6697 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6698 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6699 | /* WaForceL3Serialization:ivb */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 6700 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 6701 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 6702 | |
Ville Syrjälä | 1b80a19a | 2014-01-22 21:32:53 +0200 | [diff] [blame] | 6703 | /* |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6704 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6705 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6706 | */ |
| 6707 | I915_WRITE(GEN6_UCGCTL2, |
Ville Syrjälä | 28acf3b | 2014-01-22 21:32:48 +0200 | [diff] [blame] | 6708 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6709 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6710 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6711 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 6712 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 6713 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 6714 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6715 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6716 | |
| 6717 | gen7_setup_fixed_func_scheduler(dev_priv); |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 6718 | |
Chris Wilson | 2272134 | 2014-03-04 09:41:43 +0000 | [diff] [blame] | 6719 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
| 6720 | /* enable HiZ Raw Stall Optimization */ |
| 6721 | I915_WRITE(CACHE_MODE_0_GEN7, |
| 6722 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
| 6723 | } |
Chia-I Wu | 116f2b6 | 2014-01-28 13:29:34 +0800 | [diff] [blame] | 6724 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6725 | /* WaDisable4x2SubspanOptimization:ivb */ |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 6726 | I915_WRITE(CACHE_MODE_1, |
| 6727 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 6728 | |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 6729 | /* |
| 6730 | * BSpec recommends 8x4 when MSAA is used, |
| 6731 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 6732 | * |
| 6733 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 6734 | * disable bit, which we don't touch here, but it's good |
| 6735 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 6736 | */ |
| 6737 | I915_WRITE(GEN7_GT_MODE, |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 6738 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 6739 | |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 6740 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 6741 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 6742 | snpcr |= GEN6_MBC_SNPCR_MED; |
| 6743 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 6744 | |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 6745 | if (!HAS_PCH_NOP(dev)) |
| 6746 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 6747 | |
| 6748 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6749 | } |
| 6750 | |
Ville Syrjälä | c6beb13 | 2015-03-05 21:19:48 +0200 | [diff] [blame] | 6751 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
| 6752 | { |
| 6753 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
| 6754 | |
| 6755 | /* |
| 6756 | * Disable trickle feed and enable pnd deadline calculation |
| 6757 | */ |
| 6758 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
| 6759 | I915_WRITE(CBR1_VLV, 0); |
| 6760 | } |
| 6761 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6762 | static void valleyview_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6763 | { |
| 6764 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6765 | |
Ville Syrjälä | c6beb13 | 2015-03-05 21:19:48 +0200 | [diff] [blame] | 6766 | vlv_init_display_clock_gating(dev_priv); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6767 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6768 | /* WaDisableEarlyCull:vlv */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 6769 | I915_WRITE(_3D_CHICKEN3, |
| 6770 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 6771 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6772 | /* WaDisableBackToBackFlipFix:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6773 | I915_WRITE(IVB_CHICKEN3, |
| 6774 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 6775 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 6776 | |
Ville Syrjälä | fad7d36 | 2014-01-22 21:32:39 +0200 | [diff] [blame] | 6777 | /* WaPsdDispatchEnable:vlv */ |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6778 | /* WaDisablePSDDualDispatchEnable:vlv */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 6779 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
Jesse Barnes | d3bc030 | 2013-03-08 10:45:51 -0800 | [diff] [blame] | 6780 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
| 6781 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 6782 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6783 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
| 6784 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6785 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6786 | /* WaForceL3Serialization:vlv */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 6787 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 6788 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 6789 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6790 | /* WaDisableDopClockGating:vlv */ |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 6791 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 6792 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 6793 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6794 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6795 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 6796 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 6797 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 6798 | |
Ville Syrjälä | 46680e0 | 2014-01-22 21:33:01 +0200 | [diff] [blame] | 6799 | gen7_setup_fixed_func_scheduler(dev_priv); |
| 6800 | |
Ville Syrjälä | 3c0edae | 2014-01-22 21:32:56 +0200 | [diff] [blame] | 6801 | /* |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6802 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6803 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6804 | */ |
| 6805 | I915_WRITE(GEN6_UCGCTL2, |
Ville Syrjälä | 3c0edae | 2014-01-22 21:32:56 +0200 | [diff] [blame] | 6806 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 6807 | |
Akash Goel | c98f506 | 2014-03-24 23:00:07 +0530 | [diff] [blame] | 6808 | /* WaDisableL3Bank2xClockGate:vlv |
| 6809 | * Disabling L3 clock gating- MMIO 940c[25] = 1 |
| 6810 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ |
| 6811 | I915_WRITE(GEN7_UCGCTL4, |
| 6812 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
Jesse Barnes | e3f33d4 | 2012-06-14 11:04:50 -0700 | [diff] [blame] | 6813 | |
Ville Syrjälä | afd58e7 | 2014-01-22 21:33:03 +0200 | [diff] [blame] | 6814 | /* |
| 6815 | * BSpec says this must be set, even though |
| 6816 | * WaDisable4x2SubspanOptimization isn't listed for VLV. |
| 6817 | */ |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 6818 | I915_WRITE(CACHE_MODE_1, |
| 6819 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Jesse Barnes | 7983117 | 2012-06-20 10:53:12 -0700 | [diff] [blame] | 6820 | |
| 6821 | /* |
Ville Syrjälä | da2518f | 2015-01-21 19:38:01 +0200 | [diff] [blame] | 6822 | * BSpec recommends 8x4 when MSAA is used, |
| 6823 | * however in practice 16x4 seems fastest. |
| 6824 | * |
| 6825 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 6826 | * disable bit, which we don't touch here, but it's good |
| 6827 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
| 6828 | */ |
| 6829 | I915_WRITE(GEN7_GT_MODE, |
| 6830 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
| 6831 | |
| 6832 | /* |
Ville Syrjälä | 031994e | 2014-01-22 21:32:46 +0200 | [diff] [blame] | 6833 | * WaIncreaseL3CreditsForVLVB0:vlv |
| 6834 | * This is the hardware default actually. |
| 6835 | */ |
| 6836 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); |
| 6837 | |
| 6838 | /* |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 6839 | * WaDisableVLVClockGating_VBIIssue:vlv |
Jesse Barnes | 2d80957 | 2012-10-25 12:15:44 -0700 | [diff] [blame] | 6840 | * Disable clock gating on th GCFG unit to prevent a delay |
| 6841 | * in the reporting of vblank events. |
| 6842 | */ |
Ville Syrjälä | 7a0d1ee | 2014-01-22 21:33:04 +0200 | [diff] [blame] | 6843 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6844 | } |
| 6845 | |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 6846 | static void cherryview_init_clock_gating(struct drm_device *dev) |
| 6847 | { |
| 6848 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6849 | |
Ville Syrjälä | c6beb13 | 2015-03-05 21:19:48 +0200 | [diff] [blame] | 6850 | vlv_init_display_clock_gating(dev_priv); |
Ville Syrjälä | dd811e7 | 2014-04-09 13:28:33 +0300 | [diff] [blame] | 6851 | |
Ville Syrjälä | 232ce33 | 2014-04-09 13:28:35 +0300 | [diff] [blame] | 6852 | /* WaVSRefCountFullforceMissDisable:chv */ |
| 6853 | /* WaDSRefCountFullforceMissDisable:chv */ |
| 6854 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 6855 | I915_READ(GEN7_FF_THREAD_MODE) & |
| 6856 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
Ville Syrjälä | acea6f9 | 2014-04-09 13:28:36 +0300 | [diff] [blame] | 6857 | |
| 6858 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ |
| 6859 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
| 6860 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
Ville Syrjälä | 0846697 | 2014-04-09 13:28:37 +0300 | [diff] [blame] | 6861 | |
| 6862 | /* WaDisableCSUnitClockGating:chv */ |
| 6863 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | |
| 6864 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
Ville Syrjälä | c631780 | 2014-04-09 13:28:38 +0300 | [diff] [blame] | 6865 | |
| 6866 | /* WaDisableSDEUnitClockGating:chv */ |
| 6867 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 6868 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
Ville Syrjälä | 6d50b06 | 2015-05-19 20:32:57 +0300 | [diff] [blame] | 6869 | |
| 6870 | /* |
| 6871 | * GTT cache may not work with big pages, so if those |
| 6872 | * are ever enabled GTT cache may need to be disabled. |
| 6873 | */ |
| 6874 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 6875 | } |
| 6876 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6877 | static void g4x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6878 | { |
| 6879 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6880 | uint32_t dspclk_gate; |
| 6881 | |
| 6882 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 6883 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 6884 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 6885 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 6886 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 6887 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 6888 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 6889 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 6890 | if (IS_GM45(dev)) |
| 6891 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 6892 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 6893 | |
| 6894 | /* WaDisableRenderCachePipelinedFlush */ |
| 6895 | I915_WRITE(CACHE_MODE_0, |
| 6896 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 6897 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6898 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
| 6899 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 6900 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 6901 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6902 | } |
| 6903 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6904 | static void crestline_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6905 | { |
| 6906 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6907 | |
| 6908 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 6909 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 6910 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 6911 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 6912 | I915_WRITE16(DEUC, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 6913 | I915_WRITE(MI_ARB_STATE, |
| 6914 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6915 | |
| 6916 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
| 6917 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6918 | } |
| 6919 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6920 | static void broadwater_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6921 | { |
| 6922 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6923 | |
| 6924 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 6925 | I965_RCC_CLOCK_GATE_DISABLE | |
| 6926 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 6927 | I965_ISC_CLOCK_GATE_DISABLE | |
| 6928 | I965_FBC_CLOCK_GATE_DISABLE); |
| 6929 | I915_WRITE(RENCLK_GATE_D2, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 6930 | I915_WRITE(MI_ARB_STATE, |
| 6931 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 6932 | |
| 6933 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
| 6934 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6935 | } |
| 6936 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6937 | static void gen3_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6938 | { |
| 6939 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6940 | u32 dstate = I915_READ(D_STATE); |
| 6941 | |
| 6942 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 6943 | DSTATE_DOT_CLOCK_GATING; |
| 6944 | I915_WRITE(D_STATE, dstate); |
Chris Wilson | 13a86b8 | 2012-04-24 14:51:43 +0100 | [diff] [blame] | 6945 | |
| 6946 | if (IS_PINEVIEW(dev)) |
| 6947 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
Daniel Vetter | 974a3b0 | 2012-09-09 11:54:16 +0200 | [diff] [blame] | 6948 | |
| 6949 | /* IIR "flip pending" means done if this bit is set */ |
| 6950 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
Ville Syrjälä | 12fabbcb9 | 2014-02-25 15:13:38 +0200 | [diff] [blame] | 6951 | |
| 6952 | /* interrupts should cause a wake up from C3 */ |
Ville Syrjälä | 3299254 | 2014-02-25 15:13:39 +0200 | [diff] [blame] | 6953 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
Ville Syrjälä | dbb4274 | 2014-02-25 15:13:41 +0200 | [diff] [blame] | 6954 | |
| 6955 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 6956 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Ville Syrjälä | 1038392 | 2014-08-15 01:21:54 +0300 | [diff] [blame] | 6957 | |
| 6958 | I915_WRITE(MI_ARB_STATE, |
| 6959 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6960 | } |
| 6961 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6962 | static void i85x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6963 | { |
| 6964 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6965 | |
| 6966 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
Ville Syrjälä | 54e472a | 2014-02-25 15:13:40 +0200 | [diff] [blame] | 6967 | |
| 6968 | /* interrupts should cause a wake up from C3 */ |
| 6969 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | |
| 6970 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); |
Ville Syrjälä | 1038392 | 2014-08-15 01:21:54 +0300 | [diff] [blame] | 6971 | |
| 6972 | I915_WRITE(MEM_MODE, |
| 6973 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6974 | } |
| 6975 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6976 | static void i830_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6977 | { |
| 6978 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6979 | |
| 6980 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
Ville Syrjälä | 1038392 | 2014-08-15 01:21:54 +0300 | [diff] [blame] | 6981 | |
| 6982 | I915_WRITE(MEM_MODE, |
| 6983 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | |
| 6984 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6985 | } |
| 6986 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6987 | void intel_init_clock_gating(struct drm_device *dev) |
| 6988 | { |
| 6989 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6990 | |
Damien Lespiau | c57e355 | 2015-02-09 19:33:05 +0000 | [diff] [blame] | 6991 | if (dev_priv->display.init_clock_gating) |
| 6992 | dev_priv->display.init_clock_gating(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6993 | } |
| 6994 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 6995 | void intel_suspend_hw(struct drm_device *dev) |
| 6996 | { |
| 6997 | if (HAS_PCH_LPT(dev)) |
| 6998 | lpt_suspend_hw(dev); |
| 6999 | } |
| 7000 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7001 | /* Set up chip specific power management-related functions */ |
| 7002 | void intel_init_pm(struct drm_device *dev) |
| 7003 | { |
| 7004 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7005 | |
Rodrigo Vivi | 7ff0ebc | 2014-12-08 14:09:10 -0200 | [diff] [blame] | 7006 | intel_fbc_init(dev_priv); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7007 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 7008 | /* For cxsr */ |
| 7009 | if (IS_PINEVIEW(dev)) |
| 7010 | i915_pineview_get_mem_freq(dev); |
| 7011 | else if (IS_GEN5(dev)) |
| 7012 | i915_ironlake_get_mem_freq(dev); |
| 7013 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7014 | /* For FIFO watermark updates */ |
Damien Lespiau | f5ed50c | 2014-11-13 17:51:52 +0000 | [diff] [blame] | 7015 | if (INTEL_INFO(dev)->gen >= 9) { |
Pradeep Bhat | 2af30a5 | 2014-11-04 17:06:38 +0000 | [diff] [blame] | 7016 | skl_setup_wm_latency(dev); |
| 7017 | |
Imre Deak | a82abe4 | 2015-03-27 14:00:04 +0200 | [diff] [blame] | 7018 | if (IS_BROXTON(dev)) |
| 7019 | dev_priv->display.init_clock_gating = |
| 7020 | bxt_init_clock_gating; |
| 7021 | else if (IS_SKYLAKE(dev)) |
| 7022 | dev_priv->display.init_clock_gating = |
| 7023 | skl_init_clock_gating; |
Pradeep Bhat | 2d41c0b | 2014-11-04 17:06:42 +0000 | [diff] [blame] | 7024 | dev_priv->display.update_wm = skl_update_wm; |
Damien Lespiau | c83155a | 2014-03-28 00:18:35 +0530 | [diff] [blame] | 7025 | } else if (HAS_PCH_SPLIT(dev)) { |
Damien Lespiau | fa50ad6 | 2014-03-17 18:01:16 +0000 | [diff] [blame] | 7026 | ilk_setup_wm_latency(dev); |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 7027 | |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7028 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
| 7029 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
| 7030 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && |
| 7031 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
| 7032 | dev_priv->display.update_wm = ilk_update_wm; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7033 | } else { |
| 7034 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 7035 | "Disable CxSR\n"); |
| 7036 | } |
| 7037 | |
| 7038 | if (IS_GEN5(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7039 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7040 | else if (IS_GEN6(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7041 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7042 | else if (IS_IVYBRIDGE(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7043 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7044 | else if (IS_HASWELL(dev)) |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 7045 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7046 | else if (INTEL_INFO(dev)->gen == 8) |
Paulo Zanoni | 47c2bd9 | 2014-08-21 17:09:37 -0300 | [diff] [blame] | 7047 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 7048 | } else if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 262cd2e | 2015-06-24 22:00:04 +0300 | [diff] [blame] | 7049 | vlv_setup_wm_latency(dev); |
| 7050 | |
| 7051 | dev_priv->display.update_wm = vlv_update_wm; |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 7052 | dev_priv->display.init_clock_gating = |
| 7053 | cherryview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7054 | } else if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 26e1fe4 | 2015-06-24 22:00:06 +0300 | [diff] [blame] | 7055 | vlv_setup_wm_latency(dev); |
| 7056 | |
| 7057 | dev_priv->display.update_wm = vlv_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7058 | dev_priv->display.init_clock_gating = |
| 7059 | valleyview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7060 | } else if (IS_PINEVIEW(dev)) { |
| 7061 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
| 7062 | dev_priv->is_ddr3, |
| 7063 | dev_priv->fsb_freq, |
| 7064 | dev_priv->mem_freq)) { |
| 7065 | DRM_INFO("failed to find known CxSR latency " |
| 7066 | "(found ddr%s fsb freq %d, mem freq %d), " |
| 7067 | "disabling CxSR\n", |
| 7068 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
| 7069 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 7070 | /* Disable CxSR and never update its watermark again */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 7071 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7072 | dev_priv->display.update_wm = NULL; |
| 7073 | } else |
| 7074 | dev_priv->display.update_wm = pineview_update_wm; |
| 7075 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 7076 | } else if (IS_G4X(dev)) { |
| 7077 | dev_priv->display.update_wm = g4x_update_wm; |
| 7078 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
| 7079 | } else if (IS_GEN4(dev)) { |
| 7080 | dev_priv->display.update_wm = i965_update_wm; |
| 7081 | if (IS_CRESTLINE(dev)) |
| 7082 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
| 7083 | else if (IS_BROADWATER(dev)) |
| 7084 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
| 7085 | } else if (IS_GEN3(dev)) { |
| 7086 | dev_priv->display.update_wm = i9xx_update_wm; |
| 7087 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
| 7088 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 7089 | } else if (IS_GEN2(dev)) { |
| 7090 | if (INTEL_INFO(dev)->num_pipes == 1) { |
| 7091 | dev_priv->display.update_wm = i845_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7092 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 7093 | } else { |
| 7094 | dev_priv->display.update_wm = i9xx_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7095 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 7096 | } |
| 7097 | |
| 7098 | if (IS_I85X(dev) || IS_I865G(dev)) |
| 7099 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 7100 | else |
| 7101 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
| 7102 | } else { |
| 7103 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7104 | } |
| 7105 | } |
| 7106 | |
Tom O'Rourke | 151a49d | 2014-11-13 18:50:10 -0800 | [diff] [blame] | 7107 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 7108 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 7109 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 7110 | |
| 7111 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 7112 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
| 7113 | return -EAGAIN; |
| 7114 | } |
| 7115 | |
| 7116 | I915_WRITE(GEN6_PCODE_DATA, *val); |
Damien Lespiau | dddab34 | 2014-11-13 17:51:50 +0000 | [diff] [blame] | 7117 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 7118 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 7119 | |
| 7120 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 7121 | 500)) { |
| 7122 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
| 7123 | return -ETIMEDOUT; |
| 7124 | } |
| 7125 | |
| 7126 | *val = I915_READ(GEN6_PCODE_DATA); |
| 7127 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 7128 | |
| 7129 | return 0; |
| 7130 | } |
| 7131 | |
Tom O'Rourke | 151a49d | 2014-11-13 18:50:10 -0800 | [diff] [blame] | 7132 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 7133 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 7134 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 7135 | |
| 7136 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 7137 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
| 7138 | return -EAGAIN; |
| 7139 | } |
| 7140 | |
| 7141 | I915_WRITE(GEN6_PCODE_DATA, val); |
| 7142 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 7143 | |
| 7144 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 7145 | 500)) { |
| 7146 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
| 7147 | return -ETIMEDOUT; |
| 7148 | } |
| 7149 | |
| 7150 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 7151 | |
| 7152 | return 0; |
| 7153 | } |
Jesse Barnes | a0e4e19 | 2013-04-02 11:23:05 -0700 | [diff] [blame] | 7154 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7155 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7156 | { |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7157 | switch (czclk_freq) { |
| 7158 | case 200: |
| 7159 | return 10; |
| 7160 | case 267: |
| 7161 | return 12; |
| 7162 | case 320: |
| 7163 | case 333: |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7164 | return 16; |
Ville Syrjälä | ab3fb15 | 2014-11-10 22:55:15 +0200 | [diff] [blame] | 7165 | case 400: |
| 7166 | return 20; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7167 | default: |
| 7168 | return -1; |
| 7169 | } |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7170 | } |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7171 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7172 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
| 7173 | { |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 7174 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7175 | |
| 7176 | div = vlv_gpu_freq_div(czclk_freq); |
| 7177 | if (div < 0) |
| 7178 | return div; |
| 7179 | |
| 7180 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7181 | } |
| 7182 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 7183 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7184 | { |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 7185 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7186 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7187 | mul = vlv_gpu_freq_div(czclk_freq); |
| 7188 | if (mul < 0) |
| 7189 | return mul; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7190 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7191 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7192 | } |
| 7193 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 7194 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7195 | { |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 7196 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7197 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7198 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
| 7199 | if (div < 0) |
| 7200 | return div; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7201 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7202 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7203 | } |
| 7204 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 7205 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7206 | { |
Ville Syrjälä | bfa7df0 | 2015-09-24 23:29:18 +0300 | [diff] [blame] | 7207 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7208 | |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7209 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
| 7210 | if (mul < 0) |
| 7211 | return mul; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7212 | |
Ville Syrjälä | 1c14762 | 2014-08-18 14:42:43 +0300 | [diff] [blame] | 7213 | /* CHV needs even values */ |
Ville Syrjälä | dd06f88 | 2014-11-10 22:55:12 +0200 | [diff] [blame] | 7214 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7215 | } |
| 7216 | |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 7217 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
| 7218 | { |
Akash Goel | 80b6dda | 2015-03-06 11:07:15 +0530 | [diff] [blame] | 7219 | if (IS_GEN9(dev_priv->dev)) |
| 7220 | return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER; |
| 7221 | else if (IS_CHERRYVIEW(dev_priv->dev)) |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 7222 | return chv_gpu_freq(dev_priv, val); |
| 7223 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
| 7224 | return byt_gpu_freq(dev_priv, val); |
| 7225 | else |
| 7226 | return val * GT_FREQUENCY_MULTIPLIER; |
| 7227 | } |
| 7228 | |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 7229 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
| 7230 | { |
Akash Goel | 80b6dda | 2015-03-06 11:07:15 +0530 | [diff] [blame] | 7231 | if (IS_GEN9(dev_priv->dev)) |
| 7232 | return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER; |
| 7233 | else if (IS_CHERRYVIEW(dev_priv->dev)) |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 7234 | return chv_freq_opcode(dev_priv, val); |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7235 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
Ville Syrjälä | 616bc82 | 2015-01-23 21:04:25 +0200 | [diff] [blame] | 7236 | return byt_freq_opcode(dev_priv, val); |
| 7237 | else |
| 7238 | return val / GT_FREQUENCY_MULTIPLIER; |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7239 | } |
| 7240 | |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7241 | struct request_boost { |
| 7242 | struct work_struct work; |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 7243 | struct drm_i915_gem_request *req; |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7244 | }; |
| 7245 | |
| 7246 | static void __intel_rps_boost_work(struct work_struct *work) |
| 7247 | { |
| 7248 | struct request_boost *boost = container_of(work, struct request_boost, work); |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 7249 | struct drm_i915_gem_request *req = boost->req; |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7250 | |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 7251 | if (!i915_gem_request_completed(req, true)) |
| 7252 | gen6_rps_boost(to_i915(req->ring->dev), NULL, |
| 7253 | req->emitted_jiffies); |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7254 | |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 7255 | i915_gem_request_unreference__unlocked(req); |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7256 | kfree(boost); |
| 7257 | } |
| 7258 | |
| 7259 | void intel_queue_rps_boost_for_request(struct drm_device *dev, |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 7260 | struct drm_i915_gem_request *req) |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7261 | { |
| 7262 | struct request_boost *boost; |
| 7263 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 7264 | if (req == NULL || INTEL_INFO(dev)->gen < 6) |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7265 | return; |
| 7266 | |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 7267 | if (i915_gem_request_completed(req, true)) |
| 7268 | return; |
| 7269 | |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7270 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
| 7271 | if (boost == NULL) |
| 7272 | return; |
| 7273 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 7274 | i915_gem_request_reference(req); |
| 7275 | boost->req = req; |
Chris Wilson | 6ad790c | 2015-04-07 16:20:31 +0100 | [diff] [blame] | 7276 | |
| 7277 | INIT_WORK(&boost->work, __intel_rps_boost_work); |
| 7278 | queue_work(to_i915(dev)->wq, &boost->work); |
| 7279 | } |
| 7280 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 7281 | void intel_pm_setup(struct drm_device *dev) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 7282 | { |
| 7283 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7284 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 7285 | mutex_init(&dev_priv->rps.hw_lock); |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 7286 | spin_lock_init(&dev_priv->rps.client_lock); |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 7287 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 7288 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
| 7289 | intel_gen6_powersave_work); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 7290 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 7291 | INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); |
| 7292 | INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 7293 | |
Paulo Zanoni | 33688d9 | 2014-03-07 20:08:19 -0300 | [diff] [blame] | 7294 | dev_priv->pm.suspended = false; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 7295 | } |