blob: 0a282e5fcc9c3fe4931a871acd6d89708162bd0d [file] [log] [blame]
Mika Westerberg011f23a2010-05-06 04:47:04 +00001/*
2 * Driver for Cirrus Logic EP93xx SPI controller.
3 *
Mika Westerberg626a96d2011-05-29 13:10:06 +03004 * Copyright (C) 2010-2011 Mika Westerberg
Mika Westerberg011f23a2010-05-06 04:47:04 +00005 *
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
7 *
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
9 *
10 * For more information about the SPI controller see documentation on Cirrus
11 * Logic web site:
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/io.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/device.h>
Mika Westerberg626a96d2011-05-29 13:10:06 +030024#include <linux/dmaengine.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000025#include <linux/bitops.h>
26#include <linux/interrupt.h>
Mika Westerberg5bdb76132011-10-15 21:40:09 +030027#include <linux/module.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000028#include <linux/platform_device.h>
29#include <linux/workqueue.h>
30#include <linux/sched.h>
Mika Westerberg626a96d2011-05-29 13:10:06 +030031#include <linux/scatterlist.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000032#include <linux/spi/spi.h>
33
Mika Westerberg626a96d2011-05-29 13:10:06 +030034#include <mach/dma.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000035#include <mach/ep93xx_spi.h>
36
37#define SSPCR0 0x0000
38#define SSPCR0_MODE_SHIFT 6
39#define SSPCR0_SCR_SHIFT 8
40
41#define SSPCR1 0x0004
42#define SSPCR1_RIE BIT(0)
43#define SSPCR1_TIE BIT(1)
44#define SSPCR1_RORIE BIT(2)
45#define SSPCR1_LBM BIT(3)
46#define SSPCR1_SSE BIT(4)
47#define SSPCR1_MS BIT(5)
48#define SSPCR1_SOD BIT(6)
49
50#define SSPDR 0x0008
51
52#define SSPSR 0x000c
53#define SSPSR_TFE BIT(0)
54#define SSPSR_TNF BIT(1)
55#define SSPSR_RNE BIT(2)
56#define SSPSR_RFF BIT(3)
57#define SSPSR_BSY BIT(4)
58#define SSPCPSR 0x0010
59
60#define SSPIIR 0x0014
61#define SSPIIR_RIS BIT(0)
62#define SSPIIR_TIS BIT(1)
63#define SSPIIR_RORIS BIT(2)
64#define SSPICR SSPIIR
65
66/* timeout in milliseconds */
67#define SPI_TIMEOUT 5
68/* maximum depth of RX/TX FIFO */
69#define SPI_FIFO_SIZE 8
70
71/**
72 * struct ep93xx_spi - EP93xx SPI controller structure
73 * @lock: spinlock that protects concurrent accesses to fields @running,
74 * @current_msg and @msg_queue
75 * @pdev: pointer to platform device
76 * @clk: clock for the controller
77 * @regs_base: pointer to ioremap()'d registers
Mika Westerberg626a96d2011-05-29 13:10:06 +030078 * @sspdr_phys: physical address of the SSPDR register
Mika Westerberg011f23a2010-05-06 04:47:04 +000079 * @irq: IRQ number used by the driver
80 * @min_rate: minimum clock rate (in Hz) supported by the controller
81 * @max_rate: maximum clock rate (in Hz) supported by the controller
82 * @running: is the queue running
83 * @wq: workqueue used by the driver
84 * @msg_work: work that is queued for the driver
85 * @wait: wait here until given transfer is completed
86 * @msg_queue: queue for the messages
87 * @current_msg: message that is currently processed (or %NULL if none)
88 * @tx: current byte in transfer to transmit
89 * @rx: current byte in transfer to receive
90 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
91 * frame decreases this level and sending one frame increases it.
Mika Westerberg626a96d2011-05-29 13:10:06 +030092 * @dma_rx: RX DMA channel
93 * @dma_tx: TX DMA channel
94 * @dma_rx_data: RX parameters passed to the DMA engine
95 * @dma_tx_data: TX parameters passed to the DMA engine
96 * @rx_sgt: sg table for RX transfers
97 * @tx_sgt: sg table for TX transfers
98 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
99 * the client
Mika Westerberg011f23a2010-05-06 04:47:04 +0000100 *
101 * This structure holds EP93xx SPI controller specific information. When
102 * @running is %true, driver accepts transfer requests from protocol drivers.
103 * @current_msg is used to hold pointer to the message that is currently
104 * processed. If @current_msg is %NULL, it means that no processing is going
105 * on.
106 *
107 * Most of the fields are only written once and they can be accessed without
108 * taking the @lock. Fields that are accessed concurrently are: @current_msg,
109 * @running, and @msg_queue.
110 */
111struct ep93xx_spi {
112 spinlock_t lock;
113 const struct platform_device *pdev;
114 struct clk *clk;
115 void __iomem *regs_base;
Mika Westerberg626a96d2011-05-29 13:10:06 +0300116 unsigned long sspdr_phys;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000117 int irq;
118 unsigned long min_rate;
119 unsigned long max_rate;
120 bool running;
121 struct workqueue_struct *wq;
122 struct work_struct msg_work;
123 struct completion wait;
124 struct list_head msg_queue;
125 struct spi_message *current_msg;
126 size_t tx;
127 size_t rx;
128 size_t fifo_level;
Mika Westerberg626a96d2011-05-29 13:10:06 +0300129 struct dma_chan *dma_rx;
130 struct dma_chan *dma_tx;
131 struct ep93xx_dma_data dma_rx_data;
132 struct ep93xx_dma_data dma_tx_data;
133 struct sg_table rx_sgt;
134 struct sg_table tx_sgt;
135 void *zeropage;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000136};
137
138/**
139 * struct ep93xx_spi_chip - SPI device hardware settings
140 * @spi: back pointer to the SPI device
141 * @rate: max rate in hz this chip supports
142 * @div_cpsr: cpsr (pre-scaler) divider
143 * @div_scr: scr divider
144 * @dss: bits per word (4 - 16 bits)
145 * @ops: private chip operations
146 *
147 * This structure is used to store hardware register specific settings for each
148 * SPI device. Settings are written to hardware by function
149 * ep93xx_spi_chip_setup().
150 */
151struct ep93xx_spi_chip {
152 const struct spi_device *spi;
153 unsigned long rate;
154 u8 div_cpsr;
155 u8 div_scr;
156 u8 dss;
157 struct ep93xx_spi_chip_ops *ops;
158};
159
160/* converts bits per word to CR0.DSS value */
161#define bits_per_word_to_dss(bpw) ((bpw) - 1)
162
163static inline void
164ep93xx_spi_write_u8(const struct ep93xx_spi *espi, u16 reg, u8 value)
165{
166 __raw_writeb(value, espi->regs_base + reg);
167}
168
169static inline u8
170ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
171{
172 return __raw_readb(spi->regs_base + reg);
173}
174
175static inline void
176ep93xx_spi_write_u16(const struct ep93xx_spi *espi, u16 reg, u16 value)
177{
178 __raw_writew(value, espi->regs_base + reg);
179}
180
181static inline u16
182ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
183{
184 return __raw_readw(spi->regs_base + reg);
185}
186
187static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
188{
189 u8 regval;
190 int err;
191
192 err = clk_enable(espi->clk);
193 if (err)
194 return err;
195
196 regval = ep93xx_spi_read_u8(espi, SSPCR1);
197 regval |= SSPCR1_SSE;
198 ep93xx_spi_write_u8(espi, SSPCR1, regval);
199
200 return 0;
201}
202
203static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
204{
205 u8 regval;
206
207 regval = ep93xx_spi_read_u8(espi, SSPCR1);
208 regval &= ~SSPCR1_SSE;
209 ep93xx_spi_write_u8(espi, SSPCR1, regval);
210
211 clk_disable(espi->clk);
212}
213
214static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
215{
216 u8 regval;
217
218 regval = ep93xx_spi_read_u8(espi, SSPCR1);
219 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
220 ep93xx_spi_write_u8(espi, SSPCR1, regval);
221}
222
223static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
224{
225 u8 regval;
226
227 regval = ep93xx_spi_read_u8(espi, SSPCR1);
228 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
229 ep93xx_spi_write_u8(espi, SSPCR1, regval);
230}
231
232/**
233 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
234 * @espi: ep93xx SPI controller struct
235 * @chip: divisors are calculated for this chip
236 * @rate: desired SPI output clock rate
237 *
238 * Function calculates cpsr (clock pre-scaler) and scr divisors based on
239 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If,
240 * for some reason, divisors cannot be calculated nothing is stored and
241 * %-EINVAL is returned.
242 */
243static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
244 struct ep93xx_spi_chip *chip,
245 unsigned long rate)
246{
247 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
248 int cpsr, scr;
249
250 /*
251 * Make sure that max value is between values supported by the
252 * controller. Note that minimum value is already checked in
253 * ep93xx_spi_transfer().
254 */
255 rate = clamp(rate, espi->min_rate, espi->max_rate);
256
257 /*
258 * Calculate divisors so that we can get speed according the
259 * following formula:
260 * rate = spi_clock_rate / (cpsr * (1 + scr))
261 *
262 * cpsr must be even number and starts from 2, scr can be any number
263 * between 0 and 255.
264 */
265 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
266 for (scr = 0; scr <= 255; scr++) {
267 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
268 chip->div_scr = (u8)scr;
269 chip->div_cpsr = (u8)cpsr;
270 return 0;
271 }
272 }
273 }
274
275 return -EINVAL;
276}
277
278static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
279{
280 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
281 int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
282
283 if (chip->ops && chip->ops->cs_control)
284 chip->ops->cs_control(spi, value);
285}
286
287/**
288 * ep93xx_spi_setup() - setup an SPI device
289 * @spi: SPI device to setup
290 *
291 * This function sets up SPI device mode, speed etc. Can be called multiple
292 * times for a single device. Returns %0 in case of success, negative error in
293 * case of failure. When this function returns success, the device is
294 * deselected.
295 */
296static int ep93xx_spi_setup(struct spi_device *spi)
297{
298 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
299 struct ep93xx_spi_chip *chip;
300
301 if (spi->bits_per_word < 4 || spi->bits_per_word > 16) {
302 dev_err(&espi->pdev->dev, "invalid bits per word %d\n",
303 spi->bits_per_word);
304 return -EINVAL;
305 }
306
307 chip = spi_get_ctldata(spi);
308 if (!chip) {
309 dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
310 spi->modalias);
311
312 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
313 if (!chip)
314 return -ENOMEM;
315
316 chip->spi = spi;
317 chip->ops = spi->controller_data;
318
319 if (chip->ops && chip->ops->setup) {
320 int ret = chip->ops->setup(spi);
321 if (ret) {
322 kfree(chip);
323 return ret;
324 }
325 }
326
327 spi_set_ctldata(spi, chip);
328 }
329
330 if (spi->max_speed_hz != chip->rate) {
331 int err;
332
333 err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz);
334 if (err != 0) {
335 spi_set_ctldata(spi, NULL);
336 kfree(chip);
337 return err;
338 }
339 chip->rate = spi->max_speed_hz;
340 }
341
342 chip->dss = bits_per_word_to_dss(spi->bits_per_word);
343
344 ep93xx_spi_cs_control(spi, false);
345 return 0;
346}
347
348/**
349 * ep93xx_spi_transfer() - queue message to be transferred
350 * @spi: target SPI device
351 * @msg: message to be transferred
352 *
353 * This function is called by SPI device drivers when they are going to transfer
354 * a new message. It simply puts the message in the queue and schedules
355 * workqueue to perform the actual transfer later on.
356 *
357 * Returns %0 on success and negative error in case of failure.
358 */
359static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
360{
361 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
362 struct spi_transfer *t;
363 unsigned long flags;
364
365 if (!msg || !msg->complete)
366 return -EINVAL;
367
368 /* first validate each transfer */
369 list_for_each_entry(t, &msg->transfers, transfer_list) {
370 if (t->bits_per_word) {
371 if (t->bits_per_word < 4 || t->bits_per_word > 16)
372 return -EINVAL;
373 }
374 if (t->speed_hz && t->speed_hz < espi->min_rate)
375 return -EINVAL;
376 }
377
378 /*
379 * Now that we own the message, let's initialize it so that it is
380 * suitable for us. We use @msg->status to signal whether there was
381 * error in transfer and @msg->state is used to hold pointer to the
382 * current transfer (or %NULL if no active current transfer).
383 */
384 msg->state = NULL;
385 msg->status = 0;
386 msg->actual_length = 0;
387
388 spin_lock_irqsave(&espi->lock, flags);
389 if (!espi->running) {
390 spin_unlock_irqrestore(&espi->lock, flags);
391 return -ESHUTDOWN;
392 }
393 list_add_tail(&msg->queue, &espi->msg_queue);
394 queue_work(espi->wq, &espi->msg_work);
395 spin_unlock_irqrestore(&espi->lock, flags);
396
397 return 0;
398}
399
400/**
401 * ep93xx_spi_cleanup() - cleans up master controller specific state
402 * @spi: SPI device to cleanup
403 *
404 * This function releases master controller specific state for given @spi
405 * device.
406 */
407static void ep93xx_spi_cleanup(struct spi_device *spi)
408{
409 struct ep93xx_spi_chip *chip;
410
411 chip = spi_get_ctldata(spi);
412 if (chip) {
413 if (chip->ops && chip->ops->cleanup)
414 chip->ops->cleanup(spi);
415 spi_set_ctldata(spi, NULL);
416 kfree(chip);
417 }
418}
419
420/**
421 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
422 * @espi: ep93xx SPI controller struct
423 * @chip: chip specific settings
424 *
425 * This function sets up the actual hardware registers with settings given in
426 * @chip. Note that no validation is done so make sure that callers validate
427 * settings before calling this.
428 */
429static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
430 const struct ep93xx_spi_chip *chip)
431{
432 u16 cr0;
433
434 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT;
435 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
436 cr0 |= chip->dss;
437
438 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
439 chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss);
440 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0);
441
442 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr);
443 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
444}
445
446static inline int bits_per_word(const struct ep93xx_spi *espi)
447{
448 struct spi_message *msg = espi->current_msg;
449 struct spi_transfer *t = msg->state;
450
451 return t->bits_per_word ? t->bits_per_word : msg->spi->bits_per_word;
452}
453
454static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
455{
456 if (bits_per_word(espi) > 8) {
457 u16 tx_val = 0;
458
459 if (t->tx_buf)
460 tx_val = ((u16 *)t->tx_buf)[espi->tx];
461 ep93xx_spi_write_u16(espi, SSPDR, tx_val);
462 espi->tx += sizeof(tx_val);
463 } else {
464 u8 tx_val = 0;
465
466 if (t->tx_buf)
467 tx_val = ((u8 *)t->tx_buf)[espi->tx];
468 ep93xx_spi_write_u8(espi, SSPDR, tx_val);
469 espi->tx += sizeof(tx_val);
470 }
471}
472
473static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
474{
475 if (bits_per_word(espi) > 8) {
476 u16 rx_val;
477
478 rx_val = ep93xx_spi_read_u16(espi, SSPDR);
479 if (t->rx_buf)
480 ((u16 *)t->rx_buf)[espi->rx] = rx_val;
481 espi->rx += sizeof(rx_val);
482 } else {
483 u8 rx_val;
484
485 rx_val = ep93xx_spi_read_u8(espi, SSPDR);
486 if (t->rx_buf)
487 ((u8 *)t->rx_buf)[espi->rx] = rx_val;
488 espi->rx += sizeof(rx_val);
489 }
490}
491
492/**
493 * ep93xx_spi_read_write() - perform next RX/TX transfer
494 * @espi: ep93xx SPI controller struct
495 *
496 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
497 * called several times, the whole transfer will be completed. Returns
498 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
499 *
500 * When this function is finished, RX FIFO should be empty and TX FIFO should be
501 * full.
502 */
503static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
504{
505 struct spi_message *msg = espi->current_msg;
506 struct spi_transfer *t = msg->state;
507
508 /* read as long as RX FIFO has frames in it */
509 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
510 ep93xx_do_read(espi, t);
511 espi->fifo_level--;
512 }
513
514 /* write as long as TX FIFO has room */
515 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
516 ep93xx_do_write(espi, t);
517 espi->fifo_level++;
518 }
519
Mika Westerberg626a96d2011-05-29 13:10:06 +0300520 if (espi->rx == t->len)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000521 return 0;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000522
523 return -EINPROGRESS;
524}
525
Mika Westerberg626a96d2011-05-29 13:10:06 +0300526static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
527{
528 /*
529 * Now everything is set up for the current transfer. We prime the TX
530 * FIFO, enable interrupts, and wait for the transfer to complete.
531 */
532 if (ep93xx_spi_read_write(espi)) {
533 ep93xx_spi_enable_interrupts(espi);
534 wait_for_completion(&espi->wait);
535 }
536}
537
538/**
539 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
540 * @espi: ep93xx SPI controller struct
541 * @dir: DMA transfer direction
542 *
543 * Function configures the DMA, maps the buffer and prepares the DMA
544 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
545 * in case of failure.
546 */
547static struct dma_async_tx_descriptor *
548ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
549{
550 struct spi_transfer *t = espi->current_msg->state;
551 struct dma_async_tx_descriptor *txd;
552 enum dma_slave_buswidth buswidth;
553 struct dma_slave_config conf;
554 struct scatterlist *sg;
555 struct sg_table *sgt;
556 struct dma_chan *chan;
557 const void *buf, *pbuf;
558 size_t len = t->len;
559 int i, ret, nents;
560
561 if (bits_per_word(espi) > 8)
562 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
563 else
564 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
565
566 memset(&conf, 0, sizeof(conf));
567 conf.direction = dir;
568
569 if (dir == DMA_FROM_DEVICE) {
570 chan = espi->dma_rx;
571 buf = t->rx_buf;
572 sgt = &espi->rx_sgt;
573
574 conf.src_addr = espi->sspdr_phys;
575 conf.src_addr_width = buswidth;
576 } else {
577 chan = espi->dma_tx;
578 buf = t->tx_buf;
579 sgt = &espi->tx_sgt;
580
581 conf.dst_addr = espi->sspdr_phys;
582 conf.dst_addr_width = buswidth;
583 }
584
585 ret = dmaengine_slave_config(chan, &conf);
586 if (ret)
587 return ERR_PTR(ret);
588
589 /*
590 * We need to split the transfer into PAGE_SIZE'd chunks. This is
591 * because we are using @espi->zeropage to provide a zero RX buffer
592 * for the TX transfers and we have only allocated one page for that.
593 *
594 * For performance reasons we allocate a new sg_table only when
595 * needed. Otherwise we will re-use the current one. Eventually the
596 * last sg_table is released in ep93xx_spi_release_dma().
597 */
598
599 nents = DIV_ROUND_UP(len, PAGE_SIZE);
600 if (nents != sgt->nents) {
601 sg_free_table(sgt);
602
603 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
604 if (ret)
605 return ERR_PTR(ret);
606 }
607
608 pbuf = buf;
609 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
610 size_t bytes = min_t(size_t, len, PAGE_SIZE);
611
612 if (buf) {
613 sg_set_page(sg, virt_to_page(pbuf), bytes,
614 offset_in_page(pbuf));
615 } else {
616 sg_set_page(sg, virt_to_page(espi->zeropage),
617 bytes, 0);
618 }
619
620 pbuf += bytes;
621 len -= bytes;
622 }
623
624 if (WARN_ON(len)) {
625 dev_warn(&espi->pdev->dev, "len = %d expected 0!", len);
626 return ERR_PTR(-EINVAL);
627 }
628
629 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
630 if (!nents)
631 return ERR_PTR(-ENOMEM);
632
633 txd = chan->device->device_prep_slave_sg(chan, sgt->sgl, nents,
634 dir, DMA_CTRL_ACK);
635 if (!txd) {
636 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
637 return ERR_PTR(-ENOMEM);
638 }
639 return txd;
640}
641
642/**
643 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
644 * @espi: ep93xx SPI controller struct
645 * @dir: DMA transfer direction
646 *
647 * Function finishes with the DMA transfer. After this, the DMA buffer is
648 * unmapped.
649 */
650static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
651 enum dma_data_direction dir)
652{
653 struct dma_chan *chan;
654 struct sg_table *sgt;
655
656 if (dir == DMA_FROM_DEVICE) {
657 chan = espi->dma_rx;
658 sgt = &espi->rx_sgt;
659 } else {
660 chan = espi->dma_tx;
661 sgt = &espi->tx_sgt;
662 }
663
664 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
665}
666
667static void ep93xx_spi_dma_callback(void *callback_param)
668{
669 complete(callback_param);
670}
671
672static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
673{
674 struct spi_message *msg = espi->current_msg;
675 struct dma_async_tx_descriptor *rxd, *txd;
676
677 rxd = ep93xx_spi_dma_prepare(espi, DMA_FROM_DEVICE);
678 if (IS_ERR(rxd)) {
679 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
680 msg->status = PTR_ERR(rxd);
681 return;
682 }
683
684 txd = ep93xx_spi_dma_prepare(espi, DMA_TO_DEVICE);
685 if (IS_ERR(txd)) {
686 ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE);
687 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd));
688 msg->status = PTR_ERR(txd);
689 return;
690 }
691
692 /* We are ready when RX is done */
693 rxd->callback = ep93xx_spi_dma_callback;
694 rxd->callback_param = &espi->wait;
695
696 /* Now submit both descriptors and wait while they finish */
697 dmaengine_submit(rxd);
698 dmaengine_submit(txd);
699
700 dma_async_issue_pending(espi->dma_rx);
701 dma_async_issue_pending(espi->dma_tx);
702
703 wait_for_completion(&espi->wait);
704
705 ep93xx_spi_dma_finish(espi, DMA_TO_DEVICE);
706 ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE);
707}
708
Mika Westerberg011f23a2010-05-06 04:47:04 +0000709/**
710 * ep93xx_spi_process_transfer() - processes one SPI transfer
711 * @espi: ep93xx SPI controller struct
712 * @msg: current message
713 * @t: transfer to process
714 *
715 * This function processes one SPI transfer given in @t. Function waits until
716 * transfer is complete (may sleep) and updates @msg->status based on whether
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300717 * transfer was successfully processed or not.
Mika Westerberg011f23a2010-05-06 04:47:04 +0000718 */
719static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
720 struct spi_message *msg,
721 struct spi_transfer *t)
722{
723 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
724
725 msg->state = t;
726
727 /*
728 * Handle any transfer specific settings if needed. We use
729 * temporary chip settings here and restore original later when
730 * the transfer is finished.
731 */
732 if (t->speed_hz || t->bits_per_word) {
733 struct ep93xx_spi_chip tmp_chip = *chip;
734
735 if (t->speed_hz) {
736 int err;
737
738 err = ep93xx_spi_calc_divisors(espi, &tmp_chip,
739 t->speed_hz);
740 if (err) {
741 dev_err(&espi->pdev->dev,
742 "failed to adjust speed\n");
743 msg->status = err;
744 return;
745 }
746 }
747
748 if (t->bits_per_word)
749 tmp_chip.dss = bits_per_word_to_dss(t->bits_per_word);
750
751 /*
752 * Set up temporary new hw settings for this transfer.
753 */
754 ep93xx_spi_chip_setup(espi, &tmp_chip);
755 }
756
757 espi->rx = 0;
758 espi->tx = 0;
759
760 /*
Mika Westerberg626a96d2011-05-29 13:10:06 +0300761 * There is no point of setting up DMA for the transfers which will
762 * fit into the FIFO and can be transferred with a single interrupt.
763 * So in these cases we will be using PIO and don't bother for DMA.
Mika Westerberg011f23a2010-05-06 04:47:04 +0000764 */
Mika Westerberg626a96d2011-05-29 13:10:06 +0300765 if (espi->dma_rx && t->len > SPI_FIFO_SIZE)
766 ep93xx_spi_dma_transfer(espi);
767 else
768 ep93xx_spi_pio_transfer(espi);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000769
770 /*
771 * In case of error during transmit, we bail out from processing
772 * the message.
773 */
774 if (msg->status)
775 return;
776
Mika Westerberg626a96d2011-05-29 13:10:06 +0300777 msg->actual_length += t->len;
778
Mika Westerberg011f23a2010-05-06 04:47:04 +0000779 /*
780 * After this transfer is finished, perform any possible
781 * post-transfer actions requested by the protocol driver.
782 */
783 if (t->delay_usecs) {
784 set_current_state(TASK_UNINTERRUPTIBLE);
785 schedule_timeout(usecs_to_jiffies(t->delay_usecs));
786 }
787 if (t->cs_change) {
788 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
789 /*
790 * In case protocol driver is asking us to drop the
791 * chipselect briefly, we let the scheduler to handle
792 * any "delay" here.
793 */
794 ep93xx_spi_cs_control(msg->spi, false);
795 cond_resched();
796 ep93xx_spi_cs_control(msg->spi, true);
797 }
798 }
799
800 if (t->speed_hz || t->bits_per_word)
801 ep93xx_spi_chip_setup(espi, chip);
802}
803
804/*
805 * ep93xx_spi_process_message() - process one SPI message
806 * @espi: ep93xx SPI controller struct
807 * @msg: message to process
808 *
809 * This function processes a single SPI message. We go through all transfers in
810 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
811 * asserted during the whole message (unless per transfer cs_change is set).
812 *
813 * @msg->status contains %0 in case of success or negative error code in case of
814 * failure.
815 */
816static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
817 struct spi_message *msg)
818{
819 unsigned long timeout;
820 struct spi_transfer *t;
821 int err;
822
823 /*
824 * Enable the SPI controller and its clock.
825 */
826 err = ep93xx_spi_enable(espi);
827 if (err) {
828 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
829 msg->status = err;
830 return;
831 }
832
833 /*
834 * Just to be sure: flush any data from RX FIFO.
835 */
836 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
837 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
838 if (time_after(jiffies, timeout)) {
839 dev_warn(&espi->pdev->dev,
840 "timeout while flushing RX FIFO\n");
841 msg->status = -ETIMEDOUT;
842 return;
843 }
844 ep93xx_spi_read_u16(espi, SSPDR);
845 }
846
847 /*
848 * We explicitly handle FIFO level. This way we don't have to check TX
849 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
850 */
851 espi->fifo_level = 0;
852
853 /*
854 * Update SPI controller registers according to spi device and assert
855 * the chipselect.
856 */
857 ep93xx_spi_chip_setup(espi, spi_get_ctldata(msg->spi));
858 ep93xx_spi_cs_control(msg->spi, true);
859
860 list_for_each_entry(t, &msg->transfers, transfer_list) {
861 ep93xx_spi_process_transfer(espi, msg, t);
862 if (msg->status)
863 break;
864 }
865
866 /*
867 * Now the whole message is transferred (or failed for some reason). We
868 * deselect the device and disable the SPI controller.
869 */
870 ep93xx_spi_cs_control(msg->spi, false);
871 ep93xx_spi_disable(espi);
872}
873
874#define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work))
875
876/**
877 * ep93xx_spi_work() - EP93xx SPI workqueue worker function
878 * @work: work struct
879 *
880 * Workqueue worker function. This function is called when there are new
881 * SPI messages to be processed. Message is taken out from the queue and then
882 * passed to ep93xx_spi_process_message().
883 *
884 * After message is transferred, protocol driver is notified by calling
885 * @msg->complete(). In case of error, @msg->status is set to negative error
886 * number, otherwise it contains zero (and @msg->actual_length is updated).
887 */
888static void ep93xx_spi_work(struct work_struct *work)
889{
890 struct ep93xx_spi *espi = work_to_espi(work);
891 struct spi_message *msg;
892
893 spin_lock_irq(&espi->lock);
894 if (!espi->running || espi->current_msg ||
895 list_empty(&espi->msg_queue)) {
896 spin_unlock_irq(&espi->lock);
897 return;
898 }
899 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue);
900 list_del_init(&msg->queue);
901 espi->current_msg = msg;
902 spin_unlock_irq(&espi->lock);
903
904 ep93xx_spi_process_message(espi, msg);
905
906 /*
907 * Update the current message and re-schedule ourselves if there are
908 * more messages in the queue.
909 */
910 spin_lock_irq(&espi->lock);
911 espi->current_msg = NULL;
912 if (espi->running && !list_empty(&espi->msg_queue))
913 queue_work(espi->wq, &espi->msg_work);
914 spin_unlock_irq(&espi->lock);
915
916 /* notify the protocol driver that we are done with this message */
917 msg->complete(msg->context);
918}
919
920static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
921{
922 struct ep93xx_spi *espi = dev_id;
923 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
924
925 /*
926 * If we got ROR (receive overrun) interrupt we know that something is
927 * wrong. Just abort the message.
928 */
929 if (unlikely(irq_status & SSPIIR_RORIS)) {
930 /* clear the overrun interrupt */
931 ep93xx_spi_write_u8(espi, SSPICR, 0);
932 dev_warn(&espi->pdev->dev,
933 "receive overrun, aborting the message\n");
934 espi->current_msg->status = -EIO;
935 } else {
936 /*
937 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
938 * simply execute next data transfer.
939 */
940 if (ep93xx_spi_read_write(espi)) {
941 /*
942 * In normal case, there still is some processing left
943 * for current transfer. Let's wait for the next
944 * interrupt then.
945 */
946 return IRQ_HANDLED;
947 }
948 }
949
950 /*
951 * Current transfer is finished, either with error or with success. In
952 * any case we disable interrupts and notify the worker to handle
953 * any post-processing of the message.
954 */
955 ep93xx_spi_disable_interrupts(espi);
956 complete(&espi->wait);
957 return IRQ_HANDLED;
958}
959
Mika Westerberg626a96d2011-05-29 13:10:06 +0300960static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
961{
962 if (ep93xx_dma_chan_is_m2p(chan))
963 return false;
964
965 chan->private = filter_param;
966 return true;
967}
968
969static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
970{
971 dma_cap_mask_t mask;
972 int ret;
973
974 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
975 if (!espi->zeropage)
976 return -ENOMEM;
977
978 dma_cap_zero(mask);
979 dma_cap_set(DMA_SLAVE, mask);
980
981 espi->dma_rx_data.port = EP93XX_DMA_SSP;
982 espi->dma_rx_data.direction = DMA_FROM_DEVICE;
983 espi->dma_rx_data.name = "ep93xx-spi-rx";
984
985 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
986 &espi->dma_rx_data);
987 if (!espi->dma_rx) {
988 ret = -ENODEV;
989 goto fail_free_page;
990 }
991
992 espi->dma_tx_data.port = EP93XX_DMA_SSP;
993 espi->dma_tx_data.direction = DMA_TO_DEVICE;
994 espi->dma_tx_data.name = "ep93xx-spi-tx";
995
996 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
997 &espi->dma_tx_data);
998 if (!espi->dma_tx) {
999 ret = -ENODEV;
1000 goto fail_release_rx;
1001 }
1002
1003 return 0;
1004
1005fail_release_rx:
1006 dma_release_channel(espi->dma_rx);
1007 espi->dma_rx = NULL;
1008fail_free_page:
1009 free_page((unsigned long)espi->zeropage);
1010
1011 return ret;
1012}
1013
1014static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
1015{
1016 if (espi->dma_rx) {
1017 dma_release_channel(espi->dma_rx);
1018 sg_free_table(&espi->rx_sgt);
1019 }
1020 if (espi->dma_tx) {
1021 dma_release_channel(espi->dma_tx);
1022 sg_free_table(&espi->tx_sgt);
1023 }
1024
1025 if (espi->zeropage)
1026 free_page((unsigned long)espi->zeropage);
1027}
1028
Grant Likely940ab882011-10-05 11:29:49 -06001029static int __devinit ep93xx_spi_probe(struct platform_device *pdev)
Mika Westerberg011f23a2010-05-06 04:47:04 +00001030{
1031 struct spi_master *master;
1032 struct ep93xx_spi_info *info;
1033 struct ep93xx_spi *espi;
1034 struct resource *res;
1035 int error;
1036
1037 info = pdev->dev.platform_data;
1038
1039 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
1040 if (!master) {
1041 dev_err(&pdev->dev, "failed to allocate spi master\n");
1042 return -ENOMEM;
1043 }
1044
1045 master->setup = ep93xx_spi_setup;
1046 master->transfer = ep93xx_spi_transfer;
1047 master->cleanup = ep93xx_spi_cleanup;
1048 master->bus_num = pdev->id;
1049 master->num_chipselect = info->num_chipselect;
1050 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1051
1052 platform_set_drvdata(pdev, master);
1053
1054 espi = spi_master_get_devdata(master);
1055
1056 espi->clk = clk_get(&pdev->dev, NULL);
1057 if (IS_ERR(espi->clk)) {
1058 dev_err(&pdev->dev, "unable to get spi clock\n");
1059 error = PTR_ERR(espi->clk);
1060 goto fail_release_master;
1061 }
1062
1063 spin_lock_init(&espi->lock);
1064 init_completion(&espi->wait);
1065
1066 /*
1067 * Calculate maximum and minimum supported clock rates
1068 * for the controller.
1069 */
1070 espi->max_rate = clk_get_rate(espi->clk) / 2;
1071 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
1072 espi->pdev = pdev;
1073
1074 espi->irq = platform_get_irq(pdev, 0);
1075 if (espi->irq < 0) {
1076 error = -EBUSY;
1077 dev_err(&pdev->dev, "failed to get irq resources\n");
1078 goto fail_put_clock;
1079 }
1080
1081 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082 if (!res) {
1083 dev_err(&pdev->dev, "unable to get iomem resource\n");
1084 error = -ENODEV;
1085 goto fail_put_clock;
1086 }
1087
1088 res = request_mem_region(res->start, resource_size(res), pdev->name);
1089 if (!res) {
1090 dev_err(&pdev->dev, "unable to request iomem resources\n");
1091 error = -EBUSY;
1092 goto fail_put_clock;
1093 }
1094
Mika Westerberg626a96d2011-05-29 13:10:06 +03001095 espi->sspdr_phys = res->start + SSPDR;
Mika Westerberg011f23a2010-05-06 04:47:04 +00001096 espi->regs_base = ioremap(res->start, resource_size(res));
1097 if (!espi->regs_base) {
1098 dev_err(&pdev->dev, "failed to map resources\n");
1099 error = -ENODEV;
1100 goto fail_free_mem;
1101 }
1102
1103 error = request_irq(espi->irq, ep93xx_spi_interrupt, 0,
1104 "ep93xx-spi", espi);
1105 if (error) {
1106 dev_err(&pdev->dev, "failed to request irq\n");
1107 goto fail_unmap_regs;
1108 }
1109
Mika Westerberg626a96d2011-05-29 13:10:06 +03001110 if (info->use_dma && ep93xx_spi_setup_dma(espi))
1111 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
1112
Mika Westerberg011f23a2010-05-06 04:47:04 +00001113 espi->wq = create_singlethread_workqueue("ep93xx_spid");
1114 if (!espi->wq) {
1115 dev_err(&pdev->dev, "unable to create workqueue\n");
Mika Westerberg626a96d2011-05-29 13:10:06 +03001116 goto fail_free_dma;
Mika Westerberg011f23a2010-05-06 04:47:04 +00001117 }
1118 INIT_WORK(&espi->msg_work, ep93xx_spi_work);
1119 INIT_LIST_HEAD(&espi->msg_queue);
1120 espi->running = true;
1121
1122 /* make sure that the hardware is disabled */
1123 ep93xx_spi_write_u8(espi, SSPCR1, 0);
1124
1125 error = spi_register_master(master);
1126 if (error) {
1127 dev_err(&pdev->dev, "failed to register SPI master\n");
1128 goto fail_free_queue;
1129 }
1130
1131 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
1132 (unsigned long)res->start, espi->irq);
1133
1134 return 0;
1135
1136fail_free_queue:
1137 destroy_workqueue(espi->wq);
Mika Westerberg626a96d2011-05-29 13:10:06 +03001138fail_free_dma:
1139 ep93xx_spi_release_dma(espi);
Mika Westerberg011f23a2010-05-06 04:47:04 +00001140 free_irq(espi->irq, espi);
1141fail_unmap_regs:
1142 iounmap(espi->regs_base);
1143fail_free_mem:
1144 release_mem_region(res->start, resource_size(res));
1145fail_put_clock:
1146 clk_put(espi->clk);
1147fail_release_master:
1148 spi_master_put(master);
1149 platform_set_drvdata(pdev, NULL);
1150
1151 return error;
1152}
1153
Grant Likely940ab882011-10-05 11:29:49 -06001154static int __devexit ep93xx_spi_remove(struct platform_device *pdev)
Mika Westerberg011f23a2010-05-06 04:47:04 +00001155{
1156 struct spi_master *master = platform_get_drvdata(pdev);
1157 struct ep93xx_spi *espi = spi_master_get_devdata(master);
1158 struct resource *res;
1159
1160 spin_lock_irq(&espi->lock);
1161 espi->running = false;
1162 spin_unlock_irq(&espi->lock);
1163
1164 destroy_workqueue(espi->wq);
1165
1166 /*
1167 * Complete remaining messages with %-ESHUTDOWN status.
1168 */
1169 spin_lock_irq(&espi->lock);
1170 while (!list_empty(&espi->msg_queue)) {
1171 struct spi_message *msg;
1172
1173 msg = list_first_entry(&espi->msg_queue,
1174 struct spi_message, queue);
1175 list_del_init(&msg->queue);
1176 msg->status = -ESHUTDOWN;
1177 spin_unlock_irq(&espi->lock);
1178 msg->complete(msg->context);
1179 spin_lock_irq(&espi->lock);
1180 }
1181 spin_unlock_irq(&espi->lock);
1182
Mika Westerberg626a96d2011-05-29 13:10:06 +03001183 ep93xx_spi_release_dma(espi);
Mika Westerberg011f23a2010-05-06 04:47:04 +00001184 free_irq(espi->irq, espi);
1185 iounmap(espi->regs_base);
1186 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1187 release_mem_region(res->start, resource_size(res));
1188 clk_put(espi->clk);
1189 platform_set_drvdata(pdev, NULL);
1190
1191 spi_unregister_master(master);
1192 return 0;
1193}
1194
1195static struct platform_driver ep93xx_spi_driver = {
1196 .driver = {
1197 .name = "ep93xx-spi",
1198 .owner = THIS_MODULE,
1199 },
Grant Likely940ab882011-10-05 11:29:49 -06001200 .probe = ep93xx_spi_probe,
1201 .remove = __devexit_p(ep93xx_spi_remove),
Mika Westerberg011f23a2010-05-06 04:47:04 +00001202};
Grant Likely940ab882011-10-05 11:29:49 -06001203module_platform_driver(ep93xx_spi_driver);
Mika Westerberg011f23a2010-05-06 04:47:04 +00001204
1205MODULE_DESCRIPTION("EP93xx SPI Controller driver");
1206MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
1207MODULE_LICENSE("GPL");
1208MODULE_ALIAS("platform:ep93xx-spi");