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Vladimir Barinov310355c2008-02-18 11:40:22 +01001/*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
Vladimir Barinovd6b52032008-09-29 23:14:11 +04004 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
Vladimir Barinov310355c2008-02-18 11:40:22 +01005 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/device.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/clk.h>
18
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/initval.h>
23#include <sound/soc.h>
24
25#include "davinci-pcm.h"
26
27#define DAVINCI_MCBSP_DRR_REG 0x00
28#define DAVINCI_MCBSP_DXR_REG 0x04
29#define DAVINCI_MCBSP_SPCR_REG 0x08
30#define DAVINCI_MCBSP_RCR_REG 0x0c
31#define DAVINCI_MCBSP_XCR_REG 0x10
32#define DAVINCI_MCBSP_SRGR_REG 0x14
33#define DAVINCI_MCBSP_PCR_REG 0x24
34
35#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
36#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
37#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
38#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
39#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
40#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
41#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
42
43#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
44#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
45#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
46#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
47
48#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
49#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
50#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
51#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
52#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
53
54#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
55#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
56#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
57
58#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
59#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
60#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
61#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
Hugo Villeneuveb402dff2008-11-08 13:26:09 -050062#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
Vladimir Barinov310355c2008-02-18 11:40:22 +010063#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
64#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
65#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
66#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
67
68#define MOD_REG_BIT(val, mask, set) do { \
69 if (set) { \
70 val |= mask; \
71 } else { \
72 val &= ~mask; \
73 } \
74} while (0)
75
76enum {
77 DAVINCI_MCBSP_WORD_8 = 0,
78 DAVINCI_MCBSP_WORD_12,
79 DAVINCI_MCBSP_WORD_16,
80 DAVINCI_MCBSP_WORD_20,
81 DAVINCI_MCBSP_WORD_24,
82 DAVINCI_MCBSP_WORD_32,
83};
84
85static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
86 .name = "I2S PCM Stereo out",
87};
88
89static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
90 .name = "I2S PCM Stereo in",
91};
92
93struct davinci_mcbsp_dev {
94 void __iomem *base;
95 struct clk *clk;
96 struct davinci_pcm_dma_params *dma_params[2];
97};
98
99static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
100 int reg, u32 val)
101{
102 __raw_writel(val, dev->base + reg);
103}
104
105static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
106{
107 return __raw_readl(dev->base + reg);
108}
109
110static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
111{
112 struct snd_soc_pcm_runtime *rtd = substream->private_data;
113 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530114 struct snd_soc_device *socdev = rtd->socdev;
115 struct snd_soc_platform *platform = socdev->platform;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100116 u32 w;
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530117 int ret;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100118
119 /* Start the sample generator and enable transmitter/receiver */
120 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
121 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100122 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
123
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530124 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
125 /* Stop the DMA to avoid data loss */
126 /* while the transmitter is out of reset to handle XSYNCERR */
127 if (platform->pcm_ops->trigger) {
128 ret = platform->pcm_ops->trigger(substream,
129 SNDRV_PCM_TRIGGER_STOP);
130 if (ret < 0)
131 printk(KERN_DEBUG "Playback DMA stop failed\n");
132 }
133
134 /* Enable the transmitter */
135 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
136 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
137 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
138
139 /* wait for any unexpected frame sync error to occur */
140 udelay(100);
141
142 /* Disable the transmitter to clear any outstanding XSYNCERR */
143 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
144 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
145 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
146
147 /* Restart the DMA */
148 if (platform->pcm_ops->trigger) {
149 ret = platform->pcm_ops->trigger(substream,
150 SNDRV_PCM_TRIGGER_START);
151 if (ret < 0)
152 printk(KERN_DEBUG "Playback DMA start failed\n");
153 }
154 /* Enable the transmitter */
155 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
156 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
157 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
158
159 } else {
160
161 /* Enable the reciever */
162 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
163 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
164 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
165 }
166
167
Vladimir Barinov310355c2008-02-18 11:40:22 +0100168 /* Start frame sync */
169 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
170 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
171 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
172}
173
174static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
175{
176 struct snd_soc_pcm_runtime *rtd = substream->private_data;
177 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
178 u32 w;
179
180 /* Reset transmitter/receiver and sample rate/frame sync generators */
181 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
182 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
183 DAVINCI_MCBSP_SPCR_FRST, 0);
184 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
185 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
186 else
187 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
188 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
189}
190
Mark Browndee89c42008-11-18 22:11:38 +0000191static int davinci_i2s_startup(struct snd_pcm_substream *substream,
192 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100193{
194 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100195 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100196 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
197
198 cpu_dai->dma_data = dev->dma_params[substream->stream];
199
200 return 0;
201}
202
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100203static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
Vladimir Barinov310355c2008-02-18 11:40:22 +0100204 unsigned int fmt)
205{
206 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
207 u32 w;
208
209 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
210 case SND_SOC_DAIFMT_CBS_CFS:
211 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
212 DAVINCI_MCBSP_PCR_FSXM |
213 DAVINCI_MCBSP_PCR_FSRM |
214 DAVINCI_MCBSP_PCR_CLKXM |
215 DAVINCI_MCBSP_PCR_CLKRM);
216 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
217 DAVINCI_MCBSP_SRGR_FSGM);
218 break;
Hugo Villeneuveb402dff2008-11-08 13:26:09 -0500219 case SND_SOC_DAIFMT_CBM_CFS:
220 /* McBSP CLKR pin is the input for the Sample Rate Generator.
221 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
222 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
223 DAVINCI_MCBSP_PCR_SCLKME |
224 DAVINCI_MCBSP_PCR_FSXM |
225 DAVINCI_MCBSP_PCR_FSRM);
226 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
227 DAVINCI_MCBSP_SRGR_FSGM);
228 break;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100229 case SND_SOC_DAIFMT_CBM_CFM:
230 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
231 break;
232 default:
233 return -EINVAL;
234 }
235
236 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
237 case SND_SOC_DAIFMT_IB_NF:
238 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
239 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
240 DAVINCI_MCBSP_PCR_CLKRP, 1);
241 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
242 break;
243 case SND_SOC_DAIFMT_NB_IF:
244 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
245 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP |
246 DAVINCI_MCBSP_PCR_FSRP, 1);
247 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
248 break;
249 case SND_SOC_DAIFMT_IB_IF:
250 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
251 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
252 DAVINCI_MCBSP_PCR_CLKRP |
253 DAVINCI_MCBSP_PCR_FSXP |
254 DAVINCI_MCBSP_PCR_FSRP, 1);
255 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
256 break;
257 case SND_SOC_DAIFMT_NB_NF:
258 break;
259 default:
260 return -EINVAL;
261 }
262
Hugo Villeneuveb402dff2008-11-08 13:26:09 -0500263 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
264 case SND_SOC_DAIFMT_RIGHT_J:
265 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
266 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
267 DAVINCI_MCBSP_RCR_RDATDLY(0));
268 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
269 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
270 DAVINCI_MCBSP_XCR_XDATDLY(0) |
271 DAVINCI_MCBSP_XCR_XFIG);
272 break;
273 case SND_SOC_DAIFMT_I2S:
274 default:
275 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
276 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
277 DAVINCI_MCBSP_RCR_RDATDLY(1));
278 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
279 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
280 DAVINCI_MCBSP_XCR_XDATDLY(1) |
281 DAVINCI_MCBSP_XCR_XFIG);
282 break;
283 }
284
Vladimir Barinov310355c2008-02-18 11:40:22 +0100285 return 0;
286}
287
288static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +0000289 struct snd_pcm_hw_params *params,
290 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100291{
292 struct snd_soc_pcm_runtime *rtd = substream->private_data;
293 struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
294 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
295 struct snd_interval *i = NULL;
296 int mcbsp_word_length;
297 u32 w;
298
299 /* general line settings */
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530300 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
301 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
302 w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
303 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
304 } else {
305 w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
306 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
307 }
Vladimir Barinov310355c2008-02-18 11:40:22 +0100308
309 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
310 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
311 MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
312 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
313
314 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
315 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
316 MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
317 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
318
319 /* Determine xfer data type */
320 switch (params_format(params)) {
321 case SNDRV_PCM_FORMAT_S8:
322 dma_params->data_type = 1;
323 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
324 break;
325 case SNDRV_PCM_FORMAT_S16_LE:
326 dma_params->data_type = 2;
327 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
328 break;
329 case SNDRV_PCM_FORMAT_S32_LE:
330 dma_params->data_type = 4;
331 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
332 break;
333 default:
Jean Delvare9b6e12e2008-08-26 15:47:55 +0200334 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
Vladimir Barinov310355c2008-02-18 11:40:22 +0100335 return -EINVAL;
336 }
337
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530338 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
339 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
340 MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
341 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
342 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100343
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530344 } else {
345 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
346 MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
347 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
348 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100349
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530350 }
Vladimir Barinov310355c2008-02-18 11:40:22 +0100351 return 0;
352}
353
Mark Browndee89c42008-11-18 22:11:38 +0000354static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
355 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100356{
357 int ret = 0;
358
359 switch (cmd) {
360 case SNDRV_PCM_TRIGGER_START:
361 case SNDRV_PCM_TRIGGER_RESUME:
362 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
363 davinci_mcbsp_start(substream);
364 break;
365 case SNDRV_PCM_TRIGGER_STOP:
366 case SNDRV_PCM_TRIGGER_SUSPEND:
367 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
368 davinci_mcbsp_stop(substream);
369 break;
370 default:
371 ret = -EINVAL;
372 }
373
374 return ret;
375}
376
Mark Brownbdb92872008-06-11 13:47:10 +0100377static int davinci_i2s_probe(struct platform_device *pdev,
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100378 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100379{
380 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown87506542008-11-18 20:50:34 +0000381 struct snd_soc_card *card = socdev->card;
382 struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100383 struct davinci_mcbsp_dev *dev;
384 struct resource *mem, *ioarea;
385 struct evm_snd_platform_data *pdata;
386 int ret;
387
388 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
389 if (!mem) {
390 dev_err(&pdev->dev, "no mem resource?\n");
391 return -ENODEV;
392 }
393
394 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
395 pdev->name);
396 if (!ioarea) {
397 dev_err(&pdev->dev, "McBSP region already claimed\n");
398 return -EBUSY;
399 }
400
401 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
402 if (!dev) {
403 ret = -ENOMEM;
404 goto err_release_region;
405 }
406
407 cpu_dai->private_data = dev;
408
409 dev->clk = clk_get(&pdev->dev, "McBSPCLK");
410 if (IS_ERR(dev->clk)) {
411 ret = -ENODEV;
412 goto err_free_mem;
413 }
414 clk_enable(dev->clk);
415
416 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
417 pdata = pdev->dev.platform_data;
418
419 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
420 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
421 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
422 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
423
424 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
425 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
426 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
427 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
428
429 return 0;
430
431err_free_mem:
432 kfree(dev);
433err_release_region:
434 release_mem_region(mem->start, (mem->end - mem->start) + 1);
435
436 return ret;
437}
438
Mark Brownbdb92872008-06-11 13:47:10 +0100439static void davinci_i2s_remove(struct platform_device *pdev,
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100440 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100441{
442 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown87506542008-11-18 20:50:34 +0000443 struct snd_soc_card *card = socdev->card;
444 struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100445 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
446 struct resource *mem;
447
448 clk_disable(dev->clk);
449 clk_put(dev->clk);
450 dev->clk = NULL;
451
452 kfree(dev);
453
454 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
455 release_mem_region(mem->start, (mem->end - mem->start) + 1);
456}
457
458#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
459
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100460struct snd_soc_dai davinci_i2s_dai = {
Vladimir Barinov310355c2008-02-18 11:40:22 +0100461 .name = "davinci-i2s",
462 .id = 0,
463 .type = SND_SOC_DAI_I2S,
464 .probe = davinci_i2s_probe,
465 .remove = davinci_i2s_remove,
466 .playback = {
467 .channels_min = 2,
468 .channels_max = 2,
469 .rates = DAVINCI_I2S_RATES,
470 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
471 .capture = {
472 .channels_min = 2,
473 .channels_max = 2,
474 .rates = DAVINCI_I2S_RATES,
475 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
476 .ops = {
477 .startup = davinci_i2s_startup,
478 .trigger = davinci_i2s_trigger,
Mark Browndee89c42008-11-18 22:11:38 +0000479 .hw_params = davinci_i2s_hw_params,
Vladimir Barinov310355c2008-02-18 11:40:22 +0100480 .set_fmt = davinci_i2s_set_dai_fmt,
481 },
482};
483EXPORT_SYMBOL_GPL(davinci_i2s_dai);
484
485MODULE_AUTHOR("Vladimir Barinov");
486MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
487MODULE_LICENSE("GPL");