Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/console.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include <drm/drmP.h> |
| 31 | #include <drm/drm_crtc_helper.h> |
| 32 | #include <drm/radeon_drm.h> |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 34 | #include <linux/vga_switcheroo.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 35 | #include "radeon_reg.h" |
| 36 | #include "radeon.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | #include "atom.h" |
| 38 | |
Jerome Glisse | 1b5331d | 2010-04-12 20:21:53 +0000 | [diff] [blame] | 39 | static const char radeon_family_name[][16] = { |
| 40 | "R100", |
| 41 | "RV100", |
| 42 | "RS100", |
| 43 | "RV200", |
| 44 | "RS200", |
| 45 | "R200", |
| 46 | "RV250", |
| 47 | "RS300", |
| 48 | "RV280", |
| 49 | "R300", |
| 50 | "R350", |
| 51 | "RV350", |
| 52 | "RV380", |
| 53 | "R420", |
| 54 | "R423", |
| 55 | "RV410", |
| 56 | "RS400", |
| 57 | "RS480", |
| 58 | "RS600", |
| 59 | "RS690", |
| 60 | "RS740", |
| 61 | "RV515", |
| 62 | "R520", |
| 63 | "RV530", |
| 64 | "RV560", |
| 65 | "RV570", |
| 66 | "R580", |
| 67 | "R600", |
| 68 | "RV610", |
| 69 | "RV630", |
| 70 | "RV670", |
| 71 | "RV620", |
| 72 | "RV635", |
| 73 | "RS780", |
| 74 | "RS880", |
| 75 | "RV770", |
| 76 | "RV730", |
| 77 | "RV710", |
| 78 | "RV740", |
| 79 | "CEDAR", |
| 80 | "REDWOOD", |
| 81 | "JUNIPER", |
| 82 | "CYPRESS", |
| 83 | "HEMLOCK", |
| 84 | "LAST", |
| 85 | }; |
| 86 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 87 | /* |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 88 | * Clear GPU surface registers. |
| 89 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 90 | void radeon_surface_init(struct radeon_device *rdev) |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 91 | { |
| 92 | /* FIXME: check this out */ |
| 93 | if (rdev->family < CHIP_R600) { |
| 94 | int i; |
| 95 | |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 96 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
| 97 | if (rdev->surface_regs[i].bo) |
| 98 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
| 99 | else |
| 100 | radeon_clear_surface_reg(rdev, i); |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 101 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 102 | /* enable surfaces */ |
| 103 | WREG32(RADEON_SURFACE_CNTL, 0); |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 104 | } |
| 105 | } |
| 106 | |
| 107 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 108 | * GPU scratch registers helpers function. |
| 109 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 110 | void radeon_scratch_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 111 | { |
| 112 | int i; |
| 113 | |
| 114 | /* FIXME: check this out */ |
| 115 | if (rdev->family < CHIP_R300) { |
| 116 | rdev->scratch.num_reg = 5; |
| 117 | } else { |
| 118 | rdev->scratch.num_reg = 7; |
| 119 | } |
| 120 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 121 | rdev->scratch.free[i] = true; |
| 122 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
| 127 | { |
| 128 | int i; |
| 129 | |
| 130 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 131 | if (rdev->scratch.free[i]) { |
| 132 | rdev->scratch.free[i] = false; |
| 133 | *reg = rdev->scratch.reg[i]; |
| 134 | return 0; |
| 135 | } |
| 136 | } |
| 137 | return -EINVAL; |
| 138 | } |
| 139 | |
| 140 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
| 141 | { |
| 142 | int i; |
| 143 | |
| 144 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 145 | if (rdev->scratch.reg[i] == reg) { |
| 146 | rdev->scratch.free[i] = true; |
| 147 | return; |
| 148 | } |
| 149 | } |
| 150 | } |
| 151 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 152 | /** |
| 153 | * radeon_vram_location - try to find VRAM location |
| 154 | * @rdev: radeon device structure holding all necessary informations |
| 155 | * @mc: memory controller structure holding memory informations |
| 156 | * @base: base address at which to put VRAM |
| 157 | * |
| 158 | * Function will place try to place VRAM at base address provided |
| 159 | * as parameter (which is so far either PCI aperture address or |
| 160 | * for IGP TOM base address). |
| 161 | * |
| 162 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
| 163 | * address space then we limit the VRAM size to the aperture. |
| 164 | * |
| 165 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
| 166 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
| 167 | * size and print a warning. |
| 168 | * |
| 169 | * This function will never fails, worst case are limiting VRAM. |
| 170 | * |
| 171 | * Note: GTT start, end, size should be initialized before calling this |
| 172 | * function on AGP platform. |
| 173 | * |
| 174 | * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, |
| 175 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
| 176 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
| 177 | * not IGP. |
| 178 | * |
| 179 | * Note: we use mc_vram_size as on some board we need to program the mc to |
| 180 | * cover the whole aperture even if VRAM size is inferior to aperture size |
| 181 | * Novell bug 204882 + along with lots of ubuntu ones |
| 182 | * |
| 183 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
| 184 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
| 185 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
| 186 | * ones) |
| 187 | * |
| 188 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
| 189 | * explicitly check for that thought. |
| 190 | * |
| 191 | * FIXME: when reducing VRAM size align new size on power of 2. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 192 | */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 193 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 194 | { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 195 | mc->vram_start = base; |
| 196 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
| 197 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
| 198 | mc->real_vram_size = mc->aper_size; |
| 199 | mc->mc_vram_size = mc->aper_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 200 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 201 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
| 202 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { |
| 203 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
| 204 | mc->real_vram_size = mc->aper_size; |
| 205 | mc->mc_vram_size = mc->aper_size; |
| 206 | } |
| 207 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
| 208 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
| 209 | mc->mc_vram_size >> 20, mc->vram_start, |
| 210 | mc->vram_end, mc->real_vram_size >> 20); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 211 | } |
| 212 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 213 | /** |
| 214 | * radeon_gtt_location - try to find GTT location |
| 215 | * @rdev: radeon device structure holding all necessary informations |
| 216 | * @mc: memory controller structure holding memory informations |
| 217 | * |
| 218 | * Function will place try to place GTT before or after VRAM. |
| 219 | * |
| 220 | * If GTT size is bigger than space left then we ajust GTT size. |
| 221 | * Thus function will never fails. |
| 222 | * |
| 223 | * FIXME: when reducing GTT size align new size on power of 2. |
| 224 | */ |
| 225 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
| 226 | { |
| 227 | u64 size_af, size_bf; |
| 228 | |
| 229 | size_af = 0xFFFFFFFF - mc->vram_end; |
| 230 | size_bf = mc->vram_start; |
| 231 | if (size_bf > size_af) { |
| 232 | if (mc->gtt_size > size_bf) { |
| 233 | dev_warn(rdev->dev, "limiting GTT\n"); |
| 234 | mc->gtt_size = size_bf; |
| 235 | } |
| 236 | mc->gtt_start = mc->vram_start - mc->gtt_size; |
| 237 | } else { |
| 238 | if (mc->gtt_size > size_af) { |
| 239 | dev_warn(rdev->dev, "limiting GTT\n"); |
| 240 | mc->gtt_size = size_af; |
| 241 | } |
| 242 | mc->gtt_start = mc->vram_end + 1; |
| 243 | } |
| 244 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
| 245 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", |
| 246 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
| 247 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 248 | |
| 249 | /* |
| 250 | * GPU helpers function. |
| 251 | */ |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 252 | bool radeon_card_posted(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 253 | { |
| 254 | uint32_t reg; |
| 255 | |
| 256 | /* first check CRTCs */ |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 257 | if (ASIC_IS_DCE4(rdev)) { |
| 258 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
| 259 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
| 260 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
| 261 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
| 262 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
| 263 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
| 264 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
| 265 | return true; |
| 266 | } else if (ASIC_IS_AVIVO(rdev)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 267 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
| 268 | RREG32(AVIVO_D2CRTC_CONTROL); |
| 269 | if (reg & AVIVO_CRTC_EN) { |
| 270 | return true; |
| 271 | } |
| 272 | } else { |
| 273 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
| 274 | RREG32(RADEON_CRTC2_GEN_CNTL); |
| 275 | if (reg & RADEON_CRTC_EN) { |
| 276 | return true; |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | /* then check MEM_SIZE, in case the crtcs are off */ |
| 281 | if (rdev->family >= CHIP_R600) |
| 282 | reg = RREG32(R600_CONFIG_MEMSIZE); |
| 283 | else |
| 284 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
| 285 | |
| 286 | if (reg) |
| 287 | return true; |
| 288 | |
| 289 | return false; |
| 290 | |
| 291 | } |
| 292 | |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 293 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
| 294 | { |
| 295 | fixed20_12 a; |
| 296 | u32 sclk, mclk; |
| 297 | |
| 298 | if (rdev->flags & RADEON_IS_IGP) { |
| 299 | sclk = radeon_get_engine_clock(rdev); |
| 300 | mclk = rdev->clock.default_mclk; |
| 301 | |
| 302 | a.full = rfixed_const(100); |
| 303 | rdev->pm.sclk.full = rfixed_const(sclk); |
| 304 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
| 305 | rdev->pm.mclk.full = rfixed_const(mclk); |
| 306 | rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); |
| 307 | |
| 308 | a.full = rfixed_const(16); |
| 309 | /* core_bandwidth = sclk(Mhz) * 16 */ |
| 310 | rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); |
| 311 | } else { |
| 312 | sclk = radeon_get_engine_clock(rdev); |
| 313 | mclk = radeon_get_memory_clock(rdev); |
| 314 | |
| 315 | a.full = rfixed_const(100); |
| 316 | rdev->pm.sclk.full = rfixed_const(sclk); |
| 317 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
| 318 | rdev->pm.mclk.full = rfixed_const(mclk); |
| 319 | rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); |
| 320 | } |
| 321 | } |
| 322 | |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 323 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
| 324 | { |
| 325 | if (radeon_card_posted(rdev)) |
| 326 | return true; |
| 327 | |
| 328 | if (rdev->bios) { |
| 329 | DRM_INFO("GPU not posted. posting now...\n"); |
| 330 | if (rdev->is_atom_bios) |
| 331 | atom_asic_init(rdev->mode_info.atom_context); |
| 332 | else |
| 333 | radeon_combios_asic_init(rdev->ddev); |
| 334 | return true; |
| 335 | } else { |
| 336 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
| 337 | return false; |
| 338 | } |
| 339 | } |
| 340 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 341 | int radeon_dummy_page_init(struct radeon_device *rdev) |
| 342 | { |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 343 | if (rdev->dummy_page.page) |
| 344 | return 0; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 345 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
| 346 | if (rdev->dummy_page.page == NULL) |
| 347 | return -ENOMEM; |
| 348 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, |
| 349 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 350 | if (!rdev->dummy_page.addr) { |
| 351 | __free_page(rdev->dummy_page.page); |
| 352 | rdev->dummy_page.page = NULL; |
| 353 | return -ENOMEM; |
| 354 | } |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
| 359 | { |
| 360 | if (rdev->dummy_page.page == NULL) |
| 361 | return; |
| 362 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, |
| 363 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 364 | __free_page(rdev->dummy_page.page); |
| 365 | rdev->dummy_page.page = NULL; |
| 366 | } |
| 367 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 368 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 369 | /* ATOM accessor methods */ |
| 370 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
| 371 | { |
| 372 | struct radeon_device *rdev = info->dev->dev_private; |
| 373 | uint32_t r; |
| 374 | |
| 375 | r = rdev->pll_rreg(rdev, reg); |
| 376 | return r; |
| 377 | } |
| 378 | |
| 379 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 380 | { |
| 381 | struct radeon_device *rdev = info->dev->dev_private; |
| 382 | |
| 383 | rdev->pll_wreg(rdev, reg, val); |
| 384 | } |
| 385 | |
| 386 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
| 387 | { |
| 388 | struct radeon_device *rdev = info->dev->dev_private; |
| 389 | uint32_t r; |
| 390 | |
| 391 | r = rdev->mc_rreg(rdev, reg); |
| 392 | return r; |
| 393 | } |
| 394 | |
| 395 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 396 | { |
| 397 | struct radeon_device *rdev = info->dev->dev_private; |
| 398 | |
| 399 | rdev->mc_wreg(rdev, reg, val); |
| 400 | } |
| 401 | |
| 402 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 403 | { |
| 404 | struct radeon_device *rdev = info->dev->dev_private; |
| 405 | |
| 406 | WREG32(reg*4, val); |
| 407 | } |
| 408 | |
| 409 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
| 410 | { |
| 411 | struct radeon_device *rdev = info->dev->dev_private; |
| 412 | uint32_t r; |
| 413 | |
| 414 | r = RREG32(reg*4); |
| 415 | return r; |
| 416 | } |
| 417 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 418 | int radeon_atombios_init(struct radeon_device *rdev) |
| 419 | { |
Mathias Fröhlich | 61c4b24 | 2009-10-27 15:08:01 -0400 | [diff] [blame] | 420 | struct card_info *atom_card_info = |
| 421 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
| 422 | |
| 423 | if (!atom_card_info) |
| 424 | return -ENOMEM; |
| 425 | |
| 426 | rdev->mode_info.atom_card_info = atom_card_info; |
| 427 | atom_card_info->dev = rdev->ddev; |
| 428 | atom_card_info->reg_read = cail_reg_read; |
| 429 | atom_card_info->reg_write = cail_reg_write; |
| 430 | atom_card_info->mc_read = cail_mc_read; |
| 431 | atom_card_info->mc_write = cail_mc_write; |
| 432 | atom_card_info->pll_read = cail_pll_read; |
| 433 | atom_card_info->pll_write = cail_pll_write; |
| 434 | |
| 435 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
Rafał Miłecki | c31ad97 | 2009-12-17 00:00:46 +0100 | [diff] [blame] | 436 | mutex_init(&rdev->mode_info.atom_context->mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 437 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
Dave Airlie | d904ef9 | 2009-11-17 06:29:46 +1000 | [diff] [blame] | 438 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | void radeon_atombios_fini(struct radeon_device *rdev) |
| 443 | { |
Jerome Glisse | 4a04a84 | 2009-12-09 17:39:16 +0100 | [diff] [blame] | 444 | if (rdev->mode_info.atom_context) { |
| 445 | kfree(rdev->mode_info.atom_context->scratch); |
| 446 | kfree(rdev->mode_info.atom_context); |
| 447 | } |
Mathias Fröhlich | 61c4b24 | 2009-10-27 15:08:01 -0400 | [diff] [blame] | 448 | kfree(rdev->mode_info.atom_card_info); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 449 | } |
| 450 | |
| 451 | int radeon_combios_init(struct radeon_device *rdev) |
| 452 | { |
| 453 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
| 454 | return 0; |
| 455 | } |
| 456 | |
| 457 | void radeon_combios_fini(struct radeon_device *rdev) |
| 458 | { |
| 459 | } |
| 460 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 461 | /* if we get transitioned to only one device, tak VGA back */ |
| 462 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
| 463 | { |
| 464 | struct radeon_device *rdev = cookie; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 465 | radeon_vga_set_state(rdev, state); |
| 466 | if (state) |
| 467 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 468 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 469 | else |
| 470 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 471 | } |
Dave Airlie | c1176d6 | 2009-10-08 14:03:05 +1000 | [diff] [blame] | 472 | |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 473 | void radeon_check_arguments(struct radeon_device *rdev) |
| 474 | { |
| 475 | /* vramlimit must be a power of two */ |
| 476 | switch (radeon_vram_limit) { |
| 477 | case 0: |
| 478 | case 4: |
| 479 | case 8: |
| 480 | case 16: |
| 481 | case 32: |
| 482 | case 64: |
| 483 | case 128: |
| 484 | case 256: |
| 485 | case 512: |
| 486 | case 1024: |
| 487 | case 2048: |
| 488 | case 4096: |
| 489 | break; |
| 490 | default: |
| 491 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
| 492 | radeon_vram_limit); |
| 493 | radeon_vram_limit = 0; |
| 494 | break; |
| 495 | } |
| 496 | radeon_vram_limit = radeon_vram_limit << 20; |
| 497 | /* gtt size must be power of two and greater or equal to 32M */ |
| 498 | switch (radeon_gart_size) { |
| 499 | case 4: |
| 500 | case 8: |
| 501 | case 16: |
| 502 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
| 503 | radeon_gart_size); |
| 504 | radeon_gart_size = 512; |
| 505 | break; |
| 506 | case 32: |
| 507 | case 64: |
| 508 | case 128: |
| 509 | case 256: |
| 510 | case 512: |
| 511 | case 1024: |
| 512 | case 2048: |
| 513 | case 4096: |
| 514 | break; |
| 515 | default: |
| 516 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
| 517 | radeon_gart_size); |
| 518 | radeon_gart_size = 512; |
| 519 | break; |
| 520 | } |
| 521 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| 522 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
| 523 | switch (radeon_agpmode) { |
| 524 | case -1: |
| 525 | case 0: |
| 526 | case 1: |
| 527 | case 2: |
| 528 | case 4: |
| 529 | case 8: |
| 530 | break; |
| 531 | default: |
| 532 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
| 533 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
| 534 | radeon_agpmode = 0; |
| 535 | break; |
| 536 | } |
| 537 | } |
| 538 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 539 | static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
| 540 | { |
| 541 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 542 | struct radeon_device *rdev = dev->dev_private; |
| 543 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
| 544 | if (state == VGA_SWITCHEROO_ON) { |
| 545 | printk(KERN_INFO "radeon: switched on\n"); |
| 546 | /* don't suspend or resume card normally */ |
| 547 | rdev->powered_down = false; |
| 548 | radeon_resume_kms(dev); |
| 549 | } else { |
| 550 | printk(KERN_INFO "radeon: switched off\n"); |
| 551 | radeon_suspend_kms(dev, pmm); |
| 552 | /* don't suspend or resume card normally */ |
| 553 | rdev->powered_down = true; |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) |
| 558 | { |
| 559 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 560 | bool can_switch; |
| 561 | |
| 562 | spin_lock(&dev->count_lock); |
| 563 | can_switch = (dev->open_count == 0); |
| 564 | spin_unlock(&dev->count_lock); |
| 565 | return can_switch; |
| 566 | } |
| 567 | |
| 568 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 569 | int radeon_device_init(struct radeon_device *rdev, |
| 570 | struct drm_device *ddev, |
| 571 | struct pci_dev *pdev, |
| 572 | uint32_t flags) |
| 573 | { |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 574 | int r; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 575 | int dma_bits; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 576 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 577 | rdev->shutdown = false; |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 578 | rdev->dev = &pdev->dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 579 | rdev->ddev = ddev; |
| 580 | rdev->pdev = pdev; |
| 581 | rdev->flags = flags; |
| 582 | rdev->family = flags & RADEON_FAMILY_MASK; |
| 583 | rdev->is_atom_bios = false; |
| 584 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
| 585 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| 586 | rdev->gpu_lockup = false; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 587 | rdev->accel_working = false; |
Jerome Glisse | 1b5331d | 2010-04-12 20:21:53 +0000 | [diff] [blame] | 588 | |
| 589 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", |
| 590 | radeon_family_name[rdev->family], pdev->vendor, pdev->device); |
| 591 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 592 | /* mutex initialization are all done here so we |
| 593 | * can recall function without having locking issues */ |
| 594 | mutex_init(&rdev->cs_mutex); |
| 595 | mutex_init(&rdev->ib_pool.mutex); |
| 596 | mutex_init(&rdev->cp.mutex); |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 597 | mutex_init(&rdev->dc_hw_i2c_mutex); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 598 | if (rdev->family >= CHIP_R600) |
| 599 | spin_lock_init(&rdev->ih.lock); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 600 | mutex_init(&rdev->gem.mutex); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 601 | mutex_init(&rdev->pm.mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 602 | rwlock_init(&rdev->fence_drv.lock); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 603 | INIT_LIST_HEAD(&rdev->gem.objects); |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 604 | init_waitqueue_head(&rdev->irq.vblank_queue); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 605 | |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 606 | /* setup workqueue */ |
| 607 | rdev->wq = create_workqueue("radeon"); |
| 608 | if (rdev->wq == NULL) |
| 609 | return -ENOMEM; |
| 610 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 611 | /* Set asic functions */ |
| 612 | r = radeon_asic_init(rdev); |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 613 | if (r) |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 614 | return r; |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 615 | radeon_check_arguments(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 616 | |
Alex Deucher | f95df9c | 2010-03-21 14:02:25 -0400 | [diff] [blame] | 617 | /* all of the newer IGP chips have an internal gart |
| 618 | * However some rs4xx report as AGP, so remove that here. |
| 619 | */ |
| 620 | if ((rdev->family >= CHIP_RS400) && |
| 621 | (rdev->flags & RADEON_IS_IGP)) { |
| 622 | rdev->flags &= ~RADEON_IS_AGP; |
| 623 | } |
| 624 | |
Jerome Glisse | 30256a3 | 2009-11-30 17:47:59 +0100 | [diff] [blame] | 625 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 626 | radeon_agp_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 627 | } |
| 628 | |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 629 | /* set DMA mask + need_dma32 flags. |
| 630 | * PCIE - can handle 40-bits. |
| 631 | * IGP - can handle 40-bits (in theory) |
| 632 | * AGP - generally dma32 is safest |
| 633 | * PCI - only dma32 |
| 634 | */ |
| 635 | rdev->need_dma32 = false; |
| 636 | if (rdev->flags & RADEON_IS_AGP) |
| 637 | rdev->need_dma32 = true; |
| 638 | if (rdev->flags & RADEON_IS_PCI) |
| 639 | rdev->need_dma32 = true; |
| 640 | |
| 641 | dma_bits = rdev->need_dma32 ? 32 : 40; |
| 642 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 643 | if (r) { |
| 644 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
| 645 | } |
| 646 | |
| 647 | /* Registers mapping */ |
| 648 | /* TODO: block userspace mapping of io register */ |
| 649 | rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); |
| 650 | rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); |
| 651 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
| 652 | if (rdev->rmmio == NULL) { |
| 653 | return -ENOMEM; |
| 654 | } |
| 655 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
| 656 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
| 657 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 658 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
Dave Airlie | 93239ea | 2009-10-28 11:09:58 +1000 | [diff] [blame] | 659 | /* this will fail for cards that aren't VGA class devices, just |
| 660 | * ignore it */ |
| 661 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 662 | vga_switcheroo_register_client(rdev->pdev, |
| 663 | radeon_switcheroo_set_state, |
| 664 | radeon_switcheroo_can_switch); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 665 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 666 | r = radeon_init(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 667 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 668 | return r; |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 669 | |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 670 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
| 671 | /* Acceleration not working on AGP card try again |
| 672 | * with fallback to PCI or PCIE GART |
| 673 | */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 674 | radeon_asic_reset(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 675 | radeon_fini(rdev); |
| 676 | radeon_agp_disable(rdev); |
| 677 | r = radeon_init(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 678 | if (r) |
| 679 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 680 | } |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 681 | if (radeon_testing) { |
| 682 | radeon_test_moves(rdev); |
| 683 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 684 | if (radeon_benchmarking) { |
| 685 | radeon_benchmark(rdev); |
| 686 | } |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 687 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 688 | } |
| 689 | |
| 690 | void radeon_device_fini(struct radeon_device *rdev) |
| 691 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 692 | DRM_INFO("radeon: finishing device.\n"); |
| 693 | rdev->shutdown = true; |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 694 | /* evict vram memory */ |
| 695 | radeon_bo_evict_vram(rdev); |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 696 | radeon_fini(rdev); |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 697 | destroy_workqueue(rdev->wq); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 698 | vga_switcheroo_unregister_client(rdev->pdev); |
Dave Airlie | c1176d6 | 2009-10-08 14:03:05 +1000 | [diff] [blame] | 699 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 700 | iounmap(rdev->rmmio); |
| 701 | rdev->rmmio = NULL; |
| 702 | } |
| 703 | |
| 704 | |
| 705 | /* |
| 706 | * Suspend & resume. |
| 707 | */ |
| 708 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) |
| 709 | { |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 710 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 711 | struct drm_crtc *crtc; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 712 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 713 | |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 714 | if (dev == NULL || dev->dev_private == NULL) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 715 | return -ENODEV; |
| 716 | } |
| 717 | if (state.event == PM_EVENT_PRETHAW) { |
| 718 | return 0; |
| 719 | } |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 720 | rdev = dev->dev_private; |
| 721 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 722 | if (rdev->powered_down) |
| 723 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 724 | /* unpin the front buffers */ |
| 725 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 726 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 727 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 728 | |
| 729 | if (rfb == NULL || rfb->obj == NULL) { |
| 730 | continue; |
| 731 | } |
| 732 | robj = rfb->obj->driver_private; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 733 | /* don't unpin kernel fb objects */ |
| 734 | if (!radeon_fbdev_robj_is_fb(rdev, robj)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 735 | r = radeon_bo_reserve(robj, false); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 736 | if (r == 0) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 737 | radeon_bo_unpin(robj); |
| 738 | radeon_bo_unreserve(robj); |
| 739 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 740 | } |
| 741 | } |
| 742 | /* evict vram memory */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 743 | radeon_bo_evict_vram(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 744 | /* wait for gpu to finish processing current batch */ |
| 745 | radeon_fence_wait_last(rdev); |
| 746 | |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 747 | radeon_save_bios_scratch_regs(rdev); |
| 748 | |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 749 | radeon_suspend(rdev); |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 750 | radeon_hpd_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 751 | /* evict remaining vram memory */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 752 | radeon_bo_evict_vram(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 753 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 754 | pci_save_state(dev->pdev); |
| 755 | if (state.event == PM_EVENT_SUSPEND) { |
| 756 | /* Shut down the device */ |
| 757 | pci_disable_device(dev->pdev); |
| 758 | pci_set_power_state(dev->pdev, PCI_D3hot); |
| 759 | } |
| 760 | acquire_console_sem(); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 761 | radeon_fbdev_set_suspend(rdev, 1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 762 | release_console_sem(); |
| 763 | return 0; |
| 764 | } |
| 765 | |
| 766 | int radeon_resume_kms(struct drm_device *dev) |
| 767 | { |
| 768 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 769 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 770 | if (rdev->powered_down) |
| 771 | return 0; |
| 772 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 773 | acquire_console_sem(); |
| 774 | pci_set_power_state(dev->pdev, PCI_D0); |
| 775 | pci_restore_state(dev->pdev); |
| 776 | if (pci_enable_device(dev->pdev)) { |
| 777 | release_console_sem(); |
| 778 | return -1; |
| 779 | } |
| 780 | pci_set_master(dev->pdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 781 | /* resume AGP if in use */ |
| 782 | radeon_agp_resume(rdev); |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 783 | radeon_resume(rdev); |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 784 | radeon_restore_bios_scratch_regs(rdev); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 785 | radeon_fbdev_set_suspend(rdev, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 786 | release_console_sem(); |
| 787 | |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 788 | /* reset hpd state */ |
| 789 | radeon_hpd_init(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 790 | /* blat the mode back in */ |
| 791 | drm_helper_resume_force_mode(dev); |
| 792 | return 0; |
| 793 | } |
| 794 | |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 795 | int radeon_gpu_reset(struct radeon_device *rdev) |
| 796 | { |
| 797 | int r; |
| 798 | |
| 799 | radeon_save_bios_scratch_regs(rdev); |
| 800 | radeon_suspend(rdev); |
| 801 | |
| 802 | r = radeon_asic_reset(rdev); |
| 803 | if (!r) { |
| 804 | dev_info(rdev->dev, "GPU reset succeed\n"); |
| 805 | radeon_resume(rdev); |
| 806 | radeon_restore_bios_scratch_regs(rdev); |
| 807 | drm_helper_resume_force_mode(rdev->ddev); |
| 808 | return 0; |
| 809 | } |
| 810 | /* bad news, how to tell it to userspace ? */ |
| 811 | dev_info(rdev->dev, "GPU reset failed\n"); |
| 812 | return r; |
| 813 | } |
| 814 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 815 | |
| 816 | /* |
| 817 | * Debugfs |
| 818 | */ |
| 819 | struct radeon_debugfs { |
| 820 | struct drm_info_list *files; |
| 821 | unsigned num_files; |
| 822 | }; |
| 823 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; |
| 824 | static unsigned _radeon_debugfs_count = 0; |
| 825 | |
| 826 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 827 | struct drm_info_list *files, |
| 828 | unsigned nfiles) |
| 829 | { |
| 830 | unsigned i; |
| 831 | |
| 832 | for (i = 0; i < _radeon_debugfs_count; i++) { |
| 833 | if (_radeon_debugfs[i].files == files) { |
| 834 | /* Already registered */ |
| 835 | return 0; |
| 836 | } |
| 837 | } |
| 838 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { |
| 839 | DRM_ERROR("Reached maximum number of debugfs files.\n"); |
| 840 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); |
| 841 | return -EINVAL; |
| 842 | } |
| 843 | _radeon_debugfs[_radeon_debugfs_count].files = files; |
| 844 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; |
| 845 | _radeon_debugfs_count++; |
| 846 | #if defined(CONFIG_DEBUG_FS) |
| 847 | drm_debugfs_create_files(files, nfiles, |
| 848 | rdev->ddev->control->debugfs_root, |
| 849 | rdev->ddev->control); |
| 850 | drm_debugfs_create_files(files, nfiles, |
| 851 | rdev->ddev->primary->debugfs_root, |
| 852 | rdev->ddev->primary); |
| 853 | #endif |
| 854 | return 0; |
| 855 | } |
| 856 | |
| 857 | #if defined(CONFIG_DEBUG_FS) |
| 858 | int radeon_debugfs_init(struct drm_minor *minor) |
| 859 | { |
| 860 | return 0; |
| 861 | } |
| 862 | |
| 863 | void radeon_debugfs_cleanup(struct drm_minor *minor) |
| 864 | { |
| 865 | unsigned i; |
| 866 | |
| 867 | for (i = 0; i < _radeon_debugfs_count; i++) { |
| 868 | drm_debugfs_remove_files(_radeon_debugfs[i].files, |
| 869 | _radeon_debugfs[i].num_files, minor); |
| 870 | } |
| 871 | } |
| 872 | #endif |