Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2010 Intel Corporation |
| 3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Eric Anholt <eric@anholt.net> |
| 26 | * Dave Airlie <airlied@linux.ie> |
| 27 | * Jesse Barnes <jesse.barnes@intel.com> |
| 28 | * Chris Wilson <chris@chris-wilson.co.uk> |
| 29 | */ |
| 30 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 32 | |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 33 | #include <linux/moduleparam.h> |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
| 35 | |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 36 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ |
| 37 | |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 38 | void |
| 39 | intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
| 40 | struct drm_display_mode *adjusted_mode) |
| 41 | { |
| 42 | adjusted_mode->hdisplay = fixed_mode->hdisplay; |
| 43 | adjusted_mode->hsync_start = fixed_mode->hsync_start; |
| 44 | adjusted_mode->hsync_end = fixed_mode->hsync_end; |
| 45 | adjusted_mode->htotal = fixed_mode->htotal; |
| 46 | |
| 47 | adjusted_mode->vdisplay = fixed_mode->vdisplay; |
| 48 | adjusted_mode->vsync_start = fixed_mode->vsync_start; |
| 49 | adjusted_mode->vsync_end = fixed_mode->vsync_end; |
| 50 | adjusted_mode->vtotal = fixed_mode->vtotal; |
| 51 | |
| 52 | adjusted_mode->clock = fixed_mode->clock; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | /* adjusted_mode has been preset to be the panel's fixed mode */ |
| 56 | void |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 57 | intel_pch_panel_fitting(struct intel_crtc *intel_crtc, |
| 58 | struct intel_crtc_config *pipe_config, |
| 59 | int fitting_mode) |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 60 | { |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 61 | struct drm_display_mode *mode, *adjusted_mode; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 62 | int x, y, width, height; |
| 63 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 64 | mode = &pipe_config->requested_mode; |
| 65 | adjusted_mode = &pipe_config->adjusted_mode; |
| 66 | |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 67 | x = y = width = height = 0; |
| 68 | |
| 69 | /* Native modes don't need fitting */ |
| 70 | if (adjusted_mode->hdisplay == mode->hdisplay && |
| 71 | adjusted_mode->vdisplay == mode->vdisplay) |
| 72 | goto done; |
| 73 | |
| 74 | switch (fitting_mode) { |
| 75 | case DRM_MODE_SCALE_CENTER: |
| 76 | width = mode->hdisplay; |
| 77 | height = mode->vdisplay; |
| 78 | x = (adjusted_mode->hdisplay - width + 1)/2; |
| 79 | y = (adjusted_mode->vdisplay - height + 1)/2; |
| 80 | break; |
| 81 | |
| 82 | case DRM_MODE_SCALE_ASPECT: |
| 83 | /* Scale but preserve the aspect ratio */ |
| 84 | { |
| 85 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
| 86 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; |
| 87 | if (scaled_width > scaled_height) { /* pillar */ |
| 88 | width = scaled_height / mode->vdisplay; |
Adam Jackson | 302983e | 2011-07-13 16:32:32 -0400 | [diff] [blame] | 89 | if (width & 1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 90 | width++; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 91 | x = (adjusted_mode->hdisplay - width + 1) / 2; |
| 92 | y = 0; |
| 93 | height = adjusted_mode->vdisplay; |
| 94 | } else if (scaled_width < scaled_height) { /* letter */ |
| 95 | height = scaled_width / mode->hdisplay; |
Adam Jackson | 302983e | 2011-07-13 16:32:32 -0400 | [diff] [blame] | 96 | if (height & 1) |
| 97 | height++; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 98 | y = (adjusted_mode->vdisplay - height + 1) / 2; |
| 99 | x = 0; |
| 100 | width = adjusted_mode->hdisplay; |
| 101 | } else { |
| 102 | x = y = 0; |
| 103 | width = adjusted_mode->hdisplay; |
| 104 | height = adjusted_mode->vdisplay; |
| 105 | } |
| 106 | } |
| 107 | break; |
| 108 | |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 109 | case DRM_MODE_SCALE_FULLSCREEN: |
| 110 | x = y = 0; |
| 111 | width = adjusted_mode->hdisplay; |
| 112 | height = adjusted_mode->vdisplay; |
| 113 | break; |
Jesse Barnes | ab3e67f | 2013-04-25 12:55:03 -0700 | [diff] [blame] | 114 | |
| 115 | default: |
| 116 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); |
| 117 | return; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | done: |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 121 | pipe_config->pch_pfit.pos = (x << 16) | y; |
| 122 | pipe_config->pch_pfit.size = (width << 16) | height; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 123 | } |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 124 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 125 | static void |
| 126 | centre_horizontally(struct drm_display_mode *mode, |
| 127 | int width) |
| 128 | { |
| 129 | u32 border, sync_pos, blank_width, sync_width; |
| 130 | |
| 131 | /* keep the hsync and hblank widths constant */ |
| 132 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; |
| 133 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; |
| 134 | sync_pos = (blank_width - sync_width + 1) / 2; |
| 135 | |
| 136 | border = (mode->hdisplay - width + 1) / 2; |
| 137 | border += border & 1; /* make the border even */ |
| 138 | |
| 139 | mode->crtc_hdisplay = width; |
| 140 | mode->crtc_hblank_start = width + border; |
| 141 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; |
| 142 | |
| 143 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; |
| 144 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; |
| 145 | } |
| 146 | |
| 147 | static void |
| 148 | centre_vertically(struct drm_display_mode *mode, |
| 149 | int height) |
| 150 | { |
| 151 | u32 border, sync_pos, blank_width, sync_width; |
| 152 | |
| 153 | /* keep the vsync and vblank widths constant */ |
| 154 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 155 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; |
| 156 | sync_pos = (blank_width - sync_width + 1) / 2; |
| 157 | |
| 158 | border = (mode->vdisplay - height + 1) / 2; |
| 159 | |
| 160 | mode->crtc_vdisplay = height; |
| 161 | mode->crtc_vblank_start = height + border; |
| 162 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; |
| 163 | |
| 164 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; |
| 165 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; |
| 166 | } |
| 167 | |
| 168 | static inline u32 panel_fitter_scaling(u32 source, u32 target) |
| 169 | { |
| 170 | /* |
| 171 | * Floating point operation is not supported. So the FACTOR |
| 172 | * is defined, which can avoid the floating point computation |
| 173 | * when calculating the panel ratio. |
| 174 | */ |
| 175 | #define ACCURACY 12 |
| 176 | #define FACTOR (1 << ACCURACY) |
| 177 | u32 ratio = source * FACTOR / target; |
| 178 | return (FACTOR * ratio + FACTOR/2) / FACTOR; |
| 179 | } |
| 180 | |
| 181 | void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, |
| 182 | struct intel_crtc_config *pipe_config, |
| 183 | int fitting_mode) |
| 184 | { |
| 185 | struct drm_device *dev = intel_crtc->base.dev; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 186 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
| 187 | struct drm_display_mode *mode, *adjusted_mode; |
| 188 | |
| 189 | mode = &pipe_config->requested_mode; |
| 190 | adjusted_mode = &pipe_config->adjusted_mode; |
| 191 | |
| 192 | /* Native modes don't need fitting */ |
| 193 | if (adjusted_mode->hdisplay == mode->hdisplay && |
| 194 | adjusted_mode->vdisplay == mode->vdisplay) |
| 195 | goto out; |
| 196 | |
| 197 | switch (fitting_mode) { |
| 198 | case DRM_MODE_SCALE_CENTER: |
| 199 | /* |
| 200 | * For centered modes, we have to calculate border widths & |
| 201 | * heights and modify the values programmed into the CRTC. |
| 202 | */ |
| 203 | centre_horizontally(adjusted_mode, mode->hdisplay); |
| 204 | centre_vertically(adjusted_mode, mode->vdisplay); |
| 205 | border = LVDS_BORDER_ENABLE; |
| 206 | break; |
| 207 | case DRM_MODE_SCALE_ASPECT: |
| 208 | /* Scale but preserve the aspect ratio */ |
| 209 | if (INTEL_INFO(dev)->gen >= 4) { |
| 210 | u32 scaled_width = adjusted_mode->hdisplay * |
| 211 | mode->vdisplay; |
| 212 | u32 scaled_height = mode->hdisplay * |
| 213 | adjusted_mode->vdisplay; |
| 214 | |
| 215 | /* 965+ is easy, it does everything in hw */ |
| 216 | if (scaled_width > scaled_height) |
| 217 | pfit_control |= PFIT_ENABLE | |
| 218 | PFIT_SCALING_PILLAR; |
| 219 | else if (scaled_width < scaled_height) |
| 220 | pfit_control |= PFIT_ENABLE | |
| 221 | PFIT_SCALING_LETTER; |
| 222 | else if (adjusted_mode->hdisplay != mode->hdisplay) |
| 223 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; |
| 224 | } else { |
| 225 | u32 scaled_width = adjusted_mode->hdisplay * |
| 226 | mode->vdisplay; |
| 227 | u32 scaled_height = mode->hdisplay * |
| 228 | adjusted_mode->vdisplay; |
| 229 | /* |
| 230 | * For earlier chips we have to calculate the scaling |
| 231 | * ratio by hand and program it into the |
| 232 | * PFIT_PGM_RATIO register |
| 233 | */ |
| 234 | if (scaled_width > scaled_height) { /* pillar */ |
| 235 | centre_horizontally(adjusted_mode, |
| 236 | scaled_height / |
| 237 | mode->vdisplay); |
| 238 | |
| 239 | border = LVDS_BORDER_ENABLE; |
| 240 | if (mode->vdisplay != adjusted_mode->vdisplay) { |
| 241 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); |
| 242 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | |
| 243 | bits << PFIT_VERT_SCALE_SHIFT); |
| 244 | pfit_control |= (PFIT_ENABLE | |
| 245 | VERT_INTERP_BILINEAR | |
| 246 | HORIZ_INTERP_BILINEAR); |
| 247 | } |
| 248 | } else if (scaled_width < scaled_height) { /* letter */ |
| 249 | centre_vertically(adjusted_mode, |
| 250 | scaled_width / |
| 251 | mode->hdisplay); |
| 252 | |
| 253 | border = LVDS_BORDER_ENABLE; |
| 254 | if (mode->hdisplay != adjusted_mode->hdisplay) { |
| 255 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); |
| 256 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | |
| 257 | bits << PFIT_VERT_SCALE_SHIFT); |
| 258 | pfit_control |= (PFIT_ENABLE | |
| 259 | VERT_INTERP_BILINEAR | |
| 260 | HORIZ_INTERP_BILINEAR); |
| 261 | } |
| 262 | } else { |
| 263 | /* Aspects match, Let hw scale both directions */ |
| 264 | pfit_control |= (PFIT_ENABLE | |
| 265 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | |
| 266 | VERT_INTERP_BILINEAR | |
| 267 | HORIZ_INTERP_BILINEAR); |
| 268 | } |
| 269 | } |
| 270 | break; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 271 | case DRM_MODE_SCALE_FULLSCREEN: |
| 272 | /* |
| 273 | * Full scaling, even if it changes the aspect ratio. |
| 274 | * Fortunately this is all done for us in hw. |
| 275 | */ |
| 276 | if (mode->vdisplay != adjusted_mode->vdisplay || |
| 277 | mode->hdisplay != adjusted_mode->hdisplay) { |
| 278 | pfit_control |= PFIT_ENABLE; |
| 279 | if (INTEL_INFO(dev)->gen >= 4) |
| 280 | pfit_control |= PFIT_SCALING_AUTO; |
| 281 | else |
| 282 | pfit_control |= (VERT_AUTO_SCALE | |
| 283 | VERT_INTERP_BILINEAR | |
| 284 | HORIZ_AUTO_SCALE | |
| 285 | HORIZ_INTERP_BILINEAR); |
| 286 | } |
| 287 | break; |
Jesse Barnes | ab3e67f | 2013-04-25 12:55:03 -0700 | [diff] [blame] | 288 | default: |
| 289 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); |
| 290 | return; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | /* 965+ wants fuzzy fitting */ |
| 294 | /* FIXME: handle multiple panels by failing gracefully */ |
| 295 | if (INTEL_INFO(dev)->gen >= 4) |
| 296 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
| 297 | PFIT_FILTER_FUZZY); |
| 298 | |
| 299 | out: |
| 300 | if ((pfit_control & PFIT_ENABLE) == 0) { |
| 301 | pfit_control = 0; |
| 302 | pfit_pgm_ratios = 0; |
| 303 | } |
| 304 | |
| 305 | /* Make sure pre-965 set dither correctly for 18bpp panels. */ |
| 306 | if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) |
| 307 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; |
| 308 | |
Daniel Vetter | 2deefda | 2013-04-25 22:52:17 +0200 | [diff] [blame] | 309 | pipe_config->gmch_pfit.control = pfit_control; |
| 310 | pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios; |
Daniel Vetter | 68fc874 | 2013-04-25 22:52:16 +0200 | [diff] [blame] | 311 | pipe_config->gmch_pfit.lvds_border_bits = border; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 312 | } |
| 313 | |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 314 | static int is_backlight_combination_mode(struct drm_device *dev) |
| 315 | { |
| 316 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 317 | |
| 318 | if (INTEL_INFO(dev)->gen >= 4) |
| 319 | return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; |
| 320 | |
| 321 | if (IS_GEN2(dev)) |
| 322 | return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; |
| 323 | |
| 324 | return 0; |
| 325 | } |
| 326 | |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 327 | /* XXX: query mode clock or hardware clock and program max PWM appropriately |
| 328 | * when it's 0. |
| 329 | */ |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 330 | static u32 i915_read_blc_pwm_ctl(struct drm_device *dev) |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 331 | { |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 332 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 333 | u32 val; |
| 334 | |
Ville Syrjälä | df0a679 | 2013-05-22 11:36:40 +0300 | [diff] [blame^] | 335 | WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock)); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 336 | |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 337 | /* Restore the CTL value if it lost, e.g. GPU reset */ |
| 338 | |
| 339 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
| 340 | val = I915_READ(BLC_PWM_PCH_CTL2); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 341 | if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) { |
| 342 | dev_priv->regfile.saveBLC_PWM_CTL2 = val; |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 343 | } else if (val == 0) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 344 | val = dev_priv->regfile.saveBLC_PWM_CTL2; |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 345 | I915_WRITE(BLC_PWM_PCH_CTL2, val); |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 346 | } |
| 347 | } else { |
| 348 | val = I915_READ(BLC_PWM_CTL); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 349 | if (dev_priv->regfile.saveBLC_PWM_CTL == 0) { |
| 350 | dev_priv->regfile.saveBLC_PWM_CTL = val; |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 351 | if (INTEL_INFO(dev)->gen >= 4) |
| 352 | dev_priv->regfile.saveBLC_PWM_CTL2 = |
| 353 | I915_READ(BLC_PWM_CTL2); |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 354 | } else if (val == 0) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 355 | val = dev_priv->regfile.saveBLC_PWM_CTL; |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 356 | I915_WRITE(BLC_PWM_CTL, val); |
| 357 | if (INTEL_INFO(dev)->gen >= 4) |
| 358 | I915_WRITE(BLC_PWM_CTL2, |
| 359 | dev_priv->regfile.saveBLC_PWM_CTL2); |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 360 | } |
| 361 | } |
| 362 | |
| 363 | return val; |
| 364 | } |
| 365 | |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 366 | static u32 intel_panel_get_max_backlight(struct drm_device *dev) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 367 | { |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 368 | u32 max; |
| 369 | |
Jani Nikula | bfd7590 | 2012-12-04 16:36:28 +0200 | [diff] [blame] | 370 | max = i915_read_blc_pwm_ctl(dev); |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 371 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 372 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | 0b0b053 | 2010-11-23 09:45:50 +0000 | [diff] [blame] | 373 | max >>= 16; |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 374 | } else { |
Keith Packard | ca88479 | 2011-11-18 11:09:24 -0800 | [diff] [blame] | 375 | if (INTEL_INFO(dev)->gen < 4) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 376 | max >>= 17; |
Keith Packard | ca88479 | 2011-11-18 11:09:24 -0800 | [diff] [blame] | 377 | else |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 378 | max >>= 16; |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 379 | |
| 380 | if (is_backlight_combination_mode(dev)) |
| 381 | max *= 0xff; |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 382 | } |
| 383 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 384 | DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 385 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 386 | return max; |
| 387 | } |
| 388 | |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 389 | static int i915_panel_invert_brightness; |
| 390 | MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness " |
| 391 | "(-1 force normal, 0 machine defaults, 1 force inversion), please " |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 392 | "report PCI device ID, subsystem vendor and subsystem device ID " |
| 393 | "to dri-devel@lists.freedesktop.org, if your machine needs it. " |
| 394 | "It will then be included in an upcoming module version."); |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 395 | module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600); |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 396 | static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val) |
| 397 | { |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 398 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 399 | |
| 400 | if (i915_panel_invert_brightness < 0) |
| 401 | return val; |
| 402 | |
| 403 | if (i915_panel_invert_brightness > 0 || |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 404 | dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { |
| 405 | u32 max = intel_panel_get_max_backlight(dev); |
| 406 | if (max) |
| 407 | return max - val; |
| 408 | } |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 409 | |
| 410 | return val; |
| 411 | } |
| 412 | |
Stéphane Marchesin | faea35d | 2012-07-30 13:51:38 -0700 | [diff] [blame] | 413 | static u32 intel_panel_get_backlight(struct drm_device *dev) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 414 | { |
| 415 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 416 | u32 val; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 417 | unsigned long flags; |
| 418 | |
| 419 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 420 | |
| 421 | if (HAS_PCH_SPLIT(dev)) { |
| 422 | val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
| 423 | } else { |
| 424 | val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
Keith Packard | ca88479 | 2011-11-18 11:09:24 -0800 | [diff] [blame] | 425 | if (INTEL_INFO(dev)->gen < 4) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 426 | val >>= 1; |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 427 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 428 | if (is_backlight_combination_mode(dev)) { |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 429 | u8 lbpc; |
| 430 | |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 431 | pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
| 432 | val *= lbpc; |
| 433 | } |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 434 | } |
| 435 | |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 436 | val = intel_panel_compute_brightness(dev, val); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 437 | |
| 438 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
| 439 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 440 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
| 441 | return val; |
| 442 | } |
| 443 | |
| 444 | static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) |
| 445 | { |
| 446 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 447 | u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
| 448 | I915_WRITE(BLC_PWM_CPU_CTL, val | level); |
| 449 | } |
| 450 | |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 451 | static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 452 | { |
| 453 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 454 | u32 tmp; |
| 455 | |
| 456 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); |
Carsten Emde | 7bd9090 | 2012-03-15 15:56:25 +0100 | [diff] [blame] | 457 | level = intel_panel_compute_brightness(dev, level); |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 458 | |
| 459 | if (HAS_PCH_SPLIT(dev)) |
| 460 | return intel_pch_panel_set_backlight(dev, level); |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 461 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 462 | if (is_backlight_combination_mode(dev)) { |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 463 | u32 max = intel_panel_get_max_backlight(dev); |
| 464 | u8 lbpc; |
| 465 | |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 466 | /* we're screwed, but keep behaviour backwards compatible */ |
| 467 | if (!max) |
| 468 | max = 1; |
| 469 | |
Takashi Iwai | ba3820a | 2011-03-10 14:02:12 +0100 | [diff] [blame] | 470 | lbpc = level * 0xfe / max + 1; |
| 471 | level /= lbpc; |
| 472 | pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); |
| 473 | } |
| 474 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 475 | tmp = I915_READ(BLC_PWM_CTL); |
Daniel Vetter | a726915 | 2012-11-20 14:50:08 +0100 | [diff] [blame] | 476 | if (INTEL_INFO(dev)->gen < 4) |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 477 | level <<= 1; |
Keith Packard | ca88479 | 2011-11-18 11:09:24 -0800 | [diff] [blame] | 478 | tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK; |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 479 | I915_WRITE(BLC_PWM_CTL, tmp | level); |
| 480 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 481 | |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 482 | /* set backlight brightness to level in range [0..max] */ |
| 483 | void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max) |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 484 | { |
| 485 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 486 | u32 freq; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 487 | unsigned long flags; |
| 488 | |
| 489 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 490 | |
| 491 | freq = intel_panel_get_max_backlight(dev); |
| 492 | if (!freq) { |
| 493 | /* we are screwed, bail out */ |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 494 | goto out; |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 495 | } |
| 496 | |
| 497 | /* scale to hardware */ |
| 498 | level = level * freq / max; |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 499 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 500 | dev_priv->backlight.level = level; |
| 501 | if (dev_priv->backlight.device) |
| 502 | dev_priv->backlight.device->props.brightness = level; |
Jani Nikula | b6b3ba5 | 2013-03-12 11:44:15 +0200 | [diff] [blame] | 503 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 504 | if (dev_priv->backlight.enabled) |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 505 | intel_panel_actually_set_backlight(dev, level); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 506 | out: |
| 507 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 508 | } |
| 509 | |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 510 | void intel_panel_disable_backlight(struct drm_device *dev) |
| 511 | { |
| 512 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 513 | unsigned long flags; |
| 514 | |
| 515 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 516 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 517 | dev_priv->backlight.enabled = false; |
Takashi Iwai | f52c619 | 2011-10-14 11:45:40 +0200 | [diff] [blame] | 518 | intel_panel_actually_set_backlight(dev, 0); |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 519 | |
| 520 | if (INTEL_INFO(dev)->gen >= 4) { |
Paulo Zanoni | a4f32fc | 2012-07-14 11:57:12 -0300 | [diff] [blame] | 521 | uint32_t reg, tmp; |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 522 | |
| 523 | reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; |
| 524 | |
| 525 | I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); |
Paulo Zanoni | a4f32fc | 2012-07-14 11:57:12 -0300 | [diff] [blame] | 526 | |
| 527 | if (HAS_PCH_SPLIT(dev)) { |
| 528 | tmp = I915_READ(BLC_PWM_PCH_CTL1); |
| 529 | tmp &= ~BLM_PCH_PWM_ENABLE; |
| 530 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp); |
| 531 | } |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 532 | } |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 533 | |
| 534 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 535 | } |
| 536 | |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 537 | void intel_panel_enable_backlight(struct drm_device *dev, |
| 538 | enum pipe pipe) |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 539 | { |
| 540 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 35ffda4 | 2013-04-25 16:49:25 +0300 | [diff] [blame] | 541 | enum transcoder cpu_transcoder = |
| 542 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 543 | unsigned long flags; |
| 544 | |
| 545 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 546 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 547 | if (dev_priv->backlight.level == 0) { |
| 548 | dev_priv->backlight.level = intel_panel_get_max_backlight(dev); |
| 549 | if (dev_priv->backlight.device) |
| 550 | dev_priv->backlight.device->props.brightness = |
| 551 | dev_priv->backlight.level; |
Jani Nikula | b6b3ba5 | 2013-03-12 11:44:15 +0200 | [diff] [blame] | 552 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 553 | |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 554 | if (INTEL_INFO(dev)->gen >= 4) { |
| 555 | uint32_t reg, tmp; |
| 556 | |
| 557 | reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; |
| 558 | |
| 559 | |
| 560 | tmp = I915_READ(reg); |
| 561 | |
| 562 | /* Note that this can also get called through dpms changes. And |
| 563 | * we don't track the backlight dpms state, hence check whether |
| 564 | * we have to do anything first. */ |
| 565 | if (tmp & BLM_PWM_ENABLE) |
Takashi Iwai | 770c123 | 2012-08-11 08:56:42 +0200 | [diff] [blame] | 566 | goto set_level; |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 567 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 568 | if (INTEL_INFO(dev)->num_pipes == 3) |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 569 | tmp &= ~BLM_PIPE_SELECT_IVB; |
| 570 | else |
| 571 | tmp &= ~BLM_PIPE_SELECT; |
| 572 | |
Jani Nikula | 35ffda4 | 2013-04-25 16:49:25 +0300 | [diff] [blame] | 573 | if (cpu_transcoder == TRANSCODER_EDP) |
| 574 | tmp |= BLM_TRANSCODER_EDP; |
| 575 | else |
| 576 | tmp |= BLM_PIPE(cpu_transcoder); |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 577 | tmp &= ~BLM_PWM_ENABLE; |
| 578 | |
| 579 | I915_WRITE(reg, tmp); |
| 580 | POSTING_READ(reg); |
| 581 | I915_WRITE(reg, tmp | BLM_PWM_ENABLE); |
Paulo Zanoni | a4f32fc | 2012-07-14 11:57:12 -0300 | [diff] [blame] | 582 | |
| 583 | if (HAS_PCH_SPLIT(dev)) { |
| 584 | tmp = I915_READ(BLC_PWM_PCH_CTL1); |
| 585 | tmp |= BLM_PCH_PWM_ENABLE; |
| 586 | tmp &= ~BLM_PCH_OVERRIDE_ENABLE; |
| 587 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp); |
| 588 | } |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 589 | } |
Takashi Iwai | 770c123 | 2012-08-11 08:56:42 +0200 | [diff] [blame] | 590 | |
| 591 | set_level: |
Daniel Vetter | b128937 | 2013-03-22 15:44:46 +0100 | [diff] [blame] | 592 | /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1. |
| 593 | * BLC_PWM_CPU_CTL may be cleared to zero automatically when these |
| 594 | * registers are set. |
Takashi Iwai | 770c123 | 2012-08-11 08:56:42 +0200 | [diff] [blame] | 595 | */ |
Daniel Vetter | ecb135a | 2013-04-03 11:25:32 +0200 | [diff] [blame] | 596 | dev_priv->backlight.enabled = true; |
| 597 | intel_panel_actually_set_backlight(dev, dev_priv->backlight.level); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 598 | |
| 599 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 600 | } |
| 601 | |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 602 | static void intel_panel_init_backlight(struct drm_device *dev) |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 603 | { |
| 604 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 605 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 606 | dev_priv->backlight.level = intel_panel_get_backlight(dev); |
| 607 | dev_priv->backlight.enabled = dev_priv->backlight.level != 0; |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 608 | } |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 609 | |
| 610 | enum drm_connector_status |
| 611 | intel_panel_detect(struct drm_device *dev) |
| 612 | { |
| 613 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 614 | |
| 615 | /* Assume that the BIOS does not lie through the OpRegion... */ |
Daniel Vetter | a726915 | 2012-11-20 14:50:08 +0100 | [diff] [blame] | 616 | if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) { |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 617 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? |
| 618 | connector_status_connected : |
| 619 | connector_status_disconnected; |
Daniel Vetter | a726915 | 2012-11-20 14:50:08 +0100 | [diff] [blame] | 620 | } |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 621 | |
Daniel Vetter | a726915 | 2012-11-20 14:50:08 +0100 | [diff] [blame] | 622 | switch (i915_panel_ignore_lid) { |
| 623 | case -2: |
| 624 | return connector_status_connected; |
| 625 | case -1: |
| 626 | return connector_status_disconnected; |
| 627 | default: |
| 628 | return connector_status_unknown; |
| 629 | } |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 630 | } |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 631 | |
| 632 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE |
| 633 | static int intel_panel_update_status(struct backlight_device *bd) |
| 634 | { |
| 635 | struct drm_device *dev = bl_get_data(bd); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 636 | intel_panel_set_backlight(dev, bd->props.brightness, |
| 637 | bd->props.max_brightness); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 638 | return 0; |
| 639 | } |
| 640 | |
| 641 | static int intel_panel_get_brightness(struct backlight_device *bd) |
| 642 | { |
| 643 | struct drm_device *dev = bl_get_data(bd); |
Jani Nikula | 7c23396 | 2013-03-12 11:44:16 +0200 | [diff] [blame] | 644 | return intel_panel_get_backlight(dev); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | static const struct backlight_ops intel_panel_bl_ops = { |
| 648 | .update_status = intel_panel_update_status, |
| 649 | .get_brightness = intel_panel_get_brightness, |
| 650 | }; |
| 651 | |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 652 | int intel_panel_setup_backlight(struct drm_connector *connector) |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 653 | { |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 654 | struct drm_device *dev = connector->dev; |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 655 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 656 | struct backlight_properties props; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 657 | unsigned long flags; |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 658 | |
| 659 | intel_panel_init_backlight(dev); |
| 660 | |
Jani Nikula | dc652f9 | 2013-04-12 15:18:38 +0300 | [diff] [blame] | 661 | if (WARN_ON(dev_priv->backlight.device)) |
| 662 | return -ENODEV; |
| 663 | |
Corentin Chary | af437cf | 2012-05-22 10:29:46 +0100 | [diff] [blame] | 664 | memset(&props, 0, sizeof(props)); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 665 | props.type = BACKLIGHT_RAW; |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 666 | props.brightness = dev_priv->backlight.level; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 667 | |
| 668 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
Jani Nikula | d654063 | 2013-04-12 15:18:36 +0300 | [diff] [blame] | 669 | props.max_brightness = intel_panel_get_max_backlight(dev); |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 670 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
| 671 | |
Jani Nikula | 28dcc2d | 2012-09-03 16:25:12 +0300 | [diff] [blame] | 672 | if (props.max_brightness == 0) { |
Jani Nikula | e86b618 | 2012-10-25 10:57:38 +0300 | [diff] [blame] | 673 | DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n"); |
Jani Nikula | 28dcc2d | 2012-09-03 16:25:12 +0300 | [diff] [blame] | 674 | return -ENODEV; |
| 675 | } |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 676 | dev_priv->backlight.device = |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 677 | backlight_device_register("intel_backlight", |
| 678 | &connector->kdev, dev, |
| 679 | &intel_panel_bl_ops, &props); |
| 680 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 681 | if (IS_ERR(dev_priv->backlight.device)) { |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 682 | DRM_ERROR("Failed to register backlight: %ld\n", |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 683 | PTR_ERR(dev_priv->backlight.device)); |
| 684 | dev_priv->backlight.device = NULL; |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 685 | return -ENODEV; |
| 686 | } |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 687 | return 0; |
| 688 | } |
| 689 | |
| 690 | void intel_panel_destroy_backlight(struct drm_device *dev) |
| 691 | { |
| 692 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | dc652f9 | 2013-04-12 15:18:38 +0300 | [diff] [blame] | 693 | if (dev_priv->backlight.device) { |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 694 | backlight_device_unregister(dev_priv->backlight.device); |
Jani Nikula | dc652f9 | 2013-04-12 15:18:38 +0300 | [diff] [blame] | 695 | dev_priv->backlight.device = NULL; |
| 696 | } |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 697 | } |
| 698 | #else |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 699 | int intel_panel_setup_backlight(struct drm_connector *connector) |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 700 | { |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 701 | intel_panel_init_backlight(connector->dev); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 702 | return 0; |
| 703 | } |
| 704 | |
| 705 | void intel_panel_destroy_backlight(struct drm_device *dev) |
| 706 | { |
| 707 | return; |
| 708 | } |
| 709 | #endif |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 710 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 711 | int intel_panel_init(struct intel_panel *panel, |
| 712 | struct drm_display_mode *fixed_mode) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 713 | { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 714 | panel->fixed_mode = fixed_mode; |
| 715 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 716 | return 0; |
| 717 | } |
| 718 | |
| 719 | void intel_panel_fini(struct intel_panel *panel) |
| 720 | { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 721 | struct intel_connector *intel_connector = |
| 722 | container_of(panel, struct intel_connector, panel); |
| 723 | |
| 724 | if (panel->fixed_mode) |
| 725 | drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 726 | } |