Lakshmi Narayana Kalavala | c0dac06 | 2016-12-01 17:20:09 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | &soc { |
| 15 | qcom,cam-req-mgr { |
| 16 | compatible = "qcom,cam-req-mgr"; |
| 17 | status = "ok"; |
| 18 | }; |
Jigarkumar Zala | 86123115 | 2017-02-28 14:05:11 -0800 | [diff] [blame] | 19 | |
| 20 | qcom,csiphy@ac65000 { |
| 21 | cell-index = <0>; |
| 22 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 23 | reg = <0x0ac65000 0x1000>; |
| 24 | reg-names = "csiphy"; |
| 25 | interrupts = <0 477 0>; |
| 26 | interrupt-names = "csiphy"; |
| 27 | gdscr-supply = <&titan_top_gdsc>; |
| 28 | qcom,cam-vreg-name = "gdscr"; |
| 29 | qcom,csi-vdd-voltage = <1200000>; |
| 30 | qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| 31 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 32 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 33 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 34 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 35 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 36 | <&clock_camcc CAM_CC_CSIPHY0_CLK>, |
| 37 | <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, |
| 38 | <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, |
| 39 | <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, |
| 40 | <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>; |
| 41 | clock-names = "camnoc_axi_clk", |
| 42 | "soc_ahb_clk", |
| 43 | "slow_ahb_src_clk", |
| 44 | "cpas_ahb_clk", |
| 45 | "cphy_rx_clk_src", |
| 46 | "csiphy0_clk", |
| 47 | "csi0phytimer_clk_src", |
| 48 | "csi0phytimer_clk", |
| 49 | "ife_0_csid_clk", |
| 50 | "ife_0_csid_clk_src"; |
| 51 | qcom,clock-rates = |
| 52 | <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| 53 | status = "ok"; |
| 54 | }; |
| 55 | |
| 56 | qcom,csiphy@ac66000{ |
| 57 | cell-index = <1>; |
| 58 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 59 | reg = <0xac66000 0x1000>; |
| 60 | reg-names = "csiphy"; |
| 61 | interrupts = <0 478 0>; |
| 62 | interrupt-names = "csiphy"; |
| 63 | gdscr-supply = <&titan_top_gdsc>; |
| 64 | qcom,cam-vreg-name = "gdscr"; |
| 65 | qcom,csi-vdd-voltage = <1200000>; |
| 66 | qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| 67 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 68 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 69 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 70 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 71 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 72 | <&clock_camcc CAM_CC_CSIPHY1_CLK>, |
| 73 | <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, |
| 74 | <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, |
| 75 | <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, |
| 76 | <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>; |
| 77 | clock-names = "camnoc_axi_clk", |
| 78 | "soc_ahb_clk", |
| 79 | "slow_ahb_src_clk", |
| 80 | "cpas_ahb_clk", |
| 81 | "cphy_rx_clk_src", |
| 82 | "csiphy1_clk", |
| 83 | "csi1phytimer_clk_src", |
| 84 | "csi1phytimer_clk", |
| 85 | "ife_1_csid_clk", |
| 86 | "ife_1_csid_clk_src"; |
| 87 | qcom,clock-rates = |
| 88 | <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| 89 | |
| 90 | status = "ok"; |
| 91 | }; |
| 92 | |
| 93 | qcom,csiphy@ac67000 { |
| 94 | cell-index = <2>; |
| 95 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 96 | reg = <0xac67000 0x1000>; |
| 97 | reg-names = "csiphy"; |
| 98 | interrupts = <0 479 0>; |
| 99 | interrupt-names = "csiphy"; |
| 100 | gdscr-supply = <&titan_top_gdsc>; |
| 101 | qcom,cam-vreg-name = "gdscr"; |
| 102 | qcom,csi-vdd-voltage = <1200000>; |
| 103 | qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| 104 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 105 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 106 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 107 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 108 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 109 | <&clock_camcc CAM_CC_CSIPHY2_CLK>, |
| 110 | <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, |
| 111 | <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, |
| 112 | <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, |
| 113 | <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>; |
| 114 | clock-names = "camnoc_axi_clk", |
| 115 | "soc_ahb_clk", |
| 116 | "slow_ahb_src_clk", |
| 117 | "cpas_ahb_clk", |
| 118 | "cphy_rx_clk_src", |
| 119 | "csiphy2_clk", |
| 120 | "csi2phytimer_clk_src", |
| 121 | "csi2phytimer_clk", |
| 122 | "ife_lite_csid_clk", |
| 123 | "ife_lite_csid_clk_src"; |
| 124 | qcom,clock-rates = |
| 125 | <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| 126 | status = "ok"; |
| 127 | }; |
| 128 | |
| 129 | cci: qcom,cci@ac4a000 { |
| 130 | cell-index = <0>; |
| 131 | compatible = "qcom,cci"; |
| 132 | reg = <0xac4a000 0x4000>; |
| 133 | #address-cells = <1>; |
| 134 | #size-cells = <0>; |
| 135 | reg-names = "cci"; |
| 136 | interrupts = <0 460 0>; |
| 137 | interrupt-names = "cci"; |
| 138 | status = "ok"; |
| 139 | gdscr-supply = <&titan_top_gdsc>; |
| 140 | qcom,cam-vreg-name = "gdscr"; |
| 141 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 142 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 143 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 144 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 145 | <&clock_camcc CAM_CC_CCI_CLK>, |
| 146 | <&clock_camcc CAM_CC_CCI_CLK_SRC>; |
| 147 | clock-names = "camnoc_axi_clk", |
| 148 | "soc_ahb_clk", |
| 149 | "slow_ahb_src_clk", |
| 150 | "cpas_ahb_clk", |
| 151 | "cci_clk", |
| 152 | "cci_clk_src"; |
| 153 | qcom,clock-rates = <0 0 80000000 0 0 37500000>; |
| 154 | pinctrl-names = "cci_default", "cci_suspend"; |
| 155 | pinctrl-0 = <&cci0_active &cci1_active>; |
| 156 | pinctrl-1 = <&cci0_suspend &cci1_suspend>; |
| 157 | gpios = <&tlmm 17 0>, |
| 158 | <&tlmm 18 0>, |
| 159 | <&tlmm 19 0>, |
| 160 | <&tlmm 20 0>; |
| 161 | qcom,gpio-tbl-num = <0 1 2 3>; |
| 162 | qcom,gpio-tbl-flags = <1 1 1 1>; |
| 163 | qcom,gpio-tbl-label = "CCI_I2C_DATA0", |
| 164 | "CCI_I2C_CLK0", |
| 165 | "CCI_I2C_DATA1", |
| 166 | "CCI_I2C_CLK1"; |
| 167 | |
| 168 | i2c_freq_100Khz: qcom,i2c_standard_mode { |
| 169 | qcom,hw-thigh = <201>; |
| 170 | qcom,hw-tlow = <174>; |
| 171 | qcom,hw-tsu-sto = <204>; |
| 172 | qcom,hw-tsu-sta = <231>; |
| 173 | qcom,hw-thd-dat = <22>; |
| 174 | qcom,hw-thd-sta = <162>; |
| 175 | qcom,hw-tbuf = <227>; |
| 176 | qcom,hw-scl-stretch-en = <0>; |
| 177 | qcom,hw-trdhld = <6>; |
| 178 | qcom,hw-tsp = <3>; |
| 179 | qcom,cci-clk-src = <37500000>; |
| 180 | status = "ok"; |
| 181 | }; |
| 182 | |
| 183 | i2c_freq_400Khz: qcom,i2c_fast_mode { |
| 184 | qcom,hw-thigh = <38>; |
| 185 | qcom,hw-tlow = <56>; |
| 186 | qcom,hw-tsu-sto = <40>; |
| 187 | qcom,hw-tsu-sta = <40>; |
| 188 | qcom,hw-thd-dat = <22>; |
| 189 | qcom,hw-thd-sta = <35>; |
| 190 | qcom,hw-tbuf = <62>; |
| 191 | qcom,hw-scl-stretch-en = <0>; |
| 192 | qcom,hw-trdhld = <6>; |
| 193 | qcom,hw-tsp = <3>; |
| 194 | qcom,cci-clk-src = <37500000>; |
| 195 | status = "ok"; |
| 196 | }; |
| 197 | |
| 198 | i2c_freq_custom: qcom,i2c_custom_mode { |
| 199 | qcom,hw-thigh = <38>; |
| 200 | qcom,hw-tlow = <56>; |
| 201 | qcom,hw-tsu-sto = <40>; |
| 202 | qcom,hw-tsu-sta = <40>; |
| 203 | qcom,hw-thd-dat = <22>; |
| 204 | qcom,hw-thd-sta = <35>; |
| 205 | qcom,hw-tbuf = <62>; |
| 206 | qcom,hw-scl-stretch-en = <1>; |
| 207 | qcom,hw-trdhld = <6>; |
| 208 | qcom,hw-tsp = <3>; |
| 209 | qcom,cci-clk-src = <37500000>; |
| 210 | status = "ok"; |
| 211 | }; |
| 212 | |
| 213 | i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { |
| 214 | qcom,hw-thigh = <16>; |
| 215 | qcom,hw-tlow = <22>; |
| 216 | qcom,hw-tsu-sto = <17>; |
| 217 | qcom,hw-tsu-sta = <18>; |
| 218 | qcom,hw-thd-dat = <16>; |
| 219 | qcom,hw-thd-sta = <15>; |
| 220 | qcom,hw-tbuf = <24>; |
| 221 | qcom,hw-scl-stretch-en = <0>; |
| 222 | qcom,hw-trdhld = <3>; |
| 223 | qcom,hw-tsp = <3>; |
| 224 | qcom,cci-clk-src = <37500000>; |
| 225 | status = "ok"; |
| 226 | }; |
| 227 | }; |
Lakshmi Narayana Kalavala | c0dac06 | 2016-12-01 17:20:09 -0800 | [diff] [blame] | 228 | }; |