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Stephen M. Cameronedd16362009-12-08 14:09:11 -08001/*
2 * Disk Array driver for HP Smart Array SAS controllers
Don Brace1358f6d2015-07-18 11:12:38 -05003 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
Stephen M. Cameronedd16362009-12-08 14:09:11 -08005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
Don Brace1358f6d2015-07-18 11:12:38 -050015 * Questions/Comments/Bugfixes to storagedev@pmcs.com
Stephen M. Cameronedd16362009-12-08 14:09:11 -080016 *
17 */
18#ifndef HPSA_CMD_H
19#define HPSA_CMD_H
20
21/* general boundary defintions */
22#define SENSEINFOBYTES 32 /* may vary between hbas */
Stephen M. Camerond66ae082012-01-19 14:00:48 -060023#define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
Stephen M. Cameron33a2ffc2010-02-25 14:03:27 -060024#define HPSA_SG_CHAIN 0x80000000
Matt Gatese1d9cbf2014-02-18 13:55:12 -060025#define HPSA_SG_LAST 0x40000000
Stephen M. Cameronedd16362009-12-08 14:09:11 -080026#define MAXREPLYQS 256
27
28/* Command Status value */
29#define CMD_SUCCESS 0x0000
30#define CMD_TARGET_STATUS 0x0001
31#define CMD_DATA_UNDERRUN 0x0002
32#define CMD_DATA_OVERRUN 0x0003
33#define CMD_INVALID 0x0004
34#define CMD_PROTOCOL_ERR 0x0005
35#define CMD_HARDWARE_ERR 0x0006
36#define CMD_CONNECTION_LOST 0x0007
37#define CMD_ABORTED 0x0008
38#define CMD_ABORT_FAILED 0x0009
39#define CMD_UNSOLICITED_ABORT 0x000A
40#define CMD_TIMEOUT 0x000B
41#define CMD_UNABORTABLE 0x000C
Stephen Cameron9437ac42015-04-23 09:32:16 -050042#define CMD_TMF_STATUS 0x000D
Stephen M. Cameron283b4a92014-02-18 13:55:33 -060043#define CMD_IOACCEL_DISABLED 0x000E
Webb Scales25163bd2015-04-23 09:32:00 -050044#define CMD_CTLR_LOCKUP 0xffff
45/* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
46 * it is a value defined by the driver that commands can be marked
47 * with when a controller lockup has been detected by the driver
48 */
Stephen M. Cameron283b4a92014-02-18 13:55:33 -060049
Stephen Cameron9437ac42015-04-23 09:32:16 -050050/* TMF function status values */
51#define CISS_TMF_COMPLETE 0x00
52#define CISS_TMF_INVALID_FRAME 0x02
53#define CISS_TMF_NOT_SUPPORTED 0x04
54#define CISS_TMF_FAILED 0x05
55#define CISS_TMF_SUCCESS 0x08
56#define CISS_TMF_WRONG_LUN 0x09
57#define CISS_TMF_OVERLAPPED_TAG 0x0a
Stephen M. Cameronedd16362009-12-08 14:09:11 -080058
59/* Unit Attentions ASC's as defined for the MSA2012sa */
60#define POWER_OR_RESET 0x29
61#define STATE_CHANGED 0x2a
62#define UNIT_ATTENTION_CLEARED 0x2f
63#define LUN_FAILED 0x3e
64#define REPORT_LUNS_CHANGED 0x3f
65
66/* Unit Attentions ASCQ's as defined for the MSA2012sa */
67
68 /* These ASCQ's defined for ASC = POWER_OR_RESET */
69#define POWER_ON_RESET 0x00
70#define POWER_ON_REBOOT 0x01
71#define SCSI_BUS_RESET 0x02
72#define MSA_TARGET_RESET 0x03
73#define CONTROLLER_FAILOVER 0x04
74#define TRANSCEIVER_SE 0x05
75#define TRANSCEIVER_LVD 0x06
76
77 /* These ASCQ's defined for ASC = STATE_CHANGED */
78#define RESERVATION_PREEMPTED 0x03
79#define ASYM_ACCESS_CHANGED 0x06
80#define LUN_CAPACITY_CHANGED 0x09
81
82/* transfer direction */
83#define XFER_NONE 0x00
84#define XFER_WRITE 0x01
85#define XFER_READ 0x02
86#define XFER_RSVD 0x03
87
88/* task attribute */
89#define ATTR_UNTAGGED 0x00
90#define ATTR_SIMPLE 0x04
91#define ATTR_HEADOFQUEUE 0x05
92#define ATTR_ORDERED 0x06
93#define ATTR_ACA 0x07
94
95/* cdb type */
Scott Teel54b6e9e2014-02-18 13:56:45 -060096#define TYPE_CMD 0x00
97#define TYPE_MSG 0x01
98#define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */
Stephen M. Cameronedd16362009-12-08 14:09:11 -080099
Stephen M. Cameron75167d22012-05-01 11:42:51 -0500100/* Message Types */
101#define HPSA_TASK_MANAGEMENT 0x00
102#define HPSA_RESET 0x01
103#define HPSA_SCAN 0x02
104#define HPSA_NOOP 0x03
105
106#define HPSA_CTLR_RESET_TYPE 0x00
107#define HPSA_BUS_RESET_TYPE 0x01
108#define HPSA_TARGET_RESET_TYPE 0x03
109#define HPSA_LUN_RESET_TYPE 0x04
110#define HPSA_NEXUS_RESET_TYPE 0x05
111
112/* Task Management Functions */
113#define HPSA_TMF_ABORT_TASK 0x00
114#define HPSA_TMF_ABORT_TASK_SET 0x01
115#define HPSA_TMF_CLEAR_ACA 0x02
116#define HPSA_TMF_CLEAR_TASK_SET 0x03
117#define HPSA_TMF_QUERY_TASK 0x04
118#define HPSA_TMF_QUERY_TASK_SET 0x05
119#define HPSA_TMF_QUERY_ASYNCEVENT 0x06
120
121
122
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800123/* config space register offsets */
124#define CFG_VENDORID 0x00
125#define CFG_DEVICEID 0x02
126#define CFG_I2OBAR 0x10
127#define CFG_MEM1BAR 0x14
128
129/* i2o space register offsets */
130#define I2O_IBDB_SET 0x20
131#define I2O_IBDB_CLEAR 0x70
132#define I2O_INT_STATUS 0x30
133#define I2O_INT_MASK 0x34
134#define I2O_IBPOST_Q 0x40
135#define I2O_OBPOST_Q 0x44
136#define I2O_DMA1_CFG 0x214
137
138/* Configuration Table */
139#define CFGTBL_ChangeReq 0x00000001l
140#define CFGTBL_AccCmds 0x00000001l
Stephen M. Cameron1df85522010-06-16 13:51:40 -0500141#define DOORBELL_CTLR_RESET 0x00000004l
Stephen M. Cameroncf0b08d2011-05-03 14:59:46 -0500142#define DOORBELL_CTLR_RESET2 0x00000020l
Stephen M. Cameron76438d02014-02-18 13:55:43 -0600143#define DOORBELL_CLEAR_EVENTS 0x00000040l
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800144
145#define CFGTBL_Trans_Simple 0x00000002l
Don Brace303932f2010-02-04 08:42:40 -0600146#define CFGTBL_Trans_Performant 0x00000004l
Matt Gatese1f7de02014-02-18 13:55:17 -0600147#define CFGTBL_Trans_io_accel1 0x00000080l
Stephen M. Cameron1f7cee82014-02-18 13:56:09 -0600148#define CFGTBL_Trans_io_accel2 0x00000100l
Stephen M. Cameron960a30e2011-02-15 15:33:03 -0600149#define CFGTBL_Trans_use_short_tags 0x20000000l
Matt Gates254f7962012-05-01 11:43:06 -0500150#define CFGTBL_Trans_enable_directed_msix (1 << 30)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800151
152#define CFGTBL_BusType_Ultra2 0x00000001l
153#define CFGTBL_BusType_Ultra3 0x00000002l
154#define CFGTBL_BusType_Fibre1G 0x00000100l
155#define CFGTBL_BusType_Fibre2G 0x00000200l
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600156
157/* VPD Inquiry types */
Stephen M. Cameron1b70150a2014-02-18 13:57:16 -0600158#define HPSA_VPD_SUPPORTED_PAGES 0x00
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600159#define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1
160#define HPSA_VPD_LV_IOACCEL_STATUS 0xC2
Stephen M. Cameron98465902014-02-21 16:25:00 -0600161#define HPSA_VPD_LV_STATUS 0xC3
Stephen M. Cameron1b70150a2014-02-18 13:57:16 -0600162#define HPSA_VPD_HEADER_SZ 4
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600163
Stephen M. Cameron98465902014-02-21 16:25:00 -0600164/* Logical volume states */
Stephen M. Cameron67955ba2014-05-29 10:54:25 -0500165#define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff
Stephen M. Cameron98465902014-02-21 16:25:00 -0600166#define HPSA_LV_OK 0x0
Scott Benesh5ca01202015-07-18 11:13:04 -0500167#define HPSA_LV_NOT_AVAILABLE 0x0b
Stephen M. Cameron98465902014-02-21 16:25:00 -0600168#define HPSA_LV_UNDERGOING_ERASE 0x0F
169#define HPSA_LV_UNDERGOING_RPI 0x12
170#define HPSA_LV_PENDING_RPI 0x13
171#define HPSA_LV_ENCRYPTED_NO_KEY 0x14
172#define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15
173#define HPSA_LV_UNDERGOING_ENCRYPTION 0x16
174#define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17
175#define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18
176#define HPSA_LV_PENDING_ENCRYPTION 0x19
177#define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A
178
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800179struct vals32 {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600180 u32 lower;
181 u32 upper;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800182};
183
184union u64bit {
185 struct vals32 val32;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600186 u64 val;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800187};
188
189/* FIXME this is a per controller value (barf!) */
Scott Teelb7ec0212011-10-26 16:21:12 -0500190#define HPSA_MAX_LUN 1024
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800191#define HPSA_MAX_PHYS_LUN 1024
Scott Teelaca4a522012-01-19 14:01:19 -0600192#define MAX_EXT_TARGETS 32
Scott Teelb7ec0212011-10-26 16:21:12 -0500193#define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
Scott Teelaca4a522012-01-19 14:01:19 -0600194 MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800195
196/* SCSI-3 Commands */
197#pragma pack(1)
198
199#define HPSA_INQUIRY 0x12
200struct InquiryData {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600201 u8 data_byte[36];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800202};
203
204#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
205#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
Matt Gatesa93aa1f2014-02-18 13:55:07 -0600206#define HPSA_REPORT_PHYS_EXTENDED 0x02
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600207#define HPSA_CISS_READ 0xc0 /* CISS Read */
208#define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */
209
210#define RAID_MAP_MAX_ENTRIES 256
211
212struct raid_map_disk_data {
213 u32 ioaccel_handle; /**< Handle to access this disk via the
214 * I/O accelerator */
215 u8 xor_mult[2]; /**< XOR multipliers for this position,
216 * valid for data disks only */
217 u8 reserved[2];
218};
219
220struct raid_map_data {
Don Brace2b08b3e2015-01-23 16:41:09 -0600221 __le32 structure_size; /* Size of entire structure in bytes */
222 __le32 volume_blk_size; /* bytes / block in the volume */
223 __le64 volume_blk_cnt; /* logical blocks on the volume */
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600224 u8 phys_blk_shift; /* Shift factor to convert between
225 * units of logical blocks and physical
226 * disk blocks */
227 u8 parity_rotation_shift; /* Shift factor to convert between units
228 * of logical stripes and physical
229 * stripes */
Don Brace2b08b3e2015-01-23 16:41:09 -0600230 __le16 strip_size; /* blocks used on each disk / stripe */
231 __le64 disk_starting_blk; /* First disk block used in volume */
232 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
233 __le16 data_disks_per_row; /* data disk entries / row in the map */
234 __le16 metadata_disks_per_row;/* mirror/parity disk entries / row
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600235 * in the map */
Don Brace2b08b3e2015-01-23 16:41:09 -0600236 __le16 row_cnt; /* rows in each layout map */
237 __le16 layout_map_count; /* layout maps (1 map per mirror/parity
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600238 * group) */
Don Brace2b08b3e2015-01-23 16:41:09 -0600239 __le16 flags; /* Bit 0 set if encryption enabled */
Scott Teeldd0e19f2014-02-18 13:57:31 -0600240#define RAID_MAP_FLAG_ENCRYPT_ON 0x01
Don Brace2b08b3e2015-01-23 16:41:09 -0600241 __le16 dekindex; /* Data encryption key index. */
Scott Teeldd0e19f2014-02-18 13:57:31 -0600242 u8 reserved[16];
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600243 struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
244};
245
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800246struct ReportLUNdata {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600247 u8 LUNListLength[4];
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600248 u8 extended_response_flag;
249 u8 reserved[3];
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600250 u8 LUN[HPSA_MAX_LUN][8];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800251};
252
Stephen M. Camerond5b5d962014-05-29 10:53:34 -0500253struct ext_report_lun_entry {
254 u8 lunid[8];
Stephen Cameron41ce4c32015-04-23 09:31:47 -0500255#define MASKED_DEVICE(x) ((x)[3] & 0xC0)
Don Brace03383732015-01-23 16:43:30 -0600256#define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
257#define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
258#define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
259 GET_BMIC_LEVEL_TWO_TARGET((lunid)))
Stephen M. Camerond5b5d962014-05-29 10:53:34 -0500260 u8 wwid[8];
261 u8 device_type;
262 u8 device_flags;
Stephen Cameron41ce4c32015-04-23 09:31:47 -0500263#define NON_DISK_PHYS_DEV(x) ((x)[17] & 0x01)
264#define PHYS_IOACCEL(x) ((x)[17] & 0x08)
Stephen M. Camerond5b5d962014-05-29 10:53:34 -0500265 u8 lun_count; /* multi-lun device, how many luns */
266 u8 redundant_paths;
267 u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
268};
269
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800270struct ReportExtendedLUNdata {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600271 u8 LUNListLength[4];
272 u8 extended_response_flag;
273 u8 reserved[3];
Stephen M. Cameron92084712014-11-14 17:26:54 -0600274 struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800275};
276
277struct SenseSubsystem_info {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600278 u8 reserved[36];
279 u8 portname[8];
280 u8 reserved1[1108];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800281};
282
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800283/* BMIC commands */
284#define BMIC_READ 0x26
285#define BMIC_WRITE 0x27
286#define BMIC_CACHE_FLUSH 0xc2
287#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
Stephen M. Camerone85c5972012-05-01 11:43:42 -0500288#define BMIC_FLASH_FIRMWARE 0xF7
Stephen M. Cameron316b2212014-02-21 16:25:15 -0600289#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
Don Brace03383732015-01-23 16:43:30 -0600290#define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800291
292/* Command List Structure */
293union SCSI3Addr {
294 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600295 u8 Dev;
296 u8 Bus:6;
297 u8 Mode:2; /* b00 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800298 } PeripDev;
299 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600300 u8 DevLSB;
301 u8 DevMSB:6;
302 u8 Mode:2; /* b01 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800303 } LogDev;
304 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600305 u8 Dev:5;
306 u8 Bus:3;
307 u8 Targ:6;
308 u8 Mode:2; /* b10 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800309 } LogUnit;
310};
311
312struct PhysDevAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600313 u32 TargetId:24;
314 u32 Bus:6;
315 u32 Mode:2;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800316 /* 2 level target device addr */
317 union SCSI3Addr Target[2];
318};
319
320struct LogDevAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600321 u32 VolId:30;
322 u32 Mode:2;
323 u8 reserved[4];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800324};
325
326union LUNAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600327 u8 LunAddrBytes[8];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800328 union SCSI3Addr SCSI3Lun[4];
329 struct PhysDevAddr PhysDev;
330 struct LogDevAddr LogDev;
331};
332
333struct CommandListHeader {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600334 u8 ReplyQueue;
335 u8 SGList;
Don Brace2b08b3e2015-01-23 16:41:09 -0600336 __le16 SGTotal;
337 __le64 tag;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800338 union LUNAddr LUN;
339};
340
341struct RequestBlock {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600342 u8 CDBLen;
Stephen M. Camerona505b862014-11-14 17:27:04 -0600343 /*
344 * type_attr_dir:
345 * type: low 3 bits
346 * attr: middle 3 bits
347 * dir: high 2 bits
348 */
349 u8 type_attr_dir;
350#define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
351 (((a) & 0x07) << 3) |\
352 ((t) & 0x07))
353#define GET_TYPE(tad) ((tad) & 0x07)
354#define GET_ATTR(tad) (((tad) >> 3) & 0x07)
355#define GET_DIR(tad) (((tad) >> 6) & 0x03)
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600356 u16 Timeout;
357 u8 CDB[16];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800358};
359
360struct ErrDescriptor {
Don Brace2b08b3e2015-01-23 16:41:09 -0600361 __le64 Addr;
362 __le32 Len;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800363};
364
365struct SGDescriptor {
Don Brace2b08b3e2015-01-23 16:41:09 -0600366 __le64 Addr;
367 __le32 Len;
368 __le32 Ext;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800369};
370
371union MoreErrInfo {
372 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600373 u8 Reserved[3];
374 u8 Type;
375 u32 ErrorInfo;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800376 } Common_Info;
377 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600378 u8 Reserved[2];
379 u8 offense_size; /* size of offending entry */
380 u8 offense_num; /* byte # of offense 0-base */
381 u32 offense_value;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800382 } Invalid_Cmd;
383};
384struct ErrorInfo {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600385 u8 ScsiStatus;
386 u8 SenseLen;
387 u16 CommandStatus;
388 u32 ResidualCnt;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800389 union MoreErrInfo MoreErrInfo;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600390 u8 SenseInfo[SENSEINFOBYTES];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800391};
392/* Command types */
393#define CMD_IOCTL_PEND 0x01
394#define CMD_SCSI 0x03
Matt Gatese1f7de02014-02-18 13:55:17 -0600395#define CMD_IOACCEL1 0x04
Mike Millerb66cc252014-02-18 13:56:04 -0600396#define CMD_IOACCEL2 0x05
Stephen Cameron8be986c2015-04-23 09:34:06 -0500397#define IOACCEL2_TMF 0x06
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800398
Don Bracef2405db2015-01-23 16:43:09 -0600399#define DIRECT_LOOKUP_SHIFT 4
Stephen M. Camerond896f3f2011-01-06 14:47:53 -0600400#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
Don Brace303932f2010-02-04 08:42:40 -0600401
402#define HPSA_ERROR_BIT 0x02
403struct ctlr_info; /* defined in hpsa.h */
Don Bracef2405db2015-01-23 16:43:09 -0600404/* The size of this structure needs to be divisible by 128
405 * on all architectures. The low 4 bits of the addresses
Don Brace303932f2010-02-04 08:42:40 -0600406 * are used as follows:
407 *
408 * bit 0: to device, used to indicate "performant mode" command
409 * from device, indidcates error status.
410 * bit 1-3: to device, indicates block fetch table entry for
411 * reducing DMA in fetching commands from host memory.
Don Brace303932f2010-02-04 08:42:40 -0600412 */
413
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500414#define COMMANDLIST_ALIGNMENT 128
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800415struct CommandList {
416 struct CommandListHeader Header;
417 struct RequestBlock Request;
418 struct ErrDescriptor ErrDesc;
Stephen M. Camerond66ae082012-01-19 14:00:48 -0600419 struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800420 /* information associated with the command */
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600421 u32 busaddr; /* physical addr of this record */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800422 struct ErrorInfo *err_info; /* pointer to the allocated mem */
423 struct ctlr_info *h;
424 int cmd_type;
425 long cmdindex;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800426 struct completion *waiting;
Stephen Cameron7fa30302015-01-23 16:44:30 -0600427 struct scsi_cmnd *scsi_cmd;
Don Brace080ef1c2015-01-23 16:43:25 -0600428 struct work_struct work;
Don Brace03383732015-01-23 16:43:30 -0600429
430 /*
431 * For commands using either of the two "ioaccel" paths to
432 * bypass the RAID stack and go directly to the physical disk
433 * phys_disk is a pointer to the hpsa_scsi_dev_t to which the
434 * i/o is destined. We need to store that here because the command
435 * may potentially encounter TASK SET FULL and need to be resubmitted
436 * For "normal" i/o's not using the "ioaccel" paths, phys_disk is
437 * not used.
438 */
439 struct hpsa_scsi_dev_t *phys_disk;
Webb Scalesa58e7e52015-04-23 09:34:16 -0500440
441 int abort_pending;
Webb Scalesd604f532015-04-23 09:35:22 -0500442 struct hpsa_scsi_dev_t *reset_pending;
Stephen Cameron360c73b2015-04-23 09:32:32 -0500443 atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500444} __aligned(COMMANDLIST_ALIGNMENT);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800445
Matt Gatese1f7de02014-02-18 13:55:17 -0600446/* Max S/G elements in I/O accelerator command */
447#define IOACCEL1_MAXSGENTRIES 24
Mike Millerb66cc252014-02-18 13:56:04 -0600448#define IOACCEL2_MAXSGENTRIES 28
Matt Gatese1f7de02014-02-18 13:55:17 -0600449
450/*
451 * Structure for I/O accelerator (mode 1) commands.
452 * Note that this structure must be 128-byte aligned in size.
453 */
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500454#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
Matt Gatese1f7de02014-02-18 13:55:17 -0600455struct io_accel1_cmd {
Don Brace2b08b3e2015-01-23 16:41:09 -0600456 __le16 dev_handle; /* 0x00 - 0x01 */
Matt Gatese1f7de02014-02-18 13:55:17 -0600457 u8 reserved1; /* 0x02 */
458 u8 function; /* 0x03 */
459 u8 reserved2[8]; /* 0x04 - 0x0B */
460 u32 err_info; /* 0x0C - 0x0F */
461 u8 reserved3[2]; /* 0x10 - 0x11 */
462 u8 err_info_len; /* 0x12 */
463 u8 reserved4; /* 0x13 */
464 u8 sgl_offset; /* 0x14 */
465 u8 reserved5[7]; /* 0x15 - 0x1B */
Don Brace2b08b3e2015-01-23 16:41:09 -0600466 __le32 transfer_len; /* 0x1C - 0x1F */
Matt Gatese1f7de02014-02-18 13:55:17 -0600467 u8 reserved6[4]; /* 0x20 - 0x23 */
Don Brace2b08b3e2015-01-23 16:41:09 -0600468 __le16 io_flags; /* 0x24 - 0x25 */
Matt Gatese1f7de02014-02-18 13:55:17 -0600469 u8 reserved7[14]; /* 0x26 - 0x33 */
470 u8 LUN[8]; /* 0x34 - 0x3B */
Don Brace2b08b3e2015-01-23 16:41:09 -0600471 __le32 control; /* 0x3C - 0x3F */
Matt Gatese1f7de02014-02-18 13:55:17 -0600472 u8 CDB[16]; /* 0x40 - 0x4F */
473 u8 reserved8[16]; /* 0x50 - 0x5F */
Don Brace2b08b3e2015-01-23 16:41:09 -0600474 __le16 host_context_flags; /* 0x60 - 0x61 */
475 __le16 timeout_sec; /* 0x62 - 0x63 */
Matt Gatese1f7de02014-02-18 13:55:17 -0600476 u8 ReplyQueue; /* 0x64 */
477 u8 reserved9[3]; /* 0x65 - 0x67 */
Don Brace2b08b3e2015-01-23 16:41:09 -0600478 __le64 tag; /* 0x68 - 0x6F */
479 __le64 host_addr; /* 0x70 - 0x77 */
Matt Gatese1f7de02014-02-18 13:55:17 -0600480 u8 CISS_LUN[8]; /* 0x78 - 0x7F */
481 struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500482} __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
Matt Gatese1f7de02014-02-18 13:55:17 -0600483
484#define IOACCEL1_FUNCTION_SCSIIO 0x00
485#define IOACCEL1_SGLOFFSET 32
486
487#define IOACCEL1_IOFLAGS_IO_REQ 0x4000
488#define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F
489#define IOACCEL1_IOFLAGS_CDBLEN_MAX 16
490
491#define IOACCEL1_CONTROL_NODATAXFER 0x00000000
492#define IOACCEL1_CONTROL_DATA_OUT 0x01000000
493#define IOACCEL1_CONTROL_DATA_IN 0x02000000
494#define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800
495#define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
496#define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000
497#define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100
498#define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200
499#define IOACCEL1_CONTROL_ACA 0x00000400
500
501#define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013
502
503#define IOACCEL1_BUSADDR_CMDTYPE 0x00000060
504
Mike Millerb66cc252014-02-18 13:56:04 -0600505struct ioaccel2_sg_element {
Don Brace2b08b3e2015-01-23 16:41:09 -0600506 __le64 address;
507 __le32 length;
Mike Millerb66cc252014-02-18 13:56:04 -0600508 u8 reserved[3];
509 u8 chain_indicator;
510#define IOACCEL2_CHAIN 0x80
511};
512
513/*
514 * SCSI Response Format structure for IO Accelerator Mode 2
515 */
516struct io_accel2_scsi_response {
517 u8 IU_type;
518#define IOACCEL2_IU_TYPE_SRF 0x60
519 u8 reserved1[3];
520 u8 req_id[4]; /* request identifier */
521 u8 reserved2[4];
522 u8 serv_response; /* service response */
523#define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000
524#define IOACCEL2_SERV_RESPONSE_FAILURE 0x001
525#define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002
526#define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003
527#define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004
528#define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005
529 u8 status; /* status */
530#define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00
531#define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02
532#define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08
533#define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18
534#define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
535#define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
Scott Teelc3497752014-02-18 13:56:34 -0600536#define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
Joe Handzikc40820d2015-04-23 09:33:32 -0500537#define IOACCEL2_STATUS_SR_IO_ERROR 0x01
538#define IOACCEL2_STATUS_SR_IO_ABORTED 0x02
539#define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03
540#define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04
541#define IOACCEL2_STATUS_SR_UNDERRUN 0x51
542#define IOACCEL2_STATUS_SR_OVERRUN 0x75
Mike Millerb66cc252014-02-18 13:56:04 -0600543 u8 data_present; /* low 2 bits */
544#define IOACCEL2_NO_DATAPRESENT 0x000
545#define IOACCEL2_RESPONSE_DATAPRESENT 0x001
546#define IOACCEL2_SENSE_DATA_PRESENT 0x002
547#define IOACCEL2_RESERVED 0x003
548 u8 sense_data_len; /* sense/response data length */
549 u8 resid_cnt[4]; /* residual count */
550 u8 sense_data_buff[32]; /* sense/response data buffer */
551};
552
Mike Millerb66cc252014-02-18 13:56:04 -0600553/*
554 * Structure for I/O accelerator (mode 2 or m2) commands.
555 * Note that this structure must be 128-byte aligned in size.
556 */
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500557#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
Mike Millerb66cc252014-02-18 13:56:04 -0600558struct io_accel2_cmd {
559 u8 IU_type; /* IU Type */
Scott Teeldd0e19f2014-02-18 13:57:31 -0600560 u8 direction; /* direction, memtype, and encryption */
561#define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */
562#define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
563 /* 0b=PCIe, 1b=DDR */
564#define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
565 /* 0=off, 1=on */
Mike Millerb66cc252014-02-18 13:56:04 -0600566 u8 reply_queue; /* Reply Queue ID */
567 u8 reserved1; /* Reserved */
Don Brace2b08b3e2015-01-23 16:41:09 -0600568 __le32 scsi_nexus; /* Device Handle */
569 __le32 Tag; /* cciss tag, lower 4 bytes only */
570 __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */
Mike Millerb66cc252014-02-18 13:56:04 -0600571 u8 cdb[16]; /* SCSI Command Descriptor Block */
572 u8 cciss_lun[8]; /* 8 byte SCSI address */
Don Brace2b08b3e2015-01-23 16:41:09 -0600573 __le32 data_len; /* Total bytes to transfer */
Mike Millerb66cc252014-02-18 13:56:04 -0600574 u8 cmd_priority_task_attr; /* priority and task attrs */
575#define IOACCEL2_PRIORITY_MASK 0x78
576#define IOACCEL2_ATTR_MASK 0x07
577 u8 sg_count; /* Number of sg elements */
Don Brace2b08b3e2015-01-23 16:41:09 -0600578 __le16 dekindex; /* Data encryption key index */
579 __le64 err_ptr; /* Error Pointer */
580 __le32 err_len; /* Error Length*/
581 __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */
Mike Millerb66cc252014-02-18 13:56:04 -0600582 struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
583 struct io_accel2_scsi_response error_data;
Stephen M. Cameron35d697c2014-05-29 10:52:52 -0500584} __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
Mike Millerb66cc252014-02-18 13:56:04 -0600585
586/*
587 * defines for Mode 2 command struct
588 * FIXME: this can't be all I need mfm
589 */
590#define IOACCEL2_IU_TYPE 0x40
Scott Teel54b6e9e2014-02-18 13:56:45 -0600591#define IOACCEL2_IU_TMF_TYPE 0x41
Mike Millerb66cc252014-02-18 13:56:04 -0600592#define IOACCEL2_DIR_NO_DATA 0x00
593#define IOACCEL2_DIR_DATA_IN 0x01
594#define IOACCEL2_DIR_DATA_OUT 0x02
Stephen Cameron8be986c2015-04-23 09:34:06 -0500595#define IOACCEL2_TMF_ABORT 0x01
Mike Millerb66cc252014-02-18 13:56:04 -0600596/*
597 * SCSI Task Management Request format for Accelerator Mode 2
598 */
599struct hpsa_tmf_struct {
600 u8 iu_type; /* Information Unit Type */
601 u8 reply_queue; /* Reply Queue ID */
602 u8 tmf; /* Task Management Function */
603 u8 reserved1; /* byte 3 Reserved */
Stephen Cameron8be986c2015-04-23 09:34:06 -0500604 __le32 it_nexus; /* SCSI I-T Nexus */
Mike Millerb66cc252014-02-18 13:56:04 -0600605 u8 lun_id[8]; /* LUN ID for TMF request */
Don Brace2b08b3e2015-01-23 16:41:09 -0600606 __le64 tag; /* cciss tag associated w/ request */
607 __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */
608 __le64 error_ptr; /* Error Pointer */
609 __le32 error_len; /* Error Length */
Stephen Cameron8be986c2015-04-23 09:34:06 -0500610} __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
Mike Millerb66cc252014-02-18 13:56:04 -0600611
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800612/* Configuration Table Structure */
613struct HostWrite {
Don Brace2b08b3e2015-01-23 16:41:09 -0600614 __le32 TransportRequest;
615 __le32 command_pool_addr_hi;
616 __le32 CoalIntDelay;
617 __le32 CoalIntCount;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800618};
619
Don Brace303932f2010-02-04 08:42:40 -0600620#define SIMPLE_MODE 0x02
621#define PERFORMANT_MODE 0x04
622#define MEMQ_MODE 0x08
Matt Gatese1f7de02014-02-18 13:55:17 -0600623#define IOACCEL_MODE_1 0x80
Don Brace303932f2010-02-04 08:42:40 -0600624
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600625#define DRIVER_SUPPORT_UA_ENABLE 0x00000001
626
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800627struct CfgTable {
Don Brace2b08b3e2015-01-23 16:41:09 -0600628 u8 Signature[4];
629 __le32 SpecValence;
630 __le32 TransportSupport;
631 __le32 TransportActive;
632 struct HostWrite HostWrite;
633 __le32 CmdsOutMax;
634 __le32 BusTypes;
635 __le32 TransMethodOffset;
636 u8 ServerName[16];
637 __le32 HeartBeat;
638 __le32 driver_support;
639#define ENABLE_SCSI_PREFETCH 0x100
640#define ENABLE_UNIT_ATTN 0x01
641 __le32 MaxScatterGatherElements;
642 __le32 MaxLogicalUnits;
643 __le32 MaxPhysicalDevices;
644 __le32 MaxPhysicalDrivesPerLogicalUnit;
645 __le32 MaxPerformantModeCommands;
646 __le32 MaxBlockFetch;
647 __le32 PowerConservationSupport;
648 __le32 PowerConservationEnable;
649 __le32 TMFSupportFlags;
Stephen M. Cameron75167d22012-05-01 11:42:51 -0500650 u8 TMFTagMask[8];
651 u8 reserved[0x78 - 0x70];
Don Brace2b08b3e2015-01-23 16:41:09 -0600652 __le32 misc_fw_support; /* offset 0x78 */
653#define MISC_FW_DOORBELL_RESET 0x02
654#define MISC_FW_DOORBELL_RESET2 0x010
655#define MISC_FW_RAID_OFFLOAD_BASIC 0x020
656#define MISC_FW_EVENT_NOTIFY 0x080
Stephen M. Cameron580ada32011-05-03 14:59:10 -0500657 u8 driver_version[32];
Don Brace2b08b3e2015-01-23 16:41:09 -0600658 __le32 max_cached_write_size;
659 u8 driver_scratchpad[16];
660 __le32 max_error_info_length;
661 __le32 io_accel_max_embedded_sg_count;
662 __le32 io_accel_request_size_offset;
663 __le32 event_notify;
664#define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
665#define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
666 __le32 clear_event_notify;
Don Brace303932f2010-02-04 08:42:40 -0600667};
668
669#define NUM_BLOCKFETCH_ENTRIES 8
670struct TransTable_struct {
Don Brace2b08b3e2015-01-23 16:41:09 -0600671 __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
672 __le32 RepQSize;
673 __le32 RepQCount;
674 __le32 RepQCtrAddrLow32;
675 __le32 RepQCtrAddrHigh32;
Stephen M. Cameronf89439b2014-05-29 10:53:02 -0500676#define MAX_REPLY_QUEUES 64
Matt Gates254f7962012-05-01 11:43:06 -0500677 struct vals32 RepQAddr[MAX_REPLY_QUEUES];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800678};
679
680struct hpsa_pci_info {
681 unsigned char bus;
682 unsigned char dev_fn;
683 unsigned short domain;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600684 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800685};
686
Don Brace03383732015-01-23 16:43:30 -0600687struct bmic_identify_physical_device {
688 u8 scsi_bus; /* SCSI Bus number on controller */
689 u8 scsi_id; /* SCSI ID on this bus */
690 __le16 block_size; /* sector size in bytes */
691 __le32 total_blocks; /* number for sectors on drive */
692 __le32 reserved_blocks; /* controller reserved (RIS) */
693 u8 model[40]; /* Physical Drive Model */
694 u8 serial_number[40]; /* Drive Serial Number */
695 u8 firmware_revision[8]; /* drive firmware revision */
696 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
697 u8 compaq_drive_stamp; /* 0 means drive not stamped */
698 u8 last_failure_reason;
699#define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01
700#define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02
701#define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03
702#define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04
703#define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05
704#define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06
705#define BMIC_LAST_FAILURE_TIMEOUT 0x07
706#define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08
707#define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09
708#define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a
709#define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b
710#define BMIC_LAST_FAILURE_NOT_READY 0x0c
711#define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d
712#define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e
713#define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f
714#define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10
715#define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11
716#define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12
717#define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13
718#define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14
719#define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15
720#define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16
721#define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17
722#define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18
723#define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19
724#define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a
725#define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b
726#define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c
727#define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d
728#define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e
729#define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f
730#define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20
731#define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21
732#define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22
733#define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23
734#define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24
735#define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25
736#define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26
737#define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27
738#define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28
739#define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29
740#define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a
741#define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b
742
743#define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37
744#define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38
745#define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40
746#define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41
747#define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42
748#define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80
749#define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81
750#define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82
751#define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83
752
753 u8 flags;
754 u8 more_flags;
755 u8 scsi_lun; /* SCSI LUN for phys drive */
756 u8 yet_more_flags;
757 u8 even_more_flags;
758 __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */
759 u8 phys_connector[2]; /* connector number on controller */
760 u8 phys_box_on_bus; /* phys enclosure this drive resides */
761 u8 phys_bay_in_box; /* phys drv bay this drive resides */
762 __le32 rpm; /* Drive rotational speed in rpm */
763 u8 device_type; /* type of drive */
764 u8 sata_version; /* only valid when drive_type is SATA */
765 __le64 big_total_block_count;
766 __le64 ris_starting_lba;
767 __le32 ris_size;
768 u8 wwid[20];
769 u8 controller_phy_map[32];
770 __le16 phy_count;
771 u8 phy_connected_dev_type[256];
772 u8 phy_to_drive_bay_num[256];
773 __le16 phy_to_attached_dev_index[256];
774 u8 box_index;
775 u8 reserved;
776 __le16 extra_physical_drive_flags;
777#define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \
778 (idphydrv->extra_physical_drive_flags & (1 << 10))
779 u8 negotiated_link_rate[256];
780 u8 phy_to_phy_map[256];
781 u8 redundant_path_present_map;
782 u8 redundant_path_failure_map;
783 u8 active_path_number;
784 __le16 alternate_paths_phys_connector[8];
785 u8 alternate_paths_phys_box_on_port[8];
786 u8 multi_lun_device_lun_count;
787 u8 minimum_good_fw_revision[8];
788 u8 unique_inquiry_bytes[20];
789 u8 current_temperature_degreesC;
790 u8 temperature_threshold_degreesC;
791 u8 max_temperature_degreesC;
792 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */
793 __le16 current_queue_depth_limit;
794 u8 switch_name[10];
795 __le16 switch_port;
796 u8 alternate_paths_switch_name[40];
797 u8 alternate_paths_switch_port[8];
798 __le16 power_on_hours; /* valid only if gas gauge supported */
799 __le16 percent_endurance_used; /* valid only if gas gauge supported. */
800#define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \
801 ((idphydrv->percent_endurance_used & 0x80) || \
802 (idphydrv->percent_endurance_used > 10000))
803 u8 drive_authentication;
804#define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \
805 (idphydrv->drive_authentication == 0x80)
806 u8 smart_carrier_authentication;
807#define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \
808 (idphydrv->smart_carrier_authentication != 0x0)
809#define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \
810 (idphydrv->smart_carrier_authentication == 0x01)
811 u8 smart_carrier_app_fw_version;
812 u8 smart_carrier_bootloader_fw_version;
813 u8 encryption_key_name[64];
814 __le32 misc_drive_flags;
815 __le16 dek_index;
816 u8 padding[112];
817};
818
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800819#pragma pack()
820#endif /* HPSA_CMD_H */