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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
34
Jesse Barnes585fb112008-07-29 11:54:06 -070035#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080037#include "intel_ringbuffer.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070038#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070039#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010040#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020041#include <drm/intel-gtt.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020042#include <linux/backlight.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070043#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020044#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010045#include <linux/pm_qos.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070046
Linus Torvalds1da177e2005-04-16 15:20:36 -070047/* General customization:
48 */
49
50#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52#define DRIVER_NAME "i915"
53#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070054#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Jesse Barnes317c35d2008-08-25 15:11:06 -070056enum pipe {
57 PIPE_A = 0,
58 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080059 PIPE_C,
60 I915_MAX_PIPES
Jesse Barnes317c35d2008-08-25 15:11:06 -070061};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080062#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -070063
Paulo Zanonia5c961d2012-10-24 15:59:34 -020064enum transcoder {
65 TRANSCODER_A = 0,
66 TRANSCODER_B,
67 TRANSCODER_C,
68 TRANSCODER_EDP = 0xF,
69};
70#define transcoder_name(t) ((t) + 'A')
71
Jesse Barnes80824002009-09-10 15:28:06 -070072enum plane {
73 PLANE_A = 0,
74 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080075 PLANE_C,
Jesse Barnes80824002009-09-10 15:28:06 -070076};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080077#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -080078
Eugeni Dodonov2b139522012-03-29 12:32:22 -030079enum port {
80 PORT_A = 0,
81 PORT_B,
82 PORT_C,
83 PORT_D,
84 PORT_E,
85 I915_MAX_PORTS
86};
87#define port_name(p) ((p) + 'A')
88
Egbert Eich1d843f92013-02-25 12:06:49 -050089enum hpd_pin {
90 HPD_NONE = 0,
91 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
92 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
93 HPD_CRT,
94 HPD_SDVO_B,
95 HPD_SDVO_C,
96 HPD_PORT_B,
97 HPD_PORT_C,
98 HPD_PORT_D,
99 HPD_NUM_PINS
100};
101
Chris Wilson2a2d5482012-12-03 11:49:06 +0000102#define I915_GEM_GPU_DOMAINS \
103 (I915_GEM_DOMAIN_RENDER | \
104 I915_GEM_DOMAIN_SAMPLER | \
105 I915_GEM_DOMAIN_COMMAND | \
106 I915_GEM_DOMAIN_INSTRUCTION | \
107 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700108
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700109#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800110
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200111#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
112 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
113 if ((intel_encoder)->base.crtc == (__crtc))
114
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100115struct intel_pch_pll {
116 int refcount; /* count of number of CRTCs sharing this PLL */
117 int active; /* count of number of active CRTCs (i.e. DPMS on) */
118 bool on; /* is the PLL actually active? Disabled during modeset */
119 int pll_reg;
120 int fp0_reg;
121 int fp1_reg;
122};
123#define I915_NUM_PLLS 2
124
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100125/* Used by dp and fdi links */
126struct intel_link_m_n {
127 uint32_t tu;
128 uint32_t gmch_m;
129 uint32_t gmch_n;
130 uint32_t link_m;
131 uint32_t link_n;
132};
133
134void intel_link_compute_m_n(int bpp, int nlanes,
135 int pixel_clock, int link_clock,
136 struct intel_link_m_n *m_n);
137
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300138struct intel_ddi_plls {
139 int spll_refcount;
140 int wrpll1_refcount;
141 int wrpll2_refcount;
142};
143
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144/* Interface history:
145 *
146 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100147 * 1.2: Add Power Management
148 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100149 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000150 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000151 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
152 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 */
154#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000155#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156#define DRIVER_PATCHLEVEL 0
157
Eric Anholt673a3942008-07-30 12:06:12 -0700158#define WATCH_COHERENCY 0
Chris Wilson23bc5982010-09-29 16:10:57 +0100159#define WATCH_LISTS 0
Chris Wilson42d6ab42012-07-26 11:49:32 +0100160#define WATCH_GTT 0
Eric Anholt673a3942008-07-30 12:06:12 -0700161
Dave Airlie71acb5e2008-12-30 20:31:46 +1000162#define I915_GEM_PHYS_CURSOR_0 1
163#define I915_GEM_PHYS_CURSOR_1 2
164#define I915_GEM_PHYS_OVERLAY_REGS 3
165#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
166
167struct drm_i915_gem_phys_object {
168 int id;
169 struct page **page_list;
170 drm_dma_handle_t *handle;
Chris Wilson05394f32010-11-08 19:18:58 +0000171 struct drm_i915_gem_object *cur_obj;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000172};
173
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700174struct opregion_header;
175struct opregion_acpi;
176struct opregion_swsci;
177struct opregion_asle;
Keith Packard8d715f02011-11-18 20:39:01 -0800178struct drm_i915_private;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700179
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100180struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700181 struct opregion_header __iomem *header;
182 struct opregion_acpi __iomem *acpi;
183 struct opregion_swsci __iomem *swsci;
184 struct opregion_asle __iomem *asle;
185 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000186 u32 __iomem *lid_state;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100187};
Chris Wilson44834a62010-08-19 16:09:23 +0100188#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100189
Chris Wilson6ef3d422010-08-04 20:26:07 +0100190struct intel_overlay;
191struct intel_overlay_error_state;
192
Dave Airlie7c1c2872008-11-28 14:22:24 +1000193struct drm_i915_master_private {
194 drm_local_map_t *sarea;
195 struct _drm_i915_sarea *sarea_priv;
196};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800197#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300198#define I915_MAX_NUM_FENCES 32
199/* 32 fences + sign bit for FENCE_REG_NONE */
200#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800201
202struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200203 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000204 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100205 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800206};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000207
yakui_zhao9b9d1722009-05-31 17:17:17 +0800208struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100209 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800210 u8 dvo_port;
211 u8 slave_addr;
212 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100213 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400214 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800215};
216
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000217struct intel_display_error_state;
218
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700219struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200220 struct kref ref;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700221 u32 eir;
222 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700223 u32 ier;
Ben Widawskyb9a39062012-06-04 14:42:52 -0700224 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000225 u32 derrmr;
226 u32 forcewake;
Ben Widawsky9574b3f2012-04-26 16:03:01 -0700227 bool waiting[I915_NUM_RINGS];
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800228 u32 pipestat[I915_MAX_PIPES];
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100229 u32 tail[I915_NUM_RINGS];
230 u32 head[I915_NUM_RINGS];
Chris Wilson0f3b6842013-01-15 12:05:55 +0000231 u32 ctl[I915_NUM_RINGS];
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100232 u32 ipeir[I915_NUM_RINGS];
233 u32 ipehr[I915_NUM_RINGS];
234 u32 instdone[I915_NUM_RINGS];
235 u32 acthd[I915_NUM_RINGS];
Daniel Vetter7e3b8732012-02-01 22:26:45 +0100236 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
Chris Wilsondf2b23d2012-11-27 17:06:54 +0000237 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
Chris Wilson12f55812012-07-05 17:14:01 +0100238 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
Daniel Vetter7e3b8732012-02-01 22:26:45 +0100239 /* our own tracking of ring head and tail */
240 u32 cpu_ring_head[I915_NUM_RINGS];
241 u32 cpu_ring_tail[I915_NUM_RINGS];
Chris Wilson1d8f38f2010-10-29 19:00:51 +0100242 u32 error; /* gen6+ */
Ben Widawsky71e172e2012-08-20 16:15:13 -0700243 u32 err_int; /* gen7 */
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100244 u32 instpm[I915_NUM_RINGS];
245 u32 instps[I915_NUM_RINGS];
Ben Widawsky050ee912012-08-22 11:32:15 -0700246 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100247 u32 seqno[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000248 u64 bbaddr;
Daniel Vetter33f3f512011-12-14 13:57:39 +0100249 u32 fault_reg[I915_NUM_RINGS];
250 u32 done_reg;
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100251 u32 faddr[I915_NUM_RINGS];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200252 u64 fence[I915_MAX_NUM_FENCES];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700253 struct timeval time;
Chris Wilson52d39a22012-02-15 11:25:37 +0000254 struct drm_i915_error_ring {
255 struct drm_i915_error_object {
256 int page_count;
257 u32 gtt_offset;
258 u32 *pages[0];
Ben Widawsky8c123e52013-03-04 17:00:29 -0800259 } *ringbuffer, *batchbuffer, *ctx;
Chris Wilson52d39a22012-02-15 11:25:37 +0000260 struct drm_i915_error_request {
261 long jiffies;
262 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000263 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000264 } *requests;
265 int num_requests;
266 } ring[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000267 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000268 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000269 u32 name;
Chris Wilson0201f1e2012-07-20 12:41:01 +0100270 u32 rseqno, wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000271 u32 gtt_offset;
272 u32 read_domains;
273 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200274 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000275 s32 pinned:2;
276 u32 tiling:2;
277 u32 dirty:1;
278 u32 purgeable:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100279 s32 ring:4;
Chris Wilson93dfb402011-03-29 16:59:50 -0700280 u32 cache_level:2;
Chris Wilsonc724e8a2010-11-22 08:07:02 +0000281 } *active_bo, *pinned_bo;
282 u32 active_bo_count, pinned_bo_count;
Chris Wilson6ef3d422010-08-04 20:26:07 +0100283 struct intel_overlay_error_state *overlay;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000284 struct intel_display_error_state *display;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700285};
286
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100287struct intel_crtc_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100288struct intel_crtc;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100289
Jesse Barnese70236a2009-09-21 10:42:27 -0700290struct drm_i915_display_funcs {
Adam Jacksonee5382a2010-04-23 11:17:39 -0400291 bool (*fbc_enabled)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700292 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
293 void (*disable_fbc)(struct drm_device *dev);
294 int (*get_display_clock_speed)(struct drm_device *dev);
295 int (*get_fifo_size)(struct drm_device *dev, int plane);
Chris Wilsond2102462011-01-24 17:43:27 +0000296 void (*update_wm)(struct drm_device *dev);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800297 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
298 uint32_t sprite_width, int pixel_size);
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -0300299 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
300 struct drm_display_mode *mode);
Daniel Vetter47fab732012-10-26 10:58:18 +0200301 void (*modeset_global_resources)(struct drm_device *dev);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100302 /* Returns the active state of the crtc, and if the crtc is active,
303 * fills out the pipe-config with the hw state. */
304 bool (*get_pipe_config)(struct intel_crtc *,
305 struct intel_crtc_config *);
Eric Anholtf564048e2011-03-30 13:01:02 -0700306 int (*crtc_mode_set)(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -0700307 int x, int y,
308 struct drm_framebuffer *old_fb);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200309 void (*crtc_enable)(struct drm_crtc *crtc);
310 void (*crtc_disable)(struct drm_crtc *crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100311 void (*off)(struct drm_crtc *crtc);
Wu Fengguange0dac652011-09-05 14:25:34 +0800312 void (*write_eld)(struct drm_connector *connector,
313 struct drm_crtc *crtc);
Jesse Barnes674cf962011-04-28 14:27:04 -0700314 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700315 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700316 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
317 struct drm_framebuffer *fb,
318 struct drm_i915_gem_object *obj);
Jesse Barnes17638cd2011-06-24 12:19:23 -0700319 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
320 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100321 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700322 /* clock updates for mode set */
323 /* cursor updates */
324 /* render clock increase/decrease */
325 /* display clock increase/decrease */
326 /* pll clock increase/decrease */
Jesse Barnese70236a2009-09-21 10:42:27 -0700327};
328
Chris Wilson990bbda2012-07-02 11:51:02 -0300329struct drm_i915_gt_funcs {
330 void (*force_wake_get)(struct drm_i915_private *dev_priv);
331 void (*force_wake_put)(struct drm_i915_private *dev_priv);
332};
333
Daniel Vetterc96ea642012-08-08 22:01:51 +0200334#define DEV_INFO_FLAGS \
335 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
336 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
337 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
338 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
339 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
340 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
341 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
342 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
343 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
344 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
345 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
346 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
347 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
348 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
349 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
350 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
351 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
352 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
353 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
354 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
355 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
356 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
357 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
358 DEV_INFO_FLAG(has_llc)
359
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500360struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200361 u32 display_mmio_offset;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700362 u8 num_pipes:3;
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100363 u8 gen;
Akshay Joshi0206e352011-08-16 15:34:10 -0400364 u8 is_mobile:1;
365 u8 is_i85x:1;
366 u8 is_i915g:1;
367 u8 is_i945gm:1;
368 u8 is_g33:1;
369 u8 need_gfx_hws:1;
370 u8 is_g4x:1;
371 u8 is_pineview:1;
372 u8 is_broadwater:1;
373 u8 is_crestline:1;
374 u8 is_ivybridge:1;
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700375 u8 is_valleyview:1;
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200376 u8 has_force_wake:1;
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300377 u8 is_haswell:1;
Akshay Joshi0206e352011-08-16 15:34:10 -0400378 u8 has_fbc:1;
379 u8 has_pipe_cxsr:1;
380 u8 has_hotplug:1;
381 u8 cursor_needs_physical:1;
382 u8 has_overlay:1;
383 u8 overlay_needs_physical:1;
384 u8 supports_tv:1;
385 u8 has_bsd_ring:1;
386 u8 has_blt_ring:1;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200387 u8 has_llc:1;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500388};
389
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800390enum i915_cache_level {
391 I915_CACHE_NONE = 0,
392 I915_CACHE_LLC,
393 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
394};
395
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800396/* The Graphics Translation Table is the way in which GEN hardware translates a
397 * Graphics Virtual Address into a Physical Address. In addition to the normal
398 * collateral associated with any va->pa translations GEN hardware also has a
399 * portion of the GTT which can be mapped by the CPU and remain both coherent
400 * and correct (in cases like swizzling). That region is referred to as GMADR in
401 * the spec.
402 */
403struct i915_gtt {
404 unsigned long start; /* Start offset of used GTT */
405 size_t total; /* Total size GTT can map */
Ben Widawskybaa09f52013-01-24 13:49:57 -0800406 size_t stolen_size; /* Total size of stolen memory */
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800407
408 unsigned long mappable_end; /* End offset that we can CPU map */
409 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
410 phys_addr_t mappable_base; /* PA of our GMADR */
411
412 /** "Graphics Stolen Memory" holds the global PTEs */
413 void __iomem *gsm;
Ben Widawskya81cc002013-01-18 12:30:31 -0800414
415 bool do_idle_maps;
Ben Widawsky9c61a322013-01-18 12:30:32 -0800416 dma_addr_t scratch_page_dma;
417 struct page *scratch_page;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800418
419 /* global gtt ops */
Ben Widawskybaa09f52013-01-24 13:49:57 -0800420 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -0800421 size_t *stolen, phys_addr_t *mappable_base,
422 unsigned long *mappable_end);
Ben Widawskybaa09f52013-01-24 13:49:57 -0800423 void (*gtt_remove)(struct drm_device *dev);
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800424 void (*gtt_clear_range)(struct drm_device *dev,
425 unsigned int first_entry,
426 unsigned int num_entries);
427 void (*gtt_insert_entries)(struct drm_device *dev,
428 struct sg_table *st,
429 unsigned int pg_start,
430 enum i915_cache_level cache_level);
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800431};
Ben Widawskya54c0c22013-01-24 14:45:00 -0800432#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800433
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100434#define I915_PPGTT_PD_ENTRIES 512
435#define I915_PPGTT_PT_ENTRIES 1024
436struct i915_hw_ppgtt {
Ben Widawsky8f2c59f2012-09-24 08:55:51 -0700437 struct drm_device *dev;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100438 unsigned num_pd_entries;
439 struct page **pt_pages;
440 uint32_t pd_offset;
441 dma_addr_t *pt_dma_addr;
442 dma_addr_t scratch_page_dma_addr;
Daniel Vetterdef886c2013-01-24 14:44:56 -0800443
444 /* pte functions, mirroring the interface of the global gtt. */
445 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
446 unsigned int first_entry,
447 unsigned int num_entries);
448 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
449 struct sg_table *st,
450 unsigned int pg_start,
451 enum i915_cache_level cache_level);
Ben Widawskyb7c36d22013-04-08 18:43:56 -0700452 int (*enable)(struct drm_device *dev);
Daniel Vetter3440d262013-01-24 13:49:56 -0800453 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100454};
455
Ben Widawsky40521052012-06-04 14:42:43 -0700456
457/* This must match up with the value previously used for execbuf2.rsvd1. */
458#define DEFAULT_CONTEXT_ID 0
459struct i915_hw_context {
460 int id;
Ben Widawskye0556842012-06-04 14:42:46 -0700461 bool is_initialized;
Ben Widawsky40521052012-06-04 14:42:43 -0700462 struct drm_i915_file_private *file_priv;
463 struct intel_ring_buffer *ring;
464 struct drm_i915_gem_object *obj;
465};
466
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800467enum no_fbc_reason {
Chris Wilsonbed4a672010-09-11 10:47:47 +0100468 FBC_NO_OUTPUT, /* no outputs enabled to compress */
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800469 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
470 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
471 FBC_MODE_TOO_LARGE, /* mode too large for compression */
472 FBC_BAD_PLANE, /* fbc not supported on plane */
473 FBC_NOT_TILED, /* buffer not tiled */
Jesse Barnes9c928d12010-07-23 15:20:00 -0700474 FBC_MULTIPLE_PIPES, /* more than one pipe active */
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700475 FBC_MODULE_PARAM,
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800476};
477
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800478enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300479 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800480 PCH_IBX, /* Ibexpeak PCH */
481 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300482 PCH_LPT, /* Lynxpoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700483 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800484};
485
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200486enum intel_sbi_destination {
487 SBI_ICLK,
488 SBI_MPHY,
489};
490
Jesse Barnesb690e962010-07-19 13:53:12 -0700491#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700492#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100493#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Jesse Barnesb690e962010-07-19 13:53:12 -0700494
Dave Airlie8be48d92010-03-30 05:34:14 +0000495struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100496struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000497
Daniel Vetterc2b91522012-02-14 22:37:19 +0100498struct intel_gmbus {
499 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000500 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100501 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100502 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100503 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100504 struct drm_i915_private *dev_priv;
505};
506
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100507struct i915_suspend_saved_registers {
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000508 u8 saveLBB;
509 u32 saveDSPACNTR;
510 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000511 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000512 u32 savePIPEACONF;
513 u32 savePIPEBCONF;
514 u32 savePIPEASRC;
515 u32 savePIPEBSRC;
516 u32 saveFPA0;
517 u32 saveFPA1;
518 u32 saveDPLL_A;
519 u32 saveDPLL_A_MD;
520 u32 saveHTOTAL_A;
521 u32 saveHBLANK_A;
522 u32 saveHSYNC_A;
523 u32 saveVTOTAL_A;
524 u32 saveVBLANK_A;
525 u32 saveVSYNC_A;
526 u32 saveBCLRPAT_A;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000527 u32 saveTRANSACONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800528 u32 saveTRANS_HTOTAL_A;
529 u32 saveTRANS_HBLANK_A;
530 u32 saveTRANS_HSYNC_A;
531 u32 saveTRANS_VTOTAL_A;
532 u32 saveTRANS_VBLANK_A;
533 u32 saveTRANS_VSYNC_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000534 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000535 u32 saveDSPASTRIDE;
536 u32 saveDSPASIZE;
537 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700538 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000539 u32 saveDSPASURF;
540 u32 saveDSPATILEOFF;
541 u32 savePFIT_PGM_RATIOS;
Jesse Barnes0eb96d62009-10-14 12:33:41 -0700542 u32 saveBLC_HIST_CTL;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000543 u32 saveBLC_PWM_CTL;
544 u32 saveBLC_PWM_CTL2;
Zhenyu Wang42048782009-10-21 15:27:01 +0800545 u32 saveBLC_CPU_PWM_CTL;
546 u32 saveBLC_CPU_PWM_CTL2;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000547 u32 saveFPB0;
548 u32 saveFPB1;
549 u32 saveDPLL_B;
550 u32 saveDPLL_B_MD;
551 u32 saveHTOTAL_B;
552 u32 saveHBLANK_B;
553 u32 saveHSYNC_B;
554 u32 saveVTOTAL_B;
555 u32 saveVBLANK_B;
556 u32 saveVSYNC_B;
557 u32 saveBCLRPAT_B;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000558 u32 saveTRANSBCONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800559 u32 saveTRANS_HTOTAL_B;
560 u32 saveTRANS_HBLANK_B;
561 u32 saveTRANS_HSYNC_B;
562 u32 saveTRANS_VTOTAL_B;
563 u32 saveTRANS_VBLANK_B;
564 u32 saveTRANS_VSYNC_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000565 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000566 u32 saveDSPBSTRIDE;
567 u32 saveDSPBSIZE;
568 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700569 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000570 u32 saveDSPBSURF;
571 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700572 u32 saveVGA0;
573 u32 saveVGA1;
574 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000575 u32 saveVGACNTRL;
576 u32 saveADPA;
577 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700578 u32 savePP_ON_DELAYS;
579 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000580 u32 saveDVOA;
581 u32 saveDVOB;
582 u32 saveDVOC;
583 u32 savePP_ON;
584 u32 savePP_OFF;
585 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700586 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000587 u32 savePFIT_CONTROL;
588 u32 save_palette_a[256];
589 u32 save_palette_b[256];
Jesse Barnes06027f92009-10-05 13:47:26 -0700590 u32 saveDPFC_CB_BASE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000591 u32 saveFBC_CFB_BASE;
592 u32 saveFBC_LL_BASE;
593 u32 saveFBC_CONTROL;
594 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000595 u32 saveIER;
596 u32 saveIIR;
597 u32 saveIMR;
Zhenyu Wang42048782009-10-21 15:27:01 +0800598 u32 saveDEIER;
599 u32 saveDEIMR;
600 u32 saveGTIER;
601 u32 saveGTIMR;
602 u32 saveFDI_RXA_IMR;
603 u32 saveFDI_RXB_IMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800604 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800605 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000606 u32 saveSWF0[16];
607 u32 saveSWF1[16];
608 u32 saveSWF2[3];
609 u8 saveMSR;
610 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800611 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000612 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000613 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000614 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000615 u8 saveCR[37];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200616 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000617 u32 saveCURACNTR;
618 u32 saveCURAPOS;
619 u32 saveCURABASE;
620 u32 saveCURBCNTR;
621 u32 saveCURBPOS;
622 u32 saveCURBBASE;
623 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700624 u32 saveDP_B;
625 u32 saveDP_C;
626 u32 saveDP_D;
627 u32 savePIPEA_GMCH_DATA_M;
628 u32 savePIPEB_GMCH_DATA_M;
629 u32 savePIPEA_GMCH_DATA_N;
630 u32 savePIPEB_GMCH_DATA_N;
631 u32 savePIPEA_DP_LINK_M;
632 u32 savePIPEB_DP_LINK_M;
633 u32 savePIPEA_DP_LINK_N;
634 u32 savePIPEB_DP_LINK_N;
Zhenyu Wang42048782009-10-21 15:27:01 +0800635 u32 saveFDI_RXA_CTL;
636 u32 saveFDI_TXA_CTL;
637 u32 saveFDI_RXB_CTL;
638 u32 saveFDI_TXB_CTL;
639 u32 savePFA_CTL_1;
640 u32 savePFB_CTL_1;
641 u32 savePFA_WIN_SZ;
642 u32 savePFB_WIN_SZ;
643 u32 savePFA_WIN_POS;
644 u32 savePFB_WIN_POS;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000645 u32 savePCH_DREF_CONTROL;
646 u32 saveDISP_ARB_CTL;
647 u32 savePIPEA_DATA_M1;
648 u32 savePIPEA_DATA_N1;
649 u32 savePIPEA_LINK_M1;
650 u32 savePIPEA_LINK_N1;
651 u32 savePIPEB_DATA_M1;
652 u32 savePIPEB_DATA_N1;
653 u32 savePIPEB_LINK_M1;
654 u32 savePIPEB_LINK_N1;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000655 u32 saveMCHBAR_RENDER_STANDBY;
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400656 u32 savePCH_PORT_HOTPLUG;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100657};
Daniel Vetterc85aa882012-11-02 19:55:03 +0100658
659struct intel_gen6_power_mgmt {
660 struct work_struct work;
661 u32 pm_iir;
662 /* lock - irqsave spinlock that protectects the work_struct and
663 * pm_iir. */
664 spinlock_t lock;
665
666 /* The below variables an all the rps hw state are protected by
667 * dev->struct mutext. */
668 u8 cur_delay;
669 u8 min_delay;
670 u8 max_delay;
Ben Widawsky31c77382013-04-05 14:29:22 -0700671 u8 hw_max;
Jesse Barnes1a01ab32012-11-02 11:14:00 -0700672
673 struct delayed_work delayed_resume_work;
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700674
675 /*
676 * Protects RPS/RC6 register access and PCU communication.
677 * Must be taken after struct_mutex if nested.
678 */
679 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100680};
681
Daniel Vetter1a240d42012-11-29 22:18:51 +0100682/* defined intel_pm.c */
683extern spinlock_t mchdev_lock;
684
Daniel Vetterc85aa882012-11-02 19:55:03 +0100685struct intel_ilk_power_mgmt {
686 u8 cur_delay;
687 u8 min_delay;
688 u8 max_delay;
689 u8 fmax;
690 u8 fstart;
691
692 u64 last_count1;
693 unsigned long last_time1;
694 unsigned long chipset_power;
695 u64 last_count2;
696 struct timespec last_time2;
697 unsigned long gfx_power;
698 u8 corr;
699
700 int c_m;
701 int r_t;
Daniel Vetter3e373942012-11-02 19:55:04 +0100702
703 struct drm_i915_gem_object *pwrctx;
704 struct drm_i915_gem_object *renderctx;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100705};
706
Daniel Vetter231f42a2012-11-02 19:55:05 +0100707struct i915_dri1_state {
708 unsigned allow_batchbuffer : 1;
709 u32 __iomem *gfx_hws_cpu_addr;
710
711 unsigned int cpp;
712 int back_offset;
713 int front_offset;
714 int current_page;
715 int page_flipping;
716
717 uint32_t counter;
718};
719
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100720struct intel_l3_parity {
721 u32 *remap_info;
722 struct work_struct error_work;
723};
724
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100725struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100726 /** Memory allocator for GTT stolen memory */
727 struct drm_mm stolen;
728 /** Memory allocator for GTT */
729 struct drm_mm gtt_space;
730 /** List of all objects in gtt_space. Used to restore gtt
731 * mappings on resume */
732 struct list_head bound_list;
733 /**
734 * List of objects which are not bound to the GTT (thus
735 * are idle and not used by the GPU) but still have
736 * (presumably uncached) pages still attached.
737 */
738 struct list_head unbound_list;
739
740 /** Usable portion of the GTT for GEM */
741 unsigned long stolen_base; /* limited to low memory (32-bit) */
742
743 int gtt_mtrr;
744
745 /** PPGTT used for aliasing the PPGTT with the GTT */
746 struct i915_hw_ppgtt *aliasing_ppgtt;
747
748 struct shrinker inactive_shrinker;
749 bool shrinker_no_lock_stealing;
750
751 /**
752 * List of objects currently involved in rendering.
753 *
754 * Includes buffers having the contents of their GPU caches
755 * flushed, not necessarily primitives. last_rendering_seqno
756 * represents when the rendering involved will be completed.
757 *
758 * A reference is held on the buffer while on this list.
759 */
760 struct list_head active_list;
761
762 /**
763 * LRU list of objects which are not in the ringbuffer and
764 * are ready to unbind, but are still in the GTT.
765 *
766 * last_rendering_seqno is 0 while an object is in this list.
767 *
768 * A reference is not held on the buffer while on this list,
769 * as merely being GTT-bound shouldn't prevent its being
770 * freed, and we'll pull it off the list in the free path.
771 */
772 struct list_head inactive_list;
773
774 /** LRU list of objects with fence regs on them. */
775 struct list_head fence_list;
776
777 /**
778 * We leave the user IRQ off as much as possible,
779 * but this means that requests will finish and never
780 * be retired once the system goes idle. Set a timer to
781 * fire periodically while the ring is running. When it
782 * fires, go retire requests.
783 */
784 struct delayed_work retire_work;
785
786 /**
787 * Are we in a non-interruptible section of code like
788 * modesetting?
789 */
790 bool interruptible;
791
792 /**
793 * Flag if the X Server, and thus DRM, is not currently in
794 * control of the device.
795 *
796 * This is set between LeaveVT and EnterVT. It needs to be
797 * replaced with a semaphore. It also needs to be
798 * transitioned away from for kernel modesetting.
799 */
800 int suspended;
801
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100802 /** Bit 6 swizzling required for X tiling */
803 uint32_t bit_6_swizzle_x;
804 /** Bit 6 swizzling required for Y tiling */
805 uint32_t bit_6_swizzle_y;
806
807 /* storage for physical objects */
808 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
809
810 /* accounting, useful for userland debugging */
811 size_t object_memory;
812 u32 object_count;
813};
814
Daniel Vetter99584db2012-11-14 17:14:04 +0100815struct i915_gpu_error {
816 /* For hangcheck timer */
817#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
818#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
819 struct timer_list hangcheck_timer;
820 int hangcheck_count;
821 uint32_t last_acthd[I915_NUM_RINGS];
822 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
823
824 /* For reset and error_state handling. */
825 spinlock_t lock;
826 /* Protected by the above dev->gpu_error.lock. */
827 struct drm_i915_error_state *first_error;
828 struct work_struct work;
Daniel Vetter99584db2012-11-14 17:14:04 +0100829
830 unsigned long last_reset;
831
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100832 /**
Daniel Vetterf69061b2012-12-06 09:01:42 +0100833 * State variable and reset counter controlling the reset flow
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100834 *
Daniel Vetterf69061b2012-12-06 09:01:42 +0100835 * Upper bits are for the reset counter. This counter is used by the
836 * wait_seqno code to race-free noticed that a reset event happened and
837 * that it needs to restart the entire ioctl (since most likely the
838 * seqno it waited for won't ever signal anytime soon).
839 *
840 * This is important for lock-free wait paths, where no contended lock
841 * naturally enforces the correct ordering between the bail-out of the
842 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100843 *
844 * Lowest bit controls the reset state machine: Set means a reset is in
845 * progress. This state will (presuming we don't have any bugs) decay
846 * into either unset (successful reset) or the special WEDGED value (hw
847 * terminally sour). All waiters on the reset_queue will be woken when
848 * that happens.
849 */
850 atomic_t reset_counter;
851
852 /**
853 * Special values/flags for reset_counter
854 *
855 * Note that the code relies on
856 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
857 * being true.
858 */
859#define I915_RESET_IN_PROGRESS_FLAG 1
860#define I915_WEDGED 0xffffffff
861
862 /**
863 * Waitqueue to signal when the reset has completed. Used by clients
864 * that wait for dev_priv->mm.wedged to settle.
865 */
866 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +0100867
Daniel Vetter99584db2012-11-14 17:14:04 +0100868 /* For gpu hang simulation. */
869 unsigned int stop_rings;
870};
871
Zhang Ruib8efb172013-02-05 15:41:53 +0800872enum modeset_restore {
873 MODESET_ON_LID_OPEN,
874 MODESET_DONE,
875 MODESET_SUSPENDED,
876};
877
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100878typedef struct drm_i915_private {
879 struct drm_device *dev;
Chris Wilson42dcedd2012-11-15 11:32:30 +0000880 struct kmem_cache *slab;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100881
882 const struct intel_device_info *info;
883
884 int relative_constants_mode;
885
886 void __iomem *regs;
887
888 struct drm_i915_gt_funcs gt;
889 /** gt_fifo_count and the subsequent register write are synchronized
890 * with dev->struct_mutex. */
891 unsigned gt_fifo_count;
892 /** forcewake_count is protected by gt_lock */
893 unsigned forcewake_count;
894 /** gt_lock is also taken in irq contexts. */
Luis R. Rodriguez99057c82012-11-29 12:45:06 -0800895 spinlock_t gt_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100896
897 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
898
Daniel Vetter28c70f12012-12-01 13:53:45 +0100899
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100900 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
901 * controller on different i2c buses. */
902 struct mutex gmbus_mutex;
903
904 /**
905 * Base address of the gmbus and gpio block.
906 */
907 uint32_t gpio_mmio_base;
908
Daniel Vetter28c70f12012-12-01 13:53:45 +0100909 wait_queue_head_t gmbus_wait_queue;
910
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100911 struct pci_dev *bridge_dev;
912 struct intel_ring_buffer ring[I915_NUM_RINGS];
Mika Kuoppalaf72b3432012-12-10 15:41:48 +0200913 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100914
915 drm_dma_handle_t *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100916 struct resource mch_res;
917
918 atomic_t irq_received;
919
920 /* protects the irq masks */
921 spinlock_t irq_lock;
922
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100923 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
924 struct pm_qos_request pm_qos;
925
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100926 /* DPIO indirect register protection */
Daniel Vetter09153002012-12-12 14:06:44 +0100927 struct mutex dpio_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100928
929 /** Cached value of IMR to avoid reads in updating the bitfield */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100930 u32 irq_mask;
931 u32 gt_irq_mask;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100932
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100933 struct work_struct hotplug_work;
Daniel Vetter52d7ece2012-12-01 21:03:22 +0100934 bool enable_hotplug_processing;
Egbert Eichb543fb02013-04-16 13:36:54 +0200935 struct {
936 unsigned long hpd_last_jiffies;
937 int hpd_cnt;
938 enum {
939 HPD_ENABLED = 0,
940 HPD_DISABLED = 1,
941 HPD_MARK_DISABLED = 2
942 } hpd_mark;
943 } hpd_stats[HPD_NUM_PINS];
Egbert Eichac4c16c2013-04-16 13:36:58 +0200944 struct timer_list hotplug_reenable_timer;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100945
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100946 int num_pch_pll;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700947 int num_plane;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100948
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100949 unsigned long cfb_size;
950 unsigned int cfb_fb;
951 enum plane cfb_plane;
952 int cfb_y;
953 struct intel_fbc_work *fbc_work;
954
955 struct intel_opregion opregion;
956
957 /* overlay */
958 struct intel_overlay *overlay;
Ville Syrjälä2c6602d2013-02-08 23:13:35 +0200959 unsigned int sprite_scaling_enabled;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100960
Jani Nikula31ad8ec2013-04-02 15:48:09 +0300961 /* backlight */
962 struct {
963 int level;
964 bool enabled;
965 struct backlight_device *device;
966 } backlight;
967
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100968 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100969 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
970 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
971
972 /* Feature bits from the VBIOS */
973 unsigned int int_tv_support:1;
974 unsigned int lvds_dither:1;
975 unsigned int lvds_vbt:1;
976 unsigned int int_crt_support:1;
977 unsigned int lvds_use_ssc:1;
978 unsigned int display_clock_mode:1;
Paulo Zanoni3f704fa2013-04-08 15:48:07 -0300979 unsigned int fdi_rx_polarity_inverted:1;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100980 int lvds_ssc_freq;
981 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100982 struct {
983 int rate;
984 int lanes;
985 int preemphasis;
986 int vswing;
987
988 bool initialized;
989 bool support;
990 int bpp;
991 struct edp_power_seq pps;
992 } edp;
993 bool no_aux_handshake;
994
995 int crt_ddc_pin;
996 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
997 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
998 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
999
1000 unsigned int fsb_freq, mem_freq, is_ddr3;
1001
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001002 struct workqueue_struct *wq;
1003
1004 /* Display functions */
1005 struct drm_i915_display_funcs display;
1006
1007 /* PCH chipset type */
1008 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001009 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001010
1011 unsigned long quirks;
1012
Zhang Ruib8efb172013-02-05 15:41:53 +08001013 enum modeset_restore modeset_restore;
1014 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001015
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001016 struct i915_gtt gtt;
1017
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001018 struct i915_gem_mm mm;
Daniel Vetter87813422012-05-02 11:49:32 +02001019
Daniel Vetter87813422012-05-02 11:49:32 +02001020 /* Kernel Modesetting */
1021
yakui_zhao9b9d1722009-05-31 17:17:17 +08001022 struct sdvo_device_mapping sdvo_mappings[2];
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08001023 /* indicate whether the LVDS_BORDER should be enabled or not */
1024 unsigned int lvds_border_bits;
Chris Wilson1d8e1c72010-08-07 11:01:28 +01001025 /* Panel fitter placement and size for Ironlake+ */
1026 u32 pch_pf_pos, pch_pf_size;
Jesse Barnes652c3932009-08-17 13:31:43 -07001027
Jesse Barnes27f82272011-09-02 12:54:37 -07001028 struct drm_crtc *plane_to_crtc_mapping[3];
1029 struct drm_crtc *pipe_to_crtc_mapping[3];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001030 wait_queue_head_t pending_flip_queue;
1031
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001032 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001033 struct intel_ddi_plls ddi_plls;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001034
Jesse Barnes652c3932009-08-17 13:31:43 -07001035 /* Reclocking support */
1036 bool render_reclock_avail;
1037 bool lvds_downclock_avail;
Zhao Yakui18f9ed12009-11-20 03:24:16 +00001038 /* indicates the reduced downclock for LVDS*/
1039 int lvds_downclock;
Jesse Barnes652c3932009-08-17 13:31:43 -07001040 u16 orig_clock;
Zhao Yakui6363ee62009-11-24 09:48:44 +08001041 int child_dev_num;
1042 struct child_device_config *child_dev;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001043
Zhenyu Wangc48044112009-12-17 14:48:43 +08001044 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001045
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001046 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001047
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001048 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001049 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001050
Daniel Vetter20e4d402012-08-08 23:35:39 +02001051 /* ilk-only ips/rps state. Everything in here is protected by the global
1052 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001053 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001054
1055 enum no_fbc_reason no_fbc_reason;
Dave Airlie38651672010-03-30 05:34:13 +00001056
Jesse Barnes20bf3772010-04-21 11:39:22 -07001057 struct drm_mm_node *compressed_fb;
1058 struct drm_mm_node *compressed_llb;
Eric Anholt34dc4d42010-05-07 14:30:03 -07001059
Daniel Vetter99584db2012-11-14 17:14:04 +01001060 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001061
Dave Airlie8be48d92010-03-30 05:34:14 +00001062 /* list of fbdev register on this device */
1063 struct intel_fbdev *fbdev;
Chris Wilsone953fd72011-02-21 22:23:52 +00001064
Jesse Barnes073f34d2012-11-02 11:13:59 -07001065 /*
1066 * The console may be contended at resume, but we don't
1067 * want it to block on it.
1068 */
1069 struct work_struct console_resume_work;
1070
Chris Wilsone953fd72011-02-21 22:23:52 +00001071 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001072 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001073
Ben Widawsky254f9652012-06-04 14:42:42 -07001074 bool hw_contexts_disabled;
1075 uint32_t hw_context_size;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001076
Damien Lespiau3e683202012-12-11 18:48:29 +00001077 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001078
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001079 struct i915_suspend_saved_registers regfile;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001080
1081 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1082 * here! */
1083 struct i915_dri1_state dri1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084} drm_i915_private_t;
1085
Chris Wilsonb4519512012-05-11 14:29:30 +01001086/* Iterate over initialised rings */
1087#define for_each_ring(ring__, dev_priv__, i__) \
1088 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1089 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1090
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001091enum hdmi_force_audio {
1092 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1093 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1094 HDMI_AUDIO_AUTO, /* trust EDID */
1095 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1096};
1097
Chris Wilsoned2f3452012-11-15 11:32:19 +00001098#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1099
Chris Wilson37e680a2012-06-07 15:38:42 +01001100struct drm_i915_gem_object_ops {
1101 /* Interface between the GEM object and its backing storage.
1102 * get_pages() is called once prior to the use of the associated set
1103 * of pages before to binding them into the GTT, and put_pages() is
1104 * called after we no longer need them. As we expect there to be
1105 * associated cost with migrating pages between the backing storage
1106 * and making them available for the GPU (e.g. clflush), we may hold
1107 * onto the pages after they are no longer referenced by the GPU
1108 * in case they may be used again shortly (for example migrating the
1109 * pages to a different memory domain within the GTT). put_pages()
1110 * will therefore most likely be called when the object itself is
1111 * being released or under memory pressure (where we attempt to
1112 * reap pages for the shrinker).
1113 */
1114 int (*get_pages)(struct drm_i915_gem_object *);
1115 void (*put_pages)(struct drm_i915_gem_object *);
1116};
1117
Eric Anholt673a3942008-07-30 12:06:12 -07001118struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00001119 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07001120
Chris Wilson37e680a2012-06-07 15:38:42 +01001121 const struct drm_i915_gem_object_ops *ops;
1122
Eric Anholt673a3942008-07-30 12:06:12 -07001123 /** Current space allocated to this object in the GTT, if any. */
1124 struct drm_mm_node *gtt_space;
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00001125 /** Stolen memory for this object, instead of being backed by shmem. */
1126 struct drm_mm_node *stolen;
Daniel Vetter93a37f22010-11-05 20:24:53 +01001127 struct list_head gtt_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001128
Chris Wilson65ce3022012-07-20 12:41:02 +01001129 /** This object's place on the active/inactive lists */
Chris Wilson69dc4982010-10-19 10:36:51 +01001130 struct list_head ring_list;
1131 struct list_head mm_list;
Chris Wilson432e58e2010-11-25 19:32:06 +00001132 /** This object's place in the batchbuffer or on the eviction list */
1133 struct list_head exec_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001134
1135 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01001136 * This is set if the object is on the active lists (has pending
1137 * rendering and so a non-zero seqno), and is not set if it i s on
1138 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07001139 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001140 unsigned int active:1;
Eric Anholt673a3942008-07-30 12:06:12 -07001141
1142 /**
1143 * This is set if the object has been written to since last bound
1144 * to the GTT
1145 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001146 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001147
1148 /**
1149 * Fence register bits (if any) for this object. Will be set
1150 * as needed when mapped into the GTT.
1151 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02001152 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02001153 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02001154
1155 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001156 * Advice: are the backing pages purgeable?
1157 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001158 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02001159
1160 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001161 * Current tiling mode for the object.
1162 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001163 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01001164 /**
1165 * Whether the tiling parameters for the currently associated fence
1166 * register have changed. Note that for the purposes of tracking
1167 * tiling changes we also treat the unfenced register, the register
1168 * slot that the object occupies whilst it executes a fenced
1169 * command (such as BLT on gen2/3), as a "fence".
1170 */
1171 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001172
1173 /** How many users have pinned this object in GTT space. The following
1174 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1175 * (via user_pin_count), execbuffer (objects are not allowed multiple
1176 * times for the same batchbuffer), and the framebuffer code. When
1177 * switching/pageflipping, the framebuffer code has at most two buffers
1178 * pinned per crtc.
1179 *
1180 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1181 * bits with absolutely no headroom. So use 4 bits. */
Akshay Joshi0206e352011-08-16 15:34:10 -04001182 unsigned int pin_count:4;
Daniel Vetter778c3542010-05-13 11:49:44 +02001183#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
Eric Anholt673a3942008-07-30 12:06:12 -07001184
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001185 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01001186 * Is the object at the current location in the gtt mappable and
1187 * fenceable? Used to avoid costly recalculations.
1188 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001189 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01001190
1191 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001192 * Whether the current gtt mapping needs to be mappable (and isn't just
1193 * mappable by accident). Track pin and fault separate for a more
1194 * accurate mappable working set.
1195 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001196 unsigned int fault_mappable:1;
1197 unsigned int pin_mappable:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001198
Chris Wilsoncaea7472010-11-12 13:53:37 +00001199 /*
1200 * Is the GPU currently using a fence to access this buffer,
1201 */
1202 unsigned int pending_fenced_gpu_access:1;
1203 unsigned int fenced_gpu_access:1;
1204
Chris Wilson93dfb402011-03-29 16:59:50 -07001205 unsigned int cache_level:2;
1206
Daniel Vetter7bddb012012-02-09 17:15:47 +01001207 unsigned int has_aliasing_ppgtt_mapping:1;
Daniel Vetter74898d72012-02-15 23:50:22 +01001208 unsigned int has_global_gtt_mapping:1;
Chris Wilson9da3da62012-06-01 15:20:22 +01001209 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001210
Chris Wilson9da3da62012-06-01 15:20:22 +01001211 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01001212 int pages_pin_count;
Eric Anholt673a3942008-07-30 12:06:12 -07001213
Daniel Vetter1286ff72012-05-10 15:25:09 +02001214 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01001215 void *dma_buf_vmapping;
1216 int vmapping_count;
1217
Daniel Vetter185cbcb2010-11-06 12:12:35 +01001218 /**
Chris Wilson67731b82010-12-08 10:38:14 +00001219 * Used for performing relocations during execbuffer insertion.
1220 */
1221 struct hlist_node exec_node;
1222 unsigned long exec_handle;
Chris Wilson6fe4f142011-01-10 17:35:37 +00001223 struct drm_i915_gem_exec_object2 *exec_entry;
Chris Wilson67731b82010-12-08 10:38:14 +00001224
1225 /**
Eric Anholt673a3942008-07-30 12:06:12 -07001226 * Current offset of the object in GTT space.
1227 *
1228 * This is the same as gtt_space->start
1229 */
1230 uint32_t gtt_offset;
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001231
Chris Wilsoncaea7472010-11-12 13:53:37 +00001232 struct intel_ring_buffer *ring;
1233
Chris Wilson1c293ea2012-04-17 15:31:27 +01001234 /** Breadcrumb of last rendering to the buffer. */
Chris Wilson0201f1e2012-07-20 12:41:01 +01001235 uint32_t last_read_seqno;
1236 uint32_t last_write_seqno;
Chris Wilsoncaea7472010-11-12 13:53:37 +00001237 /** Breadcrumb of last fenced GPU access to the buffer. */
1238 uint32_t last_fenced_seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001239
Daniel Vetter778c3542010-05-13 11:49:44 +02001240 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08001241 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07001242
Eric Anholt280b7132009-03-12 16:56:27 -07001243 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01001244 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07001245
Jesse Barnes79e53942008-11-07 14:24:08 -08001246 /** User space pin count and filp owning the pin */
1247 uint32_t user_pin_count;
1248 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001249
1250 /** for phy allocated objects */
1251 struct drm_i915_gem_phys_object *phys_obj;
Eric Anholt673a3942008-07-30 12:06:12 -07001252};
Daniel Vetterb45305f2012-12-17 16:21:27 +01001253#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
Eric Anholt673a3942008-07-30 12:06:12 -07001254
Daniel Vetter62b8b212010-04-09 19:05:08 +00001255#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01001256
Eric Anholt673a3942008-07-30 12:06:12 -07001257/**
1258 * Request queue structure.
1259 *
1260 * The request queue allows us to note sequence numbers that have been emitted
1261 * and may be associated with active buffers to be retired.
1262 *
1263 * By keeping this list, we can avoid having to do questionable
1264 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1265 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1266 */
1267struct drm_i915_gem_request {
Zou Nan hai852835f2010-05-21 09:08:56 +08001268 /** On Which ring this request was generated */
1269 struct intel_ring_buffer *ring;
1270
Eric Anholt673a3942008-07-30 12:06:12 -07001271 /** GEM sequence number associated with this request. */
1272 uint32_t seqno;
1273
Chris Wilsona71d8d92012-02-15 11:25:36 +00001274 /** Postion in the ringbuffer of the end of the request */
1275 u32 tail;
1276
Eric Anholt673a3942008-07-30 12:06:12 -07001277 /** Time at which this request was emitted, in jiffies. */
1278 unsigned long emitted_jiffies;
1279
Eric Anholtb9624422009-06-03 07:27:35 +00001280 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07001281 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00001282
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001283 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00001284 /** file_priv list entry for this request */
1285 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001286};
1287
1288struct drm_i915_file_private {
1289 struct {
Luis R. Rodriguez99057c82012-11-29 12:45:06 -08001290 spinlock_t lock;
Eric Anholtb9624422009-06-03 07:27:35 +00001291 struct list_head request_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001292 } mm;
Ben Widawsky40521052012-06-04 14:42:43 -07001293 struct idr context_idr;
Eric Anholt673a3942008-07-30 12:06:12 -07001294};
1295
Zou Nan haicae58522010-11-09 17:17:32 +08001296#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1297
1298#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1299#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1300#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1301#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1302#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1303#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1304#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1305#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1306#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1307#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1308#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1309#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1310#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1311#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1312#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1313#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1314#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1315#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07001316#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Jesse Barnes8ab43972012-10-25 12:15:42 -07001317#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1318 (dev)->pci_device == 0x0152 || \
1319 (dev)->pci_device == 0x015a)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01001320#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1321 (dev)->pci_device == 0x0106 || \
1322 (dev)->pci_device == 0x010A)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07001323#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03001324#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Zou Nan haicae58522010-11-09 17:17:32 +08001325#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonid567b072012-11-20 13:27:43 -02001326#define IS_ULT(dev) (IS_HASWELL(dev) && \
1327 ((dev)->pci_device & 0xFF00) == 0x0A00)
Zou Nan haicae58522010-11-09 17:17:32 +08001328
Jesse Barnes85436692011-04-06 12:11:14 -07001329/*
1330 * The genX designation typically refers to the render engine, so render
1331 * capability related checks should use IS_GEN, while display and other checks
1332 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1333 * chips, etc.).
1334 */
Zou Nan haicae58522010-11-09 17:17:32 +08001335#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1336#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1337#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1338#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1339#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07001340#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Zou Nan haicae58522010-11-09 17:17:32 +08001341
1342#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1343#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
Eugeni Dodonov3d29b842012-01-17 14:43:53 -02001344#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
Zou Nan haicae58522010-11-09 17:17:32 +08001345#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1346
Ben Widawsky254f9652012-06-04 14:42:42 -07001347#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Jesse Barnes93553602012-06-15 11:55:23 -07001348#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001349
Chris Wilson05394f32010-11-08 19:18:58 +00001350#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08001351#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1352
Daniel Vetterb45305f2012-12-17 16:21:27 +01001353/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1354#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1355
Zou Nan haicae58522010-11-09 17:17:32 +08001356/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1357 * rows, which changed the alignment requirements and fence programming.
1358 */
1359#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1360 IS_I915GM(dev)))
1361#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1362#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1363#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1364#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1365#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1366#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1367/* dsparb controlled by hw only */
1368#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1369
1370#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1371#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1372#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08001373
Jesse Barneseceae482011-04-06 12:15:08 -07001374#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
Zou Nan haicae58522010-11-09 17:17:32 +08001375
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001376#define HAS_DDI(dev) (IS_HASWELL(dev))
Paulo Zanoni86d52df2013-03-06 20:03:18 -03001377#define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001378
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001379#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1380#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1381#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1382#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1383#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1384#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1385
Zou Nan haicae58522010-11-09 17:17:32 +08001386#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03001387#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08001388#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1389#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07001390#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03001391#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08001392
Daniel Vetterb7884eb2012-06-04 11:18:15 +02001393#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1394
Ben Widawskyf27b9262012-07-24 20:47:32 -07001395#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07001396
Ben Widawskyc8735b02012-09-07 19:43:39 -07001397#define GT_FREQUENCY_MULTIPLIER 50
1398
Chris Wilson05394f32010-11-08 19:18:58 +00001399#include "i915_trace.h"
1400
Eugeni Dodonov83b7f9a2012-03-23 11:57:18 -03001401/**
1402 * RC6 is a special power stage which allows the GPU to enter an very
1403 * low-voltage mode when idle, using down to 0V while at this stage. This
1404 * stage is entered automatically when the GPU is idle when RC6 support is
1405 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1406 *
1407 * There are different RC6 modes available in Intel GPU, which differentiate
1408 * among each other with the latency required to enter and leave RC6 and
1409 * voltage consumed by the GPU in different states.
1410 *
1411 * The combination of the following flags define which states GPU is allowed
1412 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1413 * RC6pp is deepest RC6. Their support by hardware varies according to the
1414 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1415 * which brings the most power savings; deeper states save more power, but
1416 * require higher latency to switch to and wake up.
1417 */
1418#define INTEL_RC6_ENABLE (1<<0)
1419#define INTEL_RC6p_ENABLE (1<<1)
1420#define INTEL_RC6pp_ENABLE (1<<2)
1421
Eric Anholtc153f452007-09-03 12:06:45 +10001422extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10001423extern int i915_max_ioctl;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001424extern unsigned int i915_fbpercrtc __always_unused;
1425extern int i915_panel_ignore_lid __read_mostly;
1426extern unsigned int i915_powersave __read_mostly;
Eugeni Dodonovf45b5552011-12-09 17:16:37 -08001427extern int i915_semaphores __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001428extern unsigned int i915_lvds_downclock __read_mostly;
Takashi Iwai121d5272012-03-20 13:07:06 +01001429extern int i915_lvds_channel_mode __read_mostly;
Keith Packard4415e632011-11-09 09:57:50 -08001430extern int i915_panel_use_ssc __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001431extern int i915_vbt_sdvo_panel_type __read_mostly;
Keith Packardc0f372b32011-11-16 22:24:52 -08001432extern int i915_enable_rc6 __read_mostly;
Keith Packard4415e632011-11-09 09:57:50 -08001433extern int i915_enable_fbc __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001434extern bool i915_enable_hangcheck __read_mostly;
Daniel Vetter650dc072012-04-02 10:08:35 +02001435extern int i915_enable_ppgtt __read_mostly;
Rodrigo Vivi0a3af262012-10-15 17:16:23 -03001436extern unsigned int i915_preliminary_hw_support __read_mostly;
Paulo Zanoni2124b722013-03-22 14:07:23 -03001437extern int i915_disable_power_well __read_mostly;
Dave Airlieb3a83632005-09-30 18:37:36 +10001438
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001439extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1440extern int i915_resume(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001441extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1442extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1443
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444 /* i915_dma.c */
Daniel Vetterd05c6172012-04-26 23:28:09 +02001445void i915_update_dri1_breadcrumb(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001446extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +11001447extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001448extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -07001449extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001450extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10001451extern void i915_driver_preclose(struct drm_device *dev,
1452 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001453extern void i915_driver_postclose(struct drm_device *dev,
1454 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001455extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001456#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11001457extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1458 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001459#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001460extern int i915_emit_box(struct drm_device *dev,
Chris Wilsonc4e7a412010-11-30 14:10:25 +00001461 struct drm_clip_rect *box,
1462 int DR1, int DR4);
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07001463extern int intel_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02001464extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001465extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1466extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1467extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1468extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1469
Jesse Barnes073f34d2012-11-02 11:13:59 -07001470extern void intel_console_resume(struct work_struct *work);
Dave Airlieaf6061a2008-05-07 12:15:39 +10001471
Linus Torvalds1da177e2005-04-16 15:20:36 -07001472/* i915_irq.c */
Ben Gamarif65d9422009-09-14 17:48:44 -04001473void i915_hangcheck_elapsed(unsigned long data);
Chris Wilson527f9e92010-11-11 01:16:58 +00001474void i915_handle_error(struct drm_device *dev, bool wedged);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001476extern void intel_irq_init(struct drm_device *dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01001477extern void intel_hpd_init(struct drm_device *dev);
Chris Wilson990bbda2012-07-02 11:51:02 -03001478extern void intel_gt_init(struct drm_device *dev);
Chris Wilson16995a92012-10-18 11:46:10 +01001479extern void intel_gt_reset(struct drm_device *dev);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001480
Daniel Vetter742cbee2012-04-27 15:17:39 +02001481void i915_error_state_free(struct kref *error_ref);
1482
Keith Packard7c463582008-11-04 02:03:27 -08001483void
1484i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1485
1486void
1487i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1488
Akshay Joshi0206e352011-08-16 15:34:10 -04001489void intel_enable_asle(struct drm_device *dev);
Zhao Yakui01c66882009-10-28 05:10:00 +00001490
Chris Wilson3bd3c932010-08-19 08:19:30 +01001491#ifdef CONFIG_DEBUG_FS
1492extern void i915_destroy_error_state(struct drm_device *dev);
1493#else
1494#define i915_destroy_error_state(x)
1495#endif
1496
Keith Packard7c463582008-11-04 02:03:27 -08001497
Eric Anholt673a3942008-07-30 12:06:12 -07001498/* i915_gem.c */
1499int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1500 struct drm_file *file_priv);
1501int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1502 struct drm_file *file_priv);
1503int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1504 struct drm_file *file_priv);
1505int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1506 struct drm_file *file_priv);
1507int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1508 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001509int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1510 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001511int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1512 struct drm_file *file_priv);
1513int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1514 struct drm_file *file_priv);
1515int i915_gem_execbuffer(struct drm_device *dev, void *data,
1516 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05001517int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1518 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001519int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1520 struct drm_file *file_priv);
1521int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1522 struct drm_file *file_priv);
1523int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1524 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07001525int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1526 struct drm_file *file);
1527int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1528 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07001529int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1530 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001531int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1532 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001533int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1534 struct drm_file *file_priv);
1535int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1536 struct drm_file *file_priv);
1537int i915_gem_set_tiling(struct drm_device *dev, void *data,
1538 struct drm_file *file_priv);
1539int i915_gem_get_tiling(struct drm_device *dev, void *data,
1540 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -07001541int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1542 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07001543int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1544 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001545void i915_gem_load(struct drm_device *dev);
Chris Wilson42dcedd2012-11-15 11:32:30 +00001546void *i915_gem_object_alloc(struct drm_device *dev);
1547void i915_gem_object_free(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001548int i915_gem_init_object(struct drm_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01001549void i915_gem_object_init(struct drm_i915_gem_object *obj,
1550 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00001551struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1552 size_t size);
Eric Anholt673a3942008-07-30 12:06:12 -07001553void i915_gem_free_object(struct drm_gem_object *obj);
Chris Wilson42dcedd2012-11-15 11:32:30 +00001554
Chris Wilson20217462010-11-23 15:26:33 +00001555int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1556 uint32_t alignment,
Chris Wilson86a1ee22012-08-11 15:41:04 +01001557 bool map_and_fenceable,
1558 bool nonblocking);
Chris Wilson05394f32010-11-08 19:18:58 +00001559void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001560int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
Chris Wilsondd624af2013-01-15 12:39:35 +00001561int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Chris Wilson05394f32010-11-08 19:18:58 +00001562void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001563void i915_gem_lastclose(struct drm_device *dev);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001564
Chris Wilson37e680a2012-06-07 15:38:42 +01001565int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01001566static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1567{
Imre Deak67d5a502013-02-18 19:28:02 +02001568 struct sg_page_iter sg_iter;
Chris Wilson1cf83782012-10-10 12:11:52 +01001569
Imre Deak67d5a502013-02-18 19:28:02 +02001570 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
Imre Deak2db76d72013-03-26 15:14:18 +02001571 return sg_page_iter_page(&sg_iter);
Imre Deak67d5a502013-02-18 19:28:02 +02001572
1573 return NULL;
Chris Wilson9da3da62012-06-01 15:20:22 +01001574}
Chris Wilsona5570172012-09-04 21:02:54 +01001575static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1576{
1577 BUG_ON(obj->pages == NULL);
1578 obj->pages_pin_count++;
1579}
1580static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1581{
1582 BUG_ON(obj->pages_pin_count == 0);
1583 obj->pages_pin_count--;
1584}
1585
Chris Wilson54cf91d2010-11-25 18:00:26 +00001586int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07001587int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1588 struct intel_ring_buffer *to);
Chris Wilson54cf91d2010-11-25 18:00:26 +00001589void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
Chris Wilson9d7730912012-11-27 16:22:52 +00001590 struct intel_ring_buffer *ring);
Chris Wilson54cf91d2010-11-25 18:00:26 +00001591
Dave Airlieff72145b2011-02-07 12:16:14 +10001592int i915_gem_dumb_create(struct drm_file *file_priv,
1593 struct drm_device *dev,
1594 struct drm_mode_create_dumb *args);
1595int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1596 uint32_t handle, uint64_t *offset);
1597int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
Akshay Joshi0206e352011-08-16 15:34:10 -04001598 uint32_t handle);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001599/**
1600 * Returns true if seq1 is later than seq2.
1601 */
1602static inline bool
1603i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1604{
1605 return (int32_t)(seq1 - seq2) >= 0;
1606}
1607
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02001608int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1609int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson06d98132012-04-17 15:31:24 +01001610int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00001611int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001612
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001613static inline bool
Chris Wilson1690e1e2011-12-14 13:57:08 +01001614i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1615{
1616 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1617 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1618 dev_priv->fence_regs[obj->fence_reg].pin_count++;
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001619 return true;
1620 } else
1621 return false;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001622}
1623
1624static inline void
1625i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1626{
1627 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1628 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1629 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1630 }
1631}
1632
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001633void i915_gem_retire_requests(struct drm_device *dev);
Chris Wilsona71d8d92012-02-15 11:25:36 +00001634void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
Daniel Vetter33196de2012-11-14 17:14:05 +01001635int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02001636 bool interruptible);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001637static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1638{
1639 return unlikely(atomic_read(&error->reset_counter)
1640 & I915_RESET_IN_PROGRESS_FLAG);
1641}
1642
1643static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1644{
1645 return atomic_read(&error->reset_counter) == I915_WEDGED;
1646}
Chris Wilsona71d8d92012-02-15 11:25:36 +00001647
Chris Wilson069efc12010-09-30 16:53:18 +01001648void i915_gem_reset(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001649void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001650int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1651 uint32_t read_domains,
1652 uint32_t write_domain);
Chris Wilsona8198ee2011-04-13 22:04:09 +01001653int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
Chris Wilson1070a422012-04-24 15:47:41 +01001654int __must_check i915_gem_init(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001655int __must_check i915_gem_init_hw(struct drm_device *dev);
Ben Widawskyb9524a12012-05-25 16:56:24 -07001656void i915_gem_l3_remap(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001657void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001658void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07001659int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson20217462010-11-23 15:26:33 +00001660int __must_check i915_gem_idle(struct drm_device *dev);
Chris Wilson3bb73ab2012-07-20 12:40:59 +01001661int i915_add_request(struct intel_ring_buffer *ring,
1662 struct drm_file *file,
Chris Wilsonacb868d2012-09-26 13:47:30 +01001663 u32 *seqno);
Ben Widawsky199b2bc2012-05-24 15:03:11 -07001664int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1665 uint32_t seqno);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001666int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00001667int __must_check
1668i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1669 bool write);
1670int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02001671i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1672int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001673i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1674 u32 alignment,
Chris Wilson20217462010-11-23 15:26:33 +00001675 struct intel_ring_buffer *pipelined);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001676int i915_gem_attach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001677 struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01001678 int id,
1679 int align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001680void i915_gem_detach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001681 struct drm_i915_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001682void i915_gem_free_all_phys_object(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001683void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07001684
Chris Wilson467cffb2011-03-07 10:42:03 +00001685uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02001686i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1687uint32_t
Imre Deakd8651102013-01-07 21:47:33 +02001688i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1689 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00001690
Chris Wilsone4ffd172011-04-04 09:44:39 +01001691int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1692 enum i915_cache_level cache_level);
1693
Daniel Vetter1286ff72012-05-10 15:25:09 +02001694struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1695 struct dma_buf *dma_buf);
1696
1697struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1698 struct drm_gem_object *gem_obj, int flags);
1699
Ben Widawsky254f9652012-06-04 14:42:42 -07001700/* i915_gem_context.c */
1701void i915_gem_context_init(struct drm_device *dev);
1702void i915_gem_context_fini(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07001703void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
Ben Widawskye0556842012-06-04 14:42:46 -07001704int i915_switch_context(struct intel_ring_buffer *ring,
1705 struct drm_file *file, int to_id);
Ben Widawsky84624812012-06-04 14:42:54 -07001706int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1707 struct drm_file *file);
1708int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1709 struct drm_file *file);
Daniel Vetter1286ff72012-05-10 15:25:09 +02001710
Daniel Vetter76aaf222010-11-05 22:23:30 +01001711/* i915_gem_gtt.c */
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001712void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
Daniel Vetter7bddb012012-02-09 17:15:47 +01001713void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1714 struct drm_i915_gem_object *obj,
1715 enum i915_cache_level cache_level);
1716void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1717 struct drm_i915_gem_object *obj);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001718
Daniel Vetter76aaf222010-11-05 22:23:30 +01001719void i915_gem_restore_gtt_mappings(struct drm_device *dev);
Daniel Vetter74163902012-02-15 23:50:21 +01001720int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1721void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
Chris Wilsone4ffd172011-04-04 09:44:39 +01001722 enum i915_cache_level cache_level);
Chris Wilson05394f32010-11-08 19:18:58 +00001723void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
Daniel Vetter74163902012-02-15 23:50:21 +01001724void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
Ben Widawskyd7e50082012-12-18 10:31:25 -08001725void i915_gem_init_global_gtt(struct drm_device *dev);
1726void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1727 unsigned long mappable_end, unsigned long end);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001728int i915_gem_gtt_init(struct drm_device *dev);
Ben Widawskyd09105c2012-11-15 12:06:09 -08001729static inline void i915_gem_chipset_flush(struct drm_device *dev)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001730{
1731 if (INTEL_INFO(dev)->gen < 6)
1732 intel_gtt_chipset_flush();
1733}
1734
Daniel Vetter76aaf222010-11-05 22:23:30 +01001735
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01001736/* i915_gem_evict.c */
Chris Wilson20217462010-11-23 15:26:33 +00001737int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01001738 unsigned alignment,
1739 unsigned cache_level,
Chris Wilson86a1ee22012-08-11 15:41:04 +01001740 bool mappable,
1741 bool nonblock);
Chris Wilson6c085a72012-08-20 11:40:46 +02001742int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01001743
Chris Wilson9797fbf2012-04-24 15:47:39 +01001744/* i915_gem_stolen.c */
1745int i915_gem_init_stolen(struct drm_device *dev);
Chris Wilson11be49e2012-11-15 11:32:20 +00001746int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1747void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
Chris Wilson9797fbf2012-04-24 15:47:39 +01001748void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00001749struct drm_i915_gem_object *
1750i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08001751struct drm_i915_gem_object *
1752i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1753 u32 stolen_offset,
1754 u32 gtt_offset,
1755 u32 size);
Chris Wilson0104fdb2012-11-15 11:32:26 +00001756void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
Chris Wilson9797fbf2012-04-24 15:47:39 +01001757
Eric Anholt673a3942008-07-30 12:06:12 -07001758/* i915_gem_tiling.c */
Chris Wilsone9b73c62012-12-03 21:03:14 +00001759inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1760{
1761 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1762
1763 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1764 obj->tiling_mode != I915_TILING_NONE;
1765}
1766
Eric Anholt673a3942008-07-30 12:06:12 -07001767void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001768void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1769void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001770
1771/* i915_gem_debug.c */
Chris Wilson05394f32010-11-08 19:18:58 +00001772void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
Eric Anholt673a3942008-07-30 12:06:12 -07001773 const char *where, uint32_t mark);
Chris Wilson23bc5982010-09-29 16:10:57 +01001774#if WATCH_LISTS
1775int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07001776#else
Chris Wilson23bc5982010-09-29 16:10:57 +01001777#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07001778#endif
Chris Wilson05394f32010-11-08 19:18:58 +00001779void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1780 int handle);
1781void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
Eric Anholt673a3942008-07-30 12:06:12 -07001782 const char *where, uint32_t mark);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001783
Ben Gamari20172632009-02-17 20:08:50 -05001784/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04001785int i915_debugfs_init(struct drm_minor *minor);
1786void i915_debugfs_cleanup(struct drm_minor *minor);
Ben Gamari20172632009-02-17 20:08:50 -05001787
Jesse Barnes317c35d2008-08-25 15:11:06 -07001788/* i915_suspend.c */
1789extern int i915_save_state(struct drm_device *dev);
1790extern int i915_restore_state(struct drm_device *dev);
1791
Daniel Vetterd8157a32013-01-25 17:53:20 +01001792/* i915_ums.c */
1793void i915_save_display_reg(struct drm_device *dev);
1794void i915_restore_display_reg(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001795
Ben Widawsky0136db582012-04-10 21:17:01 -07001796/* i915_sysfs.c */
1797void i915_setup_sysfs(struct drm_device *dev_priv);
1798void i915_teardown_sysfs(struct drm_device *dev_priv);
1799
Chris Wilsonf899fc62010-07-20 15:44:45 -07001800/* intel_i2c.c */
1801extern int intel_setup_gmbus(struct drm_device *dev);
1802extern void intel_teardown_gmbus(struct drm_device *dev);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08001803extern inline bool intel_gmbus_is_port_valid(unsigned port)
1804{
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08001805 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08001806}
1807
1808extern struct i2c_adapter *intel_gmbus_get_adapter(
1809 struct drm_i915_private *dev_priv, unsigned port);
Chris Wilsone957d772010-09-24 12:52:03 +01001810extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1811extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Chris Wilsonb8232e92010-09-28 16:41:32 +01001812extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1813{
1814 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1815}
Chris Wilsonf899fc62010-07-20 15:44:45 -07001816extern void intel_i2c_reset(struct drm_device *dev);
1817
Chris Wilson3b617962010-08-24 09:02:58 +01001818/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01001819extern int intel_opregion_setup(struct drm_device *dev);
1820#ifdef CONFIG_ACPI
1821extern void intel_opregion_init(struct drm_device *dev);
1822extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01001823extern void intel_opregion_asle_intr(struct drm_device *dev);
1824extern void intel_opregion_gse_intr(struct drm_device *dev);
1825extern void intel_opregion_enable_asle(struct drm_device *dev);
Len Brown65e082c2008-10-24 17:18:10 -04001826#else
Chris Wilson44834a62010-08-19 16:09:23 +01001827static inline void intel_opregion_init(struct drm_device *dev) { return; }
1828static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01001829static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1830static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1831static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
Len Brown65e082c2008-10-24 17:18:10 -04001832#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001833
Jesse Barnes723bfd72010-10-07 16:01:13 -07001834/* intel_acpi.c */
1835#ifdef CONFIG_ACPI
1836extern void intel_register_dsm_handler(void);
1837extern void intel_unregister_dsm_handler(void);
1838#else
1839static inline void intel_register_dsm_handler(void) { return; }
1840static inline void intel_unregister_dsm_handler(void) { return; }
1841#endif /* CONFIG_ACPI */
1842
Jesse Barnes79e53942008-11-07 14:24:08 -08001843/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02001844extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001845extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01001846extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001847extern void intel_modeset_cleanup(struct drm_device *dev);
Dave Airlie28d52042009-09-21 14:33:58 +10001848extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01001849extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1850 bool force_restore);
Daniel Vetter44cec742013-01-25 17:53:21 +01001851extern void i915_redisable_vga(struct drm_device *dev);
Adam Jacksonee5382a2010-04-23 11:17:39 -04001852extern bool intel_fbc_enabled(struct drm_device *dev);
Chris Wilson43a95392011-07-08 12:22:36 +01001853extern void intel_disable_fbc(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001854extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02001855extern void intel_init_pch_refclk(struct drm_device *dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001856extern void gen6_set_rps(struct drm_device *dev, u8 val);
Akshay Joshi0206e352011-08-16 15:34:10 -04001857extern void intel_detect_pch(struct drm_device *dev);
1858extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db582012-04-10 21:17:01 -07001859extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001860
Ben Widawsky2911a352012-04-05 14:47:36 -07001861extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001862int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07001864
Chris Wilson6ef3d422010-08-04 20:26:07 +01001865/* overlay */
Chris Wilson3bd3c932010-08-19 08:19:30 +01001866#ifdef CONFIG_DEBUG_FS
Chris Wilson6ef3d422010-08-04 20:26:07 +01001867extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1868extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00001869
1870extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1871extern void intel_display_print_error_state(struct seq_file *m,
1872 struct drm_device *dev,
1873 struct intel_display_error_state *error);
Chris Wilson3bd3c932010-08-19 08:19:30 +01001874#endif
Chris Wilson6ef3d422010-08-04 20:26:07 +01001875
Ben Widawskyb7287d82011-04-25 11:22:22 -07001876/* On SNB platform, before reading ring registers forcewake bit
1877 * must be set to prevent GT core from power down and stale values being
1878 * returned.
1879 */
Ben Widawskyfcca7922011-04-25 11:23:07 -07001880void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1881void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
Ben Widawsky67a37442012-02-09 10:15:20 +01001882int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
Ben Widawskyb7287d82011-04-25 11:22:22 -07001883
Ben Widawsky42c05262012-09-26 10:34:00 -07001884int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1885int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
Jesse Barnesa0e4e192013-04-02 11:23:05 -07001886int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1887int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
Ben Widawsky42c05262012-09-26 10:34:00 -07001888
Keith Packard5f753772010-11-22 09:24:22 +00001889#define __i915_read(x, y) \
Andi Kleenf7000882011-10-13 16:08:51 -07001890 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
Ben Widawskyfcca7922011-04-25 11:23:07 -07001891
Keith Packard5f753772010-11-22 09:24:22 +00001892__i915_read(8, b)
1893__i915_read(16, w)
1894__i915_read(32, l)
1895__i915_read(64, q)
1896#undef __i915_read
1897
1898#define __i915_write(x, y) \
Andi Kleenf7000882011-10-13 16:08:51 -07001899 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1900
Keith Packard5f753772010-11-22 09:24:22 +00001901__i915_write(8, b)
1902__i915_write(16, w)
1903__i915_write(32, l)
1904__i915_write(64, q)
1905#undef __i915_write
1906
1907#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1908#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1909
1910#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1911#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1912#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1913#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1914
1915#define I915_READ(reg) i915_read32(dev_priv, (reg))
1916#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
Zou Nan haicae58522010-11-09 17:17:32 +08001917#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1918#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
Keith Packard5f753772010-11-22 09:24:22 +00001919
1920#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1921#define I915_READ64(reg) i915_read64(dev_priv, (reg))
Zou Nan haicae58522010-11-09 17:17:32 +08001922
1923#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1924#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1925
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001926/* "Broadcast RGB" property */
1927#define INTEL_BROADCAST_RGB_AUTO 0
1928#define INTEL_BROADCAST_RGB_FULL 1
1929#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08001930
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02001931static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1932{
1933 if (HAS_PCH_SPLIT(dev))
1934 return CPU_VGACNTRL;
1935 else if (IS_VALLEYVIEW(dev))
1936 return VLV_VGACNTRL;
1937 else
1938 return VGACNTRL;
1939}
1940
Ville Syrjälä2bb46292013-02-22 16:12:51 +02001941static inline void __user *to_user_ptr(u64 address)
1942{
1943 return (void __user *)(uintptr_t)address;
1944}
1945
Imre Deakdf977292013-05-21 20:03:17 +03001946static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
1947{
1948 unsigned long j = msecs_to_jiffies(m);
1949
1950 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
1951}
1952
1953static inline unsigned long
1954timespec_to_jiffies_timeout(const struct timespec *value)
1955{
1956 unsigned long j = timespec_to_jiffies(value);
1957
1958 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
1959}
1960
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961#endif