Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of version 2 of the GNU General Public License as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | ******************************************************************************/ |
| 15 | #define _HCI_HAL_INIT_C_ |
| 16 | |
| 17 | #include <osdep_service.h> |
| 18 | #include <drv_types.h> |
| 19 | #include <rtw_efuse.h> |
| 20 | |
| 21 | #include <HalPwrSeqCmd.h> |
| 22 | #include <Hal8723PwrSeq.h> |
| 23 | #include <rtl8723a_hal.h> |
| 24 | #include <rtl8723a_led.h> |
| 25 | #include <linux/ieee80211.h> |
| 26 | |
| 27 | #include <usb_ops.h> |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 28 | |
| 29 | static void |
| 30 | _ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe) |
| 31 | { |
| 32 | u8 value8; |
| 33 | struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); |
| 34 | |
| 35 | pHalData->OutEpQueueSel = 0; |
| 36 | pHalData->OutEpNumber = 0; |
| 37 | |
| 38 | /* Normal and High queue */ |
| 39 | value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1)); |
| 40 | |
| 41 | if (value8 & USB_NORMAL_SIE_EP_MASK) { |
| 42 | pHalData->OutEpQueueSel |= TX_SELE_HQ; |
| 43 | pHalData->OutEpNumber++; |
| 44 | } |
| 45 | |
| 46 | if ((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK) { |
| 47 | pHalData->OutEpQueueSel |= TX_SELE_NQ; |
| 48 | pHalData->OutEpNumber++; |
| 49 | } |
| 50 | |
| 51 | /* Low queue */ |
| 52 | value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2)); |
| 53 | if (value8 & USB_NORMAL_SIE_EP_MASK) { |
| 54 | pHalData->OutEpQueueSel |= TX_SELE_LQ; |
| 55 | pHalData->OutEpNumber++; |
| 56 | } |
| 57 | |
| 58 | /* TODO: Error recovery for this case */ |
| 59 | /* RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), |
| 60 | ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", |
| 61 | (u32)NumOutPipe, (u32)pHalData->OutEpNumber)); */ |
| 62 | } |
| 63 | |
| 64 | static bool rtl8723au_set_queue_pipe_mapping(struct rtw_adapter *pAdapter, |
| 65 | u8 NumInPipe, u8 NumOutPipe) |
| 66 | { |
| 67 | struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); |
| 68 | bool result = false; |
| 69 | |
| 70 | _ConfigChipOutEP(pAdapter, NumOutPipe); |
| 71 | |
| 72 | /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */ |
| 73 | if (pHalData->OutEpNumber == 1) { |
| 74 | if (NumInPipe != 1) |
| 75 | return result; |
| 76 | } |
| 77 | |
| 78 | result = Hal_MappingOutPipe23a(pAdapter, NumOutPipe); |
| 79 | |
| 80 | return result; |
| 81 | } |
| 82 | |
Jes Sorensen | 82ccb59 | 2014-05-16 10:04:07 +0200 | [diff] [blame] | 83 | void rtl8723au_chip_configure(struct rtw_adapter *padapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 84 | { |
| 85 | struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); |
| 86 | struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); |
| 87 | |
| 88 | if (pdvobjpriv->ishighspeed == true) { |
| 89 | /* 512 bytes */ |
| 90 | pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE; |
| 91 | } else { |
| 92 | /* 64 bytes */ |
| 93 | pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE; |
| 94 | } |
| 95 | |
| 96 | pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber; |
| 97 | |
| 98 | rtl8723au_set_queue_pipe_mapping(padapter, |
| 99 | pdvobjpriv->RtNumInPipes, |
| 100 | pdvobjpriv->RtNumOutPipes); |
| 101 | } |
| 102 | |
Jes Sorensen | e04cd3f | 2014-05-16 10:04:44 +0200 | [diff] [blame^] | 103 | static int _InitPowerOn(struct rtw_adapter *padapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 104 | { |
Jes Sorensen | e04cd3f | 2014-05-16 10:04:44 +0200 | [diff] [blame^] | 105 | int status = _SUCCESS; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 106 | u16 value16 = 0; |
| 107 | u8 value8 = 0; |
| 108 | |
| 109 | /* RSV_CTRL 0x1C[7:0] = 0x00 |
| 110 | unlock ISO/CLK/Power control register */ |
| 111 | rtw_write8(padapter, REG_RSV_CTRL, 0x0); |
| 112 | |
| 113 | /* HW Power on sequence */ |
| 114 | if (!HalPwrSeqCmdParsing23a(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, |
| 115 | PWR_INTF_USB_MSK, rtl8723AU_card_enable_flow)) |
| 116 | return _FAIL; |
| 117 | |
| 118 | /* 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051 */ |
| 119 | value8 = rtw_read8(padapter, REG_APS_FSMCO+2); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 120 | rtw_write8(padapter, REG_APS_FSMCO + 2, value8 | BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 121 | |
| 122 | /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ |
| 123 | /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. |
| 124 | Added by tynli. 2011.08.31. */ |
| 125 | value16 = rtw_read16(padapter, REG_CR); |
| 126 | value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | |
| 127 | PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | |
| 128 | ENSEC | CALTMR_EN); |
| 129 | rtw_write16(padapter, REG_CR, value16); |
| 130 | |
| 131 | /* for Efuse PG, suggest by Jackie 2011.11.23 */ |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 132 | PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT(28)|BIT(29)|BIT(30), 0x06); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 133 | |
| 134 | return status; |
| 135 | } |
| 136 | |
| 137 | /* Shall USB interface init this? */ |
| 138 | static void _InitInterrupt(struct rtw_adapter *Adapter) |
| 139 | { |
| 140 | u32 value32; |
| 141 | |
| 142 | /* HISR - turn all on */ |
| 143 | value32 = 0xFFFFFFFF; |
| 144 | rtw_write32(Adapter, REG_HISR, value32); |
| 145 | |
| 146 | /* HIMR - turn all on */ |
| 147 | rtw_write32(Adapter, REG_HIMR, value32); |
| 148 | } |
| 149 | |
| 150 | static void _InitQueueReservedPage(struct rtw_adapter *Adapter) |
| 151 | { |
| 152 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 153 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
| 154 | u32 numHQ = 0; |
| 155 | u32 numLQ = 0; |
| 156 | u32 numNQ = 0; |
| 157 | u32 numPubQ; |
| 158 | u32 value32; |
| 159 | u8 value8; |
| 160 | bool bWiFiConfig = pregistrypriv->wifi_spec; |
| 161 | /* u32 txQPageNum, txQPageUnit, txQRemainPage; */ |
| 162 | |
| 163 | { /* for WMM */ |
| 164 | /* RT_ASSERT((outEPNum>= 2), ("for WMM , number of out-ep " |
| 165 | "must more than or equal to 2!\n")); */ |
| 166 | |
| 167 | numPubQ = bWiFiConfig ? |
| 168 | WMM_NORMAL_PAGE_NUM_PUBQ : NORMAL_PAGE_NUM_PUBQ; |
| 169 | |
| 170 | if (pHalData->OutEpQueueSel & TX_SELE_HQ) { |
| 171 | numHQ = bWiFiConfig ? |
| 172 | WMM_NORMAL_PAGE_NUM_HPQ : NORMAL_PAGE_NUM_HPQ; |
| 173 | } |
| 174 | |
| 175 | if (pHalData->OutEpQueueSel & TX_SELE_LQ) { |
| 176 | numLQ = bWiFiConfig ? |
| 177 | WMM_NORMAL_PAGE_NUM_LPQ : NORMAL_PAGE_NUM_LPQ; |
| 178 | } |
| 179 | /* NOTE: This step shall be proceed before |
| 180 | writting REG_RQPN. */ |
| 181 | if (pHalData->OutEpQueueSel & TX_SELE_NQ) { |
| 182 | numNQ = bWiFiConfig ? |
| 183 | WMM_NORMAL_PAGE_NUM_NPQ : NORMAL_PAGE_NUM_NPQ; |
| 184 | } |
| 185 | value8 = (u8)_NPQ(numNQ); |
| 186 | rtw_write8(Adapter, REG_RQPN_NPQ, value8); |
| 187 | } |
| 188 | |
| 189 | /* TX DMA */ |
| 190 | value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; |
| 191 | rtw_write32(Adapter, REG_RQPN, value32); |
| 192 | } |
| 193 | |
| 194 | static void _InitTxBufferBoundary(struct rtw_adapter *Adapter) |
| 195 | { |
| 196 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
| 197 | |
| 198 | u8 txpktbuf_bndy; |
| 199 | |
| 200 | if (!pregistrypriv->wifi_spec) |
| 201 | txpktbuf_bndy = TX_PAGE_BOUNDARY; |
| 202 | else /* for WMM */ |
| 203 | txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY; |
| 204 | |
| 205 | rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); |
| 206 | rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); |
| 207 | rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); |
| 208 | rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy); |
| 209 | rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy); |
| 210 | } |
| 211 | |
| 212 | static void _InitPageBoundary(struct rtw_adapter *Adapter) |
| 213 | { |
| 214 | /* RX Page Boundary */ |
| 215 | /* srand(static_cast<unsigned int>(time(NULL))); */ |
| 216 | u16 rxff_bndy = 0x27FF;/* rand() % 1) ? 0x27FF : 0x23FF; */ |
| 217 | |
| 218 | rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); |
| 219 | |
| 220 | /* TODO: ?? shall we set tx boundary? */ |
| 221 | } |
| 222 | |
| 223 | static void |
| 224 | _InitNormalChipRegPriority(struct rtw_adapter *Adapter, u16 beQ, u16 bkQ, |
| 225 | u16 viQ, u16 voQ, u16 mgtQ, u16 hiQ) |
| 226 | { |
| 227 | u16 value16 = rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7; |
| 228 | |
| 229 | value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | |
| 230 | _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | |
| 231 | _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); |
| 232 | |
| 233 | rtw_write16(Adapter, REG_TRXDMA_CTRL, value16); |
| 234 | } |
| 235 | |
| 236 | static void _InitNormalChipOneOutEpPriority(struct rtw_adapter *Adapter) |
| 237 | { |
| 238 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 239 | u16 value = 0; |
| 240 | |
| 241 | switch (pHalData->OutEpQueueSel) { |
| 242 | case TX_SELE_HQ: |
| 243 | value = QUEUE_HIGH; |
| 244 | break; |
| 245 | case TX_SELE_LQ: |
| 246 | value = QUEUE_LOW; |
| 247 | break; |
| 248 | case TX_SELE_NQ: |
| 249 | value = QUEUE_NORMAL; |
| 250 | break; |
| 251 | default: |
| 252 | /* RT_ASSERT(false, ("Shall not reach here!\n")); */ |
| 253 | break; |
| 254 | } |
| 255 | |
| 256 | _InitNormalChipRegPriority(Adapter, value, value, value, |
| 257 | value, value, value); |
| 258 | } |
| 259 | |
| 260 | static void _InitNormalChipTwoOutEpPriority(struct rtw_adapter *Adapter) |
| 261 | { |
| 262 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 263 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
| 264 | u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; |
| 265 | u16 valueHi = 0; |
| 266 | u16 valueLow = 0; |
| 267 | |
| 268 | switch (pHalData->OutEpQueueSel) { |
| 269 | case (TX_SELE_HQ | TX_SELE_LQ): |
| 270 | valueHi = QUEUE_HIGH; |
| 271 | valueLow = QUEUE_LOW; |
| 272 | break; |
| 273 | case (TX_SELE_NQ | TX_SELE_LQ): |
| 274 | valueHi = QUEUE_NORMAL; |
| 275 | valueLow = QUEUE_LOW; |
| 276 | break; |
| 277 | case (TX_SELE_HQ | TX_SELE_NQ): |
| 278 | valueHi = QUEUE_HIGH; |
| 279 | valueLow = QUEUE_NORMAL; |
| 280 | break; |
| 281 | default: |
| 282 | /* RT_ASSERT(false, ("Shall not reach here!\n")); */ |
| 283 | break; |
| 284 | } |
| 285 | |
| 286 | if (!pregistrypriv->wifi_spec) { |
| 287 | beQ = valueLow; |
| 288 | bkQ = valueLow; |
| 289 | viQ = valueHi; |
| 290 | voQ = valueHi; |
| 291 | mgtQ = valueHi; |
| 292 | hiQ = valueHi; |
| 293 | } else {/* for WMM , CONFIG_OUT_EP_WIFI_MODE */ |
| 294 | beQ = valueLow; |
| 295 | bkQ = valueHi; |
| 296 | viQ = valueHi; |
| 297 | voQ = valueLow; |
| 298 | mgtQ = valueHi; |
| 299 | hiQ = valueHi; |
| 300 | } |
| 301 | |
| 302 | _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); |
| 303 | } |
| 304 | |
| 305 | static void _InitNormalChipThreeOutEpPriority(struct rtw_adapter *Adapter) |
| 306 | { |
| 307 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
| 308 | u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; |
| 309 | |
| 310 | if (!pregistrypriv->wifi_spec) {/* typical setting */ |
| 311 | beQ = QUEUE_LOW; |
| 312 | bkQ = QUEUE_LOW; |
| 313 | viQ = QUEUE_NORMAL; |
| 314 | voQ = QUEUE_HIGH; |
| 315 | mgtQ = QUEUE_HIGH; |
| 316 | hiQ = QUEUE_HIGH; |
| 317 | } else {/* for WMM */ |
| 318 | beQ = QUEUE_LOW; |
| 319 | bkQ = QUEUE_NORMAL; |
| 320 | viQ = QUEUE_NORMAL; |
| 321 | voQ = QUEUE_HIGH; |
| 322 | mgtQ = QUEUE_HIGH; |
| 323 | hiQ = QUEUE_HIGH; |
| 324 | } |
| 325 | _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); |
| 326 | } |
| 327 | |
| 328 | static void _InitNormalChipQueuePriority(struct rtw_adapter *Adapter) |
| 329 | { |
| 330 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 331 | |
| 332 | switch (pHalData->OutEpNumber) { |
| 333 | case 1: |
| 334 | _InitNormalChipOneOutEpPriority(Adapter); |
| 335 | break; |
| 336 | case 2: |
| 337 | _InitNormalChipTwoOutEpPriority(Adapter); |
| 338 | break; |
| 339 | case 3: |
| 340 | _InitNormalChipThreeOutEpPriority(Adapter); |
| 341 | break; |
| 342 | default: |
| 343 | /* RT_ASSERT(false, ("Shall not reach here!\n")); */ |
| 344 | break; |
| 345 | } |
| 346 | } |
| 347 | |
| 348 | static void _InitQueuePriority(struct rtw_adapter *Adapter) |
| 349 | { |
| 350 | _InitNormalChipQueuePriority(Adapter); |
| 351 | } |
| 352 | |
| 353 | static void _InitNetworkType(struct rtw_adapter *Adapter) |
| 354 | { |
| 355 | u32 value32; |
| 356 | |
| 357 | value32 = rtw_read32(Adapter, REG_CR); |
| 358 | |
| 359 | /* TODO: use the other function to set network type */ |
| 360 | value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); |
| 361 | rtw_write32(Adapter, REG_CR, value32); |
| 362 | } |
| 363 | |
| 364 | static void _InitTransferPageSize(struct rtw_adapter *Adapter) |
| 365 | { |
| 366 | /* Tx page size is always 128. */ |
| 367 | |
| 368 | u8 value8; |
| 369 | value8 = _PSRX(PBP_128) | _PSTX(PBP_128); |
| 370 | rtw_write8(Adapter, REG_PBP, value8); |
| 371 | } |
| 372 | |
| 373 | static void _InitDriverInfoSize(struct rtw_adapter *Adapter, u8 drvInfoSize) |
| 374 | { |
| 375 | rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize); |
| 376 | } |
| 377 | |
| 378 | static void _InitWMACSetting(struct rtw_adapter *Adapter) |
| 379 | { |
| 380 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 381 | |
| 382 | /* don't turn on AAP, it will allow all packets to driver */ |
| 383 | pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | |
| 384 | RCR_CBSSID_BCN | RCR_APP_ICV | RCR_AMF | |
| 385 | RCR_HTC_LOC_CTRL | RCR_APP_MIC | |
| 386 | RCR_APP_PHYSTS; |
| 387 | |
| 388 | /* some REG_RCR will be modified later by |
| 389 | phy_ConfigMACWithHeaderFile() */ |
| 390 | rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig); |
| 391 | |
| 392 | /* Accept all multicast address */ |
| 393 | rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF); |
| 394 | rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF); |
| 395 | |
| 396 | /* Accept all data frames */ |
| 397 | /* value16 = 0xFFFF; */ |
| 398 | /* rtw_write16(Adapter, REG_RXFLTMAP2, value16); */ |
| 399 | |
| 400 | /* 2010.09.08 hpfan */ |
| 401 | /* Since ADF is removed from RCR, ps-poll will not be indicate |
| 402 | to driver, */ |
| 403 | /* RxFilterMap should mask ps-poll to gurantee AP mode can |
| 404 | rx ps-poll. */ |
| 405 | /* value16 = 0x400; */ |
| 406 | /* rtw_write16(Adapter, REG_RXFLTMAP1, value16); */ |
| 407 | |
| 408 | /* Accept all management frames */ |
| 409 | /* value16 = 0xFFFF; */ |
| 410 | /* rtw_write16(Adapter, REG_RXFLTMAP0, value16); */ |
| 411 | |
| 412 | /* enable RX_SHIFT bits */ |
| 413 | /* rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, |
| 414 | REG_TRXDMA_CTRL)|BIT(1)); */ |
| 415 | } |
| 416 | |
| 417 | static void _InitAdaptiveCtrl(struct rtw_adapter *Adapter) |
| 418 | { |
| 419 | u16 value16; |
| 420 | u32 value32; |
| 421 | |
| 422 | /* Response Rate Set */ |
| 423 | value32 = rtw_read32(Adapter, REG_RRSR); |
| 424 | value32 &= ~RATE_BITMAP_ALL; |
| 425 | value32 |= RATE_RRSR_CCK_ONLY_1M; |
| 426 | rtw_write32(Adapter, REG_RRSR, value32); |
| 427 | |
| 428 | /* CF-END Threshold */ |
| 429 | /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */ |
| 430 | |
| 431 | /* SIFS (used in NAV) */ |
| 432 | value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); |
| 433 | rtw_write16(Adapter, REG_SPEC_SIFS, value16); |
| 434 | |
| 435 | /* Retry Limit */ |
| 436 | value16 = _LRL(0x30) | _SRL(0x30); |
| 437 | rtw_write16(Adapter, REG_RL, value16); |
| 438 | } |
| 439 | |
| 440 | static void _InitRateFallback(struct rtw_adapter *Adapter) |
| 441 | { |
| 442 | /* Set Data Auto Rate Fallback Retry Count register. */ |
| 443 | rtw_write32(Adapter, REG_DARFRC, 0x00000000); |
| 444 | rtw_write32(Adapter, REG_DARFRC+4, 0x10080404); |
| 445 | rtw_write32(Adapter, REG_RARFRC, 0x04030201); |
| 446 | rtw_write32(Adapter, REG_RARFRC+4, 0x08070605); |
| 447 | } |
| 448 | |
| 449 | static void _InitEDCA(struct rtw_adapter *Adapter) |
| 450 | { |
| 451 | /* Set Spec SIFS (used in NAV) */ |
| 452 | rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a); |
| 453 | rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a); |
| 454 | |
| 455 | /* Set SIFS for CCK */ |
| 456 | rtw_write16(Adapter, REG_SIFS_CTX, 0x100a); |
| 457 | |
| 458 | /* Set SIFS for OFDM */ |
| 459 | rtw_write16(Adapter, REG_SIFS_TRX, 0x100a); |
| 460 | |
| 461 | /* TXOP */ |
| 462 | rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B); |
| 463 | rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F); |
| 464 | rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324); |
| 465 | rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226); |
| 466 | } |
| 467 | |
| 468 | static void _InitHWLed(struct rtw_adapter *Adapter) |
| 469 | { |
| 470 | struct led_priv *pledpriv = &Adapter->ledpriv; |
| 471 | |
| 472 | if (pledpriv->LedStrategy != HW_LED) |
| 473 | return; |
| 474 | |
| 475 | /* HW led control */ |
| 476 | /* to do .... */ |
| 477 | /* must consider cases of antenna diversity/ commbo card/solo card/mini card */ |
| 478 | } |
| 479 | |
| 480 | static void _InitRDGSetting(struct rtw_adapter *Adapter) |
| 481 | { |
| 482 | rtw_write8(Adapter, REG_RD_CTRL, 0xFF); |
| 483 | rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200); |
| 484 | rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05); |
| 485 | } |
| 486 | |
| 487 | static void _InitRetryFunction(struct rtw_adapter *Adapter) |
| 488 | { |
| 489 | u8 value8; |
| 490 | |
| 491 | value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL); |
| 492 | value8 |= EN_AMPDU_RTY_NEW; |
| 493 | rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8); |
| 494 | |
| 495 | /* Set ACK timeout */ |
| 496 | rtw_write8(Adapter, REG_ACKTO, 0x40); |
| 497 | } |
| 498 | |
| 499 | /*----------------------------------------------------------------------------- |
| 500 | * Function: usb_AggSettingTxUpdate() |
| 501 | * |
| 502 | * Overview: Seperate TX/RX parameters update independent for TP |
| 503 | * detection and dynamic TX/RX aggreagtion parameters update. |
| 504 | * |
| 505 | * Input: struct rtw_adapter * |
| 506 | * |
| 507 | * Output/Return: NONE |
| 508 | * |
| 509 | * Revised History: |
| 510 | * When Who Remark |
| 511 | * 12/10/2010 MHC Seperate to smaller function. |
| 512 | * |
| 513 | *---------------------------------------------------------------------------*/ |
| 514 | static void usb_AggSettingTxUpdate(struct rtw_adapter *Adapter) |
| 515 | { |
| 516 | } /* usb_AggSettingTxUpdate */ |
| 517 | |
| 518 | /*----------------------------------------------------------------------------- |
| 519 | * Function: usb_AggSettingRxUpdate() |
| 520 | * |
| 521 | * Overview: Seperate TX/RX parameters update independent for TP |
| 522 | * detection and dynamic TX/RX aggreagtion parameters update. |
| 523 | * |
| 524 | * Input: struct rtw_adapter * |
| 525 | * |
| 526 | * Output/Return: NONE |
| 527 | * |
| 528 | * Revised History: |
| 529 | * When Who Remark |
| 530 | * 12/10/2010 MHC Seperate to smaller function. |
| 531 | * |
| 532 | *---------------------------------------------------------------------------*/ |
| 533 | static void usb_AggSettingRxUpdate(struct rtw_adapter *Adapter) |
| 534 | { |
| 535 | } /* usb_AggSettingRxUpdate */ |
| 536 | |
| 537 | static void InitUsbAggregationSetting(struct rtw_adapter *Adapter) |
| 538 | { |
| 539 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 540 | |
| 541 | /* Tx aggregation setting */ |
| 542 | usb_AggSettingTxUpdate(Adapter); |
| 543 | |
| 544 | /* Rx aggregation setting */ |
| 545 | usb_AggSettingRxUpdate(Adapter); |
| 546 | |
| 547 | /* 201/12/10 MH Add for USB agg mode dynamic switch. */ |
| 548 | pHalData->UsbRxHighSpeedMode = false; |
| 549 | } |
| 550 | |
| 551 | static void _InitOperationMode(struct rtw_adapter *Adapter) |
| 552 | { |
| 553 | } |
| 554 | |
| 555 | static void _InitRFType(struct rtw_adapter *Adapter) |
| 556 | { |
| 557 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 558 | bool is92CU = IS_92C_SERIAL(pHalData->VersionID); |
| 559 | |
| 560 | pHalData->rf_chip = RF_6052; |
| 561 | |
| 562 | if (is92CU == false) { |
| 563 | pHalData->rf_type = RF_1T1R; |
| 564 | DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n"); |
| 565 | return; |
| 566 | } |
| 567 | |
| 568 | /* TODO: Consider that EEPROM set 92CU to 1T1R later. */ |
| 569 | /* Force to overwrite setting according to chip version. Ignore |
| 570 | EEPROM setting. */ |
| 571 | /* pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; */ |
| 572 | MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n", |
| 573 | pHalData->rf_type); |
| 574 | } |
| 575 | |
| 576 | /* Set CCK and OFDM Block "ON" */ |
| 577 | static void _BBTurnOnBlock(struct rtw_adapter *Adapter) |
| 578 | { |
| 579 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); |
| 580 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); |
| 581 | } |
| 582 | |
| 583 | #define MgntActSet_RF_State(...) |
| 584 | static void _RfPowerSave(struct rtw_adapter *padapter) |
| 585 | { |
| 586 | } |
| 587 | |
| 588 | enum { |
| 589 | Antenna_Lfet = 1, |
| 590 | Antenna_Right = 2, |
| 591 | }; |
| 592 | |
| 593 | enum rt_rf_power_state RfOnOffDetect23a(struct rtw_adapter *pAdapter) |
| 594 | { |
| 595 | /* struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); */ |
| 596 | u8 val8; |
| 597 | enum rt_rf_power_state rfpowerstate = rf_off; |
| 598 | |
| 599 | if (pAdapter->pwrctrlpriv.bHWPowerdown) { |
| 600 | val8 = rtw_read8(pAdapter, REG_HSISR); |
| 601 | DBG_8723A("pwrdown, 0x5c(BIT7) =%02x\n", val8); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 602 | rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 603 | } else { /* rf on/off */ |
| 604 | rtw_write8(pAdapter, REG_MAC_PINMUX_CFG, |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 605 | rtw_read8(pAdapter, REG_MAC_PINMUX_CFG) & ~BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 606 | val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL); |
| 607 | DBG_8723A("GPIO_IN =%02x\n", val8); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 608 | rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 609 | } |
| 610 | return rfpowerstate; |
| 611 | } /* HalDetectPwrDownMode */ |
| 612 | |
| 613 | void _ps_open_RF23a(struct rtw_adapter *padapter); |
| 614 | |
Jes Sorensen | c7772697 | 2014-05-16 10:04:16 +0200 | [diff] [blame] | 615 | static int rtl8723au_hal_init(struct rtw_adapter *Adapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 616 | { |
Jes Sorensen | c7772697 | 2014-05-16 10:04:16 +0200 | [diff] [blame] | 617 | u8 val8 = 0; |
| 618 | u32 boundary; |
| 619 | int status = _SUCCESS; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 620 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 621 | struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; |
| 622 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 623 | |
| 624 | unsigned long init_start_time = jiffies; |
| 625 | |
| 626 | #define HAL_INIT_PROFILE_TAG(stage) do {} while (0) |
| 627 | |
| 628 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN); |
| 629 | if (Adapter->pwrctrlpriv.bkeepfwalive) { |
| 630 | _ps_open_RF23a(Adapter); |
| 631 | |
| 632 | if (pHalData->bIQKInitialized) { |
| 633 | rtl8723a_phy_iq_calibrate(Adapter, true); |
| 634 | } else { |
| 635 | rtl8723a_phy_iq_calibrate(Adapter, false); |
| 636 | pHalData->bIQKInitialized = true; |
| 637 | } |
| 638 | rtl8723a_odm_check_tx_power_tracking(Adapter); |
| 639 | rtl8723a_phy_lc_calibrate(Adapter); |
| 640 | |
| 641 | goto exit; |
| 642 | } |
| 643 | |
| 644 | /* Check if MAC has already power on. by tynli. 2011.05.27. */ |
| 645 | val8 = rtw_read8(Adapter, REG_CR); |
| 646 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 647 | ("%s: REG_CR 0x100 = 0x%02x\n", __func__, val8)); |
| 648 | /* Fix 92DU-VC S3 hang with the reason is that secondary mac is not |
| 649 | initialized. */ |
| 650 | /* 0x100 value of first mac is 0xEA while 0x100 value of secondary |
| 651 | is 0x00 */ |
| 652 | if (val8 == 0xEA) { |
| 653 | pHalData->bMACFuncEnable = false; |
| 654 | } else { |
| 655 | pHalData->bMACFuncEnable = true; |
| 656 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 657 | ("%s: MAC has already power on\n", __func__)); |
| 658 | } |
| 659 | |
| 660 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON); |
| 661 | status = _InitPowerOn(Adapter); |
| 662 | if (status == _FAIL) { |
| 663 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, |
| 664 | ("Failed to init power on!\n")); |
| 665 | goto exit; |
| 666 | } |
| 667 | |
| 668 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT); |
| 669 | if (!pregistrypriv->wifi_spec) { |
| 670 | boundary = TX_PAGE_BOUNDARY; |
| 671 | } else { |
| 672 | /* for WMM */ |
| 673 | boundary = WMM_NORMAL_TX_PAGE_BOUNDARY; |
| 674 | } |
| 675 | |
| 676 | if (!pHalData->bMACFuncEnable) { |
| 677 | status = InitLLTTable23a(Adapter, boundary); |
| 678 | if (status == _FAIL) { |
| 679 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, |
| 680 | ("Failed to init LLT table\n")); |
| 681 | goto exit; |
| 682 | } |
| 683 | } |
| 684 | |
| 685 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01); |
| 686 | if (pHalData->bRDGEnable) |
| 687 | _InitRDGSetting(Adapter); |
| 688 | |
| 689 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW); |
| 690 | status = rtl8723a_FirmwareDownload(Adapter); |
| 691 | if (status != _SUCCESS) { |
| 692 | Adapter->bFWReady = false; |
| 693 | pHalData->fw_ractrl = false; |
| 694 | DBG_8723A("fw download fail!\n"); |
| 695 | goto exit; |
| 696 | } else { |
| 697 | Adapter->bFWReady = true; |
| 698 | pHalData->fw_ractrl = true; |
| 699 | DBG_8723A("fw download ok!\n"); |
| 700 | } |
| 701 | |
| 702 | rtl8723a_InitializeFirmwareVars(Adapter); |
| 703 | |
| 704 | if (pwrctrlpriv->reg_rfoff == true) { |
| 705 | pwrctrlpriv->rf_pwrstate = rf_off; |
| 706 | } |
| 707 | |
| 708 | /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */ |
| 709 | /* HW GPIO pin. Before PHY_RFConfig8192C. */ |
| 710 | /* HalDetectPwrDownMode(Adapter); */ |
| 711 | /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */ |
| 712 | /* HalDetectSelectiveSuspendMode(Adapter); */ |
| 713 | |
| 714 | /* Set RF type for BB/RF configuration */ |
| 715 | _InitRFType(Adapter);/* _ReadRFType() */ |
| 716 | |
| 717 | /* Save target channel */ |
| 718 | /* <Roger_Notes> Current Channel will be updated again later. */ |
| 719 | pHalData->CurrentChannel = 6;/* default set to 6 */ |
| 720 | |
| 721 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC); |
| 722 | status = PHY_MACConfig8723A(Adapter); |
| 723 | if (status == _FAIL) { |
| 724 | DBG_8723A("PHY_MACConfig8723A fault !!\n"); |
| 725 | goto exit; |
| 726 | } |
| 727 | |
| 728 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB); |
| 729 | /* */ |
| 730 | /* d. Initialize BB related configurations. */ |
| 731 | /* */ |
| 732 | status = PHY_BBConfig8723A(Adapter); |
| 733 | if (status == _FAIL) { |
| 734 | DBG_8723A("PHY_BBConfig8723A fault !!\n"); |
| 735 | goto exit; |
| 736 | } |
| 737 | |
| 738 | /* Add for tx power by rate fine tune. We need to call the function after BB config. */ |
| 739 | /* Because the tx power by rate table is inited in BB config. */ |
| 740 | |
| 741 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF); |
| 742 | status = PHY_RFConfig8723A(Adapter); |
| 743 | if (status == _FAIL) { |
| 744 | DBG_8723A("PHY_RFConfig8723A fault !!\n"); |
| 745 | goto exit; |
| 746 | } |
| 747 | |
| 748 | /* reducing 80M spur */ |
| 749 | PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d); |
| 750 | PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83); |
| 751 | PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82); |
| 752 | PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83); |
| 753 | |
| 754 | /* RFSW Control */ |
| 755 | PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003); /* 0x804[14]= 0 */ |
| 756 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760); /* 0x870[6:5]= b'11 */ |
| 757 | PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); /* 0x860[6:5]= b'00 */ |
| 758 | |
| 759 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __func__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord))); |
| 760 | |
| 761 | /* */ |
| 762 | /* Joseph Note: Keep RfRegChnlVal for later use. */ |
| 763 | /* */ |
| 764 | pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)0, RF_CHNLBW, bRFRegOffsetMask); |
| 765 | pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)1, RF_CHNLBW, bRFRegOffsetMask); |
| 766 | |
| 767 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); |
| 768 | if (!pHalData->bMACFuncEnable) { |
| 769 | _InitQueueReservedPage(Adapter); |
| 770 | _InitTxBufferBoundary(Adapter); |
| 771 | } |
| 772 | _InitQueuePriority(Adapter); |
| 773 | _InitPageBoundary(Adapter); |
| 774 | _InitTransferPageSize(Adapter); |
| 775 | |
| 776 | /* Get Rx PHY status in order to report RSSI and others. */ |
| 777 | _InitDriverInfoSize(Adapter, DRVINFO_SZ); |
| 778 | |
| 779 | _InitInterrupt(Adapter); |
Jes Sorensen | 3c5660e | 2014-04-09 23:20:19 +0200 | [diff] [blame] | 780 | hw_var_set_macaddr(Adapter, Adapter->eeprompriv.mac_addr); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 781 | _InitNetworkType(Adapter);/* set msr */ |
| 782 | _InitWMACSetting(Adapter); |
| 783 | _InitAdaptiveCtrl(Adapter); |
| 784 | _InitEDCA(Adapter); |
| 785 | _InitRateFallback(Adapter); |
| 786 | _InitRetryFunction(Adapter); |
| 787 | InitUsbAggregationSetting(Adapter); |
| 788 | _InitOperationMode(Adapter);/* todo */ |
| 789 | rtl8723a_InitBeaconParameters(Adapter); |
| 790 | |
| 791 | _InitHWLed(Adapter); |
| 792 | |
| 793 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK); |
| 794 | _BBTurnOnBlock(Adapter); |
| 795 | /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */ |
| 796 | |
| 797 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY); |
| 798 | invalidate_cam_all23a(Adapter); |
| 799 | |
| 800 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11); |
| 801 | /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */ |
| 802 | PHY_SetTxPowerLevel8723A(Adapter, pHalData->CurrentChannel); |
| 803 | |
| 804 | rtl8723a_InitAntenna_Selection(Adapter); |
| 805 | |
| 806 | /* HW SEQ CTRL */ |
| 807 | /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ |
| 808 | rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF); |
| 809 | |
| 810 | /* */ |
| 811 | /* Disable BAR, suggested by Scott */ |
| 812 | /* 2010.04.09 add by hpfan */ |
| 813 | /* */ |
| 814 | rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff); |
| 815 | |
| 816 | if (pregistrypriv->wifi_spec) |
| 817 | rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0); |
| 818 | |
| 819 | /* Move by Neo for USB SS from above setp */ |
| 820 | _RfPowerSave(Adapter); |
| 821 | |
| 822 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK); |
| 823 | /* 2010/08/26 MH Merge from 8192CE. */ |
| 824 | /* sherry masked that it has been done in _RfPowerSave */ |
| 825 | /* 20110927 */ |
| 826 | /* recovery for 8192cu and 9723Au 20111017 */ |
| 827 | if (pwrctrlpriv->rf_pwrstate == rf_on) { |
| 828 | if (pHalData->bIQKInitialized) { |
| 829 | rtl8723a_phy_iq_calibrate(Adapter, true); |
| 830 | } else { |
| 831 | rtl8723a_phy_iq_calibrate(Adapter, false); |
| 832 | pHalData->bIQKInitialized = true; |
| 833 | } |
| 834 | |
| 835 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK); |
| 836 | rtl8723a_odm_check_tx_power_tracking(Adapter); |
| 837 | |
| 838 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK); |
| 839 | rtl8723a_phy_lc_calibrate(Adapter); |
| 840 | |
| 841 | #ifdef CONFIG_8723AU_BT_COEXIST |
| 842 | rtl8723a_SingleDualAntennaDetection(Adapter); |
| 843 | #endif |
| 844 | } |
| 845 | |
| 846 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21); |
| 847 | /* fixed USB interface interference issue */ |
| 848 | rtw_write8(Adapter, 0xfe40, 0xe0); |
| 849 | rtw_write8(Adapter, 0xfe41, 0x8d); |
| 850 | rtw_write8(Adapter, 0xfe42, 0x80); |
| 851 | rtw_write32(Adapter, 0x20c, 0xfd0320); |
| 852 | /* Solve too many protocol error on USB bus */ |
| 853 | if (!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID)) { |
| 854 | /* 0xE6 = 0x94 */ |
| 855 | rtw_write8(Adapter, 0xFE40, 0xE6); |
| 856 | rtw_write8(Adapter, 0xFE41, 0x94); |
| 857 | rtw_write8(Adapter, 0xFE42, 0x80); |
| 858 | |
| 859 | /* 0xE0 = 0x19 */ |
| 860 | rtw_write8(Adapter, 0xFE40, 0xE0); |
| 861 | rtw_write8(Adapter, 0xFE41, 0x19); |
| 862 | rtw_write8(Adapter, 0xFE42, 0x80); |
| 863 | |
| 864 | /* 0xE5 = 0x91 */ |
| 865 | rtw_write8(Adapter, 0xFE40, 0xE5); |
| 866 | rtw_write8(Adapter, 0xFE41, 0x91); |
| 867 | rtw_write8(Adapter, 0xFE42, 0x80); |
| 868 | |
| 869 | /* 0xE2 = 0x81 */ |
| 870 | rtw_write8(Adapter, 0xFE40, 0xE2); |
| 871 | rtw_write8(Adapter, 0xFE41, 0x81); |
| 872 | rtw_write8(Adapter, 0xFE42, 0x80); |
| 873 | |
| 874 | } |
| 875 | |
| 876 | /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */ |
| 877 | /* _InitPABias(Adapter); */ |
| 878 | |
| 879 | #ifdef CONFIG_8723AU_BT_COEXIST |
| 880 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST); |
| 881 | /* Init BT hw config. */ |
| 882 | BT_InitHwConfig(Adapter); |
| 883 | #endif |
| 884 | |
| 885 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); |
| 886 | rtl8723a_InitHalDm(Adapter); |
| 887 | |
| 888 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31); |
Jes Sorensen | 6883e7c | 2014-04-09 23:20:41 +0200 | [diff] [blame] | 889 | rtl8723a_set_nav_upper(Adapter, WiFiNavUpperUs); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 890 | |
| 891 | /* 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause. */ |
| 892 | if (((rtw_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != 0x83000000)) { |
| 893 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1); |
| 894 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __func__)); |
| 895 | } |
| 896 | |
| 897 | /* ack for xmit mgmt frames. */ |
| 898 | rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12)); |
| 899 | |
| 900 | exit: |
| 901 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); |
| 902 | |
| 903 | DBG_8723A("%s in %dms\n", __func__, |
| 904 | jiffies_to_msecs(jiffies - init_start_time)); |
| 905 | return status; |
| 906 | } |
| 907 | |
| 908 | static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter, |
| 909 | enum rt_rf_power_state eRFPowerState, |
| 910 | int bRegSSPwrLvl) |
| 911 | { |
| 912 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 913 | u8 value8; |
| 914 | u8 bytetmp; |
| 915 | |
| 916 | switch (eRFPowerState) { |
| 917 | case rf_on: |
| 918 | if (bRegSSPwrLvl == 1) { |
| 919 | /* 1. Enable MAC Clock. Can not be enabled now. */ |
| 920 | /* WriteXBYTE(REG_SYS_CLKR+1, |
| 921 | ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */ |
| 922 | |
| 923 | /* 2. Force PWM, Enable SPS18_LDO_Marco_Block */ |
| 924 | rtw_write8(Adapter, REG_SPS0_CTRL, |
| 925 | rtw_read8(Adapter, REG_SPS0_CTRL) | |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 926 | BIT(0) | BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 927 | |
| 928 | /* 3. restore BB, AFE control register. */ |
| 929 | /* RF */ |
| 930 | if (pHalData->rf_type == RF_2T2R) |
| 931 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 932 | 0x380038, 1); |
| 933 | else |
| 934 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 935 | 0x38, 1); |
| 936 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 937 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 938 | |
| 939 | /* AFE */ |
| 940 | if (pHalData->rf_type == RF_2T2R) |
| 941 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 942 | 0x63DB25A0); |
| 943 | else if (pHalData->rf_type == RF_1T1R) |
| 944 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 945 | 0x631B25A0); |
| 946 | |
| 947 | /* 4. issue 3-wire command that RF set to Rx idle |
| 948 | mode. This is used to re-write the RX idle mode. */ |
| 949 | /* We can only prvide a usual value instead and then |
| 950 | HW will modify the value by itself. */ |
| 951 | PHY_SetRFReg(Adapter, RF_PATH_A, 0, |
| 952 | bRFRegOffsetMask, 0x32D95); |
| 953 | if (pHalData->rf_type == RF_2T2R) { |
| 954 | PHY_SetRFReg(Adapter, RF_PATH_B, 0, |
| 955 | bRFRegOffsetMask, 0x32D95); |
| 956 | } |
| 957 | } else { /* Level 2 or others. */ |
| 958 | /* h. AFE_PLL_CTRL 0x28[7:0] = 0x80 |
| 959 | disable AFE PLL */ |
| 960 | rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x81); |
| 961 | |
| 962 | /* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F |
| 963 | gated AFE DIG_CLOCK */ |
| 964 | rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F); |
| 965 | mdelay(1); |
| 966 | |
| 967 | /* 2. Force PWM, Enable SPS18_LDO_Marco_Block */ |
| 968 | rtw_write8(Adapter, REG_SPS0_CTRL, |
| 969 | rtw_read8(Adapter, REG_SPS0_CTRL) | |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 970 | BIT(0) | BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 971 | |
| 972 | /* 3. restore BB, AFE control register. */ |
| 973 | /* RF */ |
| 974 | if (pHalData->rf_type == RF_2T2R) |
| 975 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 976 | 0x380038, 1); |
| 977 | else |
| 978 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 979 | 0x38, 1); |
| 980 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 981 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 982 | |
| 983 | /* AFE */ |
| 984 | if (pHalData->rf_type == RF_2T2R) |
| 985 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, |
| 986 | bMaskDWord, 0x63DB25A0); |
| 987 | else if (pHalData->rf_type == RF_1T1R) |
| 988 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, |
| 989 | bMaskDWord, 0x631B25A0); |
| 990 | |
| 991 | /* 4. issue 3-wire command that RF set to Rx idle |
| 992 | mode. This is used to re-write the RX idle mode. */ |
| 993 | /* We can only prvide a usual value instead and |
| 994 | then HW will modify the value by itself. */ |
| 995 | PHY_SetRFReg(Adapter, RF_PATH_A, 0, |
| 996 | bRFRegOffsetMask, 0x32D95); |
| 997 | if (pHalData->rf_type == RF_2T2R) { |
| 998 | PHY_SetRFReg(Adapter, RF_PATH_B, 0, |
| 999 | bRFRegOffsetMask, 0x32D95); |
| 1000 | } |
| 1001 | |
| 1002 | /* 5. gated MAC Clock */ |
| 1003 | bytetmp = rtw_read8(Adapter, REG_APSD_CTRL); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1004 | rtw_write8(Adapter, REG_APSD_CTRL, bytetmp & ~BIT(6)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1005 | |
| 1006 | mdelay(10); |
| 1007 | |
| 1008 | /* Set BB reset at first */ |
| 1009 | rtw_write8(Adapter, REG_SYS_FUNC_EN, 0x17); /* 0x16 */ |
| 1010 | |
| 1011 | /* Enable TX */ |
| 1012 | rtw_write8(Adapter, REG_TXPAUSE, 0x0); |
| 1013 | } |
| 1014 | break; |
| 1015 | case rf_sleep: |
| 1016 | case rf_off: |
| 1017 | value8 = rtw_read8(Adapter, REG_SPS0_CTRL) ; |
| 1018 | if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1019 | value8 &= ~BIT(0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1020 | else |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1021 | value8 &= ~(BIT(0) | BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1022 | if (bRegSSPwrLvl == 1) { |
| 1023 | RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n")); |
| 1024 | /* Disable RF and BB only for SelectSuspend. */ |
| 1025 | |
| 1026 | /* 1. Set BB/RF to shutdown. */ |
| 1027 | /* (1) Reg878[5:3]= 0 RF rx_code for |
| 1028 | preamble power saving */ |
| 1029 | /* (2)Reg878[21:19]= 0 Turn off RF-B */ |
| 1030 | /* (3) RegC04[7:4]= 0 Turn off all paths |
| 1031 | for packet detection */ |
| 1032 | /* (4) Reg800[1] = 1 enable preamble power |
| 1033 | saving */ |
| 1034 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = |
| 1035 | PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1036 | bMaskDWord); |
| 1037 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = |
| 1038 | PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, |
| 1039 | bMaskDWord); |
| 1040 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = |
| 1041 | PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, |
| 1042 | bMaskDWord); |
| 1043 | if (pHalData->rf_type == RF_2T2R) { |
| 1044 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1045 | 0x380038, 0); |
| 1046 | } else if (pHalData->rf_type == RF_1T1R) { |
| 1047 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1048 | 0x38, 0); |
| 1049 | } |
| 1050 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1051 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1052 | |
| 1053 | /* 2 .AFE control register to power down. bit[30:22] */ |
| 1054 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = |
| 1055 | PHY_QueryBBReg(Adapter, rRx_Wait_CCA, |
| 1056 | bMaskDWord); |
| 1057 | if (pHalData->rf_type == RF_2T2R) |
| 1058 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 1059 | 0x00DB25A0); |
| 1060 | else if (pHalData->rf_type == RF_1T1R) |
| 1061 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 1062 | 0x001B25A0); |
| 1063 | |
| 1064 | /* 3. issue 3-wire command that RF set to power down.*/ |
| 1065 | PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0); |
| 1066 | if (pHalData->rf_type == RF_2T2R) |
| 1067 | PHY_SetRFReg(Adapter, RF_PATH_B, 0, |
| 1068 | bRFRegOffsetMask, 0); |
| 1069 | |
| 1070 | /* 4. Force PFM , disable SPS18_LDO_Marco_Block */ |
| 1071 | rtw_write8(Adapter, REG_SPS0_CTRL, value8); |
| 1072 | } else { /* Level 2 or others. */ |
| 1073 | RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n")); |
| 1074 | { |
| 1075 | u8 eRFPath = RF_PATH_A, value8 = 0; |
| 1076 | rtw_write8(Adapter, REG_TXPAUSE, 0xFF); |
| 1077 | PHY_SetRFReg(Adapter, |
| 1078 | (enum RF_RADIO_PATH)eRFPath, |
| 1079 | 0x0, bMaskByte0, 0x0); |
| 1080 | value8 |= APSDOFF; |
| 1081 | /* 0x40 */ |
| 1082 | rtw_write8(Adapter, REG_APSD_CTRL, value8); |
| 1083 | |
| 1084 | /* After switch APSD, we need to delay |
| 1085 | for stability */ |
| 1086 | mdelay(10); |
| 1087 | |
| 1088 | /* Set BB reset at first */ |
| 1089 | value8 = 0 ; |
| 1090 | value8 |= (FEN_USBD | FEN_USBA | |
| 1091 | FEN_BB_GLB_RSTn); |
| 1092 | /* 0x16 */ |
| 1093 | rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); |
| 1094 | } |
| 1095 | |
| 1096 | /* Disable RF and BB only for SelectSuspend. */ |
| 1097 | |
| 1098 | /* 1. Set BB/RF to shutdown. */ |
| 1099 | /* (1) Reg878[5:3]= 0 RF rx_code for |
| 1100 | preamble power saving */ |
| 1101 | /* (2)Reg878[21:19]= 0 Turn off RF-B */ |
| 1102 | /* (3) RegC04[7:4]= 0 Turn off all paths for |
| 1103 | packet detection */ |
| 1104 | /* (4) Reg800[1] = 1 enable preamble power |
| 1105 | saving */ |
| 1106 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = |
| 1107 | PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1108 | bMaskDWord); |
| 1109 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = |
| 1110 | PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, |
| 1111 | bMaskDWord); |
| 1112 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = |
| 1113 | PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, |
| 1114 | bMaskDWord); |
| 1115 | if (pHalData->rf_type == RF_2T2R) |
| 1116 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1117 | 0x380038, 0); |
| 1118 | else if (pHalData->rf_type == RF_1T1R) |
| 1119 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1120 | 0x38, 0); |
| 1121 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1122 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1123 | |
| 1124 | /* 2 .AFE control register to power down. bit[30:22] */ |
| 1125 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = |
| 1126 | PHY_QueryBBReg(Adapter, rRx_Wait_CCA, |
| 1127 | bMaskDWord); |
| 1128 | if (pHalData->rf_type == RF_2T2R) |
| 1129 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 1130 | 0x00DB25A0); |
| 1131 | else if (pHalData->rf_type == RF_1T1R) |
| 1132 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 1133 | 0x001B25A0); |
| 1134 | |
| 1135 | /* 3. issue 3-wire command that RF set to power down. */ |
| 1136 | PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0); |
| 1137 | if (pHalData->rf_type == RF_2T2R) |
| 1138 | PHY_SetRFReg(Adapter, RF_PATH_B, 0, |
| 1139 | bRFRegOffsetMask, 0); |
| 1140 | |
| 1141 | /* 4. Force PFM , disable SPS18_LDO_Marco_Block */ |
| 1142 | rtw_write8(Adapter, REG_SPS0_CTRL, value8); |
| 1143 | |
| 1144 | /* 2010/10/13 MH/Isaachsu exchange sequence. */ |
| 1145 | /* h. AFE_PLL_CTRL 0x28[7:0] = 0x80 |
| 1146 | disable AFE PLL */ |
| 1147 | rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80); |
| 1148 | mdelay(1); |
| 1149 | |
| 1150 | /* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F |
| 1151 | gated AFE DIG_CLOCK */ |
| 1152 | rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F); |
| 1153 | } |
| 1154 | break; |
| 1155 | default: |
| 1156 | break; |
| 1157 | } |
| 1158 | |
| 1159 | } /* phy_PowerSwitch92CU */ |
| 1160 | |
| 1161 | void _ps_open_RF23a(struct rtw_adapter *padapter) |
| 1162 | { |
| 1163 | /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */ |
| 1164 | phy_SsPwrSwitch92CU(padapter, rf_on, 1); |
| 1165 | } |
| 1166 | |
| 1167 | static void CardDisableRTL8723U(struct rtw_adapter *Adapter) |
| 1168 | { |
| 1169 | u8 u1bTmp; |
| 1170 | |
| 1171 | DBG_8723A("CardDisableRTL8723U\n"); |
| 1172 | /* USB-MF Card Disable Flow */ |
| 1173 | /* 1. Run LPS WL RFOFF flow */ |
| 1174 | HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, |
| 1175 | PWR_INTF_USB_MSK, rtl8723AU_enter_lps_flow); |
| 1176 | |
| 1177 | /* 2. 0x1F[7:0] = 0 turn off RF */ |
| 1178 | rtw_write8(Adapter, REG_RF_CTRL, 0x00); |
| 1179 | |
| 1180 | /* ==== Reset digital sequence ====== */ |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1181 | if ((rtw_read8(Adapter, REG_MCUFWDL) & BIT(7)) && |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1182 | Adapter->bFWReady) /* 8051 RAM code */ |
| 1183 | rtl8723a_FirmwareSelfReset(Adapter); |
| 1184 | |
| 1185 | /* Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */ |
| 1186 | u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1187 | rtw_write8(Adapter, REG_SYS_FUNC_EN+1, u1bTmp & ~BIT(2)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1188 | |
| 1189 | /* g. MCUFWDL 0x80[1:0]= 0 reset MCU ready status */ |
| 1190 | rtw_write8(Adapter, REG_MCUFWDL, 0x00); |
| 1191 | |
| 1192 | /* ==== Reset digital sequence end ====== */ |
| 1193 | /* Card disable power action flow */ |
| 1194 | HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, |
| 1195 | PWR_INTF_USB_MSK, |
| 1196 | rtl8723AU_card_disable_flow); |
| 1197 | |
| 1198 | /* Reset MCU IO Wrapper, added by Roger, 2011.08.30. */ |
| 1199 | u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL + 1); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1200 | rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp & ~BIT(0)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1201 | u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL + 1); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1202 | rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp | BIT(0)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1203 | |
| 1204 | /* 7. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */ |
| 1205 | rtw_write8(Adapter, REG_RSV_CTRL, 0x0e); |
| 1206 | } |
| 1207 | |
Jes Sorensen | c7772697 | 2014-05-16 10:04:16 +0200 | [diff] [blame] | 1208 | static int rtl8723au_hal_deinit(struct rtw_adapter *padapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1209 | { |
| 1210 | DBG_8723A("==> %s\n", __func__); |
| 1211 | |
| 1212 | #ifdef CONFIG_8723AU_BT_COEXIST |
| 1213 | BT_HaltProcess(padapter); |
| 1214 | #endif |
| 1215 | /* 2011/02/18 To Fix RU LNA power leakage problem. We need to |
| 1216 | execute below below in Adapter init and halt sequence. |
| 1217 | According to EEchou's opinion, we can enable the ability for all */ |
| 1218 | /* IC. Accord to johnny's opinion, only RU need the support. */ |
| 1219 | CardDisableRTL8723U(padapter); |
| 1220 | |
| 1221 | return _SUCCESS; |
| 1222 | } |
| 1223 | |
Jes Sorensen | 1aaa376 | 2014-05-16 10:04:05 +0200 | [diff] [blame] | 1224 | int rtl8723au_inirp_init(struct rtw_adapter *Adapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1225 | { |
| 1226 | u8 i; |
| 1227 | struct recv_buf *precvbuf; |
Jes Sorensen | 1aaa376 | 2014-05-16 10:04:05 +0200 | [diff] [blame] | 1228 | int status; |
Jes Sorensen | 28c71e2 | 2014-04-26 18:55:34 +0200 | [diff] [blame] | 1229 | struct _io_ops *io_ops = &Adapter->io_ops; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1230 | struct recv_priv *precvpriv = &Adapter->recvpriv; |
Jes Sorensen | ad899b1 | 2014-05-16 10:04:31 +0200 | [diff] [blame] | 1231 | int (*_read_port)(struct rtw_adapter *padapter, u32 addr, u32 cnt, |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1232 | struct recv_buf *rbuf); |
Jes Sorensen | ad899b1 | 2014-05-16 10:04:31 +0200 | [diff] [blame] | 1233 | int (*_read_interrupt)(struct rtw_adapter *padapter, u32 addr); |
| 1234 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1235 | |
Jes Sorensen | 28c71e2 | 2014-04-26 18:55:34 +0200 | [diff] [blame] | 1236 | _read_port = io_ops->_read_port; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1237 | |
| 1238 | status = _SUCCESS; |
| 1239 | |
| 1240 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("===> usb_inirp_init\n")); |
| 1241 | |
| 1242 | precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR; |
| 1243 | |
| 1244 | /* issue Rx irp to receive data */ |
| 1245 | precvbuf = (struct recv_buf *)precvpriv->precv_buf; |
| 1246 | for (i = 0; i < NR_RECVBUFF; i++) { |
Jes Sorensen | 45c64aa | 2014-04-26 18:55:31 +0200 | [diff] [blame] | 1247 | if (_read_port(Adapter, precvpriv->ff_hwaddr, 0, precvbuf) == |
Jes Sorensen | ad899b1 | 2014-05-16 10:04:31 +0200 | [diff] [blame] | 1248 | _FAIL) { |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1249 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, |
| 1250 | ("usb_rx_init: usb_read_port error\n")); |
| 1251 | status = _FAIL; |
| 1252 | goto exit; |
| 1253 | } |
| 1254 | precvbuf++; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1255 | } |
Jes Sorensen | 28c71e2 | 2014-04-26 18:55:34 +0200 | [diff] [blame] | 1256 | _read_interrupt = io_ops->_read_interrupt; |
Jes Sorensen | ad899b1 | 2014-05-16 10:04:31 +0200 | [diff] [blame] | 1257 | if (_read_interrupt(Adapter, RECV_INT_IN_ADDR) == _FAIL) { |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1258 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, |
| 1259 | ("usb_rx_init: usb_read_interrupt error\n")); |
| 1260 | status = _FAIL; |
| 1261 | } |
| 1262 | pHalData->IntrMask[0] = rtw_read32(Adapter, REG_USB_HIMR); |
| 1263 | MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]); |
| 1264 | pHalData->IntrMask[0] |= UHIMR_C2HCMD|UHIMR_CPWM; |
| 1265 | rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]); |
| 1266 | exit: |
| 1267 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 1268 | ("<=== usb_inirp_init\n")); |
| 1269 | return status; |
| 1270 | } |
| 1271 | |
Jes Sorensen | 1aaa376 | 2014-05-16 10:04:05 +0200 | [diff] [blame] | 1272 | int rtl8723au_inirp_deinit(struct rtw_adapter *Adapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1273 | { |
| 1274 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1275 | |
| 1276 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 1277 | ("\n ===> usb_rx_deinit\n")); |
| 1278 | rtw_read_port_cancel(Adapter); |
| 1279 | pHalData->IntrMask[0] = rtw_read32(Adapter, REG_USB_HIMR); |
| 1280 | MSG_8723A("%s pHalData->IntrMask = 0x%04x\n", __func__, |
| 1281 | pHalData->IntrMask[0]); |
| 1282 | pHalData->IntrMask[0] = 0x0; |
| 1283 | rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]); |
| 1284 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 1285 | ("\n <=== usb_rx_deinit\n")); |
| 1286 | return _SUCCESS; |
| 1287 | } |
| 1288 | |
| 1289 | static void _ReadBoardType(struct rtw_adapter *Adapter, u8 *PROMContent, |
| 1290 | bool AutoloadFail) |
| 1291 | { |
| 1292 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1293 | u8 boardType = BOARD_USB_DONGLE; |
| 1294 | |
| 1295 | if (AutoloadFail) { |
| 1296 | if (IS_8723_SERIES(pHalData->VersionID)) |
| 1297 | pHalData->rf_type = RF_1T1R; |
| 1298 | else |
| 1299 | pHalData->rf_type = RF_2T2R; |
| 1300 | pHalData->BoardType = boardType; |
| 1301 | return; |
| 1302 | } |
| 1303 | |
| 1304 | boardType = PROMContent[EEPROM_NORMAL_BoardType]; |
| 1305 | boardType &= BOARD_TYPE_NORMAL_MASK;/* bit[7:5] */ |
| 1306 | boardType >>= 5; |
| 1307 | |
| 1308 | pHalData->BoardType = boardType; |
| 1309 | MSG_8723A("_ReadBoardType(%x)\n", pHalData->BoardType); |
| 1310 | |
| 1311 | if (boardType == BOARD_USB_High_PA) |
| 1312 | pHalData->ExternalPA = 1; |
| 1313 | } |
| 1314 | |
| 1315 | static void _ReadLEDSetting(struct rtw_adapter *Adapter, u8 *PROMContent, |
| 1316 | bool AutoloadFail) |
| 1317 | { |
| 1318 | struct led_priv *pledpriv = &Adapter->ledpriv; |
| 1319 | |
| 1320 | pledpriv->LedStrategy = HW_LED; |
| 1321 | } |
| 1322 | |
| 1323 | static void Hal_EfuseParsePIDVID_8723AU(struct rtw_adapter *pAdapter, |
| 1324 | u8 *hwinfo, bool AutoLoadFail) |
| 1325 | { |
| 1326 | struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); |
| 1327 | |
| 1328 | if (AutoLoadFail) { |
| 1329 | pHalData->EEPROMVID = 0; |
| 1330 | pHalData->EEPROMPID = 0; |
| 1331 | } else { |
| 1332 | /* VID, PID */ |
| 1333 | pHalData->EEPROMVID = |
| 1334 | le16_to_cpu(*(u16 *)&hwinfo[EEPROM_VID_8723AU]); |
| 1335 | pHalData->EEPROMPID = |
| 1336 | le16_to_cpu(*(u16 *)&hwinfo[EEPROM_PID_8723AU]); |
| 1337 | } |
| 1338 | |
| 1339 | MSG_8723A("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID); |
| 1340 | MSG_8723A("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID); |
| 1341 | } |
| 1342 | |
| 1343 | static void Hal_EfuseParseMACAddr_8723AU(struct rtw_adapter *padapter, |
| 1344 | u8 *hwinfo, bool AutoLoadFail) |
| 1345 | { |
| 1346 | u16 i; |
| 1347 | u8 sMacAddr[ETH_ALEN] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00}; |
| 1348 | struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); |
| 1349 | |
| 1350 | if (AutoLoadFail) { |
| 1351 | for (i = 0; i < 6; i++) |
| 1352 | pEEPROM->mac_addr[i] = sMacAddr[i]; |
| 1353 | } else { |
| 1354 | /* Read Permanent MAC address */ |
| 1355 | memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU], |
| 1356 | ETH_ALEN); |
| 1357 | } |
| 1358 | |
| 1359 | RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, |
| 1360 | ("Hal_EfuseParseMACAddr_8723AU: Permanent Address =%02x:%02x:" |
| 1361 | "%02x:%02x:%02x:%02x\n", |
| 1362 | pEEPROM->mac_addr[0], pEEPROM->mac_addr[1], |
| 1363 | pEEPROM->mac_addr[2], pEEPROM->mac_addr[3], |
| 1364 | pEEPROM->mac_addr[4], pEEPROM->mac_addr[5])); |
| 1365 | } |
| 1366 | |
| 1367 | static void readAdapterInfo(struct rtw_adapter *padapter) |
| 1368 | { |
| 1369 | struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); |
| 1370 | /* struct hal_data_8723a * pHalData = GET_HAL_DATA(padapter); */ |
| 1371 | u8 hwinfo[HWSET_MAX_SIZE]; |
| 1372 | |
| 1373 | Hal_InitPGData(padapter, hwinfo); |
| 1374 | Hal_EfuseParseIDCode(padapter, hwinfo); |
| 1375 | Hal_EfuseParsePIDVID_8723AU(padapter, hwinfo, |
| 1376 | pEEPROM->bautoload_fail_flag); |
| 1377 | Hal_EfuseParseEEPROMVer(padapter, hwinfo, |
| 1378 | pEEPROM->bautoload_fail_flag); |
| 1379 | Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo, |
| 1380 | pEEPROM->bautoload_fail_flag); |
| 1381 | Hal_EfuseParsetxpowerinfo_8723A(padapter, hwinfo, |
| 1382 | pEEPROM->bautoload_fail_flag); |
| 1383 | _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag); |
| 1384 | Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo, |
| 1385 | pEEPROM->bautoload_fail_flag); |
| 1386 | |
| 1387 | rtl8723a_EfuseParseChnlPlan(padapter, hwinfo, |
| 1388 | pEEPROM->bautoload_fail_flag); |
| 1389 | Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo, |
| 1390 | pEEPROM->bautoload_fail_flag); |
| 1391 | _ReadLEDSetting(padapter, hwinfo, pEEPROM->bautoload_fail_flag); |
| 1392 | /* _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */ |
| 1393 | /* _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */ |
| 1394 | Hal_EfuseParseAntennaDiversity(padapter, hwinfo, |
| 1395 | pEEPROM->bautoload_fail_flag); |
| 1396 | |
| 1397 | Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag); |
| 1398 | Hal_EfuseParseCustomerID(padapter, hwinfo, |
| 1399 | pEEPROM->bautoload_fail_flag); |
| 1400 | Hal_EfuseParseRateIndicationOption(padapter, hwinfo, |
| 1401 | pEEPROM->bautoload_fail_flag); |
| 1402 | Hal_EfuseParseXtal_8723A(padapter, hwinfo, |
| 1403 | pEEPROM->bautoload_fail_flag); |
| 1404 | /* */ |
| 1405 | /* The following part initialize some vars by PG info. */ |
| 1406 | /* */ |
| 1407 | Hal_InitChannelPlan23a(padapter); |
| 1408 | |
| 1409 | /* hal_CustomizedBehavior_8723U(Adapter); */ |
| 1410 | |
| 1411 | /* Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; */ |
| 1412 | DBG_8723A("%s(): REPLACEMENT = %x\n", __func__, padapter->bDongle); |
| 1413 | } |
| 1414 | |
| 1415 | static void _ReadPROMContent(struct rtw_adapter *Adapter) |
| 1416 | { |
| 1417 | struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); |
| 1418 | u8 eeValue; |
| 1419 | |
| 1420 | eeValue = rtw_read8(Adapter, REG_9346CR); |
| 1421 | /* To check system boot selection. */ |
| 1422 | pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false; |
| 1423 | pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true; |
| 1424 | |
| 1425 | DBG_8723A("Boot from %s, Autoload %s !\n", |
| 1426 | (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"), |
| 1427 | (pEEPROM->bautoload_fail_flag ? "Fail" : "OK")); |
| 1428 | |
| 1429 | readAdapterInfo(Adapter); |
| 1430 | } |
| 1431 | |
| 1432 | static void _ReadRFType(struct rtw_adapter *Adapter) |
| 1433 | { |
| 1434 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1435 | |
| 1436 | pHalData->rf_chip = RF_6052; |
| 1437 | } |
| 1438 | |
| 1439 | static void _ReadSilmComboMode(struct rtw_adapter *Adapter) |
| 1440 | { |
| 1441 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1442 | |
| 1443 | pHalData->SlimComboDbg = false; /* Default is not debug mode. */ |
| 1444 | } |
| 1445 | |
| 1446 | /* */ |
| 1447 | /* Description: */ |
| 1448 | /* We should set Efuse cell selection to WiFi cell in default. */ |
| 1449 | /* */ |
| 1450 | /* Assumption: */ |
| 1451 | /* PASSIVE_LEVEL */ |
| 1452 | /* */ |
| 1453 | /* Added by Roger, 2010.11.23. */ |
| 1454 | /* */ |
| 1455 | static void hal_EfuseCellSel(struct rtw_adapter *Adapter) |
| 1456 | { |
| 1457 | u32 value32; |
| 1458 | |
| 1459 | value32 = rtw_read32(Adapter, EFUSE_TEST); |
| 1460 | value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); |
| 1461 | rtw_write32(Adapter, EFUSE_TEST, value32); |
| 1462 | } |
| 1463 | |
Jes Sorensen | 1f4746f | 2014-05-16 10:03:58 +0200 | [diff] [blame] | 1464 | void rtl8723a_read_adapter_info(struct rtw_adapter *Adapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1465 | { |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1466 | unsigned long start = jiffies; |
| 1467 | |
Jes Sorensen | 1f4746f | 2014-05-16 10:03:58 +0200 | [diff] [blame] | 1468 | /* Read EEPROM size before call any EEPROM function */ |
| 1469 | Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter); |
| 1470 | |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1471 | MSG_8723A("====> _ReadAdapterInfo8723AU\n"); |
| 1472 | |
| 1473 | hal_EfuseCellSel(Adapter); |
| 1474 | |
| 1475 | _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */ |
| 1476 | _ReadPROMContent(Adapter); |
| 1477 | |
| 1478 | /* 2010/10/25 MH THe function must be called after |
| 1479 | borad_type & IC-Version recognize. */ |
| 1480 | _ReadSilmComboMode(Adapter); |
| 1481 | |
| 1482 | /* MSG_8723A("%s()(done), rf_chip = 0x%x, rf_type = 0x%x\n", |
| 1483 | __func__, pHalData->rf_chip, pHalData->rf_type); */ |
| 1484 | |
| 1485 | MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n", |
| 1486 | jiffies_to_msecs(jiffies - start)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1487 | } |
| 1488 | |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1489 | /* */ |
| 1490 | /* Description: */ |
| 1491 | /* Query setting of specified variable. */ |
| 1492 | /* */ |
Jes Sorensen | 39f1a8e | 2014-05-16 10:04:20 +0200 | [diff] [blame] | 1493 | int GetHalDefVar8192CUsb(struct rtw_adapter *Adapter, |
| 1494 | enum hal_def_variable eVariable, void *pValue) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1495 | { |
Jes Sorensen | 39f1a8e | 2014-05-16 10:04:20 +0200 | [diff] [blame] | 1496 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1497 | int bResult = _SUCCESS; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1498 | |
| 1499 | switch (eVariable) { |
| 1500 | case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: |
| 1501 | *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB; |
| 1502 | break; |
| 1503 | case HAL_DEF_IS_SUPPORT_ANT_DIV: |
| 1504 | break; |
| 1505 | case HAL_DEF_CURRENT_ANTENNA: |
| 1506 | break; |
| 1507 | case HAL_DEF_DRVINFO_SZ: |
| 1508 | *((u32 *)pValue) = DRVINFO_SZ; |
| 1509 | break; |
| 1510 | case HAL_DEF_MAX_RECVBUF_SZ: |
| 1511 | *((u32 *)pValue) = MAX_RECVBUF_SZ; |
| 1512 | break; |
| 1513 | case HAL_DEF_RX_PACKET_OFFSET: |
| 1514 | *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ; |
| 1515 | break; |
| 1516 | case HAL_DEF_DBG_DUMP_RXPKT: |
| 1517 | *((u8 *)pValue) = pHalData->bDumpRxPkt; |
| 1518 | break; |
| 1519 | case HAL_DEF_DBG_DM_FUNC: |
| 1520 | *((u32 *)pValue) = pHalData->odmpriv.SupportAbility; |
| 1521 | break; |
| 1522 | case HW_VAR_MAX_RX_AMPDU_FACTOR: |
| 1523 | *((u32 *)pValue) = IEEE80211_HT_MAX_AMPDU_64K; |
| 1524 | break; |
| 1525 | case HW_DEF_ODM_DBG_FLAG: |
| 1526 | { |
| 1527 | struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; |
| 1528 | printk("pDM_Odm->DebugComponents = 0x%llx\n", |
| 1529 | pDM_Odm->DebugComponents); |
| 1530 | } |
| 1531 | break; |
| 1532 | default: |
| 1533 | /* RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): " |
| 1534 | "Unkown variable: %d!\n", eVariable)); */ |
| 1535 | bResult = _FAIL; |
| 1536 | break; |
| 1537 | } |
| 1538 | |
| 1539 | return bResult; |
| 1540 | } |
| 1541 | |
Jes Sorensen | ac4cbc6 | 2014-05-16 10:04:19 +0200 | [diff] [blame] | 1542 | void rtl8723a_update_ramask(struct rtw_adapter *padapter, |
| 1543 | u32 mac_id, u8 rssi_level) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1544 | { |
| 1545 | u8 init_rate = 0; |
| 1546 | u8 networkType, raid; |
| 1547 | u32 mask, rate_bitmap; |
| 1548 | u8 shortGIrate = false; |
| 1549 | int supportRateNum = 0; |
| 1550 | struct sta_info *psta; |
| 1551 | struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); |
| 1552 | struct dm_priv *pdmpriv = &pHalData->dmpriv; |
| 1553 | struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; |
| 1554 | struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; |
| 1555 | struct wlan_bssid_ex *cur_network = &pmlmeinfo->network; |
| 1556 | |
| 1557 | if (mac_id >= NUM_STA) /* CAM_SIZE */ |
| 1558 | return; |
| 1559 | |
| 1560 | psta = pmlmeinfo->FW_sta_info[mac_id].psta; |
| 1561 | if (psta == NULL) |
| 1562 | return; |
| 1563 | |
| 1564 | switch (mac_id) { |
| 1565 | case 0:/* for infra mode */ |
| 1566 | supportRateNum = |
| 1567 | rtw_get_rateset_len23a(cur_network->SupportedRates); |
| 1568 | networkType = judge_network_type23a(padapter, |
| 1569 | cur_network->SupportedRates, |
| 1570 | supportRateNum) & 0xf; |
| 1571 | /* pmlmeext->cur_wireless_mode = networkType; */ |
| 1572 | raid = networktype_to_raid23a(networkType); |
| 1573 | |
| 1574 | mask = update_supported_rate23a(cur_network->SupportedRates, |
| 1575 | supportRateNum); |
| 1576 | mask |= (pmlmeinfo->HT_enable) ? |
| 1577 | update_MSC_rate23a(&pmlmeinfo->HT_caps) : 0; |
| 1578 | |
| 1579 | if (support_short_GI23a(padapter, &pmlmeinfo->HT_caps)) |
| 1580 | shortGIrate = true; |
| 1581 | break; |
| 1582 | |
| 1583 | case 1:/* for broadcast/multicast */ |
| 1584 | supportRateNum = rtw_get_rateset_len23a( |
| 1585 | pmlmeinfo->FW_sta_info[mac_id].SupportedRates); |
| 1586 | if (pmlmeext->cur_wireless_mode & WIRELESS_11B) |
| 1587 | networkType = WIRELESS_11B; |
| 1588 | else |
| 1589 | networkType = WIRELESS_11G; |
| 1590 | raid = networktype_to_raid23a(networkType); |
| 1591 | |
| 1592 | mask = update_basic_rate23a(cur_network->SupportedRates, |
| 1593 | supportRateNum); |
| 1594 | break; |
| 1595 | |
| 1596 | default: /* for each sta in IBSS */ |
| 1597 | supportRateNum = rtw_get_rateset_len23a( |
| 1598 | pmlmeinfo->FW_sta_info[mac_id].SupportedRates); |
| 1599 | networkType = judge_network_type23a(padapter, |
| 1600 | pmlmeinfo->FW_sta_info[mac_id].SupportedRates, |
| 1601 | supportRateNum) & 0xf; |
| 1602 | /* pmlmeext->cur_wireless_mode = networkType; */ |
| 1603 | raid = networktype_to_raid23a(networkType); |
| 1604 | |
| 1605 | mask = update_supported_rate23a(cur_network->SupportedRates, |
| 1606 | supportRateNum); |
| 1607 | |
| 1608 | /* todo: support HT in IBSS */ |
| 1609 | break; |
| 1610 | } |
| 1611 | |
| 1612 | /* mask &= 0x0fffffff; */ |
| 1613 | rate_bitmap = 0x0fffffff; |
| 1614 | rate_bitmap = ODM_Get_Rate_Bitmap23a(&pHalData->odmpriv, |
| 1615 | mac_id, mask, rssi_level); |
| 1616 | printk(KERN_DEBUG "%s => mac_id:%d, networkType:0x%02x, " |
| 1617 | "mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n", |
| 1618 | __func__, |
| 1619 | mac_id, networkType, mask, rssi_level, rate_bitmap); |
| 1620 | |
| 1621 | mask &= rate_bitmap; |
| 1622 | mask |= ((raid<<28)&0xf0000000); |
| 1623 | |
| 1624 | init_rate = get_highest_rate_idx23a(mask)&0x3f; |
| 1625 | |
| 1626 | if (pHalData->fw_ractrl == true) { |
| 1627 | u8 arg = 0; |
| 1628 | |
| 1629 | /* arg = (cam_idx-4)&0x1f;MACID */ |
| 1630 | arg = mac_id&0x1f;/* MACID */ |
| 1631 | |
| 1632 | arg |= BIT(7); |
| 1633 | |
| 1634 | if (shortGIrate == true) |
| 1635 | arg |= BIT(5); |
| 1636 | |
| 1637 | DBG_8723A("update raid entry, mask = 0x%x, arg = 0x%x\n", |
| 1638 | mask, arg); |
| 1639 | |
| 1640 | rtl8723a_set_raid_cmd(padapter, mask, arg); |
| 1641 | } else { |
| 1642 | if (shortGIrate == true) |
| 1643 | init_rate |= BIT(6); |
| 1644 | |
| 1645 | rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate); |
| 1646 | } |
| 1647 | |
| 1648 | /* set ra_id */ |
| 1649 | psta->raid = raid; |
| 1650 | psta->init_rate = init_rate; |
| 1651 | |
| 1652 | /* set correct initial date rate for each mac_id */ |
| 1653 | pdmpriv->INIDATA_RATE[mac_id] = init_rate; |
| 1654 | } |
| 1655 | |
Jes Sorensen | c7772697 | 2014-05-16 10:04:16 +0200 | [diff] [blame] | 1656 | int rtw_hal_init23a(struct rtw_adapter *padapter) |
| 1657 | { |
| 1658 | int status; |
| 1659 | |
| 1660 | padapter->hw_init_completed = false; |
| 1661 | |
| 1662 | status = rtl8723au_hal_init(padapter); |
| 1663 | |
| 1664 | if (status == _SUCCESS) { |
| 1665 | padapter->hw_init_completed = true; |
| 1666 | |
| 1667 | if (padapter->registrypriv.notch_filter == 1) |
| 1668 | rtl8723a_notch_filter(padapter, 1); |
| 1669 | } else { |
| 1670 | padapter->hw_init_completed = false; |
| 1671 | DBG_8723A("rtw_hal_init23a: hal__init fail\n"); |
| 1672 | } |
| 1673 | |
| 1674 | RT_TRACE(_module_hal_init_c_, _drv_err_, |
| 1675 | ("-rtl871x_hal_init:status = 0x%x\n", status)); |
| 1676 | |
| 1677 | return status; |
| 1678 | } |
| 1679 | |
| 1680 | int rtw_hal_deinit23a(struct rtw_adapter *padapter) |
| 1681 | { |
| 1682 | int status; |
| 1683 | |
| 1684 | status = rtl8723au_hal_deinit(padapter); |
| 1685 | |
| 1686 | if (status == _SUCCESS) |
| 1687 | padapter->hw_init_completed = false; |
| 1688 | else |
| 1689 | DBG_8723A("\n rtw_hal_deinit23a: hal_init fail\n"); |
| 1690 | return status; |
| 1691 | } |