| Joe.C | 1ccd653 | 2014-11-11 15:53:41 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 MediaTek Inc. |
| 3 | * Author: Joe.C <yingjoe.chen@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 17 | #include "skeleton64.dtsi" |
| 18 | |
| 19 | / { |
| 20 | compatible = "mediatek,mt8127"; |
| 21 | interrupt-parent = <&gic>; |
| 22 | |
| 23 | cpus { |
| 24 | #address-cells = <1>; |
| 25 | #size-cells = <0>; |
| 26 | |
| 27 | cpu@0 { |
| 28 | device_type = "cpu"; |
| 29 | compatible = "arm,cortex-a7"; |
| 30 | reg = <0x0>; |
| 31 | }; |
| 32 | cpu@1 { |
| 33 | device_type = "cpu"; |
| 34 | compatible = "arm,cortex-a7"; |
| 35 | reg = <0x1>; |
| 36 | }; |
| 37 | cpu@2 { |
| 38 | device_type = "cpu"; |
| 39 | compatible = "arm,cortex-a7"; |
| 40 | reg = <0x2>; |
| 41 | }; |
| 42 | cpu@3 { |
| 43 | device_type = "cpu"; |
| 44 | compatible = "arm,cortex-a7"; |
| 45 | reg = <0x3>; |
| 46 | }; |
| 47 | |
| 48 | }; |
| 49 | |
| 50 | clocks { |
| 51 | #address-cells = <2>; |
| 52 | #size-cells = <2>; |
| 53 | compatible = "simple-bus"; |
| 54 | ranges; |
| 55 | |
| 56 | system_clk: dummy13m { |
| 57 | compatible = "fixed-clock"; |
| 58 | clock-frequency = <13000000>; |
| 59 | #clock-cells = <0>; |
| 60 | }; |
| 61 | |
| 62 | rtc_clk: dummy32k { |
| 63 | compatible = "fixed-clock"; |
| 64 | clock-frequency = <32000>; |
| 65 | #clock-cells = <0>; |
| 66 | }; |
| 67 | }; |
| 68 | |
| 69 | soc { |
| 70 | #address-cells = <2>; |
| 71 | #size-cells = <2>; |
| 72 | compatible = "simple-bus"; |
| 73 | ranges; |
| 74 | |
| 75 | timer: timer@10008000 { |
| 76 | compatible = "mediatek,mt8127-timer", |
| 77 | "mediatek,mt6577-timer"; |
| 78 | reg = <0 0x10008000 0 0x80>; |
| 79 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| 80 | clocks = <&system_clk>, <&rtc_clk>; |
| 81 | clock-names = "system-clk", "rtc-clk"; |
| 82 | }; |
| 83 | |
| 84 | gic: interrupt-controller@10211000 { |
| 85 | compatible = "arm,cortex-a7-gic"; |
| 86 | interrupt-controller; |
| 87 | #interrupt-cells = <3>; |
| 88 | reg = <0 0x10211000 0 0x1000>, |
| 89 | <0 0x10212000 0 0x1000>, |
| 90 | <0 0x10214000 0 0x2000>, |
| 91 | <0 0x10216000 0 0x2000>; |
| 92 | }; |
| 93 | }; |
| 94 | }; |