Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3 clock data |
| 3 | * |
Paul Walmsley | 8f97437 | 2012-05-07 23:55:31 -0600 | [diff] [blame] | 4 | * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc. |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 5 | * Copyright (C) 2007-2011 Nokia Corporation |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * Written by Paul Walmsley |
| 8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
| 9 | * DPLL bypass clock support added by Roman Tereshonkov |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Virtual clocks are introduced as convenient tools. |
| 15 | * They are sources for other clocks and not supposed |
| 16 | * to be requested from drivers directly. |
| 17 | */ |
| 18 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 19 | #include <linux/kernel.h> |
| 20 | #include <linux/clk.h> |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 21 | #include <linux/list.h> |
Rob Herring | 6f6f6a7 | 2012-03-10 10:30:31 -0600 | [diff] [blame] | 22 | #include <linux/io.h> |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 23 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 24 | #include "soc.h" |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 25 | #include "iomap.h" |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 26 | #include "clock.h" |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 27 | #include "clock3xxx.h" |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 28 | #include "clock34xx.h" |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 29 | #include "clock36xx.h" |
| 30 | #include "clock3517.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 31 | #include "cm2xxx_3xxx.h" |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 32 | #include "cm-regbits-34xx.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 33 | #include "prm2xxx_3xxx.h" |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 34 | #include "prm-regbits-34xx.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 35 | #include "control.h" |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 36 | |
| 37 | /* |
| 38 | * clocks |
| 39 | */ |
| 40 | |
| 41 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR |
| 42 | |
| 43 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 44 | #define OMAP3_MAX_DPLL_MULT 2047 |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 45 | #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 46 | #define OMAP3_MAX_DPLL_DIV 128 |
| 47 | |
| 48 | /* |
| 49 | * DPLL1 supplies clock to the MPU. |
| 50 | * DPLL2 supplies clock to the IVA2. |
| 51 | * DPLL3 supplies CORE domain clocks. |
| 52 | * DPLL4 supplies peripheral clocks. |
| 53 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). |
| 54 | */ |
| 55 | |
| 56 | /* Forward declarations for DPLL bypass clocks */ |
| 57 | static struct clk dpll1_fck; |
| 58 | static struct clk dpll2_fck; |
| 59 | |
| 60 | /* PRM CLOCKS */ |
| 61 | |
| 62 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ |
| 63 | static struct clk omap_32k_fck = { |
| 64 | .name = "omap_32k_fck", |
| 65 | .ops = &clkops_null, |
| 66 | .rate = 32768, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | static struct clk secure_32k_fck = { |
| 70 | .name = "secure_32k_fck", |
| 71 | .ops = &clkops_null, |
| 72 | .rate = 32768, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | /* Virtual source clocks for osc_sys_ck */ |
| 76 | static struct clk virt_12m_ck = { |
| 77 | .name = "virt_12m_ck", |
| 78 | .ops = &clkops_null, |
| 79 | .rate = 12000000, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 80 | }; |
| 81 | |
| 82 | static struct clk virt_13m_ck = { |
| 83 | .name = "virt_13m_ck", |
| 84 | .ops = &clkops_null, |
| 85 | .rate = 13000000, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | static struct clk virt_16_8m_ck = { |
| 89 | .name = "virt_16_8m_ck", |
| 90 | .ops = &clkops_null, |
| 91 | .rate = 16800000, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 92 | }; |
| 93 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 94 | static struct clk virt_38_4m_ck = { |
| 95 | .name = "virt_38_4m_ck", |
| 96 | .ops = &clkops_null, |
| 97 | .rate = 38400000, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 98 | }; |
| 99 | |
| 100 | static const struct clksel_rate osc_sys_12m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 101 | { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 102 | { .div = 0 } |
| 103 | }; |
| 104 | |
| 105 | static const struct clksel_rate osc_sys_13m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 106 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 107 | { .div = 0 } |
| 108 | }; |
| 109 | |
| 110 | static const struct clksel_rate osc_sys_16_8m_rates[] = { |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 111 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 112 | { .div = 0 } |
| 113 | }; |
| 114 | |
| 115 | static const struct clksel_rate osc_sys_19_2m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 116 | { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 117 | { .div = 0 } |
| 118 | }; |
| 119 | |
| 120 | static const struct clksel_rate osc_sys_26m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 121 | { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 122 | { .div = 0 } |
| 123 | }; |
| 124 | |
| 125 | static const struct clksel_rate osc_sys_38_4m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 126 | { .div = 1, .val = 4, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 127 | { .div = 0 } |
| 128 | }; |
| 129 | |
| 130 | static const struct clksel osc_sys_clksel[] = { |
| 131 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, |
| 132 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, |
| 133 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, |
Paul Walmsley | 571efa0 | 2012-05-29 15:26:40 +0530 | [diff] [blame] | 134 | { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates }, |
| 135 | { .parent = &virt_26000000_ck, .rates = osc_sys_26m_rates }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 136 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, |
| 137 | { .parent = NULL }, |
| 138 | }; |
| 139 | |
| 140 | /* Oscillator clock */ |
| 141 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ |
| 142 | static struct clk osc_sys_ck = { |
| 143 | .name = "osc_sys_ck", |
| 144 | .ops = &clkops_null, |
| 145 | .init = &omap2_init_clksel_parent, |
| 146 | .clksel_reg = OMAP3430_PRM_CLKSEL, |
| 147 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
| 148 | .clksel = osc_sys_clksel, |
| 149 | /* REVISIT: deal with autoextclkmode? */ |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 150 | .recalc = &omap2_clksel_recalc, |
| 151 | }; |
| 152 | |
| 153 | static const struct clksel_rate div2_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 154 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 155 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 156 | { .div = 0 } |
| 157 | }; |
| 158 | |
| 159 | static const struct clksel sys_clksel[] = { |
| 160 | { .parent = &osc_sys_ck, .rates = div2_rates }, |
| 161 | { .parent = NULL } |
| 162 | }; |
| 163 | |
| 164 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ |
| 165 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ |
| 166 | static struct clk sys_ck = { |
| 167 | .name = "sys_ck", |
| 168 | .ops = &clkops_null, |
| 169 | .parent = &osc_sys_ck, |
| 170 | .init = &omap2_init_clksel_parent, |
| 171 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, |
| 172 | .clksel_mask = OMAP_SYSCLKDIV_MASK, |
| 173 | .clksel = sys_clksel, |
| 174 | .recalc = &omap2_clksel_recalc, |
| 175 | }; |
| 176 | |
| 177 | static struct clk sys_altclk = { |
| 178 | .name = "sys_altclk", |
| 179 | .ops = &clkops_null, |
| 180 | }; |
| 181 | |
| 182 | /* Optional external clock input for some McBSPs */ |
| 183 | static struct clk mcbsp_clks = { |
| 184 | .name = "mcbsp_clks", |
| 185 | .ops = &clkops_null, |
| 186 | }; |
| 187 | |
| 188 | /* PRM EXTERNAL CLOCK OUTPUT */ |
| 189 | |
| 190 | static struct clk sys_clkout1 = { |
| 191 | .name = "sys_clkout1", |
| 192 | .ops = &clkops_omap2_dflt, |
| 193 | .parent = &osc_sys_ck, |
| 194 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, |
| 195 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, |
| 196 | .recalc = &followparent_recalc, |
| 197 | }; |
| 198 | |
| 199 | /* DPLLS */ |
| 200 | |
| 201 | /* CM CLOCKS */ |
| 202 | |
| 203 | static const struct clksel_rate div16_dpll_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 204 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 205 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
| 206 | { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, |
| 207 | { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
| 208 | { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, |
| 209 | { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, |
| 210 | { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, |
| 211 | { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, |
| 212 | { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, |
| 213 | { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, |
| 214 | { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, |
| 215 | { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, |
| 216 | { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, |
| 217 | { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, |
| 218 | { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, |
| 219 | { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 220 | { .div = 0 } |
| 221 | }; |
| 222 | |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 223 | static const struct clksel_rate dpll4_rates[] = { |
| 224 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 225 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
| 226 | { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, |
| 227 | { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
| 228 | { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, |
| 229 | { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, |
| 230 | { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, |
| 231 | { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, |
| 232 | { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, |
| 233 | { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, |
| 234 | { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, |
| 235 | { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, |
| 236 | { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, |
| 237 | { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, |
| 238 | { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, |
| 239 | { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 240 | { .div = 17, .val = 17, .flags = RATE_IN_36XX }, |
| 241 | { .div = 18, .val = 18, .flags = RATE_IN_36XX }, |
| 242 | { .div = 19, .val = 19, .flags = RATE_IN_36XX }, |
| 243 | { .div = 20, .val = 20, .flags = RATE_IN_36XX }, |
| 244 | { .div = 21, .val = 21, .flags = RATE_IN_36XX }, |
| 245 | { .div = 22, .val = 22, .flags = RATE_IN_36XX }, |
| 246 | { .div = 23, .val = 23, .flags = RATE_IN_36XX }, |
| 247 | { .div = 24, .val = 24, .flags = RATE_IN_36XX }, |
| 248 | { .div = 25, .val = 25, .flags = RATE_IN_36XX }, |
| 249 | { .div = 26, .val = 26, .flags = RATE_IN_36XX }, |
| 250 | { .div = 27, .val = 27, .flags = RATE_IN_36XX }, |
| 251 | { .div = 28, .val = 28, .flags = RATE_IN_36XX }, |
| 252 | { .div = 29, .val = 29, .flags = RATE_IN_36XX }, |
| 253 | { .div = 30, .val = 30, .flags = RATE_IN_36XX }, |
| 254 | { .div = 31, .val = 31, .flags = RATE_IN_36XX }, |
| 255 | { .div = 32, .val = 32, .flags = RATE_IN_36XX }, |
| 256 | { .div = 0 } |
| 257 | }; |
| 258 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 259 | /* DPLL1 */ |
| 260 | /* MPU clock source */ |
| 261 | /* Type: DPLL */ |
| 262 | static struct dpll_data dpll1_dd = { |
| 263 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 264 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, |
| 265 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, |
| 266 | .clk_bypass = &dpll1_fck, |
| 267 | .clk_ref = &sys_ck, |
| 268 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, |
| 269 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
| 270 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, |
| 271 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 272 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, |
| 273 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, |
| 274 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, |
| 275 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 276 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, |
| 277 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 278 | .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 279 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 280 | .min_divider = 1, |
| 281 | .max_divider = OMAP3_MAX_DPLL_DIV, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 282 | }; |
| 283 | |
| 284 | static struct clk dpll1_ck = { |
| 285 | .name = "dpll1_ck", |
Rajendra Nayak | 5a2926b | 2011-02-25 15:48:37 -0700 | [diff] [blame] | 286 | .ops = &clkops_omap3_noncore_dpll_ops, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 287 | .parent = &sys_ck, |
| 288 | .dpll_data = &dpll1_dd, |
| 289 | .round_rate = &omap2_dpll_round_rate, |
| 290 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 291 | .clkdm_name = "dpll1_clkdm", |
| 292 | .recalc = &omap3_dpll_recalc, |
| 293 | }; |
| 294 | |
| 295 | /* |
| 296 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 297 | * DPLL isn't bypassed. |
| 298 | */ |
| 299 | static struct clk dpll1_x2_ck = { |
| 300 | .name = "dpll1_x2_ck", |
| 301 | .ops = &clkops_null, |
| 302 | .parent = &dpll1_ck, |
| 303 | .clkdm_name = "dpll1_clkdm", |
| 304 | .recalc = &omap3_clkoutx2_recalc, |
| 305 | }; |
| 306 | |
| 307 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ |
| 308 | static const struct clksel div16_dpll1_x2m2_clksel[] = { |
| 309 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, |
| 310 | { .parent = NULL } |
| 311 | }; |
| 312 | |
| 313 | /* |
| 314 | * Does not exist in the TRM - needed to separate the M2 divider from |
| 315 | * bypass selection in mpu_ck |
| 316 | */ |
| 317 | static struct clk dpll1_x2m2_ck = { |
| 318 | .name = "dpll1_x2m2_ck", |
| 319 | .ops = &clkops_null, |
| 320 | .parent = &dpll1_x2_ck, |
| 321 | .init = &omap2_init_clksel_parent, |
| 322 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), |
| 323 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, |
| 324 | .clksel = div16_dpll1_x2m2_clksel, |
| 325 | .clkdm_name = "dpll1_clkdm", |
| 326 | .recalc = &omap2_clksel_recalc, |
| 327 | }; |
| 328 | |
| 329 | /* DPLL2 */ |
| 330 | /* IVA2 clock source */ |
| 331 | /* Type: DPLL */ |
| 332 | |
| 333 | static struct dpll_data dpll2_dd = { |
| 334 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 335 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, |
| 336 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, |
| 337 | .clk_bypass = &dpll2_fck, |
| 338 | .clk_ref = &sys_ck, |
| 339 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, |
| 340 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
| 341 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, |
| 342 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
| 343 | (1 << DPLL_LOW_POWER_BYPASS), |
| 344 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, |
| 345 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, |
| 346 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, |
| 347 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 348 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, |
| 349 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), |
| 350 | .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, |
| 351 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 352 | .min_divider = 1, |
| 353 | .max_divider = OMAP3_MAX_DPLL_DIV, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 354 | }; |
| 355 | |
| 356 | static struct clk dpll2_ck = { |
| 357 | .name = "dpll2_ck", |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 358 | .ops = &clkops_omap3_noncore_dpll_ops, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 359 | .parent = &sys_ck, |
| 360 | .dpll_data = &dpll2_dd, |
| 361 | .round_rate = &omap2_dpll_round_rate, |
| 362 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 363 | .clkdm_name = "dpll2_clkdm", |
| 364 | .recalc = &omap3_dpll_recalc, |
| 365 | }; |
| 366 | |
| 367 | static const struct clksel div16_dpll2_m2x2_clksel[] = { |
| 368 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, |
| 369 | { .parent = NULL } |
| 370 | }; |
| 371 | |
| 372 | /* |
| 373 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT |
| 374 | * or CLKOUTX2. CLKOUT seems most plausible. |
| 375 | */ |
| 376 | static struct clk dpll2_m2_ck = { |
| 377 | .name = "dpll2_m2_ck", |
| 378 | .ops = &clkops_null, |
| 379 | .parent = &dpll2_ck, |
| 380 | .init = &omap2_init_clksel_parent, |
| 381 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 382 | OMAP3430_CM_CLKSEL2_PLL), |
| 383 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, |
| 384 | .clksel = div16_dpll2_m2x2_clksel, |
| 385 | .clkdm_name = "dpll2_clkdm", |
| 386 | .recalc = &omap2_clksel_recalc, |
| 387 | }; |
| 388 | |
| 389 | /* |
| 390 | * DPLL3 |
| 391 | * Source clock for all interfaces and for some device fclks |
| 392 | * REVISIT: Also supports fast relock bypass - not included below |
| 393 | */ |
| 394 | static struct dpll_data dpll3_dd = { |
| 395 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 396 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, |
| 397 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, |
| 398 | .clk_bypass = &sys_ck, |
| 399 | .clk_ref = &sys_ck, |
| 400 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, |
| 401 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 402 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, |
| 403 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, |
| 404 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, |
| 405 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, |
| 406 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 407 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, |
| 408 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 409 | .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, |
| 410 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 411 | .min_divider = 1, |
| 412 | .max_divider = OMAP3_MAX_DPLL_DIV, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 413 | }; |
| 414 | |
| 415 | static struct clk dpll3_ck = { |
| 416 | .name = "dpll3_ck", |
Rajendra Nayak | 6c6f5a7 | 2011-02-25 15:49:00 -0700 | [diff] [blame] | 417 | .ops = &clkops_omap3_core_dpll_ops, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 418 | .parent = &sys_ck, |
| 419 | .dpll_data = &dpll3_dd, |
| 420 | .round_rate = &omap2_dpll_round_rate, |
| 421 | .clkdm_name = "dpll3_clkdm", |
| 422 | .recalc = &omap3_dpll_recalc, |
| 423 | }; |
| 424 | |
| 425 | /* |
| 426 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 427 | * DPLL isn't bypassed |
| 428 | */ |
| 429 | static struct clk dpll3_x2_ck = { |
| 430 | .name = "dpll3_x2_ck", |
| 431 | .ops = &clkops_null, |
| 432 | .parent = &dpll3_ck, |
| 433 | .clkdm_name = "dpll3_clkdm", |
| 434 | .recalc = &omap3_clkoutx2_recalc, |
| 435 | }; |
| 436 | |
| 437 | static const struct clksel_rate div31_dpll3_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 438 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 439 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 440 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 441 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 442 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 443 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 444 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 445 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 446 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 447 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 448 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 449 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 450 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 451 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 452 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 453 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 454 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 455 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 456 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 457 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 458 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 459 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 460 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 461 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 462 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 463 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 464 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 465 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 466 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 467 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 468 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 469 | { .div = 0 }, |
| 470 | }; |
| 471 | |
| 472 | static const struct clksel div31_dpll3m2_clksel[] = { |
| 473 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, |
| 474 | { .parent = NULL } |
| 475 | }; |
| 476 | |
| 477 | /* DPLL3 output M2 - primary control point for CORE speed */ |
| 478 | static struct clk dpll3_m2_ck = { |
| 479 | .name = "dpll3_m2_ck", |
| 480 | .ops = &clkops_null, |
| 481 | .parent = &dpll3_ck, |
| 482 | .init = &omap2_init_clksel_parent, |
| 483 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 484 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, |
| 485 | .clksel = div31_dpll3m2_clksel, |
| 486 | .clkdm_name = "dpll3_clkdm", |
| 487 | .round_rate = &omap2_clksel_round_rate, |
| 488 | .set_rate = &omap3_core_dpll_m2_set_rate, |
| 489 | .recalc = &omap2_clksel_recalc, |
| 490 | }; |
| 491 | |
| 492 | static struct clk core_ck = { |
| 493 | .name = "core_ck", |
| 494 | .ops = &clkops_null, |
| 495 | .parent = &dpll3_m2_ck, |
| 496 | .recalc = &followparent_recalc, |
| 497 | }; |
| 498 | |
| 499 | static struct clk dpll3_m2x2_ck = { |
| 500 | .name = "dpll3_m2x2_ck", |
| 501 | .ops = &clkops_null, |
| 502 | .parent = &dpll3_m2_ck, |
| 503 | .clkdm_name = "dpll3_clkdm", |
| 504 | .recalc = &omap3_clkoutx2_recalc, |
| 505 | }; |
| 506 | |
| 507 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 508 | static const struct clksel div16_dpll3_clksel[] = { |
| 509 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, |
| 510 | { .parent = NULL } |
| 511 | }; |
| 512 | |
| 513 | /* This virtual clock is the source for dpll3_m3x2_ck */ |
| 514 | static struct clk dpll3_m3_ck = { |
| 515 | .name = "dpll3_m3_ck", |
| 516 | .ops = &clkops_null, |
| 517 | .parent = &dpll3_ck, |
| 518 | .init = &omap2_init_clksel_parent, |
| 519 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 520 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, |
| 521 | .clksel = div16_dpll3_clksel, |
| 522 | .clkdm_name = "dpll3_clkdm", |
| 523 | .recalc = &omap2_clksel_recalc, |
| 524 | }; |
| 525 | |
| 526 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 527 | static struct clk dpll3_m3x2_ck = { |
| 528 | .name = "dpll3_m3x2_ck", |
| 529 | .ops = &clkops_omap2_dflt_wait, |
| 530 | .parent = &dpll3_m3_ck, |
| 531 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 532 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, |
| 533 | .flags = INVERT_ENABLE, |
| 534 | .clkdm_name = "dpll3_clkdm", |
| 535 | .recalc = &omap3_clkoutx2_recalc, |
| 536 | }; |
| 537 | |
| 538 | static struct clk emu_core_alwon_ck = { |
| 539 | .name = "emu_core_alwon_ck", |
| 540 | .ops = &clkops_null, |
| 541 | .parent = &dpll3_m3x2_ck, |
| 542 | .clkdm_name = "dpll3_clkdm", |
| 543 | .recalc = &followparent_recalc, |
| 544 | }; |
| 545 | |
| 546 | /* DPLL4 */ |
| 547 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ |
| 548 | /* Type: DPLL */ |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 549 | static struct dpll_data dpll4_dd; |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 550 | |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 551 | static struct dpll_data dpll4_dd_34xx __initdata = { |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 552 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
| 553 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, |
| 554 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
| 555 | .clk_bypass = &sys_ck, |
| 556 | .clk_ref = &sys_ck, |
| 557 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, |
| 558 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 559 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, |
| 560 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
| 561 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, |
| 562 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 563 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, |
| 564 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 565 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, |
| 566 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 567 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
| 568 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 569 | .min_divider = 1, |
| 570 | .max_divider = OMAP3_MAX_DPLL_DIV, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 571 | }; |
| 572 | |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 573 | static struct dpll_data dpll4_dd_3630 __initdata = { |
| 574 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
| 575 | .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK, |
| 576 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
| 577 | .clk_bypass = &sys_ck, |
| 578 | .clk_ref = &sys_ck, |
| 579 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 580 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, |
| 581 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
| 582 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, |
| 583 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 584 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, |
| 585 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 586 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, |
| 587 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 588 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 589 | .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK, |
| 590 | .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK, |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 591 | .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, |
| 592 | .min_divider = 1, |
| 593 | .max_divider = OMAP3_MAX_DPLL_DIV, |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 594 | .flags = DPLL_J_TYPE |
| 595 | }; |
| 596 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 597 | static struct clk dpll4_ck = { |
| 598 | .name = "dpll4_ck", |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 599 | .ops = &clkops_omap3_noncore_dpll_ops, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 600 | .parent = &sys_ck, |
| 601 | .dpll_data = &dpll4_dd, |
| 602 | .round_rate = &omap2_dpll_round_rate, |
| 603 | .set_rate = &omap3_dpll4_set_rate, |
| 604 | .clkdm_name = "dpll4_clkdm", |
| 605 | .recalc = &omap3_dpll_recalc, |
| 606 | }; |
| 607 | |
| 608 | /* |
| 609 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 610 | * DPLL isn't bypassed -- |
| 611 | * XXX does this serve any downstream clocks? |
| 612 | */ |
| 613 | static struct clk dpll4_x2_ck = { |
| 614 | .name = "dpll4_x2_ck", |
| 615 | .ops = &clkops_null, |
| 616 | .parent = &dpll4_ck, |
| 617 | .clkdm_name = "dpll4_clkdm", |
| 618 | .recalc = &omap3_clkoutx2_recalc, |
| 619 | }; |
| 620 | |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 621 | static const struct clksel dpll4_clksel[] = { |
| 622 | { .parent = &dpll4_ck, .rates = dpll4_rates }, |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 623 | { .parent = NULL } |
| 624 | }; |
| 625 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 626 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 627 | static struct clk dpll4_m2_ck = { |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 628 | .name = "dpll4_m2_ck", |
| 629 | .ops = &clkops_null, |
| 630 | .parent = &dpll4_ck, |
| 631 | .init = &omap2_init_clksel_parent, |
| 632 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), |
| 633 | .clksel_mask = OMAP3630_DIV_96M_MASK, |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 634 | .clksel = dpll4_clksel, |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 635 | .clkdm_name = "dpll4_clkdm", |
| 636 | .recalc = &omap2_clksel_recalc, |
| 637 | }; |
| 638 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 639 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 640 | static struct clk dpll4_m2x2_ck = { |
| 641 | .name = "dpll4_m2x2_ck", |
| 642 | .ops = &clkops_omap2_dflt_wait, |
| 643 | .parent = &dpll4_m2_ck, |
| 644 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 645 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, |
| 646 | .flags = INVERT_ENABLE, |
| 647 | .clkdm_name = "dpll4_clkdm", |
| 648 | .recalc = &omap3_clkoutx2_recalc, |
| 649 | }; |
| 650 | |
| 651 | /* |
| 652 | * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as |
| 653 | * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: |
| 654 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and |
| 655 | * CM_96K_(F)CLK. |
| 656 | */ |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 657 | |
| 658 | /* Adding 192MHz Clock node needed by SGX */ |
| 659 | static struct clk omap_192m_alwon_fck = { |
| 660 | .name = "omap_192m_alwon_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 661 | .ops = &clkops_null, |
| 662 | .parent = &dpll4_m2x2_ck, |
| 663 | .recalc = &followparent_recalc, |
| 664 | }; |
| 665 | |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 666 | static const struct clksel_rate omap_96m_alwon_fck_rates[] = { |
| 667 | { .div = 1, .val = 1, .flags = RATE_IN_36XX }, |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 668 | { .div = 2, .val = 2, .flags = RATE_IN_36XX }, |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 669 | { .div = 0 } |
| 670 | }; |
| 671 | |
| 672 | static const struct clksel omap_96m_alwon_fck_clksel[] = { |
| 673 | { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates }, |
| 674 | { .parent = NULL } |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 675 | }; |
| 676 | |
| 677 | static const struct clksel_rate omap_96m_dpll_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 678 | { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 679 | { .div = 0 } |
| 680 | }; |
| 681 | |
| 682 | static const struct clksel_rate omap_96m_sys_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 683 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 684 | { .div = 0 } |
| 685 | }; |
| 686 | |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 687 | static struct clk omap_96m_alwon_fck = { |
| 688 | .name = "omap_96m_alwon_fck", |
| 689 | .ops = &clkops_null, |
| 690 | .parent = &dpll4_m2x2_ck, |
| 691 | .recalc = &followparent_recalc, |
| 692 | }; |
| 693 | |
| 694 | static struct clk omap_96m_alwon_fck_3630 = { |
| 695 | .name = "omap_96m_alwon_fck", |
| 696 | .parent = &omap_192m_alwon_fck, |
| 697 | .init = &omap2_init_clksel_parent, |
| 698 | .ops = &clkops_null, |
| 699 | .recalc = &omap2_clksel_recalc, |
| 700 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 701 | .clksel_mask = OMAP3630_CLKSEL_96M_MASK, |
| 702 | .clksel = omap_96m_alwon_fck_clksel |
| 703 | }; |
| 704 | |
| 705 | static struct clk cm_96m_fck = { |
| 706 | .name = "cm_96m_fck", |
| 707 | .ops = &clkops_null, |
| 708 | .parent = &omap_96m_alwon_fck, |
| 709 | .recalc = &followparent_recalc, |
| 710 | }; |
| 711 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 712 | static const struct clksel omap_96m_fck_clksel[] = { |
| 713 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, |
| 714 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, |
| 715 | { .parent = NULL } |
| 716 | }; |
| 717 | |
| 718 | static struct clk omap_96m_fck = { |
| 719 | .name = "omap_96m_fck", |
| 720 | .ops = &clkops_null, |
| 721 | .parent = &sys_ck, |
| 722 | .init = &omap2_init_clksel_parent, |
| 723 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 724 | .clksel_mask = OMAP3430_SOURCE_96M_MASK, |
| 725 | .clksel = omap_96m_fck_clksel, |
| 726 | .recalc = &omap2_clksel_recalc, |
| 727 | }; |
| 728 | |
| 729 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 730 | static struct clk dpll4_m3_ck = { |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 731 | .name = "dpll4_m3_ck", |
| 732 | .ops = &clkops_null, |
| 733 | .parent = &dpll4_ck, |
| 734 | .init = &omap2_init_clksel_parent, |
| 735 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
Grazvydas Ignotas | ac38733 | 2012-03-26 00:08:07 +0300 | [diff] [blame] | 736 | .clksel_mask = OMAP3630_CLKSEL_TV_MASK, |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 737 | .clksel = dpll4_clksel, |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 738 | .clkdm_name = "dpll4_clkdm", |
| 739 | .recalc = &omap2_clksel_recalc, |
| 740 | }; |
| 741 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 742 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 743 | static struct clk dpll4_m3x2_ck = { |
| 744 | .name = "dpll4_m3x2_ck", |
| 745 | .ops = &clkops_omap2_dflt_wait, |
| 746 | .parent = &dpll4_m3_ck, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 747 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 748 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, |
| 749 | .flags = INVERT_ENABLE, |
| 750 | .clkdm_name = "dpll4_clkdm", |
| 751 | .recalc = &omap3_clkoutx2_recalc, |
| 752 | }; |
| 753 | |
| 754 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 755 | { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 756 | { .div = 0 } |
| 757 | }; |
| 758 | |
| 759 | static const struct clksel_rate omap_54m_alt_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 760 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 761 | { .div = 0 } |
| 762 | }; |
| 763 | |
| 764 | static const struct clksel omap_54m_clksel[] = { |
| 765 | { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, |
| 766 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
| 767 | { .parent = NULL } |
| 768 | }; |
| 769 | |
| 770 | static struct clk omap_54m_fck = { |
| 771 | .name = "omap_54m_fck", |
| 772 | .ops = &clkops_null, |
| 773 | .init = &omap2_init_clksel_parent, |
| 774 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 775 | .clksel_mask = OMAP3430_SOURCE_54M_MASK, |
| 776 | .clksel = omap_54m_clksel, |
| 777 | .recalc = &omap2_clksel_recalc, |
| 778 | }; |
| 779 | |
| 780 | static const struct clksel_rate omap_48m_cm96m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 781 | { .div = 2, .val = 0, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 782 | { .div = 0 } |
| 783 | }; |
| 784 | |
| 785 | static const struct clksel_rate omap_48m_alt_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 786 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 787 | { .div = 0 } |
| 788 | }; |
| 789 | |
| 790 | static const struct clksel omap_48m_clksel[] = { |
| 791 | { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, |
| 792 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, |
| 793 | { .parent = NULL } |
| 794 | }; |
| 795 | |
| 796 | static struct clk omap_48m_fck = { |
| 797 | .name = "omap_48m_fck", |
| 798 | .ops = &clkops_null, |
| 799 | .init = &omap2_init_clksel_parent, |
| 800 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 801 | .clksel_mask = OMAP3430_SOURCE_48M_MASK, |
| 802 | .clksel = omap_48m_clksel, |
| 803 | .recalc = &omap2_clksel_recalc, |
| 804 | }; |
| 805 | |
| 806 | static struct clk omap_12m_fck = { |
| 807 | .name = "omap_12m_fck", |
| 808 | .ops = &clkops_null, |
| 809 | .parent = &omap_48m_fck, |
| 810 | .fixed_div = 4, |
Paul Walmsley | e9b98f6 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 811 | .recalc = &omap_fixed_divisor_recalc, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 812 | }; |
| 813 | |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 814 | /* This virtual clock is the source for dpll4_m4x2_ck */ |
| 815 | static struct clk dpll4_m4_ck = { |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 816 | .name = "dpll4_m4_ck", |
| 817 | .ops = &clkops_null, |
| 818 | .parent = &dpll4_ck, |
| 819 | .init = &omap2_init_clksel_parent, |
| 820 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
Grazvydas Ignotas | ac38733 | 2012-03-26 00:08:07 +0300 | [diff] [blame] | 821 | .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 822 | .clksel = dpll4_clksel, |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 823 | .clkdm_name = "dpll4_clkdm", |
| 824 | .recalc = &omap2_clksel_recalc, |
| 825 | .set_rate = &omap2_clksel_set_rate, |
| 826 | .round_rate = &omap2_clksel_round_rate, |
| 827 | }; |
| 828 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 829 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 830 | static struct clk dpll4_m4x2_ck = { |
| 831 | .name = "dpll4_m4x2_ck", |
| 832 | .ops = &clkops_omap2_dflt_wait, |
| 833 | .parent = &dpll4_m4_ck, |
| 834 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
Ranjith Lohithakshan | d54a45e | 2010-03-31 04:16:30 -0600 | [diff] [blame] | 835 | .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 836 | .flags = INVERT_ENABLE, |
| 837 | .clkdm_name = "dpll4_clkdm", |
| 838 | .recalc = &omap3_clkoutx2_recalc, |
| 839 | }; |
| 840 | |
| 841 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 842 | static struct clk dpll4_m5_ck = { |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 843 | .name = "dpll4_m5_ck", |
| 844 | .ops = &clkops_null, |
| 845 | .parent = &dpll4_ck, |
| 846 | .init = &omap2_init_clksel_parent, |
| 847 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), |
Grazvydas Ignotas | ac38733 | 2012-03-26 00:08:07 +0300 | [diff] [blame] | 848 | .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 849 | .clksel = dpll4_clksel, |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 850 | .clkdm_name = "dpll4_clkdm", |
Vimarsh Zutshi | e8d3737 | 2010-02-22 22:09:28 -0700 | [diff] [blame] | 851 | .set_rate = &omap2_clksel_set_rate, |
| 852 | .round_rate = &omap2_clksel_round_rate, |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 853 | .recalc = &omap2_clksel_recalc, |
| 854 | }; |
| 855 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 856 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 857 | static struct clk dpll4_m5x2_ck = { |
| 858 | .name = "dpll4_m5x2_ck", |
| 859 | .ops = &clkops_omap2_dflt_wait, |
| 860 | .parent = &dpll4_m5_ck, |
| 861 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 862 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
| 863 | .flags = INVERT_ENABLE, |
| 864 | .clkdm_name = "dpll4_clkdm", |
| 865 | .recalc = &omap3_clkoutx2_recalc, |
| 866 | }; |
| 867 | |
| 868 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 869 | static struct clk dpll4_m6_ck = { |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 870 | .name = "dpll4_m6_ck", |
| 871 | .ops = &clkops_null, |
| 872 | .parent = &dpll4_ck, |
| 873 | .init = &omap2_init_clksel_parent, |
| 874 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
Grazvydas Ignotas | ac38733 | 2012-03-26 00:08:07 +0300 | [diff] [blame] | 875 | .clksel_mask = OMAP3630_DIV_DPLL4_MASK, |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 876 | .clksel = dpll4_clksel, |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 877 | .clkdm_name = "dpll4_clkdm", |
| 878 | .recalc = &omap2_clksel_recalc, |
| 879 | }; |
| 880 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 881 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 882 | static struct clk dpll4_m6x2_ck = { |
| 883 | .name = "dpll4_m6x2_ck", |
| 884 | .ops = &clkops_omap2_dflt_wait, |
| 885 | .parent = &dpll4_m6_ck, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 886 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 887 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, |
| 888 | .flags = INVERT_ENABLE, |
| 889 | .clkdm_name = "dpll4_clkdm", |
| 890 | .recalc = &omap3_clkoutx2_recalc, |
| 891 | }; |
| 892 | |
| 893 | static struct clk emu_per_alwon_ck = { |
| 894 | .name = "emu_per_alwon_ck", |
| 895 | .ops = &clkops_null, |
| 896 | .parent = &dpll4_m6x2_ck, |
| 897 | .clkdm_name = "dpll4_clkdm", |
| 898 | .recalc = &followparent_recalc, |
| 899 | }; |
| 900 | |
| 901 | /* DPLL5 */ |
| 902 | /* Supplies 120MHz clock, USIM source clock */ |
| 903 | /* Type: DPLL */ |
| 904 | /* 3430ES2 only */ |
| 905 | static struct dpll_data dpll5_dd = { |
| 906 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), |
| 907 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, |
| 908 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, |
| 909 | .clk_bypass = &sys_ck, |
| 910 | .clk_ref = &sys_ck, |
| 911 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, |
| 912 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), |
| 913 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, |
| 914 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
| 915 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, |
| 916 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 917 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, |
| 918 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
| 919 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, |
| 920 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 921 | .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, |
| 922 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 923 | .min_divider = 1, |
| 924 | .max_divider = OMAP3_MAX_DPLL_DIV, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 925 | }; |
| 926 | |
| 927 | static struct clk dpll5_ck = { |
| 928 | .name = "dpll5_ck", |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 929 | .ops = &clkops_omap3_noncore_dpll_ops, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 930 | .parent = &sys_ck, |
| 931 | .dpll_data = &dpll5_dd, |
| 932 | .round_rate = &omap2_dpll_round_rate, |
| 933 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 934 | .clkdm_name = "dpll5_clkdm", |
| 935 | .recalc = &omap3_dpll_recalc, |
| 936 | }; |
| 937 | |
| 938 | static const struct clksel div16_dpll5_clksel[] = { |
| 939 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, |
| 940 | { .parent = NULL } |
| 941 | }; |
| 942 | |
| 943 | static struct clk dpll5_m2_ck = { |
| 944 | .name = "dpll5_m2_ck", |
| 945 | .ops = &clkops_null, |
| 946 | .parent = &dpll5_ck, |
| 947 | .init = &omap2_init_clksel_parent, |
| 948 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), |
| 949 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, |
| 950 | .clksel = div16_dpll5_clksel, |
| 951 | .clkdm_name = "dpll5_clkdm", |
| 952 | .recalc = &omap2_clksel_recalc, |
| 953 | }; |
| 954 | |
| 955 | /* CM EXTERNAL CLOCK OUTPUTS */ |
| 956 | |
| 957 | static const struct clksel_rate clkout2_src_core_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 958 | { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 959 | { .div = 0 } |
| 960 | }; |
| 961 | |
| 962 | static const struct clksel_rate clkout2_src_sys_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 963 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 964 | { .div = 0 } |
| 965 | }; |
| 966 | |
| 967 | static const struct clksel_rate clkout2_src_96m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 968 | { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 969 | { .div = 0 } |
| 970 | }; |
| 971 | |
| 972 | static const struct clksel_rate clkout2_src_54m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 973 | { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 974 | { .div = 0 } |
| 975 | }; |
| 976 | |
| 977 | static const struct clksel clkout2_src_clksel[] = { |
| 978 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, |
| 979 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, |
| 980 | { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, |
| 981 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, |
| 982 | { .parent = NULL } |
| 983 | }; |
| 984 | |
| 985 | static struct clk clkout2_src_ck = { |
| 986 | .name = "clkout2_src_ck", |
| 987 | .ops = &clkops_omap2_dflt, |
| 988 | .init = &omap2_init_clksel_parent, |
| 989 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 990 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, |
| 991 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 992 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, |
| 993 | .clksel = clkout2_src_clksel, |
| 994 | .clkdm_name = "core_clkdm", |
| 995 | .recalc = &omap2_clksel_recalc, |
| 996 | }; |
| 997 | |
| 998 | static const struct clksel_rate sys_clkout2_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 999 | { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
| 1000 | { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, |
| 1001 | { .div = 4, .val = 2, .flags = RATE_IN_3XXX }, |
| 1002 | { .div = 8, .val = 3, .flags = RATE_IN_3XXX }, |
| 1003 | { .div = 16, .val = 4, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1004 | { .div = 0 }, |
| 1005 | }; |
| 1006 | |
| 1007 | static const struct clksel sys_clkout2_clksel[] = { |
| 1008 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, |
| 1009 | { .parent = NULL }, |
| 1010 | }; |
| 1011 | |
| 1012 | static struct clk sys_clkout2 = { |
| 1013 | .name = "sys_clkout2", |
| 1014 | .ops = &clkops_null, |
| 1015 | .init = &omap2_init_clksel_parent, |
| 1016 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 1017 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, |
| 1018 | .clksel = sys_clkout2_clksel, |
| 1019 | .recalc = &omap2_clksel_recalc, |
Laine Walker-Avina | 71ee297 | 2010-05-18 20:24:02 -0600 | [diff] [blame] | 1020 | .round_rate = &omap2_clksel_round_rate, |
| 1021 | .set_rate = &omap2_clksel_set_rate |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1022 | }; |
| 1023 | |
| 1024 | /* CM OUTPUT CLOCKS */ |
| 1025 | |
| 1026 | static struct clk corex2_fck = { |
| 1027 | .name = "corex2_fck", |
| 1028 | .ops = &clkops_null, |
| 1029 | .parent = &dpll3_m2x2_ck, |
| 1030 | .recalc = &followparent_recalc, |
| 1031 | }; |
| 1032 | |
| 1033 | /* DPLL power domain clock controls */ |
| 1034 | |
| 1035 | static const struct clksel_rate div4_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 1036 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 1037 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
| 1038 | { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1039 | { .div = 0 } |
| 1040 | }; |
| 1041 | |
| 1042 | static const struct clksel div4_core_clksel[] = { |
| 1043 | { .parent = &core_ck, .rates = div4_rates }, |
| 1044 | { .parent = NULL } |
| 1045 | }; |
| 1046 | |
| 1047 | /* |
| 1048 | * REVISIT: Are these in DPLL power domain or CM power domain? docs |
| 1049 | * may be inconsistent here? |
| 1050 | */ |
| 1051 | static struct clk dpll1_fck = { |
| 1052 | .name = "dpll1_fck", |
| 1053 | .ops = &clkops_null, |
| 1054 | .parent = &core_ck, |
| 1055 | .init = &omap2_init_clksel_parent, |
| 1056 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1057 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, |
| 1058 | .clksel = div4_core_clksel, |
| 1059 | .recalc = &omap2_clksel_recalc, |
| 1060 | }; |
| 1061 | |
| 1062 | static struct clk mpu_ck = { |
| 1063 | .name = "mpu_ck", |
| 1064 | .ops = &clkops_null, |
| 1065 | .parent = &dpll1_x2m2_ck, |
| 1066 | .clkdm_name = "mpu_clkdm", |
| 1067 | .recalc = &followparent_recalc, |
| 1068 | }; |
| 1069 | |
| 1070 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ |
| 1071 | static const struct clksel_rate arm_fck_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 1072 | { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
| 1073 | { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1074 | { .div = 0 }, |
| 1075 | }; |
| 1076 | |
| 1077 | static const struct clksel arm_fck_clksel[] = { |
| 1078 | { .parent = &mpu_ck, .rates = arm_fck_rates }, |
| 1079 | { .parent = NULL } |
| 1080 | }; |
| 1081 | |
| 1082 | static struct clk arm_fck = { |
| 1083 | .name = "arm_fck", |
| 1084 | .ops = &clkops_null, |
| 1085 | .parent = &mpu_ck, |
| 1086 | .init = &omap2_init_clksel_parent, |
| 1087 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1088 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1089 | .clksel = arm_fck_clksel, |
| 1090 | .clkdm_name = "mpu_clkdm", |
| 1091 | .recalc = &omap2_clksel_recalc, |
| 1092 | }; |
| 1093 | |
| 1094 | /* XXX What about neon_clkdm ? */ |
| 1095 | |
| 1096 | /* |
| 1097 | * REVISIT: This clock is never specifically defined in the 3430 TRM, |
| 1098 | * although it is referenced - so this is a guess |
| 1099 | */ |
| 1100 | static struct clk emu_mpu_alwon_ck = { |
| 1101 | .name = "emu_mpu_alwon_ck", |
| 1102 | .ops = &clkops_null, |
| 1103 | .parent = &mpu_ck, |
| 1104 | .recalc = &followparent_recalc, |
| 1105 | }; |
| 1106 | |
| 1107 | static struct clk dpll2_fck = { |
| 1108 | .name = "dpll2_fck", |
| 1109 | .ops = &clkops_null, |
| 1110 | .parent = &core_ck, |
| 1111 | .init = &omap2_init_clksel_parent, |
| 1112 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1113 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, |
| 1114 | .clksel = div4_core_clksel, |
| 1115 | .recalc = &omap2_clksel_recalc, |
| 1116 | }; |
| 1117 | |
| 1118 | static struct clk iva2_ck = { |
| 1119 | .name = "iva2_ck", |
| 1120 | .ops = &clkops_omap2_dflt_wait, |
| 1121 | .parent = &dpll2_m2_ck, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1122 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
| 1123 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, |
| 1124 | .clkdm_name = "iva2_clkdm", |
| 1125 | .recalc = &followparent_recalc, |
| 1126 | }; |
| 1127 | |
| 1128 | /* Common interface clocks */ |
| 1129 | |
| 1130 | static const struct clksel div2_core_clksel[] = { |
| 1131 | { .parent = &core_ck, .rates = div2_rates }, |
| 1132 | { .parent = NULL } |
| 1133 | }; |
| 1134 | |
| 1135 | static struct clk l3_ick = { |
| 1136 | .name = "l3_ick", |
| 1137 | .ops = &clkops_null, |
| 1138 | .parent = &core_ck, |
| 1139 | .init = &omap2_init_clksel_parent, |
| 1140 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1141 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, |
| 1142 | .clksel = div2_core_clksel, |
| 1143 | .clkdm_name = "core_l3_clkdm", |
| 1144 | .recalc = &omap2_clksel_recalc, |
| 1145 | }; |
| 1146 | |
| 1147 | static const struct clksel div2_l3_clksel[] = { |
| 1148 | { .parent = &l3_ick, .rates = div2_rates }, |
| 1149 | { .parent = NULL } |
| 1150 | }; |
| 1151 | |
| 1152 | static struct clk l4_ick = { |
| 1153 | .name = "l4_ick", |
| 1154 | .ops = &clkops_null, |
| 1155 | .parent = &l3_ick, |
| 1156 | .init = &omap2_init_clksel_parent, |
| 1157 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1158 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, |
| 1159 | .clksel = div2_l3_clksel, |
| 1160 | .clkdm_name = "core_l4_clkdm", |
| 1161 | .recalc = &omap2_clksel_recalc, |
| 1162 | |
| 1163 | }; |
| 1164 | |
| 1165 | static const struct clksel div2_l4_clksel[] = { |
| 1166 | { .parent = &l4_ick, .rates = div2_rates }, |
| 1167 | { .parent = NULL } |
| 1168 | }; |
| 1169 | |
| 1170 | static struct clk rm_ick = { |
| 1171 | .name = "rm_ick", |
| 1172 | .ops = &clkops_null, |
| 1173 | .parent = &l4_ick, |
| 1174 | .init = &omap2_init_clksel_parent, |
| 1175 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 1176 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, |
| 1177 | .clksel = div2_l4_clksel, |
| 1178 | .recalc = &omap2_clksel_recalc, |
| 1179 | }; |
| 1180 | |
| 1181 | /* GFX power domain */ |
| 1182 | |
| 1183 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ |
| 1184 | |
| 1185 | static const struct clksel gfx_l3_clksel[] = { |
| 1186 | { .parent = &l3_ick, .rates = gfx_l3_rates }, |
| 1187 | { .parent = NULL } |
| 1188 | }; |
| 1189 | |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1190 | /* |
| 1191 | * Virtual parent clock for gfx_l3_ick and gfx_l3_fck |
| 1192 | * This interface clock does not have a CM_AUTOIDLE bit |
| 1193 | */ |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1194 | static struct clk gfx_l3_ck = { |
| 1195 | .name = "gfx_l3_ck", |
| 1196 | .ops = &clkops_omap2_dflt_wait, |
| 1197 | .parent = &l3_ick, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1198 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1199 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| 1200 | .recalc = &followparent_recalc, |
| 1201 | }; |
| 1202 | |
| 1203 | static struct clk gfx_l3_fck = { |
| 1204 | .name = "gfx_l3_fck", |
| 1205 | .ops = &clkops_null, |
| 1206 | .parent = &gfx_l3_ck, |
| 1207 | .init = &omap2_init_clksel_parent, |
| 1208 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 1209 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 1210 | .clksel = gfx_l3_clksel, |
| 1211 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1212 | .recalc = &omap2_clksel_recalc, |
| 1213 | }; |
| 1214 | |
| 1215 | static struct clk gfx_l3_ick = { |
| 1216 | .name = "gfx_l3_ick", |
| 1217 | .ops = &clkops_null, |
| 1218 | .parent = &gfx_l3_ck, |
| 1219 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1220 | .recalc = &followparent_recalc, |
| 1221 | }; |
| 1222 | |
| 1223 | static struct clk gfx_cg1_ck = { |
| 1224 | .name = "gfx_cg1_ck", |
| 1225 | .ops = &clkops_omap2_dflt_wait, |
| 1226 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
| 1227 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1228 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
| 1229 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1230 | .recalc = &followparent_recalc, |
| 1231 | }; |
| 1232 | |
| 1233 | static struct clk gfx_cg2_ck = { |
| 1234 | .name = "gfx_cg2_ck", |
| 1235 | .ops = &clkops_omap2_dflt_wait, |
| 1236 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
| 1237 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1238 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
| 1239 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1240 | .recalc = &followparent_recalc, |
| 1241 | }; |
| 1242 | |
| 1243 | /* SGX power domain - 3430ES2 only */ |
| 1244 | |
| 1245 | static const struct clksel_rate sgx_core_rates[] = { |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 1246 | { .div = 2, .val = 5, .flags = RATE_IN_36XX }, |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 1247 | { .div = 3, .val = 0, .flags = RATE_IN_3XXX }, |
| 1248 | { .div = 4, .val = 1, .flags = RATE_IN_3XXX }, |
| 1249 | { .div = 6, .val = 2, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1250 | { .div = 0 }, |
| 1251 | }; |
| 1252 | |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 1253 | static const struct clksel_rate sgx_192m_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 1254 | { .div = 1, .val = 4, .flags = RATE_IN_36XX }, |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 1255 | { .div = 0 }, |
| 1256 | }; |
| 1257 | |
| 1258 | static const struct clksel_rate sgx_corex2_rates[] = { |
Paul Walmsley | d74b494 | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 1259 | { .div = 3, .val = 6, .flags = RATE_IN_36XX }, |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 1260 | { .div = 5, .val = 7, .flags = RATE_IN_36XX }, |
| 1261 | { .div = 0 }, |
| 1262 | }; |
| 1263 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1264 | static const struct clksel_rate sgx_96m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 1265 | { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1266 | { .div = 0 }, |
| 1267 | }; |
| 1268 | |
| 1269 | static const struct clksel sgx_clksel[] = { |
| 1270 | { .parent = &core_ck, .rates = sgx_core_rates }, |
| 1271 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 1272 | { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates }, |
| 1273 | { .parent = &corex2_fck, .rates = sgx_corex2_rates }, |
| 1274 | { .parent = NULL } |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1275 | }; |
| 1276 | |
| 1277 | static struct clk sgx_fck = { |
| 1278 | .name = "sgx_fck", |
| 1279 | .ops = &clkops_omap2_dflt_wait, |
| 1280 | .init = &omap2_init_clksel_parent, |
| 1281 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), |
| 1282 | .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, |
| 1283 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), |
| 1284 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, |
| 1285 | .clksel = sgx_clksel, |
| 1286 | .clkdm_name = "sgx_clkdm", |
| 1287 | .recalc = &omap2_clksel_recalc, |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 1288 | .set_rate = &omap2_clksel_set_rate, |
| 1289 | .round_rate = &omap2_clksel_round_rate |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1290 | }; |
| 1291 | |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1292 | /* This interface clock does not have a CM_AUTOIDLE bit */ |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1293 | static struct clk sgx_ick = { |
| 1294 | .name = "sgx_ick", |
| 1295 | .ops = &clkops_omap2_dflt_wait, |
| 1296 | .parent = &l3_ick, |
| 1297 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
| 1298 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, |
| 1299 | .clkdm_name = "sgx_clkdm", |
| 1300 | .recalc = &followparent_recalc, |
| 1301 | }; |
| 1302 | |
| 1303 | /* CORE power domain */ |
| 1304 | |
| 1305 | static struct clk d2d_26m_fck = { |
| 1306 | .name = "d2d_26m_fck", |
| 1307 | .ops = &clkops_omap2_dflt_wait, |
| 1308 | .parent = &sys_ck, |
| 1309 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1310 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
| 1311 | .clkdm_name = "d2d_clkdm", |
| 1312 | .recalc = &followparent_recalc, |
| 1313 | }; |
| 1314 | |
| 1315 | static struct clk modem_fck = { |
| 1316 | .name = "modem_fck", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1317 | .ops = &clkops_omap2_mdmclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1318 | .parent = &sys_ck, |
| 1319 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1320 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, |
| 1321 | .clkdm_name = "d2d_clkdm", |
| 1322 | .recalc = &followparent_recalc, |
| 1323 | }; |
| 1324 | |
| 1325 | static struct clk sad2d_ick = { |
| 1326 | .name = "sad2d_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1327 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1328 | .parent = &l3_ick, |
| 1329 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1330 | .enable_bit = OMAP3430_EN_SAD2D_SHIFT, |
| 1331 | .clkdm_name = "d2d_clkdm", |
| 1332 | .recalc = &followparent_recalc, |
| 1333 | }; |
| 1334 | |
| 1335 | static struct clk mad2d_ick = { |
| 1336 | .name = "mad2d_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1337 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1338 | .parent = &l3_ick, |
| 1339 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1340 | .enable_bit = OMAP3430_EN_MAD2D_SHIFT, |
| 1341 | .clkdm_name = "d2d_clkdm", |
| 1342 | .recalc = &followparent_recalc, |
| 1343 | }; |
| 1344 | |
| 1345 | static const struct clksel omap343x_gpt_clksel[] = { |
| 1346 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, |
| 1347 | { .parent = &sys_ck, .rates = gpt_sys_rates }, |
| 1348 | { .parent = NULL} |
| 1349 | }; |
| 1350 | |
| 1351 | static struct clk gpt10_fck = { |
| 1352 | .name = "gpt10_fck", |
| 1353 | .ops = &clkops_omap2_dflt_wait, |
| 1354 | .parent = &sys_ck, |
| 1355 | .init = &omap2_init_clksel_parent, |
| 1356 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1357 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
| 1358 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1359 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, |
| 1360 | .clksel = omap343x_gpt_clksel, |
| 1361 | .clkdm_name = "core_l4_clkdm", |
| 1362 | .recalc = &omap2_clksel_recalc, |
| 1363 | }; |
| 1364 | |
| 1365 | static struct clk gpt11_fck = { |
| 1366 | .name = "gpt11_fck", |
| 1367 | .ops = &clkops_omap2_dflt_wait, |
| 1368 | .parent = &sys_ck, |
| 1369 | .init = &omap2_init_clksel_parent, |
| 1370 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1371 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
| 1372 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1373 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, |
| 1374 | .clksel = omap343x_gpt_clksel, |
| 1375 | .clkdm_name = "core_l4_clkdm", |
| 1376 | .recalc = &omap2_clksel_recalc, |
| 1377 | }; |
| 1378 | |
| 1379 | static struct clk cpefuse_fck = { |
| 1380 | .name = "cpefuse_fck", |
| 1381 | .ops = &clkops_omap2_dflt, |
| 1382 | .parent = &sys_ck, |
Paul Walmsley | 5897a39 | 2012-04-04 10:20:15 -0600 | [diff] [blame] | 1383 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1384 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1385 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, |
| 1386 | .recalc = &followparent_recalc, |
| 1387 | }; |
| 1388 | |
| 1389 | static struct clk ts_fck = { |
| 1390 | .name = "ts_fck", |
| 1391 | .ops = &clkops_omap2_dflt, |
| 1392 | .parent = &omap_32k_fck, |
Paul Walmsley | 5897a39 | 2012-04-04 10:20:15 -0600 | [diff] [blame] | 1393 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1394 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1395 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, |
| 1396 | .recalc = &followparent_recalc, |
| 1397 | }; |
| 1398 | |
| 1399 | static struct clk usbtll_fck = { |
| 1400 | .name = "usbtll_fck", |
Anand Gadiyar | 25499d9 | 2010-07-26 16:34:27 -0600 | [diff] [blame] | 1401 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1402 | .parent = &dpll5_m2_ck, |
Paul Walmsley | 5897a39 | 2012-04-04 10:20:15 -0600 | [diff] [blame] | 1403 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1404 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1405 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
| 1406 | .recalc = &followparent_recalc, |
| 1407 | }; |
| 1408 | |
| 1409 | /* CORE 96M FCLK-derived clocks */ |
| 1410 | |
| 1411 | static struct clk core_96m_fck = { |
| 1412 | .name = "core_96m_fck", |
| 1413 | .ops = &clkops_null, |
| 1414 | .parent = &omap_96m_fck, |
| 1415 | .clkdm_name = "core_l4_clkdm", |
| 1416 | .recalc = &followparent_recalc, |
| 1417 | }; |
| 1418 | |
| 1419 | static struct clk mmchs3_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1420 | .name = "mmchs3_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1421 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1422 | .parent = &core_96m_fck, |
| 1423 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1424 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| 1425 | .clkdm_name = "core_l4_clkdm", |
| 1426 | .recalc = &followparent_recalc, |
| 1427 | }; |
| 1428 | |
| 1429 | static struct clk mmchs2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1430 | .name = "mmchs2_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1431 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1432 | .parent = &core_96m_fck, |
| 1433 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1434 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| 1435 | .clkdm_name = "core_l4_clkdm", |
| 1436 | .recalc = &followparent_recalc, |
| 1437 | }; |
| 1438 | |
| 1439 | static struct clk mspro_fck = { |
| 1440 | .name = "mspro_fck", |
| 1441 | .ops = &clkops_omap2_dflt_wait, |
| 1442 | .parent = &core_96m_fck, |
| 1443 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1444 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
| 1445 | .clkdm_name = "core_l4_clkdm", |
| 1446 | .recalc = &followparent_recalc, |
| 1447 | }; |
| 1448 | |
| 1449 | static struct clk mmchs1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1450 | .name = "mmchs1_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1451 | .ops = &clkops_omap2_dflt_wait, |
| 1452 | .parent = &core_96m_fck, |
| 1453 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1454 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
| 1455 | .clkdm_name = "core_l4_clkdm", |
| 1456 | .recalc = &followparent_recalc, |
| 1457 | }; |
| 1458 | |
| 1459 | static struct clk i2c3_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1460 | .name = "i2c3_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1461 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1462 | .parent = &core_96m_fck, |
| 1463 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1464 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| 1465 | .clkdm_name = "core_l4_clkdm", |
| 1466 | .recalc = &followparent_recalc, |
| 1467 | }; |
| 1468 | |
| 1469 | static struct clk i2c2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1470 | .name = "i2c2_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1471 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1472 | .parent = &core_96m_fck, |
| 1473 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1474 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| 1475 | .clkdm_name = "core_l4_clkdm", |
| 1476 | .recalc = &followparent_recalc, |
| 1477 | }; |
| 1478 | |
| 1479 | static struct clk i2c1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1480 | .name = "i2c1_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1481 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1482 | .parent = &core_96m_fck, |
| 1483 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1484 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| 1485 | .clkdm_name = "core_l4_clkdm", |
| 1486 | .recalc = &followparent_recalc, |
| 1487 | }; |
| 1488 | |
| 1489 | /* |
| 1490 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; |
| 1491 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. |
| 1492 | */ |
| 1493 | static const struct clksel_rate common_mcbsp_96m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 1494 | { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1495 | { .div = 0 } |
| 1496 | }; |
| 1497 | |
| 1498 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 1499 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1500 | { .div = 0 } |
| 1501 | }; |
| 1502 | |
| 1503 | static const struct clksel mcbsp_15_clksel[] = { |
| 1504 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, |
| 1505 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
| 1506 | { .parent = NULL } |
| 1507 | }; |
| 1508 | |
| 1509 | static struct clk mcbsp5_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1510 | .name = "mcbsp5_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1511 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1512 | .init = &omap2_init_clksel_parent, |
| 1513 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1514 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| 1515 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 1516 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, |
| 1517 | .clksel = mcbsp_15_clksel, |
| 1518 | .clkdm_name = "core_l4_clkdm", |
| 1519 | .recalc = &omap2_clksel_recalc, |
| 1520 | }; |
| 1521 | |
| 1522 | static struct clk mcbsp1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1523 | .name = "mcbsp1_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1524 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1525 | .init = &omap2_init_clksel_parent, |
| 1526 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1527 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| 1528 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 1529 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, |
| 1530 | .clksel = mcbsp_15_clksel, |
| 1531 | .clkdm_name = "core_l4_clkdm", |
| 1532 | .recalc = &omap2_clksel_recalc, |
| 1533 | }; |
| 1534 | |
| 1535 | /* CORE_48M_FCK-derived clocks */ |
| 1536 | |
| 1537 | static struct clk core_48m_fck = { |
| 1538 | .name = "core_48m_fck", |
| 1539 | .ops = &clkops_null, |
| 1540 | .parent = &omap_48m_fck, |
| 1541 | .clkdm_name = "core_l4_clkdm", |
| 1542 | .recalc = &followparent_recalc, |
| 1543 | }; |
| 1544 | |
| 1545 | static struct clk mcspi4_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1546 | .name = "mcspi4_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1547 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1548 | .parent = &core_48m_fck, |
| 1549 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1550 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1551 | .recalc = &followparent_recalc, |
Charulatha V | b183aaf | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 1552 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1553 | }; |
| 1554 | |
| 1555 | static struct clk mcspi3_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1556 | .name = "mcspi3_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1557 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1558 | .parent = &core_48m_fck, |
| 1559 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1560 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1561 | .recalc = &followparent_recalc, |
Charulatha V | b183aaf | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 1562 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1563 | }; |
| 1564 | |
| 1565 | static struct clk mcspi2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1566 | .name = "mcspi2_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1567 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1568 | .parent = &core_48m_fck, |
| 1569 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1570 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1571 | .recalc = &followparent_recalc, |
Charulatha V | b183aaf | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 1572 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1573 | }; |
| 1574 | |
| 1575 | static struct clk mcspi1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1576 | .name = "mcspi1_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1577 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1578 | .parent = &core_48m_fck, |
| 1579 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1580 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1581 | .recalc = &followparent_recalc, |
Charulatha V | b183aaf | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 1582 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1583 | }; |
| 1584 | |
| 1585 | static struct clk uart2_fck = { |
| 1586 | .name = "uart2_fck", |
| 1587 | .ops = &clkops_omap2_dflt_wait, |
| 1588 | .parent = &core_48m_fck, |
| 1589 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1590 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
Kevin Hilman | 9b5bc5f | 2010-01-08 15:23:06 -0700 | [diff] [blame] | 1591 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1592 | .recalc = &followparent_recalc, |
| 1593 | }; |
| 1594 | |
| 1595 | static struct clk uart1_fck = { |
| 1596 | .name = "uart1_fck", |
| 1597 | .ops = &clkops_omap2_dflt_wait, |
| 1598 | .parent = &core_48m_fck, |
| 1599 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1600 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
Kevin Hilman | 9b5bc5f | 2010-01-08 15:23:06 -0700 | [diff] [blame] | 1601 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1602 | .recalc = &followparent_recalc, |
| 1603 | }; |
| 1604 | |
| 1605 | static struct clk fshostusb_fck = { |
| 1606 | .name = "fshostusb_fck", |
| 1607 | .ops = &clkops_omap2_dflt_wait, |
| 1608 | .parent = &core_48m_fck, |
Paul Walmsley | 5897a39 | 2012-04-04 10:20:15 -0600 | [diff] [blame] | 1609 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1610 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1611 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
| 1612 | .recalc = &followparent_recalc, |
| 1613 | }; |
| 1614 | |
| 1615 | /* CORE_12M_FCK based clocks */ |
| 1616 | |
| 1617 | static struct clk core_12m_fck = { |
| 1618 | .name = "core_12m_fck", |
| 1619 | .ops = &clkops_null, |
| 1620 | .parent = &omap_12m_fck, |
| 1621 | .clkdm_name = "core_l4_clkdm", |
| 1622 | .recalc = &followparent_recalc, |
| 1623 | }; |
| 1624 | |
| 1625 | static struct clk hdq_fck = { |
| 1626 | .name = "hdq_fck", |
| 1627 | .ops = &clkops_omap2_dflt_wait, |
| 1628 | .parent = &core_12m_fck, |
Paul Walmsley | 8f97437 | 2012-05-07 23:55:31 -0600 | [diff] [blame] | 1629 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1630 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1631 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
| 1632 | .recalc = &followparent_recalc, |
| 1633 | }; |
| 1634 | |
| 1635 | /* DPLL3-derived clock */ |
| 1636 | |
| 1637 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 1638 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 1639 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
| 1640 | { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, |
| 1641 | { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
| 1642 | { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, |
| 1643 | { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1644 | { .div = 0 } |
| 1645 | }; |
| 1646 | |
| 1647 | static const struct clksel ssi_ssr_clksel[] = { |
| 1648 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, |
| 1649 | { .parent = NULL } |
| 1650 | }; |
| 1651 | |
| 1652 | static struct clk ssi_ssr_fck_3430es1 = { |
| 1653 | .name = "ssi_ssr_fck", |
| 1654 | .ops = &clkops_omap2_dflt, |
| 1655 | .init = &omap2_init_clksel_parent, |
| 1656 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1657 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1658 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1659 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, |
| 1660 | .clksel = ssi_ssr_clksel, |
| 1661 | .clkdm_name = "core_l4_clkdm", |
| 1662 | .recalc = &omap2_clksel_recalc, |
| 1663 | }; |
| 1664 | |
| 1665 | static struct clk ssi_ssr_fck_3430es2 = { |
| 1666 | .name = "ssi_ssr_fck", |
| 1667 | .ops = &clkops_omap3430es2_ssi_wait, |
| 1668 | .init = &omap2_init_clksel_parent, |
| 1669 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1670 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1671 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1672 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, |
| 1673 | .clksel = ssi_ssr_clksel, |
| 1674 | .clkdm_name = "core_l4_clkdm", |
| 1675 | .recalc = &omap2_clksel_recalc, |
| 1676 | }; |
| 1677 | |
| 1678 | static struct clk ssi_sst_fck_3430es1 = { |
| 1679 | .name = "ssi_sst_fck", |
| 1680 | .ops = &clkops_null, |
| 1681 | .parent = &ssi_ssr_fck_3430es1, |
| 1682 | .fixed_div = 2, |
Paul Walmsley | e9b98f6 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 1683 | .recalc = &omap_fixed_divisor_recalc, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1684 | }; |
| 1685 | |
| 1686 | static struct clk ssi_sst_fck_3430es2 = { |
| 1687 | .name = "ssi_sst_fck", |
| 1688 | .ops = &clkops_null, |
| 1689 | .parent = &ssi_ssr_fck_3430es2, |
| 1690 | .fixed_div = 2, |
Paul Walmsley | e9b98f6 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 1691 | .recalc = &omap_fixed_divisor_recalc, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1692 | }; |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | /* CORE_L3_ICK based clocks */ |
| 1697 | |
| 1698 | /* |
| 1699 | * XXX must add clk_enable/clk_disable for these if standard code won't |
| 1700 | * handle it |
| 1701 | */ |
| 1702 | static struct clk core_l3_ick = { |
| 1703 | .name = "core_l3_ick", |
| 1704 | .ops = &clkops_null, |
| 1705 | .parent = &l3_ick, |
| 1706 | .clkdm_name = "core_l3_clkdm", |
| 1707 | .recalc = &followparent_recalc, |
| 1708 | }; |
| 1709 | |
| 1710 | static struct clk hsotgusb_ick_3430es1 = { |
| 1711 | .name = "hsotgusb_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1712 | .ops = &clkops_omap2_iclk_dflt, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1713 | .parent = &core_l3_ick, |
| 1714 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1715 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
| 1716 | .clkdm_name = "core_l3_clkdm", |
| 1717 | .recalc = &followparent_recalc, |
| 1718 | }; |
| 1719 | |
| 1720 | static struct clk hsotgusb_ick_3430es2 = { |
| 1721 | .name = "hsotgusb_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1722 | .ops = &clkops_omap3430es2_iclk_hsotgusb_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1723 | .parent = &core_l3_ick, |
| 1724 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1725 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
| 1726 | .clkdm_name = "core_l3_clkdm", |
| 1727 | .recalc = &followparent_recalc, |
| 1728 | }; |
| 1729 | |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1730 | /* This interface clock does not have a CM_AUTOIDLE bit */ |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1731 | static struct clk sdrc_ick = { |
| 1732 | .name = "sdrc_ick", |
| 1733 | .ops = &clkops_omap2_dflt_wait, |
| 1734 | .parent = &core_l3_ick, |
| 1735 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1736 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, |
| 1737 | .flags = ENABLE_ON_INIT, |
| 1738 | .clkdm_name = "core_l3_clkdm", |
| 1739 | .recalc = &followparent_recalc, |
| 1740 | }; |
| 1741 | |
| 1742 | static struct clk gpmc_fck = { |
| 1743 | .name = "gpmc_fck", |
| 1744 | .ops = &clkops_null, |
| 1745 | .parent = &core_l3_ick, |
| 1746 | .flags = ENABLE_ON_INIT, /* huh? */ |
| 1747 | .clkdm_name = "core_l3_clkdm", |
| 1748 | .recalc = &followparent_recalc, |
| 1749 | }; |
| 1750 | |
| 1751 | /* SECURITY_L3_ICK based clocks */ |
| 1752 | |
| 1753 | static struct clk security_l3_ick = { |
| 1754 | .name = "security_l3_ick", |
| 1755 | .ops = &clkops_null, |
| 1756 | .parent = &l3_ick, |
| 1757 | .recalc = &followparent_recalc, |
| 1758 | }; |
| 1759 | |
| 1760 | static struct clk pka_ick = { |
| 1761 | .name = "pka_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1762 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1763 | .parent = &security_l3_ick, |
| 1764 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1765 | .enable_bit = OMAP3430_EN_PKA_SHIFT, |
| 1766 | .recalc = &followparent_recalc, |
| 1767 | }; |
| 1768 | |
| 1769 | /* CORE_L4_ICK based clocks */ |
| 1770 | |
| 1771 | static struct clk core_l4_ick = { |
| 1772 | .name = "core_l4_ick", |
| 1773 | .ops = &clkops_null, |
| 1774 | .parent = &l4_ick, |
| 1775 | .clkdm_name = "core_l4_clkdm", |
| 1776 | .recalc = &followparent_recalc, |
| 1777 | }; |
| 1778 | |
| 1779 | static struct clk usbtll_ick = { |
| 1780 | .name = "usbtll_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1781 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1782 | .parent = &core_l4_ick, |
| 1783 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1784 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
| 1785 | .clkdm_name = "core_l4_clkdm", |
| 1786 | .recalc = &followparent_recalc, |
| 1787 | }; |
| 1788 | |
| 1789 | static struct clk mmchs3_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1790 | .name = "mmchs3_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1791 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1792 | .parent = &core_l4_ick, |
| 1793 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1794 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| 1795 | .clkdm_name = "core_l4_clkdm", |
| 1796 | .recalc = &followparent_recalc, |
| 1797 | }; |
| 1798 | |
| 1799 | /* Intersystem Communication Registers - chassis mode only */ |
| 1800 | static struct clk icr_ick = { |
| 1801 | .name = "icr_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1802 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1803 | .parent = &core_l4_ick, |
| 1804 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1805 | .enable_bit = OMAP3430_EN_ICR_SHIFT, |
| 1806 | .clkdm_name = "core_l4_clkdm", |
| 1807 | .recalc = &followparent_recalc, |
| 1808 | }; |
| 1809 | |
| 1810 | static struct clk aes2_ick = { |
| 1811 | .name = "aes2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1812 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1813 | .parent = &core_l4_ick, |
| 1814 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1815 | .enable_bit = OMAP3430_EN_AES2_SHIFT, |
| 1816 | .clkdm_name = "core_l4_clkdm", |
| 1817 | .recalc = &followparent_recalc, |
| 1818 | }; |
| 1819 | |
| 1820 | static struct clk sha12_ick = { |
| 1821 | .name = "sha12_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1822 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1823 | .parent = &core_l4_ick, |
| 1824 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1825 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, |
| 1826 | .clkdm_name = "core_l4_clkdm", |
| 1827 | .recalc = &followparent_recalc, |
| 1828 | }; |
| 1829 | |
| 1830 | static struct clk des2_ick = { |
| 1831 | .name = "des2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1832 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1833 | .parent = &core_l4_ick, |
| 1834 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1835 | .enable_bit = OMAP3430_EN_DES2_SHIFT, |
| 1836 | .clkdm_name = "core_l4_clkdm", |
| 1837 | .recalc = &followparent_recalc, |
| 1838 | }; |
| 1839 | |
| 1840 | static struct clk mmchs2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1841 | .name = "mmchs2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1842 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1843 | .parent = &core_l4_ick, |
| 1844 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1845 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| 1846 | .clkdm_name = "core_l4_clkdm", |
| 1847 | .recalc = &followparent_recalc, |
| 1848 | }; |
| 1849 | |
| 1850 | static struct clk mmchs1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1851 | .name = "mmchs1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1852 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1853 | .parent = &core_l4_ick, |
| 1854 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1855 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
| 1856 | .clkdm_name = "core_l4_clkdm", |
| 1857 | .recalc = &followparent_recalc, |
| 1858 | }; |
| 1859 | |
| 1860 | static struct clk mspro_ick = { |
| 1861 | .name = "mspro_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1862 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1863 | .parent = &core_l4_ick, |
| 1864 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1865 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
| 1866 | .clkdm_name = "core_l4_clkdm", |
| 1867 | .recalc = &followparent_recalc, |
| 1868 | }; |
| 1869 | |
| 1870 | static struct clk hdq_ick = { |
| 1871 | .name = "hdq_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1872 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1873 | .parent = &core_l4_ick, |
| 1874 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1875 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
| 1876 | .clkdm_name = "core_l4_clkdm", |
| 1877 | .recalc = &followparent_recalc, |
| 1878 | }; |
| 1879 | |
| 1880 | static struct clk mcspi4_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1881 | .name = "mcspi4_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1882 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1883 | .parent = &core_l4_ick, |
| 1884 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1885 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1886 | .clkdm_name = "core_l4_clkdm", |
| 1887 | .recalc = &followparent_recalc, |
| 1888 | }; |
| 1889 | |
| 1890 | static struct clk mcspi3_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1891 | .name = "mcspi3_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1892 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1893 | .parent = &core_l4_ick, |
| 1894 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1895 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1896 | .clkdm_name = "core_l4_clkdm", |
| 1897 | .recalc = &followparent_recalc, |
| 1898 | }; |
| 1899 | |
| 1900 | static struct clk mcspi2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1901 | .name = "mcspi2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1902 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1903 | .parent = &core_l4_ick, |
| 1904 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1905 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1906 | .clkdm_name = "core_l4_clkdm", |
| 1907 | .recalc = &followparent_recalc, |
| 1908 | }; |
| 1909 | |
| 1910 | static struct clk mcspi1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1911 | .name = "mcspi1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1912 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1913 | .parent = &core_l4_ick, |
| 1914 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1915 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1916 | .clkdm_name = "core_l4_clkdm", |
| 1917 | .recalc = &followparent_recalc, |
| 1918 | }; |
| 1919 | |
| 1920 | static struct clk i2c3_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1921 | .name = "i2c3_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1922 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1923 | .parent = &core_l4_ick, |
| 1924 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1925 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| 1926 | .clkdm_name = "core_l4_clkdm", |
| 1927 | .recalc = &followparent_recalc, |
| 1928 | }; |
| 1929 | |
| 1930 | static struct clk i2c2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1931 | .name = "i2c2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1932 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1933 | .parent = &core_l4_ick, |
| 1934 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1935 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| 1936 | .clkdm_name = "core_l4_clkdm", |
| 1937 | .recalc = &followparent_recalc, |
| 1938 | }; |
| 1939 | |
| 1940 | static struct clk i2c1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1941 | .name = "i2c1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1942 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1943 | .parent = &core_l4_ick, |
| 1944 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1945 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| 1946 | .clkdm_name = "core_l4_clkdm", |
| 1947 | .recalc = &followparent_recalc, |
| 1948 | }; |
| 1949 | |
| 1950 | static struct clk uart2_ick = { |
| 1951 | .name = "uart2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1952 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1953 | .parent = &core_l4_ick, |
| 1954 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1955 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
| 1956 | .clkdm_name = "core_l4_clkdm", |
| 1957 | .recalc = &followparent_recalc, |
| 1958 | }; |
| 1959 | |
| 1960 | static struct clk uart1_ick = { |
| 1961 | .name = "uart1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1962 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1963 | .parent = &core_l4_ick, |
| 1964 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1965 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
| 1966 | .clkdm_name = "core_l4_clkdm", |
| 1967 | .recalc = &followparent_recalc, |
| 1968 | }; |
| 1969 | |
| 1970 | static struct clk gpt11_ick = { |
| 1971 | .name = "gpt11_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1972 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1973 | .parent = &core_l4_ick, |
| 1974 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1975 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
| 1976 | .clkdm_name = "core_l4_clkdm", |
| 1977 | .recalc = &followparent_recalc, |
| 1978 | }; |
| 1979 | |
| 1980 | static struct clk gpt10_ick = { |
| 1981 | .name = "gpt10_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1982 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1983 | .parent = &core_l4_ick, |
| 1984 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1985 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
| 1986 | .clkdm_name = "core_l4_clkdm", |
| 1987 | .recalc = &followparent_recalc, |
| 1988 | }; |
| 1989 | |
| 1990 | static struct clk mcbsp5_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1991 | .name = "mcbsp5_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 1992 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 1993 | .parent = &core_l4_ick, |
| 1994 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1995 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| 1996 | .clkdm_name = "core_l4_clkdm", |
| 1997 | .recalc = &followparent_recalc, |
| 1998 | }; |
| 1999 | |
| 2000 | static struct clk mcbsp1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 2001 | .name = "mcbsp1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2002 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2003 | .parent = &core_l4_ick, |
| 2004 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2005 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| 2006 | .clkdm_name = "core_l4_clkdm", |
| 2007 | .recalc = &followparent_recalc, |
| 2008 | }; |
| 2009 | |
| 2010 | static struct clk fac_ick = { |
| 2011 | .name = "fac_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2012 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2013 | .parent = &core_l4_ick, |
| 2014 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2015 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, |
| 2016 | .clkdm_name = "core_l4_clkdm", |
| 2017 | .recalc = &followparent_recalc, |
| 2018 | }; |
| 2019 | |
| 2020 | static struct clk mailboxes_ick = { |
| 2021 | .name = "mailboxes_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2022 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2023 | .parent = &core_l4_ick, |
| 2024 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2025 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
| 2026 | .clkdm_name = "core_l4_clkdm", |
| 2027 | .recalc = &followparent_recalc, |
| 2028 | }; |
| 2029 | |
| 2030 | static struct clk omapctrl_ick = { |
| 2031 | .name = "omapctrl_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2032 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2033 | .parent = &core_l4_ick, |
| 2034 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2035 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
| 2036 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | 5897a39 | 2012-04-04 10:20:15 -0600 | [diff] [blame] | 2037 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2038 | .recalc = &followparent_recalc, |
| 2039 | }; |
| 2040 | |
| 2041 | /* SSI_L4_ICK based clocks */ |
| 2042 | |
| 2043 | static struct clk ssi_l4_ick = { |
| 2044 | .name = "ssi_l4_ick", |
| 2045 | .ops = &clkops_null, |
| 2046 | .parent = &l4_ick, |
| 2047 | .clkdm_name = "core_l4_clkdm", |
| 2048 | .recalc = &followparent_recalc, |
| 2049 | }; |
| 2050 | |
| 2051 | static struct clk ssi_ick_3430es1 = { |
| 2052 | .name = "ssi_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2053 | .ops = &clkops_omap2_iclk_dflt, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2054 | .parent = &ssi_l4_ick, |
| 2055 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2056 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 2057 | .clkdm_name = "core_l4_clkdm", |
| 2058 | .recalc = &followparent_recalc, |
| 2059 | }; |
| 2060 | |
| 2061 | static struct clk ssi_ick_3430es2 = { |
| 2062 | .name = "ssi_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2063 | .ops = &clkops_omap3430es2_iclk_ssi_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2064 | .parent = &ssi_l4_ick, |
| 2065 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2066 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 2067 | .clkdm_name = "core_l4_clkdm", |
| 2068 | .recalc = &followparent_recalc, |
| 2069 | }; |
| 2070 | |
| 2071 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, |
| 2072 | * but l4_ick makes more sense to me */ |
| 2073 | |
| 2074 | static const struct clksel usb_l4_clksel[] = { |
| 2075 | { .parent = &l4_ick, .rates = div2_rates }, |
| 2076 | { .parent = NULL }, |
| 2077 | }; |
| 2078 | |
| 2079 | static struct clk usb_l4_ick = { |
| 2080 | .name = "usb_l4_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2081 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2082 | .parent = &l4_ick, |
| 2083 | .init = &omap2_init_clksel_parent, |
| 2084 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2085 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
| 2086 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 2087 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, |
| 2088 | .clksel = usb_l4_clksel, |
Paul Walmsley | 5897a39 | 2012-04-04 10:20:15 -0600 | [diff] [blame] | 2089 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2090 | .recalc = &omap2_clksel_recalc, |
| 2091 | }; |
| 2092 | |
| 2093 | /* SECURITY_L4_ICK2 based clocks */ |
| 2094 | |
| 2095 | static struct clk security_l4_ick2 = { |
| 2096 | .name = "security_l4_ick2", |
| 2097 | .ops = &clkops_null, |
| 2098 | .parent = &l4_ick, |
| 2099 | .recalc = &followparent_recalc, |
| 2100 | }; |
| 2101 | |
| 2102 | static struct clk aes1_ick = { |
| 2103 | .name = "aes1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2104 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2105 | .parent = &security_l4_ick2, |
| 2106 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2107 | .enable_bit = OMAP3430_EN_AES1_SHIFT, |
| 2108 | .recalc = &followparent_recalc, |
| 2109 | }; |
| 2110 | |
| 2111 | static struct clk rng_ick = { |
| 2112 | .name = "rng_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2113 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2114 | .parent = &security_l4_ick2, |
| 2115 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2116 | .enable_bit = OMAP3430_EN_RNG_SHIFT, |
| 2117 | .recalc = &followparent_recalc, |
| 2118 | }; |
| 2119 | |
| 2120 | static struct clk sha11_ick = { |
| 2121 | .name = "sha11_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2122 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2123 | .parent = &security_l4_ick2, |
| 2124 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2125 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, |
| 2126 | .recalc = &followparent_recalc, |
| 2127 | }; |
| 2128 | |
| 2129 | static struct clk des1_ick = { |
| 2130 | .name = "des1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2131 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2132 | .parent = &security_l4_ick2, |
| 2133 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2134 | .enable_bit = OMAP3430_EN_DES1_SHIFT, |
| 2135 | .recalc = &followparent_recalc, |
| 2136 | }; |
| 2137 | |
| 2138 | /* DSS */ |
| 2139 | static struct clk dss1_alwon_fck_3430es1 = { |
| 2140 | .name = "dss1_alwon_fck", |
| 2141 | .ops = &clkops_omap2_dflt, |
| 2142 | .parent = &dpll4_m4x2_ck, |
| 2143 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2144 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, |
| 2145 | .clkdm_name = "dss_clkdm", |
| 2146 | .recalc = &followparent_recalc, |
| 2147 | }; |
| 2148 | |
| 2149 | static struct clk dss1_alwon_fck_3430es2 = { |
| 2150 | .name = "dss1_alwon_fck", |
| 2151 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
| 2152 | .parent = &dpll4_m4x2_ck, |
| 2153 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2154 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, |
| 2155 | .clkdm_name = "dss_clkdm", |
| 2156 | .recalc = &followparent_recalc, |
| 2157 | }; |
| 2158 | |
| 2159 | static struct clk dss_tv_fck = { |
| 2160 | .name = "dss_tv_fck", |
| 2161 | .ops = &clkops_omap2_dflt, |
| 2162 | .parent = &omap_54m_fck, |
| 2163 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2164 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
| 2165 | .clkdm_name = "dss_clkdm", |
| 2166 | .recalc = &followparent_recalc, |
| 2167 | }; |
| 2168 | |
| 2169 | static struct clk dss_96m_fck = { |
| 2170 | .name = "dss_96m_fck", |
| 2171 | .ops = &clkops_omap2_dflt, |
| 2172 | .parent = &omap_96m_fck, |
| 2173 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2174 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
| 2175 | .clkdm_name = "dss_clkdm", |
| 2176 | .recalc = &followparent_recalc, |
| 2177 | }; |
| 2178 | |
| 2179 | static struct clk dss2_alwon_fck = { |
| 2180 | .name = "dss2_alwon_fck", |
| 2181 | .ops = &clkops_omap2_dflt, |
| 2182 | .parent = &sys_ck, |
| 2183 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2184 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
| 2185 | .clkdm_name = "dss_clkdm", |
| 2186 | .recalc = &followparent_recalc, |
| 2187 | }; |
| 2188 | |
| 2189 | static struct clk dss_ick_3430es1 = { |
| 2190 | /* Handles both L3 and L4 clocks */ |
| 2191 | .name = "dss_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2192 | .ops = &clkops_omap2_iclk_dflt, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2193 | .parent = &l4_ick, |
| 2194 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
| 2195 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
| 2196 | .clkdm_name = "dss_clkdm", |
| 2197 | .recalc = &followparent_recalc, |
| 2198 | }; |
| 2199 | |
| 2200 | static struct clk dss_ick_3430es2 = { |
| 2201 | /* Handles both L3 and L4 clocks */ |
| 2202 | .name = "dss_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2203 | .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2204 | .parent = &l4_ick, |
| 2205 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
| 2206 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
| 2207 | .clkdm_name = "dss_clkdm", |
| 2208 | .recalc = &followparent_recalc, |
| 2209 | }; |
| 2210 | |
| 2211 | /* CAM */ |
| 2212 | |
| 2213 | static struct clk cam_mclk = { |
| 2214 | .name = "cam_mclk", |
| 2215 | .ops = &clkops_omap2_dflt, |
| 2216 | .parent = &dpll4_m5x2_ck, |
| 2217 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
| 2218 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
| 2219 | .clkdm_name = "cam_clkdm", |
| 2220 | .recalc = &followparent_recalc, |
| 2221 | }; |
| 2222 | |
| 2223 | static struct clk cam_ick = { |
| 2224 | /* Handles both L3 and L4 clocks */ |
| 2225 | .name = "cam_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2226 | .ops = &clkops_omap2_iclk_dflt, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2227 | .parent = &l4_ick, |
| 2228 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
| 2229 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
| 2230 | .clkdm_name = "cam_clkdm", |
| 2231 | .recalc = &followparent_recalc, |
| 2232 | }; |
| 2233 | |
| 2234 | static struct clk csi2_96m_fck = { |
| 2235 | .name = "csi2_96m_fck", |
| 2236 | .ops = &clkops_omap2_dflt, |
| 2237 | .parent = &core_96m_fck, |
| 2238 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
| 2239 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, |
| 2240 | .clkdm_name = "cam_clkdm", |
| 2241 | .recalc = &followparent_recalc, |
| 2242 | }; |
| 2243 | |
| 2244 | /* USBHOST - 3430ES2 only */ |
| 2245 | |
| 2246 | static struct clk usbhost_120m_fck = { |
| 2247 | .name = "usbhost_120m_fck", |
| 2248 | .ops = &clkops_omap2_dflt, |
| 2249 | .parent = &dpll5_m2_ck, |
| 2250 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2251 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
| 2252 | .clkdm_name = "usbhost_clkdm", |
| 2253 | .recalc = &followparent_recalc, |
| 2254 | }; |
| 2255 | |
| 2256 | static struct clk usbhost_48m_fck = { |
| 2257 | .name = "usbhost_48m_fck", |
| 2258 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
| 2259 | .parent = &omap_48m_fck, |
| 2260 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2261 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
| 2262 | .clkdm_name = "usbhost_clkdm", |
| 2263 | .recalc = &followparent_recalc, |
| 2264 | }; |
| 2265 | |
| 2266 | static struct clk usbhost_ick = { |
| 2267 | /* Handles both L3 and L4 clocks */ |
| 2268 | .name = "usbhost_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2269 | .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2270 | .parent = &l4_ick, |
| 2271 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
| 2272 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
| 2273 | .clkdm_name = "usbhost_clkdm", |
| 2274 | .recalc = &followparent_recalc, |
| 2275 | }; |
| 2276 | |
| 2277 | /* WKUP */ |
| 2278 | |
| 2279 | static const struct clksel_rate usim_96m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 2280 | { .div = 2, .val = 3, .flags = RATE_IN_3XXX }, |
| 2281 | { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
| 2282 | { .div = 8, .val = 5, .flags = RATE_IN_3XXX }, |
| 2283 | { .div = 10, .val = 6, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2284 | { .div = 0 }, |
| 2285 | }; |
| 2286 | |
| 2287 | static const struct clksel_rate usim_120m_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 2288 | { .div = 4, .val = 7, .flags = RATE_IN_3XXX }, |
| 2289 | { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, |
| 2290 | { .div = 16, .val = 9, .flags = RATE_IN_3XXX }, |
| 2291 | { .div = 20, .val = 10, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2292 | { .div = 0 }, |
| 2293 | }; |
| 2294 | |
| 2295 | static const struct clksel usim_clksel[] = { |
| 2296 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, |
| 2297 | { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, |
| 2298 | { .parent = &sys_ck, .rates = div2_rates }, |
| 2299 | { .parent = NULL }, |
| 2300 | }; |
| 2301 | |
| 2302 | /* 3430ES2 only */ |
| 2303 | static struct clk usim_fck = { |
| 2304 | .name = "usim_fck", |
| 2305 | .ops = &clkops_omap2_dflt_wait, |
| 2306 | .init = &omap2_init_clksel_parent, |
| 2307 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2308 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2309 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2310 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, |
| 2311 | .clksel = usim_clksel, |
| 2312 | .recalc = &omap2_clksel_recalc, |
| 2313 | }; |
| 2314 | |
| 2315 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ |
| 2316 | static struct clk gpt1_fck = { |
| 2317 | .name = "gpt1_fck", |
| 2318 | .ops = &clkops_omap2_dflt_wait, |
| 2319 | .init = &omap2_init_clksel_parent, |
| 2320 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2321 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2322 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2323 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, |
| 2324 | .clksel = omap343x_gpt_clksel, |
| 2325 | .clkdm_name = "wkup_clkdm", |
| 2326 | .recalc = &omap2_clksel_recalc, |
| 2327 | }; |
| 2328 | |
| 2329 | static struct clk wkup_32k_fck = { |
| 2330 | .name = "wkup_32k_fck", |
| 2331 | .ops = &clkops_null, |
| 2332 | .parent = &omap_32k_fck, |
| 2333 | .clkdm_name = "wkup_clkdm", |
| 2334 | .recalc = &followparent_recalc, |
| 2335 | }; |
| 2336 | |
| 2337 | static struct clk gpio1_dbck = { |
| 2338 | .name = "gpio1_dbck", |
| 2339 | .ops = &clkops_omap2_dflt, |
| 2340 | .parent = &wkup_32k_fck, |
| 2341 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2342 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 2343 | .clkdm_name = "wkup_clkdm", |
| 2344 | .recalc = &followparent_recalc, |
| 2345 | }; |
| 2346 | |
| 2347 | static struct clk wdt2_fck = { |
| 2348 | .name = "wdt2_fck", |
| 2349 | .ops = &clkops_omap2_dflt_wait, |
| 2350 | .parent = &wkup_32k_fck, |
| 2351 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2352 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
| 2353 | .clkdm_name = "wkup_clkdm", |
| 2354 | .recalc = &followparent_recalc, |
| 2355 | }; |
| 2356 | |
| 2357 | static struct clk wkup_l4_ick = { |
| 2358 | .name = "wkup_l4_ick", |
| 2359 | .ops = &clkops_null, |
| 2360 | .parent = &sys_ck, |
| 2361 | .clkdm_name = "wkup_clkdm", |
| 2362 | .recalc = &followparent_recalc, |
| 2363 | }; |
| 2364 | |
| 2365 | /* 3430ES2 only */ |
| 2366 | /* Never specifically named in the TRM, so we have to infer a likely name */ |
| 2367 | static struct clk usim_ick = { |
| 2368 | .name = "usim_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2369 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2370 | .parent = &wkup_l4_ick, |
| 2371 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2372 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2373 | .clkdm_name = "wkup_clkdm", |
| 2374 | .recalc = &followparent_recalc, |
| 2375 | }; |
| 2376 | |
| 2377 | static struct clk wdt2_ick = { |
| 2378 | .name = "wdt2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2379 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2380 | .parent = &wkup_l4_ick, |
| 2381 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2382 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
| 2383 | .clkdm_name = "wkup_clkdm", |
| 2384 | .recalc = &followparent_recalc, |
| 2385 | }; |
| 2386 | |
| 2387 | static struct clk wdt1_ick = { |
| 2388 | .name = "wdt1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2389 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2390 | .parent = &wkup_l4_ick, |
| 2391 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2392 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, |
| 2393 | .clkdm_name = "wkup_clkdm", |
| 2394 | .recalc = &followparent_recalc, |
| 2395 | }; |
| 2396 | |
| 2397 | static struct clk gpio1_ick = { |
| 2398 | .name = "gpio1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2399 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2400 | .parent = &wkup_l4_ick, |
| 2401 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2402 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 2403 | .clkdm_name = "wkup_clkdm", |
| 2404 | .recalc = &followparent_recalc, |
| 2405 | }; |
| 2406 | |
| 2407 | static struct clk omap_32ksync_ick = { |
| 2408 | .name = "omap_32ksync_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2409 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2410 | .parent = &wkup_l4_ick, |
| 2411 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2412 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, |
| 2413 | .clkdm_name = "wkup_clkdm", |
| 2414 | .recalc = &followparent_recalc, |
| 2415 | }; |
| 2416 | |
| 2417 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
| 2418 | static struct clk gpt12_ick = { |
| 2419 | .name = "gpt12_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2420 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2421 | .parent = &wkup_l4_ick, |
| 2422 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2423 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, |
| 2424 | .clkdm_name = "wkup_clkdm", |
| 2425 | .recalc = &followparent_recalc, |
| 2426 | }; |
| 2427 | |
| 2428 | static struct clk gpt1_ick = { |
| 2429 | .name = "gpt1_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2430 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2431 | .parent = &wkup_l4_ick, |
| 2432 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2433 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2434 | .clkdm_name = "wkup_clkdm", |
| 2435 | .recalc = &followparent_recalc, |
| 2436 | }; |
| 2437 | |
| 2438 | |
| 2439 | |
| 2440 | /* PER clock domain */ |
| 2441 | |
| 2442 | static struct clk per_96m_fck = { |
| 2443 | .name = "per_96m_fck", |
| 2444 | .ops = &clkops_null, |
| 2445 | .parent = &omap_96m_alwon_fck, |
| 2446 | .clkdm_name = "per_clkdm", |
| 2447 | .recalc = &followparent_recalc, |
| 2448 | }; |
| 2449 | |
| 2450 | static struct clk per_48m_fck = { |
| 2451 | .name = "per_48m_fck", |
| 2452 | .ops = &clkops_null, |
| 2453 | .parent = &omap_48m_fck, |
| 2454 | .clkdm_name = "per_clkdm", |
| 2455 | .recalc = &followparent_recalc, |
| 2456 | }; |
| 2457 | |
| 2458 | static struct clk uart3_fck = { |
| 2459 | .name = "uart3_fck", |
| 2460 | .ops = &clkops_omap2_dflt_wait, |
| 2461 | .parent = &per_48m_fck, |
| 2462 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2463 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
| 2464 | .clkdm_name = "per_clkdm", |
| 2465 | .recalc = &followparent_recalc, |
| 2466 | }; |
| 2467 | |
Govindraj.R | a0edcdb | 2010-09-27 20:20:17 +0530 | [diff] [blame] | 2468 | static struct clk uart4_fck = { |
| 2469 | .name = "uart4_fck", |
| 2470 | .ops = &clkops_omap2_dflt_wait, |
| 2471 | .parent = &per_48m_fck, |
| 2472 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2473 | .enable_bit = OMAP3630_EN_UART4_SHIFT, |
| 2474 | .clkdm_name = "per_clkdm", |
| 2475 | .recalc = &followparent_recalc, |
| 2476 | }; |
| 2477 | |
Kyle Manna | 4bf90f6 | 2011-10-18 13:47:41 -0500 | [diff] [blame] | 2478 | static struct clk uart4_fck_am35xx = { |
Paul Walmsley | bf76523 | 2012-06-27 14:53:46 -0600 | [diff] [blame] | 2479 | .name = "uart4_fck", |
| 2480 | .ops = &clkops_omap2_dflt_wait, |
| 2481 | .parent = &core_48m_fck, |
| 2482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2483 | .enable_bit = AM35XX_EN_UART4_SHIFT, |
| 2484 | .clkdm_name = "core_l4_clkdm", |
| 2485 | .recalc = &followparent_recalc, |
Kyle Manna | 4bf90f6 | 2011-10-18 13:47:41 -0500 | [diff] [blame] | 2486 | }; |
| 2487 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2488 | static struct clk gpt2_fck = { |
| 2489 | .name = "gpt2_fck", |
| 2490 | .ops = &clkops_omap2_dflt_wait, |
| 2491 | .init = &omap2_init_clksel_parent, |
| 2492 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2493 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2494 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2495 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, |
| 2496 | .clksel = omap343x_gpt_clksel, |
| 2497 | .clkdm_name = "per_clkdm", |
| 2498 | .recalc = &omap2_clksel_recalc, |
| 2499 | }; |
| 2500 | |
| 2501 | static struct clk gpt3_fck = { |
| 2502 | .name = "gpt3_fck", |
| 2503 | .ops = &clkops_omap2_dflt_wait, |
| 2504 | .init = &omap2_init_clksel_parent, |
| 2505 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2506 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2507 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2508 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, |
| 2509 | .clksel = omap343x_gpt_clksel, |
| 2510 | .clkdm_name = "per_clkdm", |
| 2511 | .recalc = &omap2_clksel_recalc, |
| 2512 | }; |
| 2513 | |
| 2514 | static struct clk gpt4_fck = { |
| 2515 | .name = "gpt4_fck", |
| 2516 | .ops = &clkops_omap2_dflt_wait, |
| 2517 | .init = &omap2_init_clksel_parent, |
| 2518 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2519 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2520 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2521 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, |
| 2522 | .clksel = omap343x_gpt_clksel, |
| 2523 | .clkdm_name = "per_clkdm", |
| 2524 | .recalc = &omap2_clksel_recalc, |
| 2525 | }; |
| 2526 | |
| 2527 | static struct clk gpt5_fck = { |
| 2528 | .name = "gpt5_fck", |
| 2529 | .ops = &clkops_omap2_dflt_wait, |
| 2530 | .init = &omap2_init_clksel_parent, |
| 2531 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2532 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2533 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2534 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, |
| 2535 | .clksel = omap343x_gpt_clksel, |
| 2536 | .clkdm_name = "per_clkdm", |
| 2537 | .recalc = &omap2_clksel_recalc, |
| 2538 | }; |
| 2539 | |
| 2540 | static struct clk gpt6_fck = { |
| 2541 | .name = "gpt6_fck", |
| 2542 | .ops = &clkops_omap2_dflt_wait, |
| 2543 | .init = &omap2_init_clksel_parent, |
| 2544 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2545 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2546 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2547 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, |
| 2548 | .clksel = omap343x_gpt_clksel, |
| 2549 | .clkdm_name = "per_clkdm", |
| 2550 | .recalc = &omap2_clksel_recalc, |
| 2551 | }; |
| 2552 | |
| 2553 | static struct clk gpt7_fck = { |
| 2554 | .name = "gpt7_fck", |
| 2555 | .ops = &clkops_omap2_dflt_wait, |
| 2556 | .init = &omap2_init_clksel_parent, |
| 2557 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2558 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2559 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2560 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, |
| 2561 | .clksel = omap343x_gpt_clksel, |
| 2562 | .clkdm_name = "per_clkdm", |
| 2563 | .recalc = &omap2_clksel_recalc, |
| 2564 | }; |
| 2565 | |
| 2566 | static struct clk gpt8_fck = { |
| 2567 | .name = "gpt8_fck", |
| 2568 | .ops = &clkops_omap2_dflt_wait, |
| 2569 | .init = &omap2_init_clksel_parent, |
| 2570 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2571 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2572 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2573 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, |
| 2574 | .clksel = omap343x_gpt_clksel, |
| 2575 | .clkdm_name = "per_clkdm", |
| 2576 | .recalc = &omap2_clksel_recalc, |
| 2577 | }; |
| 2578 | |
| 2579 | static struct clk gpt9_fck = { |
| 2580 | .name = "gpt9_fck", |
| 2581 | .ops = &clkops_omap2_dflt_wait, |
| 2582 | .init = &omap2_init_clksel_parent, |
| 2583 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2584 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2585 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2586 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, |
| 2587 | .clksel = omap343x_gpt_clksel, |
| 2588 | .clkdm_name = "per_clkdm", |
| 2589 | .recalc = &omap2_clksel_recalc, |
| 2590 | }; |
| 2591 | |
| 2592 | static struct clk per_32k_alwon_fck = { |
| 2593 | .name = "per_32k_alwon_fck", |
| 2594 | .ops = &clkops_null, |
| 2595 | .parent = &omap_32k_fck, |
| 2596 | .clkdm_name = "per_clkdm", |
| 2597 | .recalc = &followparent_recalc, |
| 2598 | }; |
| 2599 | |
| 2600 | static struct clk gpio6_dbck = { |
| 2601 | .name = "gpio6_dbck", |
| 2602 | .ops = &clkops_omap2_dflt, |
| 2603 | .parent = &per_32k_alwon_fck, |
| 2604 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2605 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
| 2606 | .clkdm_name = "per_clkdm", |
| 2607 | .recalc = &followparent_recalc, |
| 2608 | }; |
| 2609 | |
| 2610 | static struct clk gpio5_dbck = { |
| 2611 | .name = "gpio5_dbck", |
| 2612 | .ops = &clkops_omap2_dflt, |
| 2613 | .parent = &per_32k_alwon_fck, |
| 2614 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2615 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
| 2616 | .clkdm_name = "per_clkdm", |
| 2617 | .recalc = &followparent_recalc, |
| 2618 | }; |
| 2619 | |
| 2620 | static struct clk gpio4_dbck = { |
| 2621 | .name = "gpio4_dbck", |
| 2622 | .ops = &clkops_omap2_dflt, |
| 2623 | .parent = &per_32k_alwon_fck, |
| 2624 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2625 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
| 2626 | .clkdm_name = "per_clkdm", |
| 2627 | .recalc = &followparent_recalc, |
| 2628 | }; |
| 2629 | |
| 2630 | static struct clk gpio3_dbck = { |
| 2631 | .name = "gpio3_dbck", |
| 2632 | .ops = &clkops_omap2_dflt, |
| 2633 | .parent = &per_32k_alwon_fck, |
| 2634 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2635 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
| 2636 | .clkdm_name = "per_clkdm", |
| 2637 | .recalc = &followparent_recalc, |
| 2638 | }; |
| 2639 | |
| 2640 | static struct clk gpio2_dbck = { |
| 2641 | .name = "gpio2_dbck", |
| 2642 | .ops = &clkops_omap2_dflt, |
| 2643 | .parent = &per_32k_alwon_fck, |
| 2644 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2645 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
| 2646 | .clkdm_name = "per_clkdm", |
| 2647 | .recalc = &followparent_recalc, |
| 2648 | }; |
| 2649 | |
| 2650 | static struct clk wdt3_fck = { |
| 2651 | .name = "wdt3_fck", |
| 2652 | .ops = &clkops_omap2_dflt_wait, |
| 2653 | .parent = &per_32k_alwon_fck, |
| 2654 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2655 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
| 2656 | .clkdm_name = "per_clkdm", |
| 2657 | .recalc = &followparent_recalc, |
| 2658 | }; |
| 2659 | |
| 2660 | static struct clk per_l4_ick = { |
| 2661 | .name = "per_l4_ick", |
| 2662 | .ops = &clkops_null, |
| 2663 | .parent = &l4_ick, |
| 2664 | .clkdm_name = "per_clkdm", |
| 2665 | .recalc = &followparent_recalc, |
| 2666 | }; |
| 2667 | |
| 2668 | static struct clk gpio6_ick = { |
| 2669 | .name = "gpio6_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2670 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2671 | .parent = &per_l4_ick, |
| 2672 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2673 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
| 2674 | .clkdm_name = "per_clkdm", |
| 2675 | .recalc = &followparent_recalc, |
| 2676 | }; |
| 2677 | |
| 2678 | static struct clk gpio5_ick = { |
| 2679 | .name = "gpio5_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2680 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2681 | .parent = &per_l4_ick, |
| 2682 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2683 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
| 2684 | .clkdm_name = "per_clkdm", |
| 2685 | .recalc = &followparent_recalc, |
| 2686 | }; |
| 2687 | |
| 2688 | static struct clk gpio4_ick = { |
| 2689 | .name = "gpio4_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2690 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2691 | .parent = &per_l4_ick, |
| 2692 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2693 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
| 2694 | .clkdm_name = "per_clkdm", |
| 2695 | .recalc = &followparent_recalc, |
| 2696 | }; |
| 2697 | |
| 2698 | static struct clk gpio3_ick = { |
| 2699 | .name = "gpio3_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2700 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2701 | .parent = &per_l4_ick, |
| 2702 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2703 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
| 2704 | .clkdm_name = "per_clkdm", |
| 2705 | .recalc = &followparent_recalc, |
| 2706 | }; |
| 2707 | |
| 2708 | static struct clk gpio2_ick = { |
| 2709 | .name = "gpio2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2710 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2711 | .parent = &per_l4_ick, |
| 2712 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2713 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
| 2714 | .clkdm_name = "per_clkdm", |
| 2715 | .recalc = &followparent_recalc, |
| 2716 | }; |
| 2717 | |
| 2718 | static struct clk wdt3_ick = { |
| 2719 | .name = "wdt3_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2720 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2721 | .parent = &per_l4_ick, |
| 2722 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2723 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
| 2724 | .clkdm_name = "per_clkdm", |
| 2725 | .recalc = &followparent_recalc, |
| 2726 | }; |
| 2727 | |
| 2728 | static struct clk uart3_ick = { |
| 2729 | .name = "uart3_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2730 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2731 | .parent = &per_l4_ick, |
| 2732 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2733 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
| 2734 | .clkdm_name = "per_clkdm", |
| 2735 | .recalc = &followparent_recalc, |
| 2736 | }; |
| 2737 | |
Govindraj.R | a0edcdb | 2010-09-27 20:20:17 +0530 | [diff] [blame] | 2738 | static struct clk uart4_ick = { |
| 2739 | .name = "uart4_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2740 | .ops = &clkops_omap2_iclk_dflt_wait, |
Govindraj.R | a0edcdb | 2010-09-27 20:20:17 +0530 | [diff] [blame] | 2741 | .parent = &per_l4_ick, |
| 2742 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2743 | .enable_bit = OMAP3630_EN_UART4_SHIFT, |
| 2744 | .clkdm_name = "per_clkdm", |
| 2745 | .recalc = &followparent_recalc, |
| 2746 | }; |
| 2747 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2748 | static struct clk gpt9_ick = { |
| 2749 | .name = "gpt9_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2750 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2751 | .parent = &per_l4_ick, |
| 2752 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2753 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2754 | .clkdm_name = "per_clkdm", |
| 2755 | .recalc = &followparent_recalc, |
| 2756 | }; |
| 2757 | |
| 2758 | static struct clk gpt8_ick = { |
| 2759 | .name = "gpt8_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2760 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2761 | .parent = &per_l4_ick, |
| 2762 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2763 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2764 | .clkdm_name = "per_clkdm", |
| 2765 | .recalc = &followparent_recalc, |
| 2766 | }; |
| 2767 | |
| 2768 | static struct clk gpt7_ick = { |
| 2769 | .name = "gpt7_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2770 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2771 | .parent = &per_l4_ick, |
| 2772 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2773 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2774 | .clkdm_name = "per_clkdm", |
| 2775 | .recalc = &followparent_recalc, |
| 2776 | }; |
| 2777 | |
| 2778 | static struct clk gpt6_ick = { |
| 2779 | .name = "gpt6_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2780 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2781 | .parent = &per_l4_ick, |
| 2782 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2783 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2784 | .clkdm_name = "per_clkdm", |
| 2785 | .recalc = &followparent_recalc, |
| 2786 | }; |
| 2787 | |
| 2788 | static struct clk gpt5_ick = { |
| 2789 | .name = "gpt5_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2790 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2791 | .parent = &per_l4_ick, |
| 2792 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2793 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2794 | .clkdm_name = "per_clkdm", |
| 2795 | .recalc = &followparent_recalc, |
| 2796 | }; |
| 2797 | |
| 2798 | static struct clk gpt4_ick = { |
| 2799 | .name = "gpt4_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2800 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2801 | .parent = &per_l4_ick, |
| 2802 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2803 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2804 | .clkdm_name = "per_clkdm", |
| 2805 | .recalc = &followparent_recalc, |
| 2806 | }; |
| 2807 | |
| 2808 | static struct clk gpt3_ick = { |
| 2809 | .name = "gpt3_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2810 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2811 | .parent = &per_l4_ick, |
| 2812 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2813 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2814 | .clkdm_name = "per_clkdm", |
| 2815 | .recalc = &followparent_recalc, |
| 2816 | }; |
| 2817 | |
| 2818 | static struct clk gpt2_ick = { |
| 2819 | .name = "gpt2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2820 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2821 | .parent = &per_l4_ick, |
| 2822 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2823 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2824 | .clkdm_name = "per_clkdm", |
| 2825 | .recalc = &followparent_recalc, |
| 2826 | }; |
| 2827 | |
| 2828 | static struct clk mcbsp2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 2829 | .name = "mcbsp2_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2830 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2831 | .parent = &per_l4_ick, |
| 2832 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2833 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| 2834 | .clkdm_name = "per_clkdm", |
| 2835 | .recalc = &followparent_recalc, |
| 2836 | }; |
| 2837 | |
| 2838 | static struct clk mcbsp3_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 2839 | .name = "mcbsp3_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2840 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2841 | .parent = &per_l4_ick, |
| 2842 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2843 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| 2844 | .clkdm_name = "per_clkdm", |
| 2845 | .recalc = &followparent_recalc, |
| 2846 | }; |
| 2847 | |
| 2848 | static struct clk mcbsp4_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 2849 | .name = "mcbsp4_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 2850 | .ops = &clkops_omap2_iclk_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2851 | .parent = &per_l4_ick, |
| 2852 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2853 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| 2854 | .clkdm_name = "per_clkdm", |
| 2855 | .recalc = &followparent_recalc, |
| 2856 | }; |
| 2857 | |
| 2858 | static const struct clksel mcbsp_234_clksel[] = { |
Paul Walmsley | 073463c | 2010-01-08 15:23:07 -0700 | [diff] [blame] | 2859 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2860 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
| 2861 | { .parent = NULL } |
| 2862 | }; |
| 2863 | |
| 2864 | static struct clk mcbsp2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 2865 | .name = "mcbsp2_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2866 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2867 | .init = &omap2_init_clksel_parent, |
| 2868 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2869 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| 2870 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 2871 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, |
| 2872 | .clksel = mcbsp_234_clksel, |
| 2873 | .clkdm_name = "per_clkdm", |
| 2874 | .recalc = &omap2_clksel_recalc, |
| 2875 | }; |
| 2876 | |
| 2877 | static struct clk mcbsp3_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 2878 | .name = "mcbsp3_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2879 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2880 | .init = &omap2_init_clksel_parent, |
| 2881 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2882 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| 2883 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2884 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, |
| 2885 | .clksel = mcbsp_234_clksel, |
| 2886 | .clkdm_name = "per_clkdm", |
| 2887 | .recalc = &omap2_clksel_recalc, |
| 2888 | }; |
| 2889 | |
| 2890 | static struct clk mcbsp4_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 2891 | .name = "mcbsp4_fck", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2892 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2893 | .init = &omap2_init_clksel_parent, |
| 2894 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2895 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| 2896 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2897 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, |
| 2898 | .clksel = mcbsp_234_clksel, |
| 2899 | .clkdm_name = "per_clkdm", |
| 2900 | .recalc = &omap2_clksel_recalc, |
| 2901 | }; |
| 2902 | |
| 2903 | /* EMU clocks */ |
| 2904 | |
| 2905 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ |
| 2906 | |
| 2907 | static const struct clksel_rate emu_src_sys_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 2908 | { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2909 | { .div = 0 }, |
| 2910 | }; |
| 2911 | |
| 2912 | static const struct clksel_rate emu_src_core_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 2913 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2914 | { .div = 0 }, |
| 2915 | }; |
| 2916 | |
| 2917 | static const struct clksel_rate emu_src_per_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 2918 | { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2919 | { .div = 0 }, |
| 2920 | }; |
| 2921 | |
| 2922 | static const struct clksel_rate emu_src_mpu_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 2923 | { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2924 | { .div = 0 }, |
| 2925 | }; |
| 2926 | |
| 2927 | static const struct clksel emu_src_clksel[] = { |
| 2928 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, |
| 2929 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, |
| 2930 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, |
| 2931 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, |
| 2932 | { .parent = NULL }, |
| 2933 | }; |
| 2934 | |
| 2935 | /* |
| 2936 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only |
| 2937 | * to switch the source of some of the EMU clocks. |
| 2938 | * XXX Are there CLKEN bits for these EMU clks? |
| 2939 | */ |
| 2940 | static struct clk emu_src_ck = { |
| 2941 | .name = "emu_src_ck", |
| 2942 | .ops = &clkops_null, |
| 2943 | .init = &omap2_init_clksel_parent, |
| 2944 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2945 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, |
| 2946 | .clksel = emu_src_clksel, |
| 2947 | .clkdm_name = "emu_clkdm", |
| 2948 | .recalc = &omap2_clksel_recalc, |
| 2949 | }; |
| 2950 | |
| 2951 | static const struct clksel_rate pclk_emu_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 2952 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
| 2953 | { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, |
| 2954 | { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
| 2955 | { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2956 | { .div = 0 }, |
| 2957 | }; |
| 2958 | |
| 2959 | static const struct clksel pclk_emu_clksel[] = { |
| 2960 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, |
| 2961 | { .parent = NULL }, |
| 2962 | }; |
| 2963 | |
| 2964 | static struct clk pclk_fck = { |
| 2965 | .name = "pclk_fck", |
| 2966 | .ops = &clkops_null, |
| 2967 | .init = &omap2_init_clksel_parent, |
| 2968 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2969 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, |
| 2970 | .clksel = pclk_emu_clksel, |
| 2971 | .clkdm_name = "emu_clkdm", |
| 2972 | .recalc = &omap2_clksel_recalc, |
| 2973 | }; |
| 2974 | |
| 2975 | static const struct clksel_rate pclkx2_emu_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 2976 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 2977 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
| 2978 | { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 2979 | { .div = 0 }, |
| 2980 | }; |
| 2981 | |
| 2982 | static const struct clksel pclkx2_emu_clksel[] = { |
| 2983 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, |
| 2984 | { .parent = NULL }, |
| 2985 | }; |
| 2986 | |
| 2987 | static struct clk pclkx2_fck = { |
| 2988 | .name = "pclkx2_fck", |
| 2989 | .ops = &clkops_null, |
| 2990 | .init = &omap2_init_clksel_parent, |
| 2991 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2992 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, |
| 2993 | .clksel = pclkx2_emu_clksel, |
| 2994 | .clkdm_name = "emu_clkdm", |
| 2995 | .recalc = &omap2_clksel_recalc, |
| 2996 | }; |
| 2997 | |
| 2998 | static const struct clksel atclk_emu_clksel[] = { |
| 2999 | { .parent = &emu_src_ck, .rates = div2_rates }, |
| 3000 | { .parent = NULL }, |
| 3001 | }; |
| 3002 | |
| 3003 | static struct clk atclk_fck = { |
| 3004 | .name = "atclk_fck", |
| 3005 | .ops = &clkops_null, |
| 3006 | .init = &omap2_init_clksel_parent, |
| 3007 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 3008 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, |
| 3009 | .clksel = atclk_emu_clksel, |
| 3010 | .clkdm_name = "emu_clkdm", |
| 3011 | .recalc = &omap2_clksel_recalc, |
| 3012 | }; |
| 3013 | |
| 3014 | static struct clk traceclk_src_fck = { |
| 3015 | .name = "traceclk_src_fck", |
| 3016 | .ops = &clkops_null, |
| 3017 | .init = &omap2_init_clksel_parent, |
| 3018 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 3019 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, |
| 3020 | .clksel = emu_src_clksel, |
| 3021 | .clkdm_name = "emu_clkdm", |
| 3022 | .recalc = &omap2_clksel_recalc, |
| 3023 | }; |
| 3024 | |
| 3025 | static const struct clksel_rate traceclk_rates[] = { |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 3026 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 3027 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
| 3028 | { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3029 | { .div = 0 }, |
| 3030 | }; |
| 3031 | |
| 3032 | static const struct clksel traceclk_clksel[] = { |
| 3033 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, |
| 3034 | { .parent = NULL }, |
| 3035 | }; |
| 3036 | |
| 3037 | static struct clk traceclk_fck = { |
| 3038 | .name = "traceclk_fck", |
| 3039 | .ops = &clkops_null, |
| 3040 | .init = &omap2_init_clksel_parent, |
| 3041 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 3042 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, |
| 3043 | .clksel = traceclk_clksel, |
| 3044 | .clkdm_name = "emu_clkdm", |
| 3045 | .recalc = &omap2_clksel_recalc, |
| 3046 | }; |
| 3047 | |
| 3048 | /* SR clocks */ |
| 3049 | |
| 3050 | /* SmartReflex fclk (VDD1) */ |
| 3051 | static struct clk sr1_fck = { |
| 3052 | .name = "sr1_fck", |
| 3053 | .ops = &clkops_omap2_dflt_wait, |
| 3054 | .parent = &sys_ck, |
| 3055 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 3056 | .enable_bit = OMAP3430_EN_SR1_SHIFT, |
Benoit Cousson | ae4b4fc | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3057 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3058 | .recalc = &followparent_recalc, |
| 3059 | }; |
| 3060 | |
| 3061 | /* SmartReflex fclk (VDD2) */ |
| 3062 | static struct clk sr2_fck = { |
| 3063 | .name = "sr2_fck", |
| 3064 | .ops = &clkops_omap2_dflt_wait, |
| 3065 | .parent = &sys_ck, |
| 3066 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 3067 | .enable_bit = OMAP3430_EN_SR2_SHIFT, |
Benoit Cousson | ae4b4fc | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3068 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3069 | .recalc = &followparent_recalc, |
| 3070 | }; |
| 3071 | |
| 3072 | static struct clk sr_l4_ick = { |
| 3073 | .name = "sr_l4_ick", |
| 3074 | .ops = &clkops_null, /* RMK: missing? */ |
| 3075 | .parent = &l4_ick, |
| 3076 | .clkdm_name = "core_l4_clkdm", |
| 3077 | .recalc = &followparent_recalc, |
| 3078 | }; |
| 3079 | |
| 3080 | /* SECURE_32K_FCK clocks */ |
| 3081 | |
| 3082 | static struct clk gpt12_fck = { |
| 3083 | .name = "gpt12_fck", |
| 3084 | .ops = &clkops_null, |
| 3085 | .parent = &secure_32k_fck, |
Paul Walmsley | e21757a | 2011-08-22 16:13:00 -0600 | [diff] [blame] | 3086 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3087 | .recalc = &followparent_recalc, |
| 3088 | }; |
| 3089 | |
| 3090 | static struct clk wdt1_fck = { |
| 3091 | .name = "wdt1_fck", |
| 3092 | .ops = &clkops_null, |
| 3093 | .parent = &secure_32k_fck, |
Paul Walmsley | e21757a | 2011-08-22 16:13:00 -0600 | [diff] [blame] | 3094 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3095 | .recalc = &followparent_recalc, |
| 3096 | }; |
| 3097 | |
Ranjith Lohithakshan | 3cc4a2f | 2010-02-24 12:05:55 -0700 | [diff] [blame] | 3098 | /* Clocks for AM35XX */ |
| 3099 | static struct clk ipss_ick = { |
| 3100 | .name = "ipss_ick", |
| 3101 | .ops = &clkops_am35xx_ipss_wait, |
| 3102 | .parent = &core_l3_ick, |
| 3103 | .clkdm_name = "core_l3_clkdm", |
| 3104 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 3105 | .enable_bit = AM35XX_EN_IPSS_SHIFT, |
| 3106 | .recalc = &followparent_recalc, |
| 3107 | }; |
| 3108 | |
| 3109 | static struct clk emac_ick = { |
| 3110 | .name = "emac_ick", |
| 3111 | .ops = &clkops_am35xx_ipss_module_wait, |
| 3112 | .parent = &ipss_ick, |
| 3113 | .clkdm_name = "core_l3_clkdm", |
| 3114 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), |
| 3115 | .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT, |
| 3116 | .recalc = &followparent_recalc, |
| 3117 | }; |
| 3118 | |
| 3119 | static struct clk rmii_ck = { |
| 3120 | .name = "rmii_ck", |
| 3121 | .ops = &clkops_null, |
Ranjith Lohithakshan | 3cc4a2f | 2010-02-24 12:05:55 -0700 | [diff] [blame] | 3122 | .rate = 50000000, |
| 3123 | }; |
| 3124 | |
| 3125 | static struct clk emac_fck = { |
| 3126 | .name = "emac_fck", |
| 3127 | .ops = &clkops_omap2_dflt, |
| 3128 | .parent = &rmii_ck, |
| 3129 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), |
| 3130 | .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT, |
| 3131 | .recalc = &followparent_recalc, |
| 3132 | }; |
| 3133 | |
| 3134 | static struct clk hsotgusb_ick_am35xx = { |
| 3135 | .name = "hsotgusb_ick", |
| 3136 | .ops = &clkops_am35xx_ipss_module_wait, |
| 3137 | .parent = &ipss_ick, |
| 3138 | .clkdm_name = "core_l3_clkdm", |
| 3139 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), |
| 3140 | .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT, |
| 3141 | .recalc = &followparent_recalc, |
| 3142 | }; |
| 3143 | |
| 3144 | static struct clk hsotgusb_fck_am35xx = { |
| 3145 | .name = "hsotgusb_fck", |
| 3146 | .ops = &clkops_omap2_dflt, |
| 3147 | .parent = &sys_ck, |
| 3148 | .clkdm_name = "core_l3_clkdm", |
| 3149 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), |
| 3150 | .enable_bit = AM35XX_USBOTG_FCLK_SHIFT, |
| 3151 | .recalc = &followparent_recalc, |
| 3152 | }; |
| 3153 | |
| 3154 | static struct clk hecc_ck = { |
| 3155 | .name = "hecc_ck", |
| 3156 | .ops = &clkops_am35xx_ipss_module_wait, |
| 3157 | .parent = &sys_ck, |
| 3158 | .clkdm_name = "core_l3_clkdm", |
| 3159 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), |
| 3160 | .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT, |
| 3161 | .recalc = &followparent_recalc, |
| 3162 | }; |
| 3163 | |
| 3164 | static struct clk vpfe_ick = { |
| 3165 | .name = "vpfe_ick", |
| 3166 | .ops = &clkops_am35xx_ipss_module_wait, |
| 3167 | .parent = &ipss_ick, |
| 3168 | .clkdm_name = "core_l3_clkdm", |
| 3169 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), |
| 3170 | .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT, |
| 3171 | .recalc = &followparent_recalc, |
| 3172 | }; |
| 3173 | |
| 3174 | static struct clk pclk_ck = { |
| 3175 | .name = "pclk_ck", |
| 3176 | .ops = &clkops_null, |
Ranjith Lohithakshan | 3cc4a2f | 2010-02-24 12:05:55 -0700 | [diff] [blame] | 3177 | .rate = 27000000, |
| 3178 | }; |
| 3179 | |
| 3180 | static struct clk vpfe_fck = { |
| 3181 | .name = "vpfe_fck", |
| 3182 | .ops = &clkops_omap2_dflt, |
| 3183 | .parent = &pclk_ck, |
| 3184 | .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), |
| 3185 | .enable_bit = AM35XX_VPFE_FCLK_SHIFT, |
| 3186 | .recalc = &followparent_recalc, |
| 3187 | }; |
| 3188 | |
| 3189 | /* |
Paul Walmsley | 82ee620 | 2012-06-27 14:53:46 -0600 | [diff] [blame] | 3190 | * The UART1/2 functional clock acts as the functional clock for |
| 3191 | * UART4. No separate fclk control available. XXX Well now we have a |
| 3192 | * uart4_fck that is apparently used as the UART4 functional clock, |
| 3193 | * but it also seems that uart1_fck or uart2_fck are still needed, at |
| 3194 | * least for UART4 softresets to complete. This really needs |
| 3195 | * clarification. |
Ranjith Lohithakshan | 3cc4a2f | 2010-02-24 12:05:55 -0700 | [diff] [blame] | 3196 | */ |
| 3197 | static struct clk uart4_ick_am35xx = { |
| 3198 | .name = "uart4_ick", |
Paul Walmsley | ec538e3 | 2011-02-25 15:39:30 -0700 | [diff] [blame] | 3199 | .ops = &clkops_omap2_iclk_dflt_wait, |
Ranjith Lohithakshan | 3cc4a2f | 2010-02-24 12:05:55 -0700 | [diff] [blame] | 3200 | .parent = &core_l4_ick, |
| 3201 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 3202 | .enable_bit = AM35XX_EN_UART4_SHIFT, |
| 3203 | .clkdm_name = "core_l4_clkdm", |
| 3204 | .recalc = &followparent_recalc, |
| 3205 | }; |
| 3206 | |
Russell King | 3126c7b | 2010-07-15 11:01:17 +0100 | [diff] [blame] | 3207 | static struct clk dummy_apb_pclk = { |
| 3208 | .name = "apb_pclk", |
| 3209 | .ops = &clkops_null, |
| 3210 | }; |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3211 | |
| 3212 | /* |
| 3213 | * clkdev |
| 3214 | */ |
| 3215 | |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3216 | static struct omap_clk omap3xxx_clks[] = { |
Russell King | 3126c7b | 2010-07-15 11:01:17 +0100 | [diff] [blame] | 3217 | CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3218 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), |
| 3219 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), |
| 3220 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3221 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Paul Walmsley | 571efa0 | 2012-05-29 15:26:40 +0530 | [diff] [blame] | 3222 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX), |
| 3223 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3224 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), |
| 3225 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), |
Tony Lindgren | defa6be | 2012-09-17 16:26:10 -0700 | [diff] [blame] | 3226 | CLK("twl", "fck", &osc_sys_ck, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3227 | CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), |
| 3228 | CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), |
| 3229 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), |
| 3230 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), |
| 3231 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), |
| 3232 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), |
| 3233 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3234 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), |
| 3235 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3236 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), |
| 3237 | CLK(NULL, "core_ck", &core_ck, CK_3XXX), |
| 3238 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), |
| 3239 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), |
| 3240 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), |
| 3241 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), |
| 3242 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3243 | CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3244 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), |
| 3245 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), |
| 3246 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 3247 | CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3248 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3249 | CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3250 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), |
| 3251 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), |
| 3252 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), |
| 3253 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), |
| 3254 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), |
| 3255 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), |
| 3256 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), |
| 3257 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), |
| 3258 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), |
| 3259 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), |
| 3260 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), |
| 3261 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), |
| 3262 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), |
| 3263 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), |
| 3264 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3265 | CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3266 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3267 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3268 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3269 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), |
| 3270 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), |
| 3271 | CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), |
| 3272 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), |
| 3273 | CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), |
| 3274 | CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3275 | CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3276 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3277 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), |
| 3278 | CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3279 | CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), |
| 3280 | CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), |
| 3281 | CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3282 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), |
| 3283 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), |
| 3284 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), |
| 3285 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), |
| 3286 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), |
Kevin Hilman | f0c54d3 | 2012-05-07 23:55:11 -0600 | [diff] [blame] | 3287 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3288 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3289 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3290 | CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), |
| 3291 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), |
| 3292 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3293 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), |
| 3294 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3295 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3296 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3297 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Keshava Munegowda | a6d3a66 | 2011-10-11 13:21:51 +0530 | [diff] [blame] | 3298 | CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Paul Walmsley | 8fde3af | 2012-09-22 02:24:14 -0600 | [diff] [blame] | 3299 | CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3300 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3301 | CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3302 | CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3303 | CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3304 | CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), |
| 3305 | CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), |
| 3306 | CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), |
| 3307 | CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), |
| 3308 | CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), |
| 3309 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3310 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3311 | CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), |
| 3312 | CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), |
| 3313 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), |
| 3314 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3315 | CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), |
| 3316 | CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3317 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3318 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3319 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3320 | CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3321 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3322 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3323 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3324 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3325 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), |
Felipe Balbi | 0349176 | 2010-12-02 09:57:08 +0200 | [diff] [blame] | 3326 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), |
Linus Torvalds | 3e5b08c | 2011-01-07 13:16:28 -0800 | [diff] [blame] | 3327 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3328 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), |
| 3329 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3330 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), |
| 3331 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3332 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), |
| 3333 | CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3334 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3335 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Keshava Munegowda | a6d3a66 | 2011-10-11 13:21:51 +0530 | [diff] [blame] | 3336 | CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Paul Walmsley | 8fde3af | 2012-09-22 02:24:14 -0600 | [diff] [blame] | 3337 | CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 3338 | CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3339 | CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3340 | CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), |
| 3341 | CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), |
| 3342 | CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), |
| 3343 | CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 3344 | CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), |
| 3345 | CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3346 | CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), |
| 3347 | CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3348 | CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3349 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3350 | CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3351 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), |
| 3352 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), |
| 3353 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), |
| 3354 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3355 | CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), |
| 3356 | CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), |
| 3357 | CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), |
| 3358 | CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), |
Benoit Cousson | f7bb0d9 | 2010-12-09 14:24:16 +0000 | [diff] [blame] | 3359 | CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), |
| 3360 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), |
| 3361 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3362 | CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), |
| 3363 | CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), |
| 3364 | CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3365 | CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), |
| 3366 | CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), |
| 3367 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), |
| 3368 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), |
| 3369 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), |
| 3370 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3371 | CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), |
| 3372 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3373 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3374 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3375 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3376 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3377 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3378 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3379 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3380 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), |
| 3381 | CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), |
| 3382 | CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), |
| 3383 | CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), |
| 3384 | CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3385 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), |
| 3386 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3387 | CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), |
| 3388 | CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), |
| 3389 | CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 3390 | CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3391 | CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 3392 | CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3393 | CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3394 | CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), |
| 3395 | CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), |
| 3396 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), |
| 3397 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3398 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3399 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Keshava Munegowda | a6d3a66 | 2011-10-11 13:21:51 +0530 | [diff] [blame] | 3400 | CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
Russ Dill | afd6bb3 | 2012-06-21 03:44:32 -0700 | [diff] [blame] | 3401 | CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX), |
| 3402 | CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX), |
| 3403 | CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), |
| 3404 | CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), |
| 3405 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), |
| 3406 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), |
Keshava Munegowda | a6d3a66 | 2011-10-11 13:21:51 +0530 | [diff] [blame] | 3407 | CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), |
| 3408 | CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), |
Paul Walmsley | 8fde3af | 2012-09-22 02:24:14 -0600 | [diff] [blame] | 3409 | CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), |
| 3410 | CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), |
Russ Dill | afd6bb3 | 2012-06-21 03:44:32 -0700 | [diff] [blame] | 3411 | CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3412 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3413 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), |
| 3414 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), |
| 3415 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3416 | CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3417 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), |
| 3418 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3419 | CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3420 | CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3421 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), |
| 3422 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), |
| 3423 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), |
| 3424 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), |
| 3425 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), |
| 3426 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), |
| 3427 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), |
| 3428 | CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), |
Govindraj.R | a0edcdb | 2010-09-27 20:20:17 +0530 | [diff] [blame] | 3429 | CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), |
Kevin Hilman | 875e689 | 2012-05-07 23:55:10 -0600 | [diff] [blame] | 3430 | CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3431 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), |
| 3432 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), |
| 3433 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), |
| 3434 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), |
| 3435 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), |
| 3436 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), |
| 3437 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), |
| 3438 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), |
| 3439 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), |
| 3440 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), |
| 3441 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), |
| 3442 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX), |
| 3443 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX), |
| 3444 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX), |
| 3445 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX), |
| 3446 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX), |
| 3447 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX), |
| 3448 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX), |
| 3449 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX), |
| 3450 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX), |
| 3451 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), |
| 3452 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), |
| 3453 | CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), |
Govindraj.R | a0edcdb | 2010-09-27 20:20:17 +0530 | [diff] [blame] | 3454 | CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3455 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), |
| 3456 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), |
| 3457 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), |
| 3458 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX), |
| 3459 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX), |
| 3460 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX), |
| 3461 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX), |
| 3462 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX), |
| 3463 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), |
| 3464 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), |
| 3465 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3466 | CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX), |
| 3467 | CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX), |
| 3468 | CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX), |
Benoit Cousson | bf1e077 | 2011-07-10 05:54:12 -0600 | [diff] [blame] | 3469 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), |
| 3470 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), |
| 3471 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3472 | CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3473 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), |
| 3474 | CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), |
| 3475 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), |
| 3476 | CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), |
| 3477 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), |
| 3478 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3479 | CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX), |
| 3480 | CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX), |
| 3481 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), |
Ranjith Lohithakshan | ced8252 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 3482 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), |
| 3483 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), |
| 3484 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), |
Ranjith Lohithakshan | 3cc4a2f | 2010-02-24 12:05:55 -0700 | [diff] [blame] | 3485 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), |
| 3486 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), |
| 3487 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3488 | CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX), |
| 3489 | CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX), |
Mark A. Greer | 31ba880 | 2012-06-27 14:59:57 -0600 | [diff] [blame] | 3490 | CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), |
Ilya Yanok | 59269b9 | 2011-12-21 00:27:14 +0100 | [diff] [blame] | 3491 | CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), |
Rajendra Nayak | 6ea74cb | 2012-09-22 02:24:16 -0600 | [diff] [blame] | 3492 | CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX), |
| 3493 | CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX), |
Ranjith Lohithakshan | 3cc4a2f | 2010-02-24 12:05:55 -0700 | [diff] [blame] | 3494 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), |
| 3495 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), |
Paul Walmsley | 89ea258 | 2012-06-27 14:53:46 -0600 | [diff] [blame] | 3496 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), |
| 3497 | CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX), |
Ranjith Lohithakshan | 3cc4a2f | 2010-02-24 12:05:55 -0700 | [diff] [blame] | 3498 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), |
| 3499 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), |
Jon Hunter | c59b537 | 2012-06-05 12:35:00 -0500 | [diff] [blame] | 3500 | CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), |
| 3501 | CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), |
Paul Walmsley | c810fde | 2012-09-22 02:24:14 -0600 | [diff] [blame] | 3502 | CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX), |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3503 | }; |
| 3504 | |
| 3505 | |
Paul Walmsley | e80a972 | 2010-01-26 20:13:12 -0700 | [diff] [blame] | 3506 | int __init omap3xxx_clk_init(void) |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3507 | { |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3508 | struct omap_clk *c; |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3509 | u32 cpu_clkflg = 0; |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3510 | |
Kevin Hilman | 00633d7 | 2012-01-04 15:33:17 -0800 | [diff] [blame] | 3511 | if (soc_is_am35xx()) { |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3512 | cpu_mask = RATE_IN_34XX; |
Kevin Hilman | f0c54d3 | 2012-05-07 23:55:11 -0600 | [diff] [blame] | 3513 | cpu_clkflg = CK_AM35XX; |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3514 | } else if (cpu_is_omap3630()) { |
| 3515 | cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); |
| 3516 | cpu_clkflg = CK_36XX; |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 3517 | } else if (cpu_is_ti816x()) { |
| 3518 | cpu_mask = RATE_IN_TI816X; |
| 3519 | cpu_clkflg = CK_TI816X; |
Vaibhav Hiremath | 971b8a9 | 2012-07-05 08:05:15 -0700 | [diff] [blame] | 3520 | } else if (soc_is_am33xx()) { |
Afzal Mohammed | 1e6cb14 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 3521 | cpu_mask = RATE_IN_AM33XX; |
Hemant Pedanekar | 4390f5b | 2011-12-13 10:46:45 -0800 | [diff] [blame] | 3522 | } else if (cpu_is_ti814x()) { |
| 3523 | cpu_mask = RATE_IN_TI814X; |
stanley.miao | 8098bb0 | 2010-08-16 09:21:19 +0300 | [diff] [blame] | 3524 | } else if (cpu_is_omap34xx()) { |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3525 | if (omap_rev() == OMAP3430_REV_ES1_0) { |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3526 | cpu_mask = RATE_IN_3430ES1; |
| 3527 | cpu_clkflg = CK_3430ES1; |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3528 | } else { |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3529 | /* |
| 3530 | * Assume that anything that we haven't matched yet |
| 3531 | * has 3430ES2-type clocks. |
| 3532 | */ |
| 3533 | cpu_mask = RATE_IN_3430ES2PLUS; |
| 3534 | cpu_clkflg = CK_3430ES2PLUS; |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3535 | } |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3536 | } else { |
| 3537 | WARN(1, "clock: could not identify OMAP3 variant\n"); |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3538 | } |
Paul Walmsley | 6340536 | 2010-05-18 18:40:25 -0600 | [diff] [blame] | 3539 | |
Vishwanath BS | 7356f0b | 2010-02-22 22:09:10 -0700 | [diff] [blame] | 3540 | if (omap3_has_192mhz_clk()) |
| 3541 | omap_96m_alwon_fck = omap_96m_alwon_fck_3630; |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3542 | |
Mike Turquette | a7e069f | 2010-02-24 12:06:00 -0700 | [diff] [blame] | 3543 | if (cpu_is_omap3630()) { |
Vishwanath BS | 678bc9a | 2010-02-22 22:09:09 -0700 | [diff] [blame] | 3544 | /* |
| 3545 | * XXX This type of dynamic rewriting of the clock tree is |
| 3546 | * deprecated and should be revised soon. |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 3547 | * |
Mike Turquette | a7e069f | 2010-02-24 12:06:00 -0700 | [diff] [blame] | 3548 | * For 3630: override clkops_omap2_dflt_wait for the |
| 3549 | * clocks affected from PWRDN reset Limitation |
| 3550 | */ |
| 3551 | dpll3_m3x2_ck.ops = |
| 3552 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; |
| 3553 | dpll4_m2x2_ck.ops = |
| 3554 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; |
| 3555 | dpll4_m3x2_ck.ops = |
| 3556 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; |
| 3557 | dpll4_m4x2_ck.ops = |
| 3558 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; |
| 3559 | dpll4_m5x2_ck.ops = |
| 3560 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; |
| 3561 | dpll4_m6x2_ck.ops = |
| 3562 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; |
| 3563 | } |
| 3564 | |
Paul Walmsley | 2a9f5a4 | 2010-05-18 18:40:26 -0600 | [diff] [blame] | 3565 | /* |
| 3566 | * XXX This type of dynamic rewriting of the clock tree is |
| 3567 | * deprecated and should be revised soon. |
| 3568 | */ |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 3569 | if (cpu_is_omap3630()) |
| 3570 | dpll4_dd = dpll4_dd_3630; |
| 3571 | else |
| 3572 | dpll4_dd = dpll4_dd_34xx; |
| 3573 | |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 3574 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); |
| 3575 | c++) |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3576 | clk_preinit(c->lk.clk); |
| 3577 | |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 3578 | for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); |
| 3579 | c++) |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3580 | if (c->cpu & cpu_clkflg) { |
| 3581 | clkdev_add(&c->lk); |
| 3582 | clk_register(c->lk.clk); |
| 3583 | omap2_init_clk_clkdm(c->lk.clk); |
| 3584 | } |
| 3585 | |
Paul Walmsley | c6461f5 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 3586 | /* Disable autoidle on all clocks; let the PM code enable it later */ |
| 3587 | omap_clk_disable_autoidle_all(); |
| 3588 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3589 | recalculate_root_clocks(); |
| 3590 | |
Paul Walmsley | 553d239 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3591 | pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
| 3592 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, |
| 3593 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3594 | |
| 3595 | /* |
| 3596 | * Only enable those clocks we will need, let the drivers |
| 3597 | * enable other clocks as necessary |
| 3598 | */ |
| 3599 | clk_enable_init_clocks(); |
| 3600 | |
| 3601 | /* |
Paul Walmsley | c6461f5 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 3602 | * Lock DPLL5 -- here only until other device init code can |
| 3603 | * handle this |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3604 | */ |
Hemant Pedanekar | a920360 | 2011-12-13 10:46:44 -0800 | [diff] [blame] | 3605 | if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0)) |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 3606 | omap3_clk_lock_dpll5(); |
| 3607 | |
| 3608 | /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ |
| 3609 | sdrc_ick_p = clk_get(NULL, "sdrc_ick"); |
| 3610 | arm_fck_p = clk_get(NULL, "arm_fck"); |
| 3611 | |
| 3612 | return 0; |
| 3613 | } |