blob: 3081d07f8de51f839d9a7c3d8b70848de0000fa5 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020029#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +000030#include "radeon_asic.h"
Jerome Glissef0ed1f62009-09-28 20:39:19 +020031#include "atom.h"
32#include "r520d.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020033
Jerome Glissef0ed1f62009-09-28 20:39:19 +020034/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020035
Jerome Glissef0ed1f62009-09-28 20:39:19 +020036static int r520_mc_wait_for_idle(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037{
38 unsigned i;
39 uint32_t tmp;
40
41 for (i = 0; i < rdev->usec_timeout; i++) {
42 /* read MC_STATUS */
43 tmp = RREG32_MC(R520_MC_STATUS);
44 if (tmp & R520_MC_STATUS_IDLE) {
45 return 0;
46 }
47 DRM_UDELAY(1);
48 }
49 return -1;
50}
51
Jerome Glissef0ed1f62009-09-28 20:39:19 +020052static void r520_gpu_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020053{
54 unsigned pipe_select_current, gb_pipe_select, tmp;
55
Jerome Glissed39c3b82009-09-28 18:34:43 +020056 rv515_vga_render_disable(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020057 /*
58 * DST_PIPE_CONFIG 0x170C
59 * GB_TILE_CONFIG 0x4018
60 * GB_FIFO_SIZE 0x4024
61 * GB_PIPE_SELECT 0x402C
62 * GB_PIPE_SELECT2 0x4124
63 * Z_PIPE_SHIFT 0
64 * Z_PIPE_MASK 0x000000003
65 * GB_FIFO_SIZE2 0x4128
66 * SC_SFIFO_SIZE_SHIFT 0
67 * SC_SFIFO_SIZE_MASK 0x000000003
68 * SC_MFIFO_SIZE_SHIFT 2
69 * SC_MFIFO_SIZE_MASK 0x00000000C
70 * FG_SFIFO_SIZE_SHIFT 4
71 * FG_SFIFO_SIZE_MASK 0x000000030
72 * ZB_MFIFO_SIZE_SHIFT 6
73 * ZB_MFIFO_SIZE_MASK 0x0000000C0
74 * GA_ENHANCE 0x4274
75 * SU_REG_DEST 0x42C8
76 */
77 /* workaround for RV530 */
78 if (rdev->family == CHIP_RV530) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +020079 WREG32(0x4128, 0xFF);
80 }
81 r420_pipes_init(rdev);
Alex Deucherd75ee3b2011-01-24 23:24:59 -050082 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
83 tmp = RREG32(R300_DST_PIPE_CONFIG);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020084 pipe_select_current = (tmp >> 2) & 3;
85 tmp = (1 << pipe_select_current) |
86 (((gb_pipe_select >> 8) & 0xF) << 4);
87 WREG32_PLL(0x000D, tmp);
88 if (r520_mc_wait_for_idle(rdev)) {
89 printk(KERN_WARNING "Failed to wait MC idle while "
90 "programming pipes. Bad things might happen.\n");
91 }
92}
93
Jerome Glisse771fe6b2009-06-05 14:42:42 +020094static void r520_vram_get_type(struct radeon_device *rdev)
95{
96 uint32_t tmp;
97
98 rdev->mc.vram_width = 128;
99 rdev->mc.vram_is_ddr = true;
100 tmp = RREG32_MC(R520_MC_CNTL0);
101 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
102 case 0:
103 rdev->mc.vram_width = 32;
104 break;
105 case 1:
106 rdev->mc.vram_width = 64;
107 break;
108 case 2:
109 rdev->mc.vram_width = 128;
110 break;
111 case 3:
112 rdev->mc.vram_width = 256;
113 break;
114 default:
115 rdev->mc.vram_width = 128;
116 break;
117 }
118 if (tmp & R520_MC_CHANNEL_SIZE)
119 rdev->mc.vram_width *= 2;
120}
121
Jerome Glissed594e462010-02-17 21:54:29 +0000122void r520_mc_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200123{
Jerome Glissec93bb852009-07-13 21:04:08 +0200124
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200125 r520_vram_get_type(rdev);
Dave Airlie2a0f8912009-07-11 04:44:47 +1000126 r100_vram_init_sizes(rdev);
Jerome Glissed594e462010-02-17 21:54:29 +0000127 radeon_vram_location(rdev, &rdev->mc, 0);
Alex Deucher8d369bb2010-07-15 10:51:10 -0400128 rdev->mc.gtt_base_align = 0;
Jerome Glissed594e462010-02-17 21:54:29 +0000129 if (!(rdev->flags & RADEON_IS_AGP))
130 radeon_gtt_location(rdev, &rdev->mc);
Alex Deucherf47299c2010-03-16 20:54:38 -0400131 radeon_update_bandwidth_info(rdev);
Jerome Glissec93bb852009-07-13 21:04:08 +0200132}
133
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200134void r520_mc_program(struct radeon_device *rdev)
Jerome Glissec93bb852009-07-13 21:04:08 +0200135{
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200136 struct rv515_mc_save save;
137
138 /* Stops all mc clients */
139 rv515_mc_stop(rdev, &save);
140
141 /* Wait for mc idle */
142 if (r520_mc_wait_for_idle(rdev))
143 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
144 /* Write VRAM size in case we are limiting it */
145 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
146 /* Program MC, should be a 32bits limited address space */
147 WREG32_MC(R_000004_MC_FB_LOCATION,
148 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
149 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
150 WREG32(R_000134_HDP_FB_LOCATION,
151 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
152 if (rdev->flags & RADEON_IS_AGP) {
153 WREG32_MC(R_000005_MC_AGP_LOCATION,
154 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
155 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
156 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
157 WREG32_MC(R_000007_AGP_BASE_2,
158 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
159 } else {
160 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
161 WREG32_MC(R_000006_AGP_BASE, 0);
162 WREG32_MC(R_000007_AGP_BASE_2, 0);
163 }
164
165 rv515_mc_resume(rdev, &save);
166}
167
168static int r520_startup(struct radeon_device *rdev)
169{
170 int r;
171
172 r520_mc_program(rdev);
173 /* Resume clock */
174 rv515_clock_startup(rdev);
175 /* Initialize GPU configuration (# pipes, ...) */
176 r520_gpu_init(rdev);
177 /* Initialize GART (initialize after TTM so we can allocate
178 * memory through TTM but finalize after TTM) */
179 if (rdev->flags & RADEON_IS_PCIE) {
180 r = rv370_pcie_gart_enable(rdev);
181 if (r)
182 return r;
183 }
Alex Deucher724c80e2010-08-27 18:25:25 -0400184
185 /* allocate wb buffer */
186 r = radeon_wb_init(rdev);
187 if (r)
188 return r;
189
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200190 /* Enable IRQ */
Jerome Glisseac447df2009-09-30 22:18:43 +0200191 rs600_irq_set(rdev);
Jerome Glissecafe6602010-01-07 12:39:21 +0100192 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200193 /* 1M ring buffer */
194 r = r100_cp_init(rdev, 1024 * 1024);
195 if (r) {
Paul Bolleec4f2ac2011-01-28 23:32:04 +0100196 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200197 return r;
198 }
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200199 r = r100_ib_init(rdev);
200 if (r) {
Paul Bolleec4f2ac2011-01-28 23:32:04 +0100201 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200202 return r;
203 }
204 return 0;
205}
206
207int r520_resume(struct radeon_device *rdev)
208{
209 /* Make sur GART are not working */
210 if (rdev->flags & RADEON_IS_PCIE)
211 rv370_pcie_gart_disable(rdev);
212 /* Resume clock before doing reset */
213 rv515_clock_startup(rdev);
214 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
Jerome Glissea2d07b72010-03-09 14:45:11 +0000215 if (radeon_asic_reset(rdev)) {
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200216 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
217 RREG32(R_000E40_RBBM_STATUS),
218 RREG32(R_0007C0_CP_STAT));
219 }
220 /* post */
221 atom_asic_init(rdev->mode_info.atom_context);
222 /* Resume clock after posting */
223 rv515_clock_startup(rdev);
Dave Airlie550e2d92009-12-09 14:15:38 +1000224 /* Initialize surface registers */
225 radeon_surface_init(rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200226 return r520_startup(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200227}
Jerome Glissed39c3b82009-09-28 18:34:43 +0200228
229int r520_init(struct radeon_device *rdev)
230{
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200231 int r;
232
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200233 /* Initialize scratch registers */
234 radeon_scratch_init(rdev);
235 /* Initialize surface registers */
236 radeon_surface_init(rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000237 /* restore some register to sane defaults */
238 r100_restore_sanity(rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200239 /* TODO: disable VGA need to use VGA request */
240 /* BIOS*/
241 if (!radeon_get_bios(rdev)) {
242 if (ASIC_IS_AVIVO(rdev))
243 return -EINVAL;
244 }
245 if (rdev->is_atom_bios) {
246 r = radeon_atombios_init(rdev);
247 if (r)
248 return r;
249 } else {
250 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
251 return -EINVAL;
252 }
253 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
Jerome Glissea2d07b72010-03-09 14:45:11 +0000254 if (radeon_asic_reset(rdev)) {
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200255 dev_warn(rdev->dev,
256 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
257 RREG32(R_000E40_RBBM_STATUS),
258 RREG32(R_0007C0_CP_STAT));
259 }
260 /* check if cards are posted or not */
Dave Airlie72542d72009-12-01 14:06:31 +1000261 if (radeon_boot_test_post_card(rdev) == false)
262 return -EINVAL;
263
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200264 if (!radeon_card_posted(rdev) && rdev->bios) {
265 DRM_INFO("GPU not posted. posting now...\n");
266 atom_asic_init(rdev->mode_info.atom_context);
267 }
268 /* Initialize clocks */
269 radeon_get_clock_info(rdev->ddev);
Jerome Glissed594e462010-02-17 21:54:29 +0000270 /* initialize AGP */
271 if (rdev->flags & RADEON_IS_AGP) {
272 r = radeon_agp_init(rdev);
273 if (r) {
274 radeon_agp_disable(rdev);
275 }
276 }
277 /* initialize memory controller */
278 r520_mc_init(rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200279 rv515_debugfs(rdev);
280 /* Fence driver */
281 r = radeon_fence_driver_init(rdev);
282 if (r)
283 return r;
284 r = radeon_irq_kms_init(rdev);
285 if (r)
286 return r;
287 /* Memory manager */
Jerome Glisse4c788672009-11-20 14:29:23 +0100288 r = radeon_bo_init(rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200289 if (r)
290 return r;
291 r = rv370_pcie_gart_init(rdev);
292 if (r)
293 return r;
Jerome Glissed39c3b82009-09-28 18:34:43 +0200294 rv515_set_safe_registers(rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200295 rdev->accel_working = true;
296 r = r520_startup(rdev);
297 if (r) {
298 /* Somethings want wront with the accel init stop accel */
299 dev_err(rdev->dev, "Disabling GPU acceleration\n");
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200300 r100_cp_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400301 radeon_wb_fini(rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200302 r100_ib_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +0100303 radeon_irq_kms_fini(rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200304 rv370_pcie_gart_fini(rdev);
305 radeon_agp_fini(rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200306 rdev->accel_working = false;
307 }
Jerome Glissed39c3b82009-09-28 18:34:43 +0200308 return 0;
309}