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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070042#include <drm/drm_plane_helper.h>
43#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080044#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080045
Matt Roper465c1202014-05-29 08:06:54 -070046/* Primary plane formats supported by all gen */
47#define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53/* Primary plane formats for gen <= 3 */
54static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58};
59
60/* Primary plane formats for gen >= 4 */
61static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69};
70
Matt Roper3d7d6512014-06-10 08:28:13 -070071/* Cursor formats */
72static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74};
75
Chon Ming Leeef9348c2014-04-09 13:28:18 +030076#define DIV_ROUND_CLOSEST_ULL(ll, d) \
Matt Roper465c1202014-05-29 08:06:54 -070077({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
Chon Ming Leeef9348c2014-04-09 13:28:18 +030078
Daniel Vettercc365132014-06-18 13:59:13 +020079static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +010081static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080082
Jesse Barnesf1f644d2013-06-27 00:39:25 +030083static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030085static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030087
Damien Lespiaue7457a92013-08-08 22:28:59 +010088static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080090static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020094static void intel_dp_set_m_n(struct intel_crtc *crtc);
95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020097static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +0200100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +0200102static void vlv_prepare_pll(struct intel_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100103
Jesse Barnes79e53942008-11-07 14:24:08 -0800104typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400105 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800106} intel_range_t;
107
108typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400109 int dot_limit;
110 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800111} intel_p2_t;
112
Ma Lingd4906092009-03-18 20:13:27 +0800113typedef struct intel_limit intel_limit_t;
114struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400115 intel_range_t dot, vco, n, m, m1, m2, p, p1;
116 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800117};
Jesse Barnes79e53942008-11-07 14:24:08 -0800118
Daniel Vetterd2acd212012-10-20 20:57:43 +0200119int
120intel_pch_rawclk(struct drm_device *dev)
121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 WARN_ON(!HAS_PCH_SPLIT(dev));
125
126 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
127}
128
Chris Wilson021357a2010-09-07 20:54:59 +0100129static inline u32 /* units of 100MHz */
130intel_fdi_link_freq(struct drm_device *dev)
131{
Chris Wilson8b99e682010-10-13 09:59:17 +0100132 if (IS_GEN5(dev)) {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135 } else
136 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100137}
138
Daniel Vetter5d536e22013-07-06 12:52:06 +0200139static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400140 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200141 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200142 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400143 .m = { .min = 96, .max = 140 },
144 .m1 = { .min = 18, .max = 26 },
145 .m2 = { .min = 6, .max = 16 },
146 .p = { .min = 4, .max = 128 },
147 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700148 .p2 = { .dot_limit = 165000,
149 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700150};
151
Daniel Vetter5d536e22013-07-06 12:52:06 +0200152static const intel_limit_t intel_limits_i8xx_dvo = {
153 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200154 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200155 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 4 },
163};
164
Keith Packarde4b36692009-06-05 19:22:17 -0700165static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400166 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200167 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200168 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700176};
Eric Anholt273e27c2011-03-30 13:01:10 -0700177
Keith Packarde4b36692009-06-05 19:22:17 -0700178static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400179 .dot = { .min = 20000, .max = 400000 },
180 .vco = { .min = 1400000, .max = 2800000 },
181 .n = { .min = 1, .max = 6 },
182 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100183 .m1 = { .min = 8, .max = 18 },
184 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700187 .p2 = { .dot_limit = 200000,
188 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700189};
190
191static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400198 .p = { .min = 7, .max = 98 },
199 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700200 .p2 = { .dot_limit = 112000,
201 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700202};
203
Eric Anholt273e27c2011-03-30 13:01:10 -0700204
Keith Packarde4b36692009-06-05 19:22:17 -0700205static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700206 .dot = { .min = 25000, .max = 270000 },
207 .vco = { .min = 1750000, .max = 3500000},
208 .n = { .min = 1, .max = 4 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 10, .max = 30 },
213 .p1 = { .min = 1, .max = 3},
214 .p2 = { .dot_limit = 270000,
215 .p2_slow = 10,
216 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800217 },
Keith Packarde4b36692009-06-05 19:22:17 -0700218};
219
220static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700221 .dot = { .min = 22000, .max = 400000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 16, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8},
229 .p2 = { .dot_limit = 165000,
230 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700231};
232
233static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700234 .dot = { .min = 20000, .max = 115000 },
235 .vco = { .min = 1750000, .max = 3500000 },
236 .n = { .min = 1, .max = 3 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 17, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 28, .max = 112 },
241 .p1 = { .min = 2, .max = 8 },
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800244 },
Keith Packarde4b36692009-06-05 19:22:17 -0700245};
246
247static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700248 .dot = { .min = 80000, .max = 224000 },
249 .vco = { .min = 1750000, .max = 3500000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 14, .max = 42 },
255 .p1 = { .min = 2, .max = 6 },
256 .p2 = { .dot_limit = 0,
257 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800258 },
Keith Packarde4b36692009-06-05 19:22:17 -0700259};
260
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500261static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400262 .dot = { .min = 20000, .max = 400000},
263 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700264 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400265 .n = { .min = 3, .max = 6 },
266 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700267 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700274};
275
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500276static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1700000, .max = 3500000 },
279 .n = { .min = 3, .max = 6 },
280 .m = { .min = 2, .max = 256 },
281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 7, .max = 112 },
284 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700287};
288
Eric Anholt273e27c2011-03-30 13:01:10 -0700289/* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800294static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700305};
306
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800307static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 79, .max = 118 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 28, .max = 112 },
315 .p1 = { .min = 2, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800331};
332
Eric Anholt273e27c2011-03-30 13:01:10 -0700333/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800334static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 2 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400342 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400355 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800358};
359
Ville Syrjälädc730512013-09-24 21:26:30 +0300360static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300361 /*
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
366 */
367 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200368 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700369 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700370 .m1 = { .min = 2, .max = 3 },
371 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300372 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300373 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700374};
375
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300376static const intel_limit_t intel_limits_chv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 540000 * 5},
384 .vco = { .min = 4860000, .max = 6700000 },
385 .n = { .min = 1, .max = 1 },
386 .m1 = { .min = 2, .max = 2 },
387 .m2 = { .min = 24 << 22, .max = 175 << 22 },
388 .p1 = { .min = 2, .max = 4 },
389 .p2 = { .p2_slow = 1, .p2_fast = 14 },
390};
391
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300392static void vlv_clock(int refclk, intel_clock_t *clock)
393{
394 clock->m = clock->m1 * clock->m2;
395 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200396 if (WARN_ON(clock->n == 0 || clock->p == 0))
397 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300398 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
399 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300400}
401
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300402/**
403 * Returns whether any output on the specified pipe is of the specified type
404 */
405static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
406{
407 struct drm_device *dev = crtc->dev;
408 struct intel_encoder *encoder;
409
410 for_each_encoder_on_crtc(dev, crtc, encoder)
411 if (encoder->type == type)
412 return true;
413
414 return false;
415}
416
Chris Wilson1b894b52010-12-14 20:04:54 +0000417static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
418 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800419{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800420 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800421 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800422
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100424 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000425 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800426 limit = &intel_limits_ironlake_dual_lvds_100m;
427 else
428 limit = &intel_limits_ironlake_dual_lvds;
429 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000430 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800431 limit = &intel_limits_ironlake_single_lvds_100m;
432 else
433 limit = &intel_limits_ironlake_single_lvds;
434 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200435 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800436 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800437
438 return limit;
439}
440
Ma Ling044c7c42009-03-18 20:13:23 +0800441static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
442{
443 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800444 const intel_limit_t *limit;
445
446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100447 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700448 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800449 else
Keith Packarde4b36692009-06-05 19:22:17 -0700450 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800451 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
452 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700453 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800454 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700455 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800456 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700457 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800458
459 return limit;
460}
461
Chris Wilson1b894b52010-12-14 20:04:54 +0000462static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800463{
464 struct drm_device *dev = crtc->dev;
465 const intel_limit_t *limit;
466
Eric Anholtbad720f2009-10-22 16:11:14 -0700467 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000468 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800469 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800470 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500471 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500473 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800474 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500475 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300476 } else if (IS_CHERRYVIEW(dev)) {
477 limit = &intel_limits_chv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700478 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300479 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100480 } else if (!IS_GEN2(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_i9xx_lvds;
483 else
484 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800485 } else {
486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700487 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700489 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200490 else
491 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800492 }
493 return limit;
494}
495
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500496/* m1 is reserved as 0 in Pineview, n is a ring counter */
497static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800498{
Shaohua Li21778322009-02-23 15:19:16 +0800499 clock->m = clock->m2 + 2;
500 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200501 if (WARN_ON(clock->n == 0 || clock->p == 0))
502 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300503 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
504 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800505}
506
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200507static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
508{
509 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
510}
511
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200512static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800513{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200514 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800515 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200516 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
517 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800520}
521
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300522static void chv_clock(int refclk, intel_clock_t *clock)
523{
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return;
528 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
529 clock->n << 22);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531}
532
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800533#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800534/**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
Chris Wilson1b894b52010-12-14 20:04:54 +0000539static bool intel_PLL_is_valid(struct drm_device *dev,
540 const intel_limit_t *limit,
541 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800542{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400546 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400548 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400550 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300551
552 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
553 if (clock->m1 <= clock->m2)
554 INTELPllInvalid("m1 <= m2\n");
555
556 if (!IS_VALLEYVIEW(dev)) {
557 if (clock->p < limit->p.min || limit->p.max < clock->p)
558 INTELPllInvalid("p out of range\n");
559 if (clock->m < limit->m.min || limit->m.max < clock->m)
560 INTELPllInvalid("m out of range\n");
561 }
562
Jesse Barnes79e53942008-11-07 14:24:08 -0800563 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400564 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
567 */
568 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400569 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800570
571 return true;
572}
573
Ma Lingd4906092009-03-18 20:13:27 +0800574static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200575i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800576 int target, int refclk, intel_clock_t *match_clock,
577 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800578{
579 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800580 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800581 int err = target;
582
Daniel Vettera210b022012-11-26 17:22:08 +0100583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800584 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800588 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100589 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800590 clock.p2 = limit->p2.p2_fast;
591 else
592 clock.p2 = limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 clock.p2 = limit->p2.p2_slow;
596 else
597 clock.p2 = limit->p2.p2_fast;
598 }
599
Akshay Joshi0206e352011-08-16 15:34:10 -0400600 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800601
Zhao Yakui42158662009-11-20 11:24:18 +0800602 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
603 clock.m1++) {
604 for (clock.m2 = limit->m2.min;
605 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200606 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800607 break;
608 for (clock.n = limit->n.min;
609 clock.n <= limit->n.max; clock.n++) {
610 for (clock.p1 = limit->p1.min;
611 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800612 int this_err;
613
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200614 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000615 if (!intel_PLL_is_valid(dev, limit,
616 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800617 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800618 if (match_clock &&
619 clock.p != match_clock->p)
620 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800621
622 this_err = abs(clock.dot - target);
623 if (this_err < err) {
624 *best_clock = clock;
625 err = this_err;
626 }
627 }
628 }
629 }
630 }
631
632 return (err != target);
633}
634
Ma Lingd4906092009-03-18 20:13:27 +0800635static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200636pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
637 int target, int refclk, intel_clock_t *match_clock,
638 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200639{
640 struct drm_device *dev = crtc->dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200667 for (clock.n = limit->n.min;
668 clock.n <= limit->n.max; clock.n++) {
669 for (clock.p1 = limit->p1.min;
670 clock.p1 <= limit->p1.max; clock.p1++) {
671 int this_err;
672
673 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800674 if (!intel_PLL_is_valid(dev, limit,
675 &clock))
676 continue;
677 if (match_clock &&
678 clock.p != match_clock->p)
679 continue;
680
681 this_err = abs(clock.dot - target);
682 if (this_err < err) {
683 *best_clock = clock;
684 err = this_err;
685 }
686 }
687 }
688 }
689 }
690
691 return (err != target);
692}
693
Ma Lingd4906092009-03-18 20:13:27 +0800694static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200695g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
696 int target, int refclk, intel_clock_t *match_clock,
697 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800698{
699 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800700 intel_clock_t clock;
701 int max_n;
702 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400703 /* approximately equals target * 0.00585 */
704 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800705 found = false;
706
707 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100708 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200721 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200723 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200732 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800735 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000736
737 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800738 if (this_err < err_most) {
739 *best_clock = clock;
740 err_most = this_err;
741 max_n = clock.n;
742 found = true;
743 }
744 }
745 }
746 }
747 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800748 return found;
749}
Ma Lingd4906092009-03-18 20:13:27 +0800750
Zhenyu Wang2c072452009-06-05 15:38:42 +0800751static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200752vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
753 int target, int refclk, intel_clock_t *match_clock,
754 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700755{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300756 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300757 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300758 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300759 /* min update 19.2 MHz */
760 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300761 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700762
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300763 target *= 5; /* fast clock */
764
765 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700766
767 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300768 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300769 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300770 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300771 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300772 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700773 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300774 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300775 unsigned int ppm, diff;
776
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300777 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
778 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300779
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300780 vlv_clock(refclk, &clock);
781
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300784 continue;
785
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300786 diff = abs(clock.dot - target);
787 ppm = div_u64(1000000ULL * diff, target);
788
789 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300790 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300791 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300792 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300793 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300794
Ville Syrjäläc6861222013-09-24 21:26:21 +0300795 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300796 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300797 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300798 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700799 }
800 }
801 }
802 }
803 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700804
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300805 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700806}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700807
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300808static bool
809chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815 uint64_t m2;
816 int found = false;
817
818 memset(best_clock, 0, sizeof(*best_clock));
819
820 /*
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
824 */
825 clock.n = 1, clock.m1 = 2;
826 target *= 5; /* fast clock */
827
828 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
829 for (clock.p2 = limit->p2.p2_fast;
830 clock.p2 >= limit->p2.p2_slow;
831 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
832
833 clock.p = clock.p1 * clock.p2;
834
835 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
836 clock.n) << 22, refclk * clock.m1);
837
838 if (m2 > INT_MAX/clock.m1)
839 continue;
840
841 clock.m2 = m2;
842
843 chv_clock(refclk, &clock);
844
845 if (!intel_PLL_is_valid(dev, limit, &clock))
846 continue;
847
848 /* based on hardware requirement, prefer bigger p
849 */
850 if (clock.p > best_clock->p) {
851 *best_clock = clock;
852 found = true;
853 }
854 }
855 }
856
857 return found;
858}
859
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300860bool intel_crtc_active(struct drm_crtc *crtc)
861{
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
866 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100867 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300868 * as Haswell has gained clock readout/fastboot support.
869 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000870 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300871 * properly reconstruct framebuffers.
872 */
Matt Roperf4510a22014-04-01 15:22:40 -0700873 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100874 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300875}
876
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200877enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
Daniel Vetter3b117c82013-04-17 20:15:07 +0200883 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200884}
885
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200886static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
Paulo Zanonia928d532012-05-04 17:18:15 -0300887{
888 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200889 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
Jesse Barnes93937072014-04-04 16:12:09 -0700894 WARN(1, "vblank wait timed out\n");
Paulo Zanonia928d532012-05-04 17:18:15 -0300895}
896
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700897/**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800906{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700907 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800908 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700909
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200910 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
911 g4x_wait_for_vblank(dev, pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300912 return;
913 }
914
Chris Wilson300387c2010-09-05 20:25:43 +0100915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700931 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700935 DRM_DEBUG_KMS("vblank wait timed out\n");
936}
937
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300938static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
939{
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 reg = PIPEDSL(pipe);
942 u32 line1, line2;
943 u32 line_mask;
944
945 if (IS_GEN2(dev))
946 line_mask = DSL_LINEMASK_GEN2;
947 else
948 line_mask = DSL_LINEMASK_GEN3;
949
950 line1 = I915_READ(reg) & line_mask;
951 mdelay(5);
952 line2 = I915_READ(reg) & line_mask;
953
954 return line1 == line2;
955}
956
Keith Packardab7ad7f2010-10-03 00:33:06 -0700957/*
958 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700959 * @dev: drm device
960 * @pipe: pipe to wait for
961 *
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
965 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700966 * On Gen4 and above:
967 * wait for the pipe register state bit to turn off
968 *
969 * Otherwise:
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100972 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700973 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100974void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700975{
976 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700979
Keith Packardab7ad7f2010-10-03 00:33:06 -0700980 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200981 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700982
Keith Packardab7ad7f2010-10-03 00:33:06 -0700983 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100984 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
985 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200986 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700987 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700988 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300989 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200990 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700991 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800992}
993
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000994/*
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
998 *
999 * Returns true if @port is connected, false otherwise.
1000 */
1001bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002 struct intel_digital_port *port)
1003{
1004 u32 bit;
1005
Damien Lespiauc36346e2012-12-13 16:09:03 +00001006 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +02001007 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001008 case PORT_B:
1009 bit = SDE_PORTB_HOTPLUG;
1010 break;
1011 case PORT_C:
1012 bit = SDE_PORTC_HOTPLUG;
1013 break;
1014 case PORT_D:
1015 bit = SDE_PORTD_HOTPLUG;
1016 break;
1017 default:
1018 return true;
1019 }
1020 } else {
Robin Schroereba905b2014-05-18 02:24:50 +02001021 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001022 case PORT_B:
1023 bit = SDE_PORTB_HOTPLUG_CPT;
1024 break;
1025 case PORT_C:
1026 bit = SDE_PORTC_HOTPLUG_CPT;
1027 break;
1028 case PORT_D:
1029 bit = SDE_PORTD_HOTPLUG_CPT;
1030 break;
1031 default:
1032 return true;
1033 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001034 }
1035
1036 return I915_READ(SDEISR) & bit;
1037}
1038
Jesse Barnesb24e7172011-01-04 15:09:30 -08001039static const char *state_string(bool enabled)
1040{
1041 return enabled ? "on" : "off";
1042}
1043
1044/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001045void assert_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001047{
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = DPLL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & DPLL_VCO_ENABLE);
1055 WARN(cur_state != state,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001059
Jani Nikula23538ef2013-08-27 15:12:22 +03001060/* XXX: the dsi pll is shared between MIPI DSI ports */
1061static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062{
1063 u32 val;
1064 bool cur_state;
1065
1066 mutex_lock(&dev_priv->dpio_lock);
1067 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068 mutex_unlock(&dev_priv->dpio_lock);
1069
1070 cur_state = val & DSI_PLL_VCO_EN;
1071 WARN(cur_state != state,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state), state_string(cur_state));
1074}
1075#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
Daniel Vetter55607e82013-06-16 21:42:39 +02001078struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001079intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001080{
Daniel Vettere2b78262013-06-07 23:10:03 +02001081 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
Daniel Vettera43f6e02013-06-07 23:10:32 +02001083 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001084 return NULL;
1085
Daniel Vettera43f6e02013-06-07 23:10:32 +02001086 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001087}
1088
Jesse Barnesb24e7172011-01-04 15:09:30 -08001089/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001090void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001093{
Jesse Barnes040484a2011-01-03 12:14:26 -08001094 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001095 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001096
Chris Wilson92b27b02012-05-20 18:10:50 +01001097 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001098 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001099 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001100
Daniel Vetter53589012013-06-05 13:34:16 +02001101 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001102 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001103 "%s assertion failure (expected %s, current %s)\n",
1104 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001105}
Jesse Barnes040484a2011-01-03 12:14:26 -08001106
1107static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109{
1110 int reg;
1111 u32 val;
1112 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001113 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1114 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001115
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001116 if (HAS_DDI(dev_priv->dev)) {
1117 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001118 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001119 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001120 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001121 } else {
1122 reg = FDI_TX_CTL(pipe);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & FDI_TX_ENABLE);
1125 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001126 WARN(cur_state != state,
1127 "FDI TX state assertion failure (expected %s, current %s)\n",
1128 state_string(state), state_string(cur_state));
1129}
1130#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1131#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1132
1133static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1134 enum pipe pipe, bool state)
1135{
1136 int reg;
1137 u32 val;
1138 bool cur_state;
1139
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001140 reg = FDI_RX_CTL(pipe);
1141 val = I915_READ(reg);
1142 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001143 WARN(cur_state != state,
1144 "FDI RX state assertion failure (expected %s, current %s)\n",
1145 state_string(state), state_string(cur_state));
1146}
1147#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1148#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1149
1150static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1151 enum pipe pipe)
1152{
1153 int reg;
1154 u32 val;
1155
1156 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001157 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001158 return;
1159
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001160 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001161 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001162 return;
1163
Jesse Barnes040484a2011-01-03 12:14:26 -08001164 reg = FDI_TX_CTL(pipe);
1165 val = I915_READ(reg);
1166 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1167}
1168
Daniel Vetter55607e82013-06-16 21:42:39 +02001169void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001171{
1172 int reg;
1173 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001174 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001175
1176 reg = FDI_RX_CTL(pipe);
1177 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001178 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1179 WARN(cur_state != state,
1180 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1181 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001182}
1183
Jesse Barnesea0760c2011-01-04 15:09:32 -08001184static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
1187 int pp_reg, lvds_reg;
1188 u32 val;
1189 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001190 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001191
1192 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1193 pp_reg = PCH_PP_CONTROL;
1194 lvds_reg = PCH_LVDS;
1195 } else {
1196 pp_reg = PP_CONTROL;
1197 lvds_reg = LVDS;
1198 }
1199
1200 val = I915_READ(pp_reg);
1201 if (!(val & PANEL_POWER_ON) ||
1202 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1203 locked = false;
1204
1205 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1206 panel_pipe = PIPE_B;
1207
1208 WARN(panel_pipe == pipe && locked,
1209 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001210 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001211}
1212
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001213static void assert_cursor(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215{
1216 struct drm_device *dev = dev_priv->dev;
1217 bool cur_state;
1218
Paulo Zanonid9d82082014-02-27 16:30:56 -03001219 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001220 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001221 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001222 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001223
1224 WARN(cur_state != state,
1225 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1226 pipe_name(pipe), state_string(state), state_string(cur_state));
1227}
1228#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1229#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1230
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001231void assert_pipe(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001233{
1234 int reg;
1235 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001236 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001237 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1238 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001239
Daniel Vetter8e636782012-01-22 01:36:48 +01001240 /* if we need the pipe A quirk it must be always on */
1241 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1242 state = true;
1243
Imre Deakda7e29b2014-02-18 00:02:02 +02001244 if (!intel_display_power_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001245 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001246 cur_state = false;
1247 } else {
1248 reg = PIPECONF(cpu_transcoder);
1249 val = I915_READ(reg);
1250 cur_state = !!(val & PIPECONF_ENABLE);
1251 }
1252
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001253 WARN(cur_state != state,
1254 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001255 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001256}
1257
Chris Wilson931872f2012-01-16 23:01:13 +00001258static void assert_plane(struct drm_i915_private *dev_priv,
1259 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001260{
1261 int reg;
1262 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001263 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001264
1265 reg = DSPCNTR(plane);
1266 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001267 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1268 WARN(cur_state != state,
1269 "plane %c assertion failure (expected %s, current %s)\n",
1270 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001271}
1272
Chris Wilson931872f2012-01-16 23:01:13 +00001273#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1274#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1275
Jesse Barnesb24e7172011-01-04 15:09:30 -08001276static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe)
1278{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001279 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001280 int reg, i;
1281 u32 val;
1282 int cur_pipe;
1283
Ville Syrjälä653e1022013-06-04 13:49:05 +03001284 /* Primary planes are fixed to pipes on gen4+ */
1285 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001286 reg = DSPCNTR(pipe);
1287 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001288 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001289 "plane %c assertion failure, should be disabled but not\n",
1290 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001291 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001292 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001293
Jesse Barnesb24e7172011-01-04 15:09:30 -08001294 /* Need to check both planes against the pipe */
Damien Lespiau08e2a7d2013-07-11 20:10:54 +01001295 for_each_pipe(i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001296 reg = DSPCNTR(i);
1297 val = I915_READ(reg);
1298 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1299 DISPPLANE_SEL_PIPE_SHIFT;
1300 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001301 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1302 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001303 }
1304}
1305
Jesse Barnes19332d72013-03-28 09:55:38 -07001306static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe)
1308{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001309 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001310 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001311 u32 val;
1312
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001313 if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001314 for_each_sprite(pipe, sprite) {
1315 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001316 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001317 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001319 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001320 }
1321 } else if (INTEL_INFO(dev)->gen >= 7) {
1322 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001323 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001324 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001325 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001326 plane_name(pipe), pipe_name(pipe));
1327 } else if (INTEL_INFO(dev)->gen >= 5) {
1328 reg = DVSCNTR(pipe);
1329 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001330 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001331 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1332 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001333 }
1334}
1335
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001336static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001337{
1338 u32 val;
1339 bool enabled;
1340
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001341 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001342
Jesse Barnes92f25842011-01-04 15:09:34 -08001343 val = I915_READ(PCH_DREF_CONTROL);
1344 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1345 DREF_SUPERSPREAD_SOURCE_MASK));
1346 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1347}
1348
Daniel Vetterab9412b2013-05-03 11:49:46 +02001349static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001351{
1352 int reg;
1353 u32 val;
1354 bool enabled;
1355
Daniel Vetterab9412b2013-05-03 11:49:46 +02001356 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001357 val = I915_READ(reg);
1358 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001359 WARN(enabled,
1360 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1361 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001362}
1363
Keith Packard4e634382011-08-06 10:39:45 -07001364static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001366{
1367 if ((val & DP_PORT_EN) == 0)
1368 return false;
1369
1370 if (HAS_PCH_CPT(dev_priv->dev)) {
1371 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1372 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1373 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1374 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001375 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1376 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1377 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001378 } else {
1379 if ((val & DP_PIPE_MASK) != (pipe << 30))
1380 return false;
1381 }
1382 return true;
1383}
1384
Keith Packard1519b992011-08-06 10:35:34 -07001385static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, u32 val)
1387{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001388 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001389 return false;
1390
1391 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001392 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001393 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001394 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1395 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1396 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001397 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001398 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001399 return false;
1400 }
1401 return true;
1402}
1403
1404static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe, u32 val)
1406{
1407 if ((val & LVDS_PORT_EN) == 0)
1408 return false;
1409
1410 if (HAS_PCH_CPT(dev_priv->dev)) {
1411 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1412 return false;
1413 } else {
1414 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1415 return false;
1416 }
1417 return true;
1418}
1419
1420static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, u32 val)
1422{
1423 if ((val & ADPA_DAC_ENABLE) == 0)
1424 return false;
1425 if (HAS_PCH_CPT(dev_priv->dev)) {
1426 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1427 return false;
1428 } else {
1429 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1430 return false;
1431 }
1432 return true;
1433}
1434
Jesse Barnes291906f2011-02-02 12:28:03 -08001435static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001436 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001437{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001438 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001439 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001440 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001441 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001442
Daniel Vetter75c5da22012-09-10 21:58:29 +02001443 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1444 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001445 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001446}
1447
1448static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1449 enum pipe pipe, int reg)
1450{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001451 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001452 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001453 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001454 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001455
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001456 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001457 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001458 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001459}
1460
1461static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe)
1463{
1464 int reg;
1465 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001466
Keith Packardf0575e92011-07-25 22:12:43 -07001467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001470
1471 reg = PCH_ADPA;
1472 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001473 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001474 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001475 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001476
1477 reg = PCH_LVDS;
1478 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001479 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001480 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001481 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001482
Paulo Zanonie2debe92013-02-18 19:00:27 -03001483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001486}
1487
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001488static void intel_init_dpio(struct drm_device *dev)
1489{
1490 struct drm_i915_private *dev_priv = dev->dev_private;
1491
1492 if (!IS_VALLEYVIEW(dev))
1493 return;
1494
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001495 /*
1496 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1497 * CHV x1 PHY (DP/HDMI D)
1498 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1499 */
1500 if (IS_CHERRYVIEW(dev)) {
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1502 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1503 } else {
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1505 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001506}
1507
1508static void intel_reset_dpio(struct drm_device *dev)
1509{
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001512 if (IS_CHERRYVIEW(dev)) {
1513 enum dpio_phy phy;
1514 u32 val;
1515
1516 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1517 /* Poll for phypwrgood signal */
1518 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1519 PHY_POWERGOOD(phy), 1))
1520 DRM_ERROR("Display PHY %d is not power up\n", phy);
1521
1522 /*
1523 * Deassert common lane reset for PHY.
1524 *
1525 * This should only be done on init and resume from S3
1526 * with both PLLs disabled, or we risk losing DPIO and
1527 * PLL synchronization.
1528 */
1529 val = I915_READ(DISPLAY_PHY_CONTROL);
1530 I915_WRITE(DISPLAY_PHY_CONTROL,
1531 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1532 }
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001533 }
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001534}
1535
Daniel Vetter426115c2013-07-11 22:13:42 +02001536static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001537{
Daniel Vetter426115c2013-07-11 22:13:42 +02001538 struct drm_device *dev = crtc->base.dev;
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 int reg = DPLL(crtc->pipe);
1541 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001542
Daniel Vetter426115c2013-07-11 22:13:42 +02001543 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001544
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001545 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001546 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1547
1548 /* PLL is protected by panel, make sure we can write it */
1549 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001550 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001551
Daniel Vetter426115c2013-07-11 22:13:42 +02001552 I915_WRITE(reg, dpll);
1553 POSTING_READ(reg);
1554 udelay(150);
1555
1556 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1557 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1558
1559 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1560 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001561
1562 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001563 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001564 POSTING_READ(reg);
1565 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001566 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001569 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001570 POSTING_READ(reg);
1571 udelay(150); /* wait for warmup */
1572}
1573
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001574static void chv_enable_pll(struct intel_crtc *crtc)
1575{
1576 struct drm_device *dev = crtc->base.dev;
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 int pipe = crtc->pipe;
1579 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001580 u32 tmp;
1581
1582 assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1585
1586 mutex_lock(&dev_priv->dpio_lock);
1587
1588 /* Enable back the 10bit clock to display controller */
1589 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1590 tmp |= DPIO_DCLKP_EN;
1591 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1592
1593 /*
1594 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1595 */
1596 udelay(1);
1597
1598 /* Enable PLL */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001599 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001600
1601 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001602 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001603 DRM_ERROR("PLL %d failed to lock\n", pipe);
1604
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001605 /* not sure when this should be written */
1606 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1607 POSTING_READ(DPLL_MD(pipe));
1608
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001609 mutex_unlock(&dev_priv->dpio_lock);
1610}
1611
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001612static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001613{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 int reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001618
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001619 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001620
1621 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001622 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001623
1624 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001625 if (IS_MOBILE(dev) && !IS_I830(dev))
1626 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001627
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001628 I915_WRITE(reg, dpll);
1629
1630 /* Wait for the clocks to stabilize. */
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (INTEL_INFO(dev)->gen >= 4) {
1635 I915_WRITE(DPLL_MD(crtc->pipe),
1636 crtc->config.dpll_hw_state.dpll_md);
1637 } else {
1638 /* The pixel multiplier can only be updated once the
1639 * DPLL is enabled and the clocks are stable.
1640 *
1641 * So write it again.
1642 */
1643 I915_WRITE(reg, dpll);
1644 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001645
1646 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001647 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001650 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001653 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656}
1657
1658/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001659 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001660 * @dev_priv: i915 private structure
1661 * @pipe: pipe PLL to disable
1662 *
1663 * Disable the PLL for @pipe, making sure the pipe is off first.
1664 *
1665 * Note! This is for pre-ILK only.
1666 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001667static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001668{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001669 /* Don't disable pipe A or pipe A PLLs if needed */
1670 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1671 return;
1672
1673 /* Make sure the pipe isn't still relying on us */
1674 assert_pipe_disabled(dev_priv, pipe);
1675
Daniel Vetter50b44a42013-06-05 13:34:33 +02001676 I915_WRITE(DPLL(pipe), 0);
1677 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001678}
1679
Jesse Barnesf6071162013-10-01 10:41:38 -07001680static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1681{
1682 u32 val = 0;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
Imre Deake5cbfbf2014-01-09 17:08:16 +02001687 /*
1688 * Leave integrated clock source and reference clock enabled for pipe B.
1689 * The latter is needed for VGA hotplug / manual detection.
1690 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001691 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001692 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001693 I915_WRITE(DPLL(pipe), val);
1694 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001695
1696}
1697
1698static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1699{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001700 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001701 u32 val;
1702
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001703 /* Make sure the pipe isn't still relying on us */
1704 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001705
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001706 /* Set PLL en = 0 */
1707 val = DPLL_SSC_REF_CLOCK_CHV;
1708 if (pipe != PIPE_A)
1709 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1710 I915_WRITE(DPLL(pipe), val);
1711 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001712
1713 mutex_lock(&dev_priv->dpio_lock);
1714
1715 /* Disable 10bit clock to display controller */
1716 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1717 val &= ~DPIO_DCLKP_EN;
1718 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1719
Ville Syrjälä61407f62014-05-27 16:32:55 +03001720 /* disable left/right clock distribution */
1721 if (pipe != PIPE_B) {
1722 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1723 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1724 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1725 } else {
1726 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1727 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1728 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1729 }
1730
Ville Syrjäläd7520482014-04-09 13:28:59 +03001731 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001732}
1733
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001734void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1735 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001736{
1737 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001738 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001739
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001740 switch (dport->port) {
1741 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001742 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001743 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001744 break;
1745 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001746 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001747 dpll_reg = DPLL(0);
1748 break;
1749 case PORT_D:
1750 port_mask = DPLL_PORTD_READY_MASK;
1751 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001752 break;
1753 default:
1754 BUG();
1755 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001756
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001757 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001758 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001759 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001760}
1761
Daniel Vetterb14b1052014-04-24 23:55:13 +02001762static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1763{
1764 struct drm_device *dev = crtc->base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1767
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001768 if (WARN_ON(pll == NULL))
1769 return;
1770
Daniel Vetterb14b1052014-04-24 23:55:13 +02001771 WARN_ON(!pll->refcount);
1772 if (pll->active == 0) {
1773 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1774 WARN_ON(pll->on);
1775 assert_shared_dpll_disabled(dev_priv, pll);
1776
1777 pll->mode_set(dev_priv, pll);
1778 }
1779}
1780
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001781/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001782 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001783 * @dev_priv: i915 private structure
1784 * @pipe: pipe PLL to enable
1785 *
1786 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1787 * drives the transcoder clock.
1788 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001789static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001790{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001791 struct drm_device *dev = crtc->base.dev;
1792 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001793 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001794
Daniel Vetter87a875b2013-06-05 13:34:19 +02001795 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001796 return;
1797
1798 if (WARN_ON(pll->refcount == 0))
1799 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001800
Daniel Vetter46edb022013-06-05 13:34:12 +02001801 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1802 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001803 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001804
Daniel Vettercdbd2312013-06-05 13:34:03 +02001805 if (pll->active++) {
1806 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001807 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001808 return;
1809 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001810 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001811
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001812 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1813
Daniel Vetter46edb022013-06-05 13:34:12 +02001814 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001815 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001816 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001817}
1818
Daniel Vetter716c2e52014-06-25 22:02:02 +03001819void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001820{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001821 struct drm_device *dev = crtc->base.dev;
1822 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001823 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001824
Jesse Barnes92f25842011-01-04 15:09:34 -08001825 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001826 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001827 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001828 return;
1829
Chris Wilson48da64a2012-05-13 20:16:12 +01001830 if (WARN_ON(pll->refcount == 0))
1831 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001832
Daniel Vetter46edb022013-06-05 13:34:12 +02001833 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1834 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001835 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001836
Chris Wilson48da64a2012-05-13 20:16:12 +01001837 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001838 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001839 return;
1840 }
1841
Daniel Vettere9d69442013-06-05 13:34:15 +02001842 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001843 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001844 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001845 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001846
Daniel Vetter46edb022013-06-05 13:34:12 +02001847 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001848 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001849 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001850
1851 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001852}
1853
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001854static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1855 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001856{
Daniel Vetter23670b322012-11-01 09:15:30 +01001857 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001858 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001860 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001861
1862 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001863 BUG_ON(INTEL_INFO(dev)->gen < 5);
Jesse Barnes040484a2011-01-03 12:14:26 -08001864
1865 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001866 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001867 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001868
1869 /* FDI must be feeding us bits for PCH ports */
1870 assert_fdi_tx_enabled(dev_priv, pipe);
1871 assert_fdi_rx_enabled(dev_priv, pipe);
1872
Daniel Vetter23670b322012-11-01 09:15:30 +01001873 if (HAS_PCH_CPT(dev)) {
1874 /* Workaround: Set the timing override bit before enabling the
1875 * pch transcoder. */
1876 reg = TRANS_CHICKEN2(pipe);
1877 val = I915_READ(reg);
1878 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1879 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001880 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001881
Daniel Vetterab9412b2013-05-03 11:49:46 +02001882 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001883 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001884 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001885
1886 if (HAS_PCH_IBX(dev_priv->dev)) {
1887 /*
1888 * make the BPC in transcoder be consistent with
1889 * that in pipeconf reg.
1890 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001891 val &= ~PIPECONF_BPC_MASK;
1892 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001893 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001894
1895 val &= ~TRANS_INTERLACE_MASK;
1896 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001897 if (HAS_PCH_IBX(dev_priv->dev) &&
1898 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1899 val |= TRANS_LEGACY_INTERLACED_ILK;
1900 else
1901 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001902 else
1903 val |= TRANS_PROGRESSIVE;
1904
Jesse Barnes040484a2011-01-03 12:14:26 -08001905 I915_WRITE(reg, val | TRANS_ENABLE);
1906 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001907 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001908}
1909
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001910static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001911 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001912{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001913 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001914
1915 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001916 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001917
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001918 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001919 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001920 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001921
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001922 /* Workaround: set timing override bit. */
1923 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001924 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001925 I915_WRITE(_TRANSA_CHICKEN2, val);
1926
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001927 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001928 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001929
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001930 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1931 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001932 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001933 else
1934 val |= TRANS_PROGRESSIVE;
1935
Daniel Vetterab9412b2013-05-03 11:49:46 +02001936 I915_WRITE(LPT_TRANSCONF, val);
1937 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001938 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001939}
1940
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001941static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001943{
Daniel Vetter23670b322012-11-01 09:15:30 +01001944 struct drm_device *dev = dev_priv->dev;
1945 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001946
1947 /* FDI relies on the transcoder */
1948 assert_fdi_tx_disabled(dev_priv, pipe);
1949 assert_fdi_rx_disabled(dev_priv, pipe);
1950
Jesse Barnes291906f2011-02-02 12:28:03 -08001951 /* Ports must be off as well */
1952 assert_pch_ports_disabled(dev_priv, pipe);
1953
Daniel Vetterab9412b2013-05-03 11:49:46 +02001954 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001955 val = I915_READ(reg);
1956 val &= ~TRANS_ENABLE;
1957 I915_WRITE(reg, val);
1958 /* wait for PCH transcoder off, transcoder state */
1959 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001960 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001961
1962 if (!HAS_PCH_IBX(dev)) {
1963 /* Workaround: Clear the timing override chicken bit again. */
1964 reg = TRANS_CHICKEN2(pipe);
1965 val = I915_READ(reg);
1966 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1967 I915_WRITE(reg, val);
1968 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001969}
1970
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001971static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001972{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001973 u32 val;
1974
Daniel Vetterab9412b2013-05-03 11:49:46 +02001975 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001976 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001977 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001978 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001979 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001980 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001981
1982 /* Workaround: clear timing override bit. */
1983 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001984 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001985 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001986}
1987
1988/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001989 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02001990 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001991 *
Paulo Zanoni03722642014-01-17 13:51:09 -02001992 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001993 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08001994 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02001995static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001996{
Paulo Zanoni03722642014-01-17 13:51:09 -02001997 struct drm_device *dev = crtc->base.dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002000 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2001 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002002 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002003 int reg;
2004 u32 val;
2005
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002006 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002007 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002008 assert_sprites_disabled(dev_priv, pipe);
2009
Paulo Zanoni681e5812012-12-06 11:12:38 -02002010 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002011 pch_transcoder = TRANSCODER_A;
2012 else
2013 pch_transcoder = pipe;
2014
Jesse Barnesb24e7172011-01-04 15:09:30 -08002015 /*
2016 * A pipe without a PLL won't actually be able to drive bits from
2017 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2018 * need the check.
2019 */
2020 if (!HAS_PCH_SPLIT(dev_priv->dev))
Paulo Zanonifbf32182014-01-17 13:51:11 -02002021 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002022 assert_dsi_pll_enabled(dev_priv);
2023 else
2024 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002025 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002026 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002027 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002028 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002029 assert_fdi_tx_pll_enabled(dev_priv,
2030 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002031 }
2032 /* FIXME: assert CPU port conditions for SNB+ */
2033 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002034
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002035 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002036 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002037 if (val & PIPECONF_ENABLE) {
2038 WARN_ON(!(pipe == PIPE_A &&
2039 dev_priv->quirks & QUIRK_PIPEA_FORCE));
Chris Wilson00d70b12011-03-17 07:18:29 +00002040 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002041 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002042
2043 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002044 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002045}
2046
2047/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002048 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002049 * @dev_priv: i915 private structure
2050 * @pipe: pipe to disable
2051 *
2052 * Disable @pipe, making sure that various hardware specific requirements
2053 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2054 *
2055 * @pipe should be %PIPE_A or %PIPE_B.
2056 *
2057 * Will wait until the pipe has shut down before returning.
2058 */
2059static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
2061{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002062 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2063 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002064 int reg;
2065 u32 val;
2066
2067 /*
2068 * Make sure planes won't keep trying to pump pixels to us,
2069 * or we might hang the display.
2070 */
2071 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002072 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002073 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002074
2075 /* Don't disable pipe A or pipe A PLLs if needed */
2076 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2077 return;
2078
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002079 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002080 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002081 if ((val & PIPECONF_ENABLE) == 0)
2082 return;
2083
2084 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002085 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2086}
2087
Keith Packardd74362c2011-07-28 14:47:14 -07002088/*
2089 * Plane regs are double buffered, going from enabled->disabled needs a
2090 * trigger in order to latch. The display address reg provides this.
2091 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002092void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2093 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002094{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002095 struct drm_device *dev = dev_priv->dev;
2096 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002097
2098 I915_WRITE(reg, I915_READ(reg));
2099 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002100}
2101
Jesse Barnesb24e7172011-01-04 15:09:30 -08002102/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002103 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002104 * @dev_priv: i915 private structure
2105 * @plane: plane to enable
2106 * @pipe: pipe being fed
2107 *
2108 * Enable @plane on @pipe, making sure that @pipe is running first.
2109 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002110static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002112{
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002113 struct drm_device *dev = dev_priv->dev;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002114 struct intel_crtc *intel_crtc =
2115 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002116 int reg;
2117 u32 val;
2118
2119 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2120 assert_pipe_enabled(dev_priv, pipe);
2121
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002122 if (intel_crtc->primary_enabled)
2123 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002124
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002125 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002126
Jesse Barnesb24e7172011-01-04 15:09:30 -08002127 reg = DSPCNTR(plane);
2128 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002129 WARN_ON(val & DISPLAY_PLANE_ENABLE);
Chris Wilson00d70b12011-03-17 07:18:29 +00002130
2131 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002132 intel_flush_primary_plane(dev_priv, plane);
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002133
2134 /*
2135 * BDW signals flip done immediately if the plane
2136 * is disabled, even if the plane enable is already
2137 * armed to occur at the next vblank :(
2138 */
2139 if (IS_BROADWELL(dev))
2140 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002141}
2142
Jesse Barnesb24e7172011-01-04 15:09:30 -08002143/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002144 * intel_disable_primary_hw_plane - disable the primary hardware plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002145 * @dev_priv: i915 private structure
2146 * @plane: plane to disable
2147 * @pipe: pipe consuming the data
2148 *
2149 * Disable @plane; should be an independent operation.
2150 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002151static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2152 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002153{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002154 struct intel_crtc *intel_crtc =
2155 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002156 int reg;
2157 u32 val;
2158
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002159 if (!intel_crtc->primary_enabled)
2160 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002161
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002162 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002163
Jesse Barnesb24e7172011-01-04 15:09:30 -08002164 reg = DSPCNTR(plane);
2165 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002166 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
Chris Wilson00d70b12011-03-17 07:18:29 +00002167
2168 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002169 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002170}
2171
Chris Wilson693db182013-03-05 14:52:39 +00002172static bool need_vtd_wa(struct drm_device *dev)
2173{
2174#ifdef CONFIG_INTEL_IOMMU
2175 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2176 return true;
2177#endif
2178 return false;
2179}
2180
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002181static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2182{
2183 int tile_height;
2184
2185 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2186 return ALIGN(height, tile_height);
2187}
2188
Chris Wilson127bd2a2010-07-23 23:32:05 +01002189int
Chris Wilson48b956c2010-09-14 12:50:34 +01002190intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002191 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002192 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002193{
Chris Wilsonce453d82011-02-21 14:43:56 +00002194 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002195 u32 alignment;
2196 int ret;
2197
Matt Roperebcdd392014-07-09 16:22:11 -07002198 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2199
Chris Wilson05394f32010-11-08 19:18:58 +00002200 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002201 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002202 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2203 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002204 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002205 alignment = 4 * 1024;
2206 else
2207 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002208 break;
2209 case I915_TILING_X:
2210 /* pin() will align the object as required by fence */
2211 alignment = 0;
2212 break;
2213 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002214 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002215 return -EINVAL;
2216 default:
2217 BUG();
2218 }
2219
Chris Wilson693db182013-03-05 14:52:39 +00002220 /* Note that the w/a also requires 64 PTE of padding following the
2221 * bo. We currently fill all unused PTE with the shadow page and so
2222 * we should always have valid PTE following the scanout preventing
2223 * the VT-d warning.
2224 */
2225 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2226 alignment = 256 * 1024;
2227
Chris Wilsonce453d82011-02-21 14:43:56 +00002228 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002229 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002230 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002231 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002232
2233 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2234 * fence, whereas 965+ only requires a fence if using
2235 * framebuffer compression. For simplicity, we always install
2236 * a fence as the cost is not that onerous.
2237 */
Chris Wilson06d98132012-04-17 15:31:24 +01002238 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002239 if (ret)
2240 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002241
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002242 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002243
Chris Wilsonce453d82011-02-21 14:43:56 +00002244 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002245 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002246
2247err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002248 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002249err_interruptible:
2250 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002251 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002252}
2253
Chris Wilson1690e1e2011-12-14 13:57:08 +01002254void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2255{
Matt Roperebcdd392014-07-09 16:22:11 -07002256 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2257
Chris Wilson1690e1e2011-12-14 13:57:08 +01002258 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002259 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002260}
2261
Daniel Vetterc2c75132012-07-05 12:17:30 +02002262/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2263 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002264unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2265 unsigned int tiling_mode,
2266 unsigned int cpp,
2267 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002268{
Chris Wilsonbc752862013-02-21 20:04:31 +00002269 if (tiling_mode != I915_TILING_NONE) {
2270 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002271
Chris Wilsonbc752862013-02-21 20:04:31 +00002272 tile_rows = *y / 8;
2273 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002274
Chris Wilsonbc752862013-02-21 20:04:31 +00002275 tiles = *x / (512/cpp);
2276 *x %= 512/cpp;
2277
2278 return tile_rows * pitch * 8 + tiles * 4096;
2279 } else {
2280 unsigned int offset;
2281
2282 offset = *y * pitch + *x * cpp;
2283 *y = 0;
2284 *x = (offset & 4095) / cpp;
2285 return offset & -4096;
2286 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002287}
2288
Jesse Barnes46f297f2014-03-07 08:57:48 -08002289int intel_format_to_fourcc(int format)
2290{
2291 switch (format) {
2292 case DISPPLANE_8BPP:
2293 return DRM_FORMAT_C8;
2294 case DISPPLANE_BGRX555:
2295 return DRM_FORMAT_XRGB1555;
2296 case DISPPLANE_BGRX565:
2297 return DRM_FORMAT_RGB565;
2298 default:
2299 case DISPPLANE_BGRX888:
2300 return DRM_FORMAT_XRGB8888;
2301 case DISPPLANE_RGBX888:
2302 return DRM_FORMAT_XBGR8888;
2303 case DISPPLANE_BGRX101010:
2304 return DRM_FORMAT_XRGB2101010;
2305 case DISPPLANE_RGBX101010:
2306 return DRM_FORMAT_XBGR2101010;
2307 }
2308}
2309
Jesse Barnes484b41d2014-03-07 08:57:55 -08002310static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002311 struct intel_plane_config *plane_config)
2312{
2313 struct drm_device *dev = crtc->base.dev;
2314 struct drm_i915_gem_object *obj = NULL;
2315 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2316 u32 base = plane_config->base;
2317
Chris Wilsonff2652e2014-03-10 08:07:02 +00002318 if (plane_config->size == 0)
2319 return false;
2320
Jesse Barnes46f297f2014-03-07 08:57:48 -08002321 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2322 plane_config->size);
2323 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002324 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002325
2326 if (plane_config->tiled) {
2327 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002328 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002329 }
2330
Dave Airlie66e514c2014-04-03 07:51:54 +10002331 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2332 mode_cmd.width = crtc->base.primary->fb->width;
2333 mode_cmd.height = crtc->base.primary->fb->height;
2334 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002335
2336 mutex_lock(&dev->struct_mutex);
2337
Dave Airlie66e514c2014-04-03 07:51:54 +10002338 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002339 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002340 DRM_DEBUG_KMS("intel fb init failed\n");
2341 goto out_unref_obj;
2342 }
2343
Daniel Vettera071fa02014-06-18 23:28:09 +02002344 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002345 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002346
2347 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2348 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002349
2350out_unref_obj:
2351 drm_gem_object_unreference(&obj->base);
2352 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002353 return false;
2354}
2355
2356static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2357 struct intel_plane_config *plane_config)
2358{
2359 struct drm_device *dev = intel_crtc->base.dev;
2360 struct drm_crtc *c;
2361 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002362 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002363
Dave Airlie66e514c2014-04-03 07:51:54 +10002364 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002365 return;
2366
2367 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2368 return;
2369
Dave Airlie66e514c2014-04-03 07:51:54 +10002370 kfree(intel_crtc->base.primary->fb);
2371 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002372
2373 /*
2374 * Failed to alloc the obj, check to see if we should share
2375 * an fb with another CRTC instead
2376 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002377 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002378 i = to_intel_crtc(c);
2379
2380 if (c == &intel_crtc->base)
2381 continue;
2382
Matt Roper2ff8fde2014-07-08 07:50:07 -07002383 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002384 continue;
2385
Matt Roper2ff8fde2014-07-08 07:50:07 -07002386 obj = intel_fb_obj(c->primary->fb);
2387 if (obj == NULL)
2388 continue;
2389
2390 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Dave Airlie66e514c2014-04-03 07:51:54 +10002391 drm_framebuffer_reference(c->primary->fb);
2392 intel_crtc->base.primary->fb = c->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002393 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002394 break;
2395 }
2396 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002397}
2398
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002399static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2400 struct drm_framebuffer *fb,
2401 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002402{
2403 struct drm_device *dev = crtc->dev;
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002406 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Jesse Barnes81255562010-08-02 12:07:50 -07002407 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002408 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002409 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002410 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002411
Chris Wilson5eddb702010-09-11 13:48:45 +01002412 reg = DSPCNTR(plane);
2413 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002414 /* Mask out pixel format bits in case we change it */
2415 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002416 switch (fb->pixel_format) {
2417 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002418 dspcntr |= DISPPLANE_8BPP;
2419 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002420 case DRM_FORMAT_XRGB1555:
2421 case DRM_FORMAT_ARGB1555:
2422 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002423 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002424 case DRM_FORMAT_RGB565:
2425 dspcntr |= DISPPLANE_BGRX565;
2426 break;
2427 case DRM_FORMAT_XRGB8888:
2428 case DRM_FORMAT_ARGB8888:
2429 dspcntr |= DISPPLANE_BGRX888;
2430 break;
2431 case DRM_FORMAT_XBGR8888:
2432 case DRM_FORMAT_ABGR8888:
2433 dspcntr |= DISPPLANE_RGBX888;
2434 break;
2435 case DRM_FORMAT_XRGB2101010:
2436 case DRM_FORMAT_ARGB2101010:
2437 dspcntr |= DISPPLANE_BGRX101010;
2438 break;
2439 case DRM_FORMAT_XBGR2101010:
2440 case DRM_FORMAT_ABGR2101010:
2441 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002442 break;
2443 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002444 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002445 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002446
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002447 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002448 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002449 dspcntr |= DISPPLANE_TILED;
2450 else
2451 dspcntr &= ~DISPPLANE_TILED;
2452 }
2453
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002454 if (IS_G4X(dev))
2455 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2456
Chris Wilson5eddb702010-09-11 13:48:45 +01002457 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002458
Daniel Vettere506a0c2012-07-05 12:17:29 +02002459 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002460
Daniel Vetterc2c75132012-07-05 12:17:30 +02002461 if (INTEL_INFO(dev)->gen >= 4) {
2462 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002463 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2464 fb->bits_per_pixel / 8,
2465 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002466 linear_offset -= intel_crtc->dspaddr_offset;
2467 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002468 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002469 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002470
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002471 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2472 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2473 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002474 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002475 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002476 I915_WRITE(DSPSURF(plane),
2477 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002478 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002479 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002480 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002481 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002482 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002483}
2484
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002485static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2486 struct drm_framebuffer *fb,
2487 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002488{
2489 struct drm_device *dev = crtc->dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002492 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002493 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002494 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002495 u32 dspcntr;
2496 u32 reg;
2497
Jesse Barnes17638cd2011-06-24 12:19:23 -07002498 reg = DSPCNTR(plane);
2499 dspcntr = I915_READ(reg);
2500 /* Mask out pixel format bits in case we change it */
2501 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002502 switch (fb->pixel_format) {
2503 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002504 dspcntr |= DISPPLANE_8BPP;
2505 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002506 case DRM_FORMAT_RGB565:
2507 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002508 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002509 case DRM_FORMAT_XRGB8888:
2510 case DRM_FORMAT_ARGB8888:
2511 dspcntr |= DISPPLANE_BGRX888;
2512 break;
2513 case DRM_FORMAT_XBGR8888:
2514 case DRM_FORMAT_ABGR8888:
2515 dspcntr |= DISPPLANE_RGBX888;
2516 break;
2517 case DRM_FORMAT_XRGB2101010:
2518 case DRM_FORMAT_ARGB2101010:
2519 dspcntr |= DISPPLANE_BGRX101010;
2520 break;
2521 case DRM_FORMAT_XBGR2101010:
2522 case DRM_FORMAT_ABGR2101010:
2523 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002524 break;
2525 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002526 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002527 }
2528
2529 if (obj->tiling_mode != I915_TILING_NONE)
2530 dspcntr |= DISPPLANE_TILED;
2531 else
2532 dspcntr &= ~DISPPLANE_TILED;
2533
Ville Syrjäläb42c6002013-11-03 13:47:27 +02002534 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002535 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2536 else
2537 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002538
2539 I915_WRITE(reg, dspcntr);
2540
Daniel Vettere506a0c2012-07-05 12:17:29 +02002541 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002542 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002543 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2544 fb->bits_per_pixel / 8,
2545 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002546 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002547
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002548 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2549 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2550 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002551 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002554 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002555 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2556 } else {
2557 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2558 I915_WRITE(DSPLINOFF(plane), linear_offset);
2559 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002560 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002561}
2562
2563/* Assume fb object is pinned & idle & fenced and just update base pointers */
2564static int
2565intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2566 int x, int y, enum mode_set_atomic state)
2567{
2568 struct drm_device *dev = crtc->dev;
2569 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002570
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002571 if (dev_priv->display.disable_fbc)
2572 dev_priv->display.disable_fbc(dev);
Daniel Vettercc365132014-06-18 13:59:13 +02002573 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
Jesse Barnes81255562010-08-02 12:07:50 -07002574
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002575 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2576
2577 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002578}
2579
Ville Syrjälä96a02912013-02-18 19:08:49 +02002580void intel_display_handle_reset(struct drm_device *dev)
2581{
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct drm_crtc *crtc;
2584
2585 /*
2586 * Flips in the rings have been nuked by the reset,
2587 * so complete all pending flips so that user space
2588 * will get its events and not get stuck.
2589 *
2590 * Also update the base address of all primary
2591 * planes to the the last fb to make sure we're
2592 * showing the correct fb after a reset.
2593 *
2594 * Need to make two loops over the crtcs so that we
2595 * don't try to grab a crtc mutex before the
2596 * pending_flip_queue really got woken up.
2597 */
2598
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002599 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 enum plane plane = intel_crtc->plane;
2602
2603 intel_prepare_page_flip(dev, plane);
2604 intel_finish_page_flip_plane(dev, plane);
2605 }
2606
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002607 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2609
Rob Clark51fd3712013-11-19 12:10:12 -05002610 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002611 /*
2612 * FIXME: Once we have proper support for primary planes (and
2613 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002614 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002615 */
Matt Roperf4510a22014-04-01 15:22:40 -07002616 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002617 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002618 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002619 crtc->x,
2620 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05002621 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002622 }
2623}
2624
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002625static int
Chris Wilson14667a42012-04-03 17:58:35 +01002626intel_finish_fb(struct drm_framebuffer *old_fb)
2627{
Matt Roper2ff8fde2014-07-08 07:50:07 -07002628 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
Chris Wilson14667a42012-04-03 17:58:35 +01002629 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2630 bool was_interruptible = dev_priv->mm.interruptible;
2631 int ret;
2632
Chris Wilson14667a42012-04-03 17:58:35 +01002633 /* Big Hammer, we also need to ensure that any pending
2634 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2635 * current scanout is retired before unpinning the old
2636 * framebuffer.
2637 *
2638 * This should only fail upon a hung GPU, in which case we
2639 * can safely continue.
2640 */
2641 dev_priv->mm.interruptible = false;
2642 ret = i915_gem_object_finish_gpu(obj);
2643 dev_priv->mm.interruptible = was_interruptible;
2644
2645 return ret;
2646}
2647
Chris Wilson7d5e3792014-03-04 13:15:08 +00002648static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2649{
2650 struct drm_device *dev = crtc->dev;
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2653 unsigned long flags;
2654 bool pending;
2655
2656 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2657 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2658 return false;
2659
2660 spin_lock_irqsave(&dev->event_lock, flags);
2661 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2662 spin_unlock_irqrestore(&dev->event_lock, flags);
2663
2664 return pending;
2665}
2666
Chris Wilson14667a42012-04-03 17:58:35 +01002667static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002668intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002669 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002670{
2671 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002672 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02002674 enum pipe pipe = intel_crtc->pipe;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002675 struct drm_framebuffer *old_fb = crtc->primary->fb;
2676 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2677 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002678 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002679
Chris Wilson7d5e3792014-03-04 13:15:08 +00002680 if (intel_crtc_has_pending_flip(crtc)) {
2681 DRM_ERROR("pipe is still busy with an old pageflip\n");
2682 return -EBUSY;
2683 }
2684
Jesse Barnes79e53942008-11-07 14:24:08 -08002685 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002686 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002687 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002688 return 0;
2689 }
2690
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002691 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002692 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2693 plane_name(intel_crtc->plane),
2694 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002695 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002696 }
2697
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002698 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02002699 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2700 if (ret == 0)
Matt Roper91565c82014-06-24 17:05:02 -07002701 i915_gem_track_fb(old_obj, obj,
Daniel Vettera071fa02014-06-18 23:28:09 +02002702 INTEL_FRONTBUFFER_PRIMARY(pipe));
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002703 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002704 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002705 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002706 return ret;
2707 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002708
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002709 /*
2710 * Update pipe size and adjust fitter if needed: the reason for this is
2711 * that in compute_mode_changes we check the native mode (not the pfit
2712 * mode) to see if we can flip rather than do a full mode set. In the
2713 * fastboot case, we'll flip, but if we don't update the pipesrc and
2714 * pfit state, we'll end up with a big fb scanned out into the wrong
2715 * sized surface.
2716 *
2717 * To fix this properly, we need to hoist the checks up into
2718 * compute_mode_changes (or above), check the actual pfit state and
2719 * whether the platform allows pfit disable with pipe active, and only
2720 * then update the pipesrc and pfit state, even on the flip path.
2721 */
Jani Nikulad330a952014-01-21 11:24:25 +02002722 if (i915.fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002723 const struct drm_display_mode *adjusted_mode =
2724 &intel_crtc->config.adjusted_mode;
2725
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002726 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002727 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2728 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002729 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002730 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2731 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2732 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2733 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2734 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2735 }
Jesse Barnes0637d602013-12-19 10:48:01 -08002736 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2737 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002738 }
2739
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002740 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002741
Daniel Vetterf99d7062014-06-19 16:01:59 +02002742 if (intel_crtc->active)
2743 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2744
Matt Roperf4510a22014-04-01 15:22:40 -07002745 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002746 crtc->x = x;
2747 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002748
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002749 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002750 if (intel_crtc->active && old_fb != fb)
2751 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002752 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002753 intel_unpin_fb_obj(old_obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002754 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002755 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002756
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002757 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002758 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002759 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002760
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002761 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002762}
2763
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002764static void intel_fdi_normal_train(struct drm_crtc *crtc)
2765{
2766 struct drm_device *dev = crtc->dev;
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769 int pipe = intel_crtc->pipe;
2770 u32 reg, temp;
2771
2772 /* enable normal train */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002775 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002776 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002778 } else {
2779 temp &= ~FDI_LINK_TRAIN_NONE;
2780 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002781 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002782 I915_WRITE(reg, temp);
2783
2784 reg = FDI_RX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 if (HAS_PCH_CPT(dev)) {
2787 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2788 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2789 } else {
2790 temp &= ~FDI_LINK_TRAIN_NONE;
2791 temp |= FDI_LINK_TRAIN_NONE;
2792 }
2793 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2794
2795 /* wait one idle pattern time */
2796 POSTING_READ(reg);
2797 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002798
2799 /* IVB wants error correction enabled */
2800 if (IS_IVYBRIDGE(dev))
2801 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2802 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002803}
2804
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002805static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002806{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002807 return crtc->base.enabled && crtc->active &&
2808 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002809}
2810
Daniel Vetter01a415f2012-10-27 15:58:40 +02002811static void ivb_modeset_global_resources(struct drm_device *dev)
2812{
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *pipe_B_crtc =
2815 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2816 struct intel_crtc *pipe_C_crtc =
2817 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2818 uint32_t temp;
2819
Daniel Vetter1e833f42013-02-19 22:31:57 +01002820 /*
2821 * When everything is off disable fdi C so that we could enable fdi B
2822 * with all lanes. Note that we don't care about enabled pipes without
2823 * an enabled pch encoder.
2824 */
2825 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2826 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002827 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2828 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2829
2830 temp = I915_READ(SOUTH_CHICKEN1);
2831 temp &= ~FDI_BC_BIFURCATION_SELECT;
2832 DRM_DEBUG_KMS("disabling fdi C rx\n");
2833 I915_WRITE(SOUTH_CHICKEN1, temp);
2834 }
2835}
2836
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002837/* The FDI link training functions for ILK/Ibexpeak. */
2838static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2839{
2840 struct drm_device *dev = crtc->dev;
2841 struct drm_i915_private *dev_priv = dev->dev_private;
2842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2843 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002844 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002845
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03002846 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002847 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002848
Adam Jacksone1a44742010-06-25 15:32:14 -04002849 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2850 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002851 reg = FDI_RX_IMR(pipe);
2852 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002853 temp &= ~FDI_RX_SYMBOL_LOCK;
2854 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002855 I915_WRITE(reg, temp);
2856 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002857 udelay(150);
2858
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002859 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002860 reg = FDI_TX_CTL(pipe);
2861 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002862 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2863 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002864 temp &= ~FDI_LINK_TRAIN_NONE;
2865 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002866 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002867
Chris Wilson5eddb702010-09-11 13:48:45 +01002868 reg = FDI_RX_CTL(pipe);
2869 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002870 temp &= ~FDI_LINK_TRAIN_NONE;
2871 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002872 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2873
2874 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002875 udelay(150);
2876
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002877 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002878 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2879 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2880 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002881
Chris Wilson5eddb702010-09-11 13:48:45 +01002882 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002883 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002884 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002885 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2886
2887 if ((temp & FDI_RX_BIT_LOCK)) {
2888 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002889 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002890 break;
2891 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002892 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002893 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002894 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002895
2896 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002899 temp &= ~FDI_LINK_TRAIN_NONE;
2900 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002901 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002902
Chris Wilson5eddb702010-09-11 13:48:45 +01002903 reg = FDI_RX_CTL(pipe);
2904 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002905 temp &= ~FDI_LINK_TRAIN_NONE;
2906 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002907 I915_WRITE(reg, temp);
2908
2909 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002910 udelay(150);
2911
Chris Wilson5eddb702010-09-11 13:48:45 +01002912 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002913 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002914 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002915 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2916
2917 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002918 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002919 DRM_DEBUG_KMS("FDI train 2 done.\n");
2920 break;
2921 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002922 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002923 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002924 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002925
2926 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002927
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002928}
2929
Akshay Joshi0206e352011-08-16 15:34:10 -04002930static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002931 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2932 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2933 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2934 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2935};
2936
2937/* The FDI link training functions for SNB/Cougarpoint. */
2938static void gen6_fdi_link_train(struct drm_crtc *crtc)
2939{
2940 struct drm_device *dev = crtc->dev;
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2943 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002944 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002945
Adam Jacksone1a44742010-06-25 15:32:14 -04002946 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2947 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002948 reg = FDI_RX_IMR(pipe);
2949 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002950 temp &= ~FDI_RX_SYMBOL_LOCK;
2951 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002952 I915_WRITE(reg, temp);
2953
2954 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002955 udelay(150);
2956
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002957 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002958 reg = FDI_TX_CTL(pipe);
2959 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002960 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2961 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002962 temp &= ~FDI_LINK_TRAIN_NONE;
2963 temp |= FDI_LINK_TRAIN_PATTERN_1;
2964 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2965 /* SNB-B */
2966 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002967 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002968
Daniel Vetterd74cf322012-10-26 10:58:13 +02002969 I915_WRITE(FDI_RX_MISC(pipe),
2970 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2971
Chris Wilson5eddb702010-09-11 13:48:45 +01002972 reg = FDI_RX_CTL(pipe);
2973 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002974 if (HAS_PCH_CPT(dev)) {
2975 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2976 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2977 } else {
2978 temp &= ~FDI_LINK_TRAIN_NONE;
2979 temp |= FDI_LINK_TRAIN_PATTERN_1;
2980 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002981 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2982
2983 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002984 udelay(150);
2985
Akshay Joshi0206e352011-08-16 15:34:10 -04002986 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002987 reg = FDI_TX_CTL(pipe);
2988 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002989 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2990 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002991 I915_WRITE(reg, temp);
2992
2993 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002994 udelay(500);
2995
Sean Paulfa37d392012-03-02 12:53:39 -05002996 for (retry = 0; retry < 5; retry++) {
2997 reg = FDI_RX_IIR(pipe);
2998 temp = I915_READ(reg);
2999 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3000 if (temp & FDI_RX_BIT_LOCK) {
3001 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3002 DRM_DEBUG_KMS("FDI train 1 done.\n");
3003 break;
3004 }
3005 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003006 }
Sean Paulfa37d392012-03-02 12:53:39 -05003007 if (retry < 5)
3008 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003009 }
3010 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003011 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003012
3013 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003014 reg = FDI_TX_CTL(pipe);
3015 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003016 temp &= ~FDI_LINK_TRAIN_NONE;
3017 temp |= FDI_LINK_TRAIN_PATTERN_2;
3018 if (IS_GEN6(dev)) {
3019 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3020 /* SNB-B */
3021 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3022 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003023 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003024
Chris Wilson5eddb702010-09-11 13:48:45 +01003025 reg = FDI_RX_CTL(pipe);
3026 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003027 if (HAS_PCH_CPT(dev)) {
3028 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3029 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3030 } else {
3031 temp &= ~FDI_LINK_TRAIN_NONE;
3032 temp |= FDI_LINK_TRAIN_PATTERN_2;
3033 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003034 I915_WRITE(reg, temp);
3035
3036 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003037 udelay(150);
3038
Akshay Joshi0206e352011-08-16 15:34:10 -04003039 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003040 reg = FDI_TX_CTL(pipe);
3041 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003042 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3043 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003044 I915_WRITE(reg, temp);
3045
3046 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003047 udelay(500);
3048
Sean Paulfa37d392012-03-02 12:53:39 -05003049 for (retry = 0; retry < 5; retry++) {
3050 reg = FDI_RX_IIR(pipe);
3051 temp = I915_READ(reg);
3052 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3053 if (temp & FDI_RX_SYMBOL_LOCK) {
3054 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3055 DRM_DEBUG_KMS("FDI train 2 done.\n");
3056 break;
3057 }
3058 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003059 }
Sean Paulfa37d392012-03-02 12:53:39 -05003060 if (retry < 5)
3061 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003062 }
3063 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003064 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003065
3066 DRM_DEBUG_KMS("FDI train done.\n");
3067}
3068
Jesse Barnes357555c2011-04-28 15:09:55 -07003069/* Manual link training for Ivy Bridge A0 parts */
3070static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3071{
3072 struct drm_device *dev = crtc->dev;
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003076 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003077
3078 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3079 for train result */
3080 reg = FDI_RX_IMR(pipe);
3081 temp = I915_READ(reg);
3082 temp &= ~FDI_RX_SYMBOL_LOCK;
3083 temp &= ~FDI_RX_BIT_LOCK;
3084 I915_WRITE(reg, temp);
3085
3086 POSTING_READ(reg);
3087 udelay(150);
3088
Daniel Vetter01a415f2012-10-27 15:58:40 +02003089 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3090 I915_READ(FDI_RX_IIR(pipe)));
3091
Jesse Barnes139ccd32013-08-19 11:04:55 -07003092 /* Try each vswing and preemphasis setting twice before moving on */
3093 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3094 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003095 reg = FDI_TX_CTL(pipe);
3096 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003097 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3098 temp &= ~FDI_TX_ENABLE;
3099 I915_WRITE(reg, temp);
3100
3101 reg = FDI_RX_CTL(pipe);
3102 temp = I915_READ(reg);
3103 temp &= ~FDI_LINK_TRAIN_AUTO;
3104 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3105 temp &= ~FDI_RX_ENABLE;
3106 I915_WRITE(reg, temp);
3107
3108 /* enable CPU FDI TX and PCH FDI RX */
3109 reg = FDI_TX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3112 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3113 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003114 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003115 temp |= snb_b_fdi_train_param[j/2];
3116 temp |= FDI_COMPOSITE_SYNC;
3117 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3118
3119 I915_WRITE(FDI_RX_MISC(pipe),
3120 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3121
3122 reg = FDI_RX_CTL(pipe);
3123 temp = I915_READ(reg);
3124 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3125 temp |= FDI_COMPOSITE_SYNC;
3126 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3127
3128 POSTING_READ(reg);
3129 udelay(1); /* should be 0.5us */
3130
3131 for (i = 0; i < 4; i++) {
3132 reg = FDI_RX_IIR(pipe);
3133 temp = I915_READ(reg);
3134 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3135
3136 if (temp & FDI_RX_BIT_LOCK ||
3137 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3138 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3139 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3140 i);
3141 break;
3142 }
3143 udelay(1); /* should be 0.5us */
3144 }
3145 if (i == 4) {
3146 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3147 continue;
3148 }
3149
3150 /* Train 2 */
3151 reg = FDI_TX_CTL(pipe);
3152 temp = I915_READ(reg);
3153 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3154 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3155 I915_WRITE(reg, temp);
3156
3157 reg = FDI_RX_CTL(pipe);
3158 temp = I915_READ(reg);
3159 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3160 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003161 I915_WRITE(reg, temp);
3162
3163 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003164 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003165
Jesse Barnes139ccd32013-08-19 11:04:55 -07003166 for (i = 0; i < 4; i++) {
3167 reg = FDI_RX_IIR(pipe);
3168 temp = I915_READ(reg);
3169 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003170
Jesse Barnes139ccd32013-08-19 11:04:55 -07003171 if (temp & FDI_RX_SYMBOL_LOCK ||
3172 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3173 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3174 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3175 i);
3176 goto train_done;
3177 }
3178 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003179 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003180 if (i == 4)
3181 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003182 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003183
Jesse Barnes139ccd32013-08-19 11:04:55 -07003184train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003185 DRM_DEBUG_KMS("FDI train done.\n");
3186}
3187
Daniel Vetter88cefb62012-08-12 19:27:14 +02003188static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003189{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003190 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003191 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003192 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003193 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003194
Jesse Barnesc64e3112010-09-10 11:27:03 -07003195
Jesse Barnes0e23b992010-09-10 11:10:00 -07003196 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003197 reg = FDI_RX_CTL(pipe);
3198 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003199 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3200 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003201 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003202 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3203
3204 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003205 udelay(200);
3206
3207 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003208 temp = I915_READ(reg);
3209 I915_WRITE(reg, temp | FDI_PCDCLK);
3210
3211 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003212 udelay(200);
3213
Paulo Zanoni20749732012-11-23 15:30:38 -02003214 /* Enable CPU FDI TX PLL, always on for Ironlake */
3215 reg = FDI_TX_CTL(pipe);
3216 temp = I915_READ(reg);
3217 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3218 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003219
Paulo Zanoni20749732012-11-23 15:30:38 -02003220 POSTING_READ(reg);
3221 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003222 }
3223}
3224
Daniel Vetter88cefb62012-08-12 19:27:14 +02003225static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3226{
3227 struct drm_device *dev = intel_crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 int pipe = intel_crtc->pipe;
3230 u32 reg, temp;
3231
3232 /* Switch from PCDclk to Rawclk */
3233 reg = FDI_RX_CTL(pipe);
3234 temp = I915_READ(reg);
3235 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3236
3237 /* Disable CPU FDI TX PLL */
3238 reg = FDI_TX_CTL(pipe);
3239 temp = I915_READ(reg);
3240 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3241
3242 POSTING_READ(reg);
3243 udelay(100);
3244
3245 reg = FDI_RX_CTL(pipe);
3246 temp = I915_READ(reg);
3247 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3248
3249 /* Wait for the clocks to turn off. */
3250 POSTING_READ(reg);
3251 udelay(100);
3252}
3253
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003254static void ironlake_fdi_disable(struct drm_crtc *crtc)
3255{
3256 struct drm_device *dev = crtc->dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3259 int pipe = intel_crtc->pipe;
3260 u32 reg, temp;
3261
3262 /* disable CPU FDI tx and PCH FDI rx */
3263 reg = FDI_TX_CTL(pipe);
3264 temp = I915_READ(reg);
3265 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3266 POSTING_READ(reg);
3267
3268 reg = FDI_RX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003271 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003272 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3273
3274 POSTING_READ(reg);
3275 udelay(100);
3276
3277 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003278 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003279 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003280
3281 /* still set train pattern 1 */
3282 reg = FDI_TX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 temp &= ~FDI_LINK_TRAIN_NONE;
3285 temp |= FDI_LINK_TRAIN_PATTERN_1;
3286 I915_WRITE(reg, temp);
3287
3288 reg = FDI_RX_CTL(pipe);
3289 temp = I915_READ(reg);
3290 if (HAS_PCH_CPT(dev)) {
3291 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3292 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3293 } else {
3294 temp &= ~FDI_LINK_TRAIN_NONE;
3295 temp |= FDI_LINK_TRAIN_PATTERN_1;
3296 }
3297 /* BPC in FDI rx is consistent with that in PIPECONF */
3298 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003299 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003300 I915_WRITE(reg, temp);
3301
3302 POSTING_READ(reg);
3303 udelay(100);
3304}
3305
Chris Wilson5dce5b932014-01-20 10:17:36 +00003306bool intel_has_pending_fb_unpin(struct drm_device *dev)
3307{
3308 struct intel_crtc *crtc;
3309
3310 /* Note that we don't need to be called with mode_config.lock here
3311 * as our list of CRTC objects is static for the lifetime of the
3312 * device and so cannot disappear as we iterate. Similarly, we can
3313 * happily treat the predicates as racy, atomic checks as userspace
3314 * cannot claim and pin a new fb without at least acquring the
3315 * struct_mutex and so serialising with us.
3316 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003317 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003318 if (atomic_read(&crtc->unpin_work_count) == 0)
3319 continue;
3320
3321 if (crtc->unpin_work)
3322 intel_wait_for_vblank(dev, crtc->pipe);
3323
3324 return true;
3325 }
3326
3327 return false;
3328}
3329
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003330void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003331{
Chris Wilson0f911282012-04-17 10:05:38 +01003332 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003333 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003334
Matt Roperf4510a22014-04-01 15:22:40 -07003335 if (crtc->primary->fb == NULL)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003336 return;
3337
Daniel Vetter2c10d572012-12-20 21:24:07 +01003338 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3339
Daniel Vettereed6d672014-05-19 16:09:35 +02003340 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3341 !intel_crtc_has_pending_flip(crtc),
3342 60*HZ) == 0);
Chris Wilson5bb61642012-09-27 21:25:58 +01003343
Chris Wilson0f911282012-04-17 10:05:38 +01003344 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07003345 intel_finish_fb(crtc->primary->fb);
Chris Wilson0f911282012-04-17 10:05:38 +01003346 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003347}
3348
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003349/* Program iCLKIP clock to the desired frequency */
3350static void lpt_program_iclkip(struct drm_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003354 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003355 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3356 u32 temp;
3357
Daniel Vetter09153002012-12-12 14:06:44 +01003358 mutex_lock(&dev_priv->dpio_lock);
3359
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003360 /* It is necessary to ungate the pixclk gate prior to programming
3361 * the divisors, and gate it back when it is done.
3362 */
3363 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3364
3365 /* Disable SSCCTL */
3366 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003367 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3368 SBI_SSCCTL_DISABLE,
3369 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003370
3371 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003372 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003373 auxdiv = 1;
3374 divsel = 0x41;
3375 phaseinc = 0x20;
3376 } else {
3377 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003378 * but the adjusted_mode->crtc_clock in in KHz. To get the
3379 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003380 * convert the virtual clock precision to KHz here for higher
3381 * precision.
3382 */
3383 u32 iclk_virtual_root_freq = 172800 * 1000;
3384 u32 iclk_pi_range = 64;
3385 u32 desired_divisor, msb_divisor_value, pi_value;
3386
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003387 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003388 msb_divisor_value = desired_divisor / iclk_pi_range;
3389 pi_value = desired_divisor % iclk_pi_range;
3390
3391 auxdiv = 0;
3392 divsel = msb_divisor_value - 2;
3393 phaseinc = pi_value;
3394 }
3395
3396 /* This should not happen with any sane values */
3397 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3398 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3399 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3400 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3401
3402 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003403 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003404 auxdiv,
3405 divsel,
3406 phasedir,
3407 phaseinc);
3408
3409 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003410 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003411 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3412 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3413 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3414 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3415 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3416 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003417 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003418
3419 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003420 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003421 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3422 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003423 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003424
3425 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003426 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003427 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003428 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003429
3430 /* Wait for initialization time */
3431 udelay(24);
3432
3433 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003434
3435 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003436}
3437
Daniel Vetter275f01b22013-05-03 11:49:47 +02003438static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3439 enum pipe pch_transcoder)
3440{
3441 struct drm_device *dev = crtc->base.dev;
3442 struct drm_i915_private *dev_priv = dev->dev_private;
3443 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3444
3445 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3446 I915_READ(HTOTAL(cpu_transcoder)));
3447 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3448 I915_READ(HBLANK(cpu_transcoder)));
3449 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3450 I915_READ(HSYNC(cpu_transcoder)));
3451
3452 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3453 I915_READ(VTOTAL(cpu_transcoder)));
3454 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3455 I915_READ(VBLANK(cpu_transcoder)));
3456 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3457 I915_READ(VSYNC(cpu_transcoder)));
3458 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3459 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3460}
3461
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003462static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3463{
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 uint32_t temp;
3466
3467 temp = I915_READ(SOUTH_CHICKEN1);
3468 if (temp & FDI_BC_BIFURCATION_SELECT)
3469 return;
3470
3471 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3472 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3473
3474 temp |= FDI_BC_BIFURCATION_SELECT;
3475 DRM_DEBUG_KMS("enabling fdi C rx\n");
3476 I915_WRITE(SOUTH_CHICKEN1, temp);
3477 POSTING_READ(SOUTH_CHICKEN1);
3478}
3479
3480static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3481{
3482 struct drm_device *dev = intel_crtc->base.dev;
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484
3485 switch (intel_crtc->pipe) {
3486 case PIPE_A:
3487 break;
3488 case PIPE_B:
3489 if (intel_crtc->config.fdi_lanes > 2)
3490 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3491 else
3492 cpt_enable_fdi_bc_bifurcation(dev);
3493
3494 break;
3495 case PIPE_C:
3496 cpt_enable_fdi_bc_bifurcation(dev);
3497
3498 break;
3499 default:
3500 BUG();
3501 }
3502}
3503
Jesse Barnesf67a5592011-01-05 10:31:48 -08003504/*
3505 * Enable PCH resources required for PCH ports:
3506 * - PCH PLLs
3507 * - FDI training & RX/TX
3508 * - update transcoder timings
3509 * - DP transcoding bits
3510 * - transcoder
3511 */
3512static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003513{
3514 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003518 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003519
Daniel Vetterab9412b2013-05-03 11:49:46 +02003520 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003521
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003522 if (IS_IVYBRIDGE(dev))
3523 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3524
Daniel Vettercd986ab2012-10-26 10:58:12 +02003525 /* Write the TU size bits before fdi link training, so that error
3526 * detection works. */
3527 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3528 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3529
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003530 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003531 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003532
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003533 /* We need to program the right clock selection before writing the pixel
3534 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003535 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003536 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003537
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003538 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003539 temp |= TRANS_DPLL_ENABLE(pipe);
3540 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003541 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003542 temp |= sel;
3543 else
3544 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003545 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003546 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003547
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003548 /* XXX: pch pll's can be enabled any time before we enable the PCH
3549 * transcoder, and we actually should do this to not upset any PCH
3550 * transcoder that already use the clock when we share it.
3551 *
3552 * Note that enable_shared_dpll tries to do the right thing, but
3553 * get_shared_dpll unconditionally resets the pll - we need that to have
3554 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003555 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003556
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003557 /* set transcoder timing, panel must allow it */
3558 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003559 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003560
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003561 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003562
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003563 /* For PCH DP, enable TRANS_DP_CTL */
3564 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003565 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3566 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003567 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003568 reg = TRANS_DP_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003571 TRANS_DP_SYNC_MASK |
3572 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003573 temp |= (TRANS_DP_OUTPUT_ENABLE |
3574 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003575 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003576
3577 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003578 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003579 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003580 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003581
3582 switch (intel_trans_dp_port_sel(crtc)) {
3583 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003584 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003585 break;
3586 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003587 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003588 break;
3589 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003590 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003591 break;
3592 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003593 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003594 }
3595
Chris Wilson5eddb702010-09-11 13:48:45 +01003596 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003597 }
3598
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003599 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003600}
3601
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003602static void lpt_pch_enable(struct drm_crtc *crtc)
3603{
3604 struct drm_device *dev = crtc->dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003607 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003608
Daniel Vetterab9412b2013-05-03 11:49:46 +02003609 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003610
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003611 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003612
Paulo Zanoni0540e482012-10-31 18:12:40 -02003613 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003614 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003615
Paulo Zanoni937bb612012-10-31 18:12:47 -02003616 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003617}
3618
Daniel Vetter716c2e52014-06-25 22:02:02 +03003619void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003620{
Daniel Vettere2b78262013-06-07 23:10:03 +02003621 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003622
3623 if (pll == NULL)
3624 return;
3625
3626 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003627 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003628 return;
3629 }
3630
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003631 if (--pll->refcount == 0) {
3632 WARN_ON(pll->on);
3633 WARN_ON(pll->active);
3634 }
3635
Daniel Vettera43f6e02013-06-07 23:10:32 +02003636 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003637}
3638
Daniel Vetter716c2e52014-06-25 22:02:02 +03003639struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003640{
Daniel Vettere2b78262013-06-07 23:10:03 +02003641 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3642 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3643 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003644
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003645 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003646 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3647 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003648 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003649 }
3650
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003651 if (HAS_PCH_IBX(dev_priv->dev)) {
3652 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003653 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003654 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003655
Daniel Vetter46edb022013-06-05 13:34:12 +02003656 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3657 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003658
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003659 WARN_ON(pll->refcount);
3660
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003661 goto found;
3662 }
3663
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003664 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3665 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003666
3667 /* Only want to check enabled timings first */
3668 if (pll->refcount == 0)
3669 continue;
3670
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003671 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3672 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003673 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003674 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003675 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003676
3677 goto found;
3678 }
3679 }
3680
3681 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003682 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3683 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003684 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003685 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3686 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003687 goto found;
3688 }
3689 }
3690
3691 return NULL;
3692
3693found:
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003694 if (pll->refcount == 0)
3695 pll->hw_state = crtc->config.dpll_hw_state;
3696
Daniel Vettera43f6e02013-06-07 23:10:32 +02003697 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003698 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3699 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003700
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003701 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003702
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003703 return pll;
3704}
3705
Daniel Vettera1520312013-05-03 11:49:50 +02003706static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003707{
3708 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003709 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003710 u32 temp;
3711
3712 temp = I915_READ(dslreg);
3713 udelay(500);
3714 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003715 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003716 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003717 }
3718}
3719
Jesse Barnesb074cec2013-04-25 12:55:02 -07003720static void ironlake_pfit_enable(struct intel_crtc *crtc)
3721{
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 int pipe = crtc->pipe;
3725
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003726 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003727 /* Force use of hard-coded filter coefficients
3728 * as some pre-programmed values are broken,
3729 * e.g. x201.
3730 */
3731 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3732 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3733 PF_PIPE_SEL_IVB(pipe));
3734 else
3735 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3736 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3737 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003738 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003739}
3740
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003741static void intel_enable_planes(struct drm_crtc *crtc)
3742{
3743 struct drm_device *dev = crtc->dev;
3744 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003745 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003746 struct intel_plane *intel_plane;
3747
Matt Roperaf2b6532014-04-01 15:22:32 -07003748 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3749 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003750 if (intel_plane->pipe == pipe)
3751 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003752 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003753}
3754
3755static void intel_disable_planes(struct drm_crtc *crtc)
3756{
3757 struct drm_device *dev = crtc->dev;
3758 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003759 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003760 struct intel_plane *intel_plane;
3761
Matt Roperaf2b6532014-04-01 15:22:32 -07003762 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3763 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003764 if (intel_plane->pipe == pipe)
3765 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003766 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003767}
3768
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003769void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003770{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003771 struct drm_device *dev = crtc->base.dev;
3772 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03003773
3774 if (!crtc->config.ips_enabled)
3775 return;
3776
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003777 /* We can only enable IPS after we enable a plane and wait for a vblank */
3778 intel_wait_for_vblank(dev, crtc->pipe);
3779
Paulo Zanonid77e4532013-09-24 13:52:55 -03003780 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003781 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003782 mutex_lock(&dev_priv->rps.hw_lock);
3783 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3784 mutex_unlock(&dev_priv->rps.hw_lock);
3785 /* Quoting Art Runyan: "its not safe to expect any particular
3786 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08003787 * mailbox." Moreover, the mailbox may return a bogus state,
3788 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003789 */
3790 } else {
3791 I915_WRITE(IPS_CTL, IPS_ENABLE);
3792 /* The bit only becomes 1 in the next vblank, so this wait here
3793 * is essentially intel_wait_for_vblank. If we don't have this
3794 * and don't wait for vblanks until the end of crtc_enable, then
3795 * the HW state readout code will complain that the expected
3796 * IPS_CTL value is not the one we read. */
3797 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3798 DRM_ERROR("Timed out waiting for IPS enable\n");
3799 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003800}
3801
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003802void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003803{
3804 struct drm_device *dev = crtc->base.dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806
3807 if (!crtc->config.ips_enabled)
3808 return;
3809
3810 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003811 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003812 mutex_lock(&dev_priv->rps.hw_lock);
3813 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3814 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003815 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3816 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3817 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08003818 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003819 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08003820 POSTING_READ(IPS_CTL);
3821 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003822
3823 /* We need to wait for a vblank before we can disable the plane. */
3824 intel_wait_for_vblank(dev, crtc->pipe);
3825}
3826
3827/** Loads the palette/gamma unit for the CRTC with the prepared values */
3828static void intel_crtc_load_lut(struct drm_crtc *crtc)
3829{
3830 struct drm_device *dev = crtc->dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3833 enum pipe pipe = intel_crtc->pipe;
3834 int palreg = PALETTE(pipe);
3835 int i;
3836 bool reenable_ips = false;
3837
3838 /* The clocks have to be on to load the palette. */
3839 if (!crtc->enabled || !intel_crtc->active)
3840 return;
3841
3842 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3843 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3844 assert_dsi_pll_enabled(dev_priv);
3845 else
3846 assert_pll_enabled(dev_priv, pipe);
3847 }
3848
3849 /* use legacy palette for Ironlake */
3850 if (HAS_PCH_SPLIT(dev))
3851 palreg = LGC_PALETTE(pipe);
3852
3853 /* Workaround : Do not read or write the pipe palette/gamma data while
3854 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3855 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02003856 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03003857 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3858 GAMMA_MODE_MODE_SPLIT)) {
3859 hsw_disable_ips(intel_crtc);
3860 reenable_ips = true;
3861 }
3862
3863 for (i = 0; i < 256; i++) {
3864 I915_WRITE(palreg + 4 * i,
3865 (intel_crtc->lut_r[i] << 16) |
3866 (intel_crtc->lut_g[i] << 8) |
3867 intel_crtc->lut_b[i]);
3868 }
3869
3870 if (reenable_ips)
3871 hsw_enable_ips(intel_crtc);
3872}
3873
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003874static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3875{
3876 if (!enable && intel_crtc->overlay) {
3877 struct drm_device *dev = intel_crtc->base.dev;
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879
3880 mutex_lock(&dev->struct_mutex);
3881 dev_priv->mm.interruptible = false;
3882 (void) intel_overlay_switch_off(intel_crtc->overlay);
3883 dev_priv->mm.interruptible = true;
3884 mutex_unlock(&dev->struct_mutex);
3885 }
3886
3887 /* Let userspace switch the overlay on again. In most cases userspace
3888 * has to recompute where to put it anyway.
3889 */
3890}
3891
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003892static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003893{
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897 int pipe = intel_crtc->pipe;
3898 int plane = intel_crtc->plane;
3899
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003900 drm_vblank_on(dev, pipe);
3901
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003902 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3903 intel_enable_planes(crtc);
3904 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003905 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003906
3907 hsw_enable_ips(intel_crtc);
3908
3909 mutex_lock(&dev->struct_mutex);
3910 intel_update_fbc(dev);
3911 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf99d7062014-06-19 16:01:59 +02003912
3913 /*
3914 * FIXME: Once we grow proper nuclear flip support out of this we need
3915 * to compute the mask of flip planes precisely. For the time being
3916 * consider this a flip from a NULL plane.
3917 */
3918 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003919}
3920
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003921static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003922{
3923 struct drm_device *dev = crtc->dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3926 int pipe = intel_crtc->pipe;
3927 int plane = intel_crtc->plane;
3928
3929 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003930
3931 if (dev_priv->fbc.plane == plane)
3932 intel_disable_fbc(dev);
3933
3934 hsw_disable_ips(intel_crtc);
3935
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003936 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003937 intel_crtc_update_cursor(crtc, false);
3938 intel_disable_planes(crtc);
3939 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003940
Daniel Vetterf99d7062014-06-19 16:01:59 +02003941 /*
3942 * FIXME: Once we grow proper nuclear flip support out of this we need
3943 * to compute the mask of flip planes precisely. For the time being
3944 * consider this a flip to a NULL plane.
3945 */
3946 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3947
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003948 drm_vblank_off(dev, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003949}
3950
Jesse Barnesf67a5592011-01-05 10:31:48 -08003951static void ironlake_crtc_enable(struct drm_crtc *crtc)
3952{
3953 struct drm_device *dev = crtc->dev;
3954 struct drm_i915_private *dev_priv = dev->dev_private;
3955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003956 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003957 int pipe = intel_crtc->pipe;
Daniel Vetter29407aa2014-04-24 23:55:08 +02003958 enum plane plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003959
Daniel Vetter08a48462012-07-02 11:43:47 +02003960 WARN_ON(!crtc->enabled);
3961
Jesse Barnesf67a5592011-01-05 10:31:48 -08003962 if (intel_crtc->active)
3963 return;
3964
Daniel Vetterb14b1052014-04-24 23:55:13 +02003965 if (intel_crtc->config.has_pch_encoder)
3966 intel_prepare_shared_dpll(intel_crtc);
3967
Daniel Vetter29407aa2014-04-24 23:55:08 +02003968 if (intel_crtc->config.has_dp_encoder)
3969 intel_dp_set_m_n(intel_crtc);
3970
3971 intel_set_pipe_timings(intel_crtc);
3972
3973 if (intel_crtc->config.has_pch_encoder) {
3974 intel_cpu_transcoder_set_m_n(intel_crtc,
3975 &intel_crtc->config.fdi_m_n);
3976 }
3977
3978 ironlake_set_pipeconf(crtc);
3979
3980 /* Set up the display plane register */
3981 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3982 POSTING_READ(DSPCNTR(plane));
3983
3984 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3985 crtc->x, crtc->y);
3986
Jesse Barnesf67a5592011-01-05 10:31:48 -08003987 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003988
3989 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3990 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3991
Daniel Vetterf6736a12013-06-05 13:34:30 +02003992 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003993 if (encoder->pre_enable)
3994 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003995
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003996 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003997 /* Note: FDI PLL enabling _must_ be done before we enable the
3998 * cpu pipes, hence this is separate from all the other fdi/pch
3999 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02004000 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02004001 } else {
4002 assert_fdi_tx_disabled(dev_priv, pipe);
4003 assert_fdi_rx_disabled(dev_priv, pipe);
4004 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004005
Jesse Barnesb074cec2013-04-25 12:55:02 -07004006 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004007
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02004008 /*
4009 * On ILK+ LUT must be loaded before the pipe is running but with
4010 * clocks enabled
4011 */
4012 intel_crtc_load_lut(crtc);
4013
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004014 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004015 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004016
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004017 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004018 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004019
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004020 for_each_encoder_on_crtc(dev, crtc, encoder)
4021 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004022
4023 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004024 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004025
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004026 intel_crtc_enable_planes(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004027}
4028
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004029/* IPS only exists on ULT machines and is tied to pipe A. */
4030static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4031{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004032 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004033}
4034
Paulo Zanonie4916942013-09-20 16:21:19 -03004035/*
4036 * This implements the workaround described in the "notes" section of the mode
4037 * set sequence documentation. When going from no pipes or single pipe to
4038 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4039 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4040 */
4041static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4042{
4043 struct drm_device *dev = crtc->base.dev;
4044 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4045
4046 /* We want to get the other_active_crtc only if there's only 1 other
4047 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004048 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004049 if (!crtc_it->active || crtc_it == crtc)
4050 continue;
4051
4052 if (other_active_crtc)
4053 return;
4054
4055 other_active_crtc = crtc_it;
4056 }
4057 if (!other_active_crtc)
4058 return;
4059
4060 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4061 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4062}
4063
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004064static void haswell_crtc_enable(struct drm_crtc *crtc)
4065{
4066 struct drm_device *dev = crtc->dev;
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069 struct intel_encoder *encoder;
4070 int pipe = intel_crtc->pipe;
Daniel Vetter229fca92014-04-24 23:55:09 +02004071 enum plane plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004072
4073 WARN_ON(!crtc->enabled);
4074
4075 if (intel_crtc->active)
4076 return;
4077
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004078 if (intel_crtc_to_shared_dpll(intel_crtc))
4079 intel_enable_shared_dpll(intel_crtc);
4080
Daniel Vetter229fca92014-04-24 23:55:09 +02004081 if (intel_crtc->config.has_dp_encoder)
4082 intel_dp_set_m_n(intel_crtc);
4083
4084 intel_set_pipe_timings(intel_crtc);
4085
4086 if (intel_crtc->config.has_pch_encoder) {
4087 intel_cpu_transcoder_set_m_n(intel_crtc,
4088 &intel_crtc->config.fdi_m_n);
4089 }
4090
4091 haswell_set_pipeconf(crtc);
4092
4093 intel_set_pipe_csc(crtc);
4094
4095 /* Set up the display plane register */
4096 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4097 POSTING_READ(DSPCNTR(plane));
4098
4099 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4100 crtc->x, crtc->y);
4101
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004102 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004103
4104 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004105 for_each_encoder_on_crtc(dev, crtc, encoder)
4106 if (encoder->pre_enable)
4107 encoder->pre_enable(encoder);
4108
Imre Deak4fe94672014-06-25 22:01:49 +03004109 if (intel_crtc->config.has_pch_encoder) {
4110 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4111 dev_priv->display.fdi_link_train(crtc);
4112 }
4113
Paulo Zanoni1f544382012-10-24 11:32:00 -02004114 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004115
Jesse Barnesb074cec2013-04-25 12:55:02 -07004116 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004117
4118 /*
4119 * On ILK+ LUT must be loaded before the pipe is running but with
4120 * clocks enabled
4121 */
4122 intel_crtc_load_lut(crtc);
4123
Paulo Zanoni1f544382012-10-24 11:32:00 -02004124 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004125 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004126
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004127 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004128 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004129
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004130 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004131 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004132
Jani Nikula8807e552013-08-30 19:40:32 +03004133 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004134 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004135 intel_opregion_notify_encoder(encoder, true);
4136 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004137
Paulo Zanonie4916942013-09-20 16:21:19 -03004138 /* If we change the relative order between pipe/planes enabling, we need
4139 * to change the workaround. */
4140 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004141 intel_crtc_enable_planes(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004142}
4143
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004144static void ironlake_pfit_disable(struct intel_crtc *crtc)
4145{
4146 struct drm_device *dev = crtc->base.dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int pipe = crtc->pipe;
4149
4150 /* To avoid upsetting the power well on haswell only disable the pfit if
4151 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004152 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004153 I915_WRITE(PF_CTL(pipe), 0);
4154 I915_WRITE(PF_WIN_POS(pipe), 0);
4155 I915_WRITE(PF_WIN_SZ(pipe), 0);
4156 }
4157}
4158
Jesse Barnes6be4a602010-09-10 10:26:01 -07004159static void ironlake_crtc_disable(struct drm_crtc *crtc)
4160{
4161 struct drm_device *dev = crtc->dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004164 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004165 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004166 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004167
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004168 if (!intel_crtc->active)
4169 return;
4170
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004171 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004172
Daniel Vetterea9d7582012-07-10 10:42:52 +02004173 for_each_encoder_on_crtc(dev, crtc, encoder)
4174 encoder->disable(encoder);
4175
Daniel Vetterd925c592013-06-05 13:34:04 +02004176 if (intel_crtc->config.has_pch_encoder)
4177 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4178
Jesse Barnesb24e7172011-01-04 15:09:30 -08004179 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004180
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004181 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004182
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004183 for_each_encoder_on_crtc(dev, crtc, encoder)
4184 if (encoder->post_disable)
4185 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004186
Daniel Vetterd925c592013-06-05 13:34:04 +02004187 if (intel_crtc->config.has_pch_encoder) {
4188 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004189
Daniel Vetterd925c592013-06-05 13:34:04 +02004190 ironlake_disable_pch_transcoder(dev_priv, pipe);
4191 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004192
Daniel Vetterd925c592013-06-05 13:34:04 +02004193 if (HAS_PCH_CPT(dev)) {
4194 /* disable TRANS_DP_CTL */
4195 reg = TRANS_DP_CTL(pipe);
4196 temp = I915_READ(reg);
4197 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4198 TRANS_DP_PORT_SEL_MASK);
4199 temp |= TRANS_DP_PORT_SEL_NONE;
4200 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004201
Daniel Vetterd925c592013-06-05 13:34:04 +02004202 /* disable DPLL_SEL */
4203 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004204 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004205 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004206 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004207
4208 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004209 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004210
4211 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004212 }
4213
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004214 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004215 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004216
4217 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004218 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004219 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004220}
4221
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004222static void haswell_crtc_disable(struct drm_crtc *crtc)
4223{
4224 struct drm_device *dev = crtc->dev;
4225 struct drm_i915_private *dev_priv = dev->dev_private;
4226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4227 struct intel_encoder *encoder;
4228 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004229 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004230
4231 if (!intel_crtc->active)
4232 return;
4233
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004234 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004235
Jani Nikula8807e552013-08-30 19:40:32 +03004236 for_each_encoder_on_crtc(dev, crtc, encoder) {
4237 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004238 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004239 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004240
Paulo Zanoni86642812013-04-12 17:57:57 -03004241 if (intel_crtc->config.has_pch_encoder)
4242 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004243 intel_disable_pipe(dev_priv, pipe);
4244
Paulo Zanoniad80a812012-10-24 16:06:19 -02004245 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004246
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004247 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004248
Paulo Zanoni1f544382012-10-24 11:32:00 -02004249 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004250
Daniel Vetter88adfff2013-03-28 10:42:01 +01004251 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004252 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03004253 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004254 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004255 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004256
Imre Deak97b040a2014-06-25 22:01:50 +03004257 for_each_encoder_on_crtc(dev, crtc, encoder)
4258 if (encoder->post_disable)
4259 encoder->post_disable(encoder);
4260
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004261 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004262 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004263
4264 mutex_lock(&dev->struct_mutex);
4265 intel_update_fbc(dev);
4266 mutex_unlock(&dev->struct_mutex);
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004267
4268 if (intel_crtc_to_shared_dpll(intel_crtc))
4269 intel_disable_shared_dpll(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004270}
4271
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004272static void ironlake_crtc_off(struct drm_crtc *crtc)
4273{
4274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004275 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004276}
4277
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004278
Jesse Barnes2dd24552013-04-25 12:55:01 -07004279static void i9xx_pfit_enable(struct intel_crtc *crtc)
4280{
4281 struct drm_device *dev = crtc->base.dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct intel_crtc_config *pipe_config = &crtc->config;
4284
Daniel Vetter328d8e82013-05-08 10:36:31 +02004285 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004286 return;
4287
Daniel Vetterc0b03412013-05-28 12:05:54 +02004288 /*
4289 * The panel fitter should only be adjusted whilst the pipe is disabled,
4290 * according to register description and PRM.
4291 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004292 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4293 assert_pipe_disabled(dev_priv, crtc->pipe);
4294
Jesse Barnesb074cec2013-04-25 12:55:02 -07004295 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4296 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004297
4298 /* Border color in case we don't scale up to the full screen. Black by
4299 * default, change to something else for debugging. */
4300 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004301}
4302
Imre Deak77d22dc2014-03-05 16:20:52 +02004303#define for_each_power_domain(domain, mask) \
4304 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4305 if ((1 << (domain)) & (mask))
4306
Imre Deak319be8a2014-03-04 19:22:57 +02004307enum intel_display_power_domain
4308intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004309{
Imre Deak319be8a2014-03-04 19:22:57 +02004310 struct drm_device *dev = intel_encoder->base.dev;
4311 struct intel_digital_port *intel_dig_port;
4312
4313 switch (intel_encoder->type) {
4314 case INTEL_OUTPUT_UNKNOWN:
4315 /* Only DDI platforms should ever use this output type */
4316 WARN_ON_ONCE(!HAS_DDI(dev));
4317 case INTEL_OUTPUT_DISPLAYPORT:
4318 case INTEL_OUTPUT_HDMI:
4319 case INTEL_OUTPUT_EDP:
4320 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4321 switch (intel_dig_port->port) {
4322 case PORT_A:
4323 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4324 case PORT_B:
4325 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4326 case PORT_C:
4327 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4328 case PORT_D:
4329 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4330 default:
4331 WARN_ON_ONCE(1);
4332 return POWER_DOMAIN_PORT_OTHER;
4333 }
4334 case INTEL_OUTPUT_ANALOG:
4335 return POWER_DOMAIN_PORT_CRT;
4336 case INTEL_OUTPUT_DSI:
4337 return POWER_DOMAIN_PORT_DSI;
4338 default:
4339 return POWER_DOMAIN_PORT_OTHER;
4340 }
4341}
4342
4343static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4344{
4345 struct drm_device *dev = crtc->dev;
4346 struct intel_encoder *intel_encoder;
4347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4348 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02004349 unsigned long mask;
4350 enum transcoder transcoder;
4351
4352 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4353
4354 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4355 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Daniel Vetterfabf6e52014-05-29 14:10:22 +02004356 if (intel_crtc->config.pch_pfit.enabled ||
4357 intel_crtc->config.pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02004358 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4359
Imre Deak319be8a2014-03-04 19:22:57 +02004360 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4361 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4362
Imre Deak77d22dc2014-03-05 16:20:52 +02004363 return mask;
4364}
4365
4366void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4367 bool enable)
4368{
4369 if (dev_priv->power_domains.init_power_on == enable)
4370 return;
4371
4372 if (enable)
4373 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4374 else
4375 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4376
4377 dev_priv->power_domains.init_power_on = enable;
4378}
4379
4380static void modeset_update_crtc_power_domains(struct drm_device *dev)
4381{
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4384 struct intel_crtc *crtc;
4385
4386 /*
4387 * First get all needed power domains, then put all unneeded, to avoid
4388 * any unnecessary toggling of the power wells.
4389 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004390 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004391 enum intel_display_power_domain domain;
4392
4393 if (!crtc->base.enabled)
4394 continue;
4395
Imre Deak319be8a2014-03-04 19:22:57 +02004396 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004397
4398 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4399 intel_display_power_get(dev_priv, domain);
4400 }
4401
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004402 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004403 enum intel_display_power_domain domain;
4404
4405 for_each_power_domain(domain, crtc->enabled_power_domains)
4406 intel_display_power_put(dev_priv, domain);
4407
4408 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4409 }
4410
4411 intel_display_set_init_power(dev_priv, false);
4412}
4413
Ville Syrjälädfcab172014-06-13 13:37:47 +03004414/* returns HPLL frequency in kHz */
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004415static int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004416{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004417 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004418
Jesse Barnes586f49d2013-11-04 16:06:59 -08004419 /* Obtain SKU information */
4420 mutex_lock(&dev_priv->dpio_lock);
4421 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4422 CCK_FUSE_HPLL_FREQ_MASK;
4423 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004424
Ville Syrjälädfcab172014-06-13 13:37:47 +03004425 return vco_freq[hpll_freq] * 1000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004426}
4427
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004428static void vlv_update_cdclk(struct drm_device *dev)
4429{
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431
4432 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4433 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4434 dev_priv->vlv_cdclk_freq);
4435
4436 /*
4437 * Program the gmbus_freq based on the cdclk frequency.
4438 * BSpec erroneously claims we should aim for 4MHz, but
4439 * in fact 1MHz is the correct frequency.
4440 */
4441 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4442}
4443
Jesse Barnes30a970c2013-11-04 13:48:12 -08004444/* Adjust CDclk dividers to allow high res or save power if possible */
4445static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4446{
4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448 u32 val, cmd;
4449
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03004450 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02004451
Ville Syrjälädfcab172014-06-13 13:37:47 +03004452 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08004453 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03004454 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004455 cmd = 1;
4456 else
4457 cmd = 0;
4458
4459 mutex_lock(&dev_priv->rps.hw_lock);
4460 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4461 val &= ~DSPFREQGUAR_MASK;
4462 val |= (cmd << DSPFREQGUAR_SHIFT);
4463 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4464 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4465 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4466 50)) {
4467 DRM_ERROR("timed out waiting for CDclk change\n");
4468 }
4469 mutex_unlock(&dev_priv->rps.hw_lock);
4470
Ville Syrjälädfcab172014-06-13 13:37:47 +03004471 if (cdclk == 400000) {
Jesse Barnes30a970c2013-11-04 13:48:12 -08004472 u32 divider, vco;
4473
4474 vco = valleyview_get_vco(dev_priv);
Ville Syrjälädfcab172014-06-13 13:37:47 +03004475 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004476
4477 mutex_lock(&dev_priv->dpio_lock);
4478 /* adjust cdclk divider */
4479 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Ville Syrjälä9cf33db2014-06-13 13:37:48 +03004480 val &= ~DISPLAY_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004481 val |= divider;
4482 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03004483
4484 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4485 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4486 50))
4487 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08004488 mutex_unlock(&dev_priv->dpio_lock);
4489 }
4490
4491 mutex_lock(&dev_priv->dpio_lock);
4492 /* adjust self-refresh exit latency value */
4493 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4494 val &= ~0x7f;
4495
4496 /*
4497 * For high bandwidth configs, we set a higher latency in the bunit
4498 * so that the core display fetch happens in time to avoid underruns.
4499 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03004500 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004501 val |= 4500 / 250; /* 4.5 usec */
4502 else
4503 val |= 3000 / 250; /* 3.0 usec */
4504 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4505 mutex_unlock(&dev_priv->dpio_lock);
4506
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004507 vlv_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004508}
4509
Jesse Barnes30a970c2013-11-04 13:48:12 -08004510static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4511 int max_pixclk)
4512{
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004513 int vco = valleyview_get_vco(dev_priv);
4514 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4515
Jesse Barnes30a970c2013-11-04 13:48:12 -08004516 /*
4517 * Really only a few cases to deal with, as only 4 CDclks are supported:
4518 * 200MHz
4519 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004520 * 320/333MHz (depends on HPLL freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004521 * 400MHz
4522 * So we check to see whether we're above 90% of the lower bin and
4523 * adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004524 *
4525 * We seem to get an unstable or solid color picture at 200MHz.
4526 * Not sure what's wrong. For now use 200MHz only when all pipes
4527 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08004528 */
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004529 if (max_pixclk > freq_320*9/10)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004530 return 400000;
4531 else if (max_pixclk > 266667*9/10)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004532 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004533 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004534 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004535 else
4536 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004537}
4538
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004539/* compute the max pixel clock for new configuration */
4540static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004541{
4542 struct drm_device *dev = dev_priv->dev;
4543 struct intel_crtc *intel_crtc;
4544 int max_pixclk = 0;
4545
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004546 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004547 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004548 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004549 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004550 }
4551
4552 return max_pixclk;
4553}
4554
4555static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004556 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004557{
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004560 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004561
Imre Deakd60c4472014-03-27 17:45:10 +02004562 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4563 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004564 return;
4565
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004566 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004567 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004568 if (intel_crtc->base.enabled)
4569 *prepare_pipes |= (1 << intel_crtc->pipe);
4570}
4571
4572static void valleyview_modeset_global_resources(struct drm_device *dev)
4573{
4574 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004575 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004576 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4577
Imre Deakd60c4472014-03-27 17:45:10 +02004578 if (req_cdclk != dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004579 valleyview_set_cdclk(dev, req_cdclk);
Imre Deak77961eb2014-03-05 16:20:56 +02004580 modeset_update_crtc_power_domains(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004581}
4582
Jesse Barnes89b667f2013-04-18 14:51:36 -07004583static void valleyview_crtc_enable(struct drm_crtc *crtc)
4584{
4585 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004586 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4588 struct intel_encoder *encoder;
4589 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004590 int plane = intel_crtc->plane;
Jani Nikula23538ef2013-08-27 15:12:22 +03004591 bool is_dsi;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004592 u32 dspcntr;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004593
4594 WARN_ON(!crtc->enabled);
4595
4596 if (intel_crtc->active)
4597 return;
4598
Shobhit Kumar8525a232014-06-25 12:20:39 +05304599 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4600
4601 if (!is_dsi && !IS_CHERRYVIEW(dev))
4602 vlv_prepare_pll(intel_crtc);
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02004603
Daniel Vetter5b18e572014-04-24 23:55:06 +02004604 /* Set up the display plane register */
4605 dspcntr = DISPPLANE_GAMMA_ENABLE;
4606
4607 if (intel_crtc->config.has_dp_encoder)
4608 intel_dp_set_m_n(intel_crtc);
4609
4610 intel_set_pipe_timings(intel_crtc);
4611
4612 /* pipesrc and dspsize control the size that is scaled from,
4613 * which should always be the user's requested size.
4614 */
4615 I915_WRITE(DSPSIZE(plane),
4616 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4617 (intel_crtc->config.pipe_src_w - 1));
4618 I915_WRITE(DSPPOS(plane), 0);
4619
4620 i9xx_set_pipeconf(intel_crtc);
4621
4622 I915_WRITE(DSPCNTR(plane), dspcntr);
4623 POSTING_READ(DSPCNTR(plane));
4624
4625 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4626 crtc->x, crtc->y);
4627
Jesse Barnes89b667f2013-04-18 14:51:36 -07004628 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004629
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004630 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4631
Jesse Barnes89b667f2013-04-18 14:51:36 -07004632 for_each_encoder_on_crtc(dev, crtc, encoder)
4633 if (encoder->pre_pll_enable)
4634 encoder->pre_pll_enable(encoder);
4635
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004636 if (!is_dsi) {
4637 if (IS_CHERRYVIEW(dev))
4638 chv_enable_pll(intel_crtc);
4639 else
4640 vlv_enable_pll(intel_crtc);
4641 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004642
4643 for_each_encoder_on_crtc(dev, crtc, encoder)
4644 if (encoder->pre_enable)
4645 encoder->pre_enable(encoder);
4646
Jesse Barnes2dd24552013-04-25 12:55:01 -07004647 i9xx_pfit_enable(intel_crtc);
4648
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004649 intel_crtc_load_lut(crtc);
4650
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004651 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004652 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004653
Jani Nikula50049452013-07-30 12:20:32 +03004654 for_each_encoder_on_crtc(dev, crtc, encoder)
4655 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004656
4657 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004658
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004659 /* Underruns don't raise interrupts, so check manually. */
4660 i9xx_check_fifo_underruns(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004661}
4662
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004663static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4664{
4665 struct drm_device *dev = crtc->base.dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667
4668 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4669 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4670}
4671
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004672static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004673{
4674 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004675 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08004676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004677 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004678 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004679 int plane = intel_crtc->plane;
4680 u32 dspcntr;
Jesse Barnes79e53942008-11-07 14:24:08 -08004681
Daniel Vetter08a48462012-07-02 11:43:47 +02004682 WARN_ON(!crtc->enabled);
4683
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004684 if (intel_crtc->active)
4685 return;
4686
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004687 i9xx_set_pll_dividers(intel_crtc);
4688
Daniel Vetter5b18e572014-04-24 23:55:06 +02004689 /* Set up the display plane register */
4690 dspcntr = DISPPLANE_GAMMA_ENABLE;
4691
4692 if (pipe == 0)
4693 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4694 else
4695 dspcntr |= DISPPLANE_SEL_PIPE_B;
4696
4697 if (intel_crtc->config.has_dp_encoder)
4698 intel_dp_set_m_n(intel_crtc);
4699
4700 intel_set_pipe_timings(intel_crtc);
4701
4702 /* pipesrc and dspsize control the size that is scaled from,
4703 * which should always be the user's requested size.
4704 */
4705 I915_WRITE(DSPSIZE(plane),
4706 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4707 (intel_crtc->config.pipe_src_w - 1));
4708 I915_WRITE(DSPPOS(plane), 0);
4709
4710 i9xx_set_pipeconf(intel_crtc);
4711
4712 I915_WRITE(DSPCNTR(plane), dspcntr);
4713 POSTING_READ(DSPCNTR(plane));
4714
4715 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4716 crtc->x, crtc->y);
4717
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004718 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004719
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004720 if (!IS_GEN2(dev))
4721 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4722
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004723 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004724 if (encoder->pre_enable)
4725 encoder->pre_enable(encoder);
4726
Daniel Vetterf6736a12013-06-05 13:34:30 +02004727 i9xx_enable_pll(intel_crtc);
4728
Jesse Barnes2dd24552013-04-25 12:55:01 -07004729 i9xx_pfit_enable(intel_crtc);
4730
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004731 intel_crtc_load_lut(crtc);
4732
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004733 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004734 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004735
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004736 for_each_encoder_on_crtc(dev, crtc, encoder)
4737 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004738
4739 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004740
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004741 /*
4742 * Gen2 reports pipe underruns whenever all planes are disabled.
4743 * So don't enable underrun reporting before at least some planes
4744 * are enabled.
4745 * FIXME: Need to fix the logic to work when we turn off all planes
4746 * but leave the pipe running.
4747 */
4748 if (IS_GEN2(dev))
4749 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4750
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004751 /* Underruns don't raise interrupts, so check manually. */
4752 i9xx_check_fifo_underruns(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004753}
4754
Daniel Vetter87476d62013-04-11 16:29:06 +02004755static void i9xx_pfit_disable(struct intel_crtc *crtc)
4756{
4757 struct drm_device *dev = crtc->base.dev;
4758 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004759
4760 if (!crtc->config.gmch_pfit.control)
4761 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004762
4763 assert_pipe_disabled(dev_priv, crtc->pipe);
4764
Daniel Vetter328d8e82013-05-08 10:36:31 +02004765 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4766 I915_READ(PFIT_CONTROL));
4767 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004768}
4769
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004770static void i9xx_crtc_disable(struct drm_crtc *crtc)
4771{
4772 struct drm_device *dev = crtc->dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004775 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004776 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004777
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004778 if (!intel_crtc->active)
4779 return;
4780
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004781 /*
4782 * Gen2 reports pipe underruns whenever all planes are disabled.
4783 * So diasble underrun reporting before all the planes get disabled.
4784 * FIXME: Need to fix the logic to work when we turn off all planes
4785 * but leave the pipe running.
4786 */
4787 if (IS_GEN2(dev))
4788 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4789
Imre Deak564ed192014-06-13 14:54:21 +03004790 /*
4791 * Vblank time updates from the shadow to live plane control register
4792 * are blocked if the memory self-refresh mode is active at that
4793 * moment. So to make sure the plane gets truly disabled, disable
4794 * first the self-refresh mode. The self-refresh enable bit in turn
4795 * will be checked/applied by the HW only at the next frame start
4796 * event which is after the vblank start event, so we need to have a
4797 * wait-for-vblank between disabling the plane and the pipe.
4798 */
4799 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004800 intel_crtc_disable_planes(crtc);
4801
Daniel Vetterea9d7582012-07-10 10:42:52 +02004802 for_each_encoder_on_crtc(dev, crtc, encoder)
4803 encoder->disable(encoder);
4804
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004805 /*
4806 * On gen2 planes are double buffered but the pipe isn't, so we must
4807 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03004808 * We also need to wait on all gmch platforms because of the
4809 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004810 */
Imre Deak564ed192014-06-13 14:54:21 +03004811 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004812
Jesse Barnesb24e7172011-01-04 15:09:30 -08004813 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004814
Daniel Vetter87476d62013-04-11 16:29:06 +02004815 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004816
Jesse Barnes89b667f2013-04-18 14:51:36 -07004817 for_each_encoder_on_crtc(dev, crtc, encoder)
4818 if (encoder->post_disable)
4819 encoder->post_disable(encoder);
4820
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03004821 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4822 if (IS_CHERRYVIEW(dev))
4823 chv_disable_pll(dev_priv, pipe);
4824 else if (IS_VALLEYVIEW(dev))
4825 vlv_disable_pll(dev_priv, pipe);
4826 else
4827 i9xx_disable_pll(dev_priv, pipe);
4828 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004829
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004830 if (!IS_GEN2(dev))
4831 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4832
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004833 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004834 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004835
Daniel Vetterefa96242014-04-24 23:55:02 +02004836 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004837 intel_update_fbc(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02004838 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004839}
4840
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004841static void i9xx_crtc_off(struct drm_crtc *crtc)
4842{
4843}
4844
Daniel Vetter976f8a22012-07-08 22:34:21 +02004845static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4846 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004847{
4848 struct drm_device *dev = crtc->dev;
4849 struct drm_i915_master_private *master_priv;
4850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4851 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004852
4853 if (!dev->primary->master)
4854 return;
4855
4856 master_priv = dev->primary->master->driver_priv;
4857 if (!master_priv->sarea_priv)
4858 return;
4859
Jesse Barnes79e53942008-11-07 14:24:08 -08004860 switch (pipe) {
4861 case 0:
4862 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4863 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4864 break;
4865 case 1:
4866 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4867 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4868 break;
4869 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004870 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004871 break;
4872 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004873}
4874
Daniel Vetter976f8a22012-07-08 22:34:21 +02004875/**
4876 * Sets the power management mode of the pipe and plane.
4877 */
4878void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004879{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004880 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004881 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter976f8a22012-07-08 22:34:21 +02004883 struct intel_encoder *intel_encoder;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004884 enum intel_display_power_domain domain;
4885 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004886 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004887
Daniel Vetter976f8a22012-07-08 22:34:21 +02004888 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4889 enable |= intel_encoder->connectors_active;
4890
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004891 if (enable) {
4892 if (!intel_crtc->active) {
Daniel Vettere1e9fb82014-06-25 22:02:04 +03004893 domains = get_crtc_power_domains(crtc);
4894 for_each_power_domain(domain, domains)
4895 intel_display_power_get(dev_priv, domain);
4896 intel_crtc->enabled_power_domains = domains;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004897
4898 dev_priv->display.crtc_enable(crtc);
4899 }
4900 } else {
4901 if (intel_crtc->active) {
4902 dev_priv->display.crtc_disable(crtc);
4903
Daniel Vettere1e9fb82014-06-25 22:02:04 +03004904 domains = intel_crtc->enabled_power_domains;
4905 for_each_power_domain(domain, domains)
4906 intel_display_power_put(dev_priv, domain);
4907 intel_crtc->enabled_power_domains = 0;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004908 }
4909 }
Daniel Vetter976f8a22012-07-08 22:34:21 +02004910
4911 intel_crtc_update_sarea(crtc, enable);
4912}
4913
Daniel Vetter976f8a22012-07-08 22:34:21 +02004914static void intel_crtc_disable(struct drm_crtc *crtc)
4915{
4916 struct drm_device *dev = crtc->dev;
4917 struct drm_connector *connector;
4918 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper2ff8fde2014-07-08 07:50:07 -07004919 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
Daniel Vettera071fa02014-06-18 23:28:09 +02004920 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004921
4922 /* crtc should still be enabled when we disable it. */
4923 WARN_ON(!crtc->enabled);
4924
4925 dev_priv->display.crtc_disable(crtc);
4926 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004927 dev_priv->display.off(crtc);
4928
Chris Wilson931872f2012-01-16 23:01:13 +00004929 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
Daniel Vettera071fa02014-06-18 23:28:09 +02004930 assert_cursor_disabled(dev_priv, pipe);
4931 assert_pipe_disabled(dev->dev_private, pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004932
Matt Roperf4510a22014-04-01 15:22:40 -07004933 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01004934 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02004935 intel_unpin_fb_obj(old_obj);
4936 i915_gem_track_fb(old_obj, NULL,
4937 INTEL_FRONTBUFFER_PRIMARY(pipe));
Chris Wilsoncdd59982010-09-08 16:30:16 +01004938 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004939 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004940 }
4941
4942 /* Update computed state. */
4943 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4944 if (!connector->encoder || !connector->encoder->crtc)
4945 continue;
4946
4947 if (connector->encoder->crtc != crtc)
4948 continue;
4949
4950 connector->dpms = DRM_MODE_DPMS_OFF;
4951 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004952 }
4953}
4954
Chris Wilsonea5b2132010-08-04 13:50:23 +01004955void intel_encoder_destroy(struct drm_encoder *encoder)
4956{
Chris Wilson4ef69c72010-09-09 15:14:28 +01004957 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01004958
Chris Wilsonea5b2132010-08-04 13:50:23 +01004959 drm_encoder_cleanup(encoder);
4960 kfree(intel_encoder);
4961}
4962
Damien Lespiau92373292013-08-08 22:28:57 +01004963/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004964 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4965 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01004966static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004967{
4968 if (mode == DRM_MODE_DPMS_ON) {
4969 encoder->connectors_active = true;
4970
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004971 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004972 } else {
4973 encoder->connectors_active = false;
4974
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004975 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004976 }
4977}
4978
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004979/* Cross check the actual hw state with our own modeset state tracking (and it's
4980 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02004981static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004982{
4983 if (connector->get_hw_state(connector)) {
4984 struct intel_encoder *encoder = connector->encoder;
4985 struct drm_crtc *crtc;
4986 bool encoder_enabled;
4987 enum pipe pipe;
4988
4989 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4990 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03004991 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004992
4993 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4994 "wrong connector dpms state\n");
4995 WARN(connector->base.encoder != &encoder->base,
4996 "active connector not linked to encoder\n");
4997 WARN(!encoder->connectors_active,
4998 "encoder->connectors_active not set\n");
4999
5000 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5001 WARN(!encoder_enabled, "encoder not enabled\n");
5002 if (WARN_ON(!encoder->base.crtc))
5003 return;
5004
5005 crtc = encoder->base.crtc;
5006
5007 WARN(!crtc->enabled, "crtc not enabled\n");
5008 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5009 WARN(pipe != to_intel_crtc(crtc)->pipe,
5010 "encoder active on the wrong pipe\n");
5011 }
5012}
5013
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005014/* Even simpler default implementation, if there's really no special case to
5015 * consider. */
5016void intel_connector_dpms(struct drm_connector *connector, int mode)
5017{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005018 /* All the simple cases only support two dpms states. */
5019 if (mode != DRM_MODE_DPMS_ON)
5020 mode = DRM_MODE_DPMS_OFF;
5021
5022 if (mode == connector->dpms)
5023 return;
5024
5025 connector->dpms = mode;
5026
5027 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01005028 if (connector->encoder)
5029 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005030
Daniel Vetterb9805142012-08-31 17:37:33 +02005031 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005032}
5033
Daniel Vetterf0947c32012-07-02 13:10:34 +02005034/* Simple connector->get_hw_state implementation for encoders that support only
5035 * one connector and no cloning and hence the encoder state determines the state
5036 * of the connector. */
5037bool intel_connector_get_hw_state(struct intel_connector *connector)
5038{
Daniel Vetter24929352012-07-02 20:28:59 +02005039 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02005040 struct intel_encoder *encoder = connector->encoder;
5041
5042 return encoder->get_hw_state(encoder, &pipe);
5043}
5044
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005045static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5046 struct intel_crtc_config *pipe_config)
5047{
5048 struct drm_i915_private *dev_priv = dev->dev_private;
5049 struct intel_crtc *pipe_B_crtc =
5050 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5051
5052 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5053 pipe_name(pipe), pipe_config->fdi_lanes);
5054 if (pipe_config->fdi_lanes > 4) {
5055 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5056 pipe_name(pipe), pipe_config->fdi_lanes);
5057 return false;
5058 }
5059
Paulo Zanonibafb6552013-11-02 21:07:44 -07005060 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005061 if (pipe_config->fdi_lanes > 2) {
5062 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5063 pipe_config->fdi_lanes);
5064 return false;
5065 } else {
5066 return true;
5067 }
5068 }
5069
5070 if (INTEL_INFO(dev)->num_pipes == 2)
5071 return true;
5072
5073 /* Ivybridge 3 pipe is really complicated */
5074 switch (pipe) {
5075 case PIPE_A:
5076 return true;
5077 case PIPE_B:
5078 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5079 pipe_config->fdi_lanes > 2) {
5080 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5081 pipe_name(pipe), pipe_config->fdi_lanes);
5082 return false;
5083 }
5084 return true;
5085 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005086 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005087 pipe_B_crtc->config.fdi_lanes <= 2) {
5088 if (pipe_config->fdi_lanes > 2) {
5089 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5090 pipe_name(pipe), pipe_config->fdi_lanes);
5091 return false;
5092 }
5093 } else {
5094 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5095 return false;
5096 }
5097 return true;
5098 default:
5099 BUG();
5100 }
5101}
5102
Daniel Vettere29c22c2013-02-21 00:00:16 +01005103#define RETRY 1
5104static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5105 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005106{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005107 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005108 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005109 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005110 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005111
Daniel Vettere29c22c2013-02-21 00:00:16 +01005112retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005113 /* FDI is a binary signal running at ~2.7GHz, encoding
5114 * each output octet as 10 bits. The actual frequency
5115 * is stored as a divider into a 100MHz clock, and the
5116 * mode pixel clock is stored in units of 1KHz.
5117 * Hence the bw of each lane in terms of the mode signal
5118 * is:
5119 */
5120 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5121
Damien Lespiau241bfc32013-09-25 16:45:37 +01005122 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005123
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005124 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005125 pipe_config->pipe_bpp);
5126
5127 pipe_config->fdi_lanes = lane;
5128
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005129 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005130 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005131
Daniel Vettere29c22c2013-02-21 00:00:16 +01005132 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5133 intel_crtc->pipe, pipe_config);
5134 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5135 pipe_config->pipe_bpp -= 2*3;
5136 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5137 pipe_config->pipe_bpp);
5138 needs_recompute = true;
5139 pipe_config->bw_constrained = true;
5140
5141 goto retry;
5142 }
5143
5144 if (needs_recompute)
5145 return RETRY;
5146
5147 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005148}
5149
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005150static void hsw_compute_ips_config(struct intel_crtc *crtc,
5151 struct intel_crtc_config *pipe_config)
5152{
Jani Nikulad330a952014-01-21 11:24:25 +02005153 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005154 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005155 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005156}
5157
Daniel Vettera43f6e02013-06-07 23:10:32 +02005158static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005159 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005160{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005161 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005162 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005163
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005164 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005165 if (INTEL_INFO(dev)->gen < 4) {
5166 struct drm_i915_private *dev_priv = dev->dev_private;
5167 int clock_limit =
5168 dev_priv->display.get_display_clock_speed(dev);
5169
5170 /*
5171 * Enable pixel doubling when the dot clock
5172 * is > 90% of the (display) core speed.
5173 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005174 * GDG double wide on either pipe,
5175 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005176 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005177 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005178 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005179 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005180 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005181 }
5182
Damien Lespiau241bfc32013-09-25 16:45:37 +01005183 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005184 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005185 }
Chris Wilson89749352010-09-12 18:25:19 +01005186
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005187 /*
5188 * Pipe horizontal size must be even in:
5189 * - DVO ganged mode
5190 * - LVDS dual channel mode
5191 * - Double wide pipe
5192 */
5193 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5194 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5195 pipe_config->pipe_src_w &= ~1;
5196
Damien Lespiau8693a822013-05-03 18:48:11 +01005197 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5198 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005199 */
5200 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5201 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005202 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005203
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005204 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005205 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005206 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005207 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5208 * for lvds. */
5209 pipe_config->pipe_bpp = 8*3;
5210 }
5211
Damien Lespiauf5adf942013-06-24 18:29:34 +01005212 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005213 hsw_compute_ips_config(crtc, pipe_config);
5214
Daniel Vetter12030432014-06-25 22:02:00 +03005215 /*
5216 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5217 * old clock survives for now.
5218 */
5219 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005220 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005221
Daniel Vetter877d48d2013-04-19 11:24:43 +02005222 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005223 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005224
Daniel Vettere29c22c2013-02-21 00:00:16 +01005225 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005226}
5227
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005228static int valleyview_get_display_clock_speed(struct drm_device *dev)
5229{
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005230 struct drm_i915_private *dev_priv = dev->dev_private;
5231 int vco = valleyview_get_vco(dev_priv);
5232 u32 val;
5233 int divider;
5234
5235 mutex_lock(&dev_priv->dpio_lock);
5236 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5237 mutex_unlock(&dev_priv->dpio_lock);
5238
5239 divider = val & DISPLAY_FREQUENCY_VALUES;
5240
Ville Syrjälä7d007f42014-06-13 13:37:53 +03005241 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5242 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5243 "cdclk change in progress\n");
5244
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005245 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005246}
5247
Jesse Barnese70236a2009-09-21 10:42:27 -07005248static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005249{
Jesse Barnese70236a2009-09-21 10:42:27 -07005250 return 400000;
5251}
Jesse Barnes79e53942008-11-07 14:24:08 -08005252
Jesse Barnese70236a2009-09-21 10:42:27 -07005253static int i915_get_display_clock_speed(struct drm_device *dev)
5254{
5255 return 333000;
5256}
Jesse Barnes79e53942008-11-07 14:24:08 -08005257
Jesse Barnese70236a2009-09-21 10:42:27 -07005258static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5259{
5260 return 200000;
5261}
Jesse Barnes79e53942008-11-07 14:24:08 -08005262
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005263static int pnv_get_display_clock_speed(struct drm_device *dev)
5264{
5265 u16 gcfgc = 0;
5266
5267 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5268
5269 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5270 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5271 return 267000;
5272 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5273 return 333000;
5274 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5275 return 444000;
5276 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5277 return 200000;
5278 default:
5279 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5280 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5281 return 133000;
5282 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5283 return 167000;
5284 }
5285}
5286
Jesse Barnese70236a2009-09-21 10:42:27 -07005287static int i915gm_get_display_clock_speed(struct drm_device *dev)
5288{
5289 u16 gcfgc = 0;
5290
5291 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5292
5293 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005294 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005295 else {
5296 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5297 case GC_DISPLAY_CLOCK_333_MHZ:
5298 return 333000;
5299 default:
5300 case GC_DISPLAY_CLOCK_190_200_MHZ:
5301 return 190000;
5302 }
5303 }
5304}
Jesse Barnes79e53942008-11-07 14:24:08 -08005305
Jesse Barnese70236a2009-09-21 10:42:27 -07005306static int i865_get_display_clock_speed(struct drm_device *dev)
5307{
5308 return 266000;
5309}
5310
5311static int i855_get_display_clock_speed(struct drm_device *dev)
5312{
5313 u16 hpllcc = 0;
5314 /* Assume that the hardware is in the high speed state. This
5315 * should be the default.
5316 */
5317 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5318 case GC_CLOCK_133_200:
5319 case GC_CLOCK_100_200:
5320 return 200000;
5321 case GC_CLOCK_166_250:
5322 return 250000;
5323 case GC_CLOCK_100_133:
5324 return 133000;
5325 }
5326
5327 /* Shouldn't happen */
5328 return 0;
5329}
5330
5331static int i830_get_display_clock_speed(struct drm_device *dev)
5332{
5333 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005334}
5335
Zhenyu Wang2c072452009-06-05 15:38:42 +08005336static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005337intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005338{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005339 while (*num > DATA_LINK_M_N_MASK ||
5340 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005341 *num >>= 1;
5342 *den >>= 1;
5343 }
5344}
5345
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005346static void compute_m_n(unsigned int m, unsigned int n,
5347 uint32_t *ret_m, uint32_t *ret_n)
5348{
5349 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5350 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5351 intel_reduce_m_n_ratio(ret_m, ret_n);
5352}
5353
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005354void
5355intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5356 int pixel_clock, int link_clock,
5357 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005358{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005359 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005360
5361 compute_m_n(bits_per_pixel * pixel_clock,
5362 link_clock * nlanes * 8,
5363 &m_n->gmch_m, &m_n->gmch_n);
5364
5365 compute_m_n(pixel_clock, link_clock,
5366 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005367}
5368
Chris Wilsona7615032011-01-12 17:04:08 +00005369static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5370{
Jani Nikulad330a952014-01-21 11:24:25 +02005371 if (i915.panel_use_ssc >= 0)
5372 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005373 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005374 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005375}
5376
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005377static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5378{
5379 struct drm_device *dev = crtc->dev;
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381 int refclk;
5382
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005383 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005384 refclk = 100000;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005386 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005387 refclk = dev_priv->vbt.lvds_ssc_freq;
5388 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005389 } else if (!IS_GEN2(dev)) {
5390 refclk = 96000;
5391 } else {
5392 refclk = 48000;
5393 }
5394
5395 return refclk;
5396}
5397
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005398static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005399{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005400 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005401}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005402
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005403static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5404{
5405 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005406}
5407
Daniel Vetterf47709a2013-03-28 10:42:02 +01005408static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005409 intel_clock_t *reduced_clock)
5410{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005411 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005412 u32 fp, fp2 = 0;
5413
5414 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005415 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005416 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005417 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005418 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005419 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005420 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005421 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005422 }
5423
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005424 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005425
Daniel Vetterf47709a2013-03-28 10:42:02 +01005426 crtc->lowfreq_avail = false;
5427 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005428 reduced_clock && i915.powersave) {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005429 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005430 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005431 } else {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005432 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005433 }
5434}
5435
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005436static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5437 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005438{
5439 u32 reg_val;
5440
5441 /*
5442 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5443 * and set it to a reasonable value instead.
5444 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005445 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005446 reg_val &= 0xffffff00;
5447 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005448 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005449
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005450 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005451 reg_val &= 0x8cffffff;
5452 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005453 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005454
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005455 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005456 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005457 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005458
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005459 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005460 reg_val &= 0x00ffffff;
5461 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005462 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005463}
5464
Daniel Vetterb5518422013-05-03 11:49:48 +02005465static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5466 struct intel_link_m_n *m_n)
5467{
5468 struct drm_device *dev = crtc->base.dev;
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470 int pipe = crtc->pipe;
5471
Daniel Vettere3b95f12013-05-03 11:49:49 +02005472 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5473 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5474 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5475 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005476}
5477
5478static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5479 struct intel_link_m_n *m_n)
5480{
5481 struct drm_device *dev = crtc->base.dev;
5482 struct drm_i915_private *dev_priv = dev->dev_private;
5483 int pipe = crtc->pipe;
5484 enum transcoder transcoder = crtc->config.cpu_transcoder;
5485
5486 if (INTEL_INFO(dev)->gen >= 5) {
5487 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5488 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5489 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5490 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5491 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005492 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5493 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5494 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5495 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005496 }
5497}
5498
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005499static void intel_dp_set_m_n(struct intel_crtc *crtc)
5500{
5501 if (crtc->config.has_pch_encoder)
5502 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5503 else
5504 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5505}
5506
Daniel Vetterf47709a2013-03-28 10:42:02 +01005507static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005508{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005509 u32 dpll, dpll_md;
5510
5511 /*
5512 * Enable DPIO clock input. We should never disable the reference
5513 * clock for pipe B, since VGA hotplug / manual detection depends
5514 * on it.
5515 */
5516 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5517 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5518 /* We should never disable this, set it here for state tracking */
5519 if (crtc->pipe == PIPE_B)
5520 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5521 dpll |= DPLL_VCO_ENABLE;
5522 crtc->config.dpll_hw_state.dpll = dpll;
5523
5524 dpll_md = (crtc->config.pixel_multiplier - 1)
5525 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5526 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5527}
5528
5529static void vlv_prepare_pll(struct intel_crtc *crtc)
5530{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005531 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005532 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005533 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005534 u32 mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005535 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005536 u32 coreclk, reg_val;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005537
Daniel Vetter09153002012-12-12 14:06:44 +01005538 mutex_lock(&dev_priv->dpio_lock);
5539
Daniel Vetterf47709a2013-03-28 10:42:02 +01005540 bestn = crtc->config.dpll.n;
5541 bestm1 = crtc->config.dpll.m1;
5542 bestm2 = crtc->config.dpll.m2;
5543 bestp1 = crtc->config.dpll.p1;
5544 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005545
Jesse Barnes89b667f2013-04-18 14:51:36 -07005546 /* See eDP HDMI DPIO driver vbios notes doc */
5547
5548 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005549 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005550 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005551
5552 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005553 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005554
5555 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005556 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005557 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005558 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005559
5560 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005561 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005562
5563 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005564 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5565 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5566 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005567 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005568
5569 /*
5570 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5571 * but we don't support that).
5572 * Note: don't use the DAC post divider as it seems unstable.
5573 */
5574 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005575 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005576
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005577 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005578 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005579
Jesse Barnes89b667f2013-04-18 14:51:36 -07005580 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02005581 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03005582 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07005583 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03005585 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005586 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005587 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005588 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005589
Jesse Barnes89b667f2013-04-18 14:51:36 -07005590 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5591 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5592 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005593 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005595 0x0df40000);
5596 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005597 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005598 0x0df70000);
5599 } else { /* HDMI or VGA */
5600 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005601 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005602 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005603 0x0df70000);
5604 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005605 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005606 0x0df40000);
5607 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005608
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005609 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005610 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5611 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5612 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5613 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005614 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005615
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005616 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005617 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005618}
5619
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005620static void chv_update_pll(struct intel_crtc *crtc)
5621{
5622 struct drm_device *dev = crtc->base.dev;
5623 struct drm_i915_private *dev_priv = dev->dev_private;
5624 int pipe = crtc->pipe;
5625 int dpll_reg = DPLL(crtc->pipe);
5626 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005627 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005628 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5629 int refclk;
5630
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005631 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5632 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5633 DPLL_VCO_ENABLE;
5634 if (pipe != PIPE_A)
5635 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5636
5637 crtc->config.dpll_hw_state.dpll_md =
5638 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005639
5640 bestn = crtc->config.dpll.n;
5641 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5642 bestm1 = crtc->config.dpll.m1;
5643 bestm2 = crtc->config.dpll.m2 >> 22;
5644 bestp1 = crtc->config.dpll.p1;
5645 bestp2 = crtc->config.dpll.p2;
5646
5647 /*
5648 * Enable Refclk and SSC
5649 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005650 I915_WRITE(dpll_reg,
5651 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5652
5653 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005654
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005655 /* p1 and p2 divider */
5656 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5657 5 << DPIO_CHV_S1_DIV_SHIFT |
5658 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5659 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5660 1 << DPIO_CHV_K_DIV_SHIFT);
5661
5662 /* Feedback post-divider - m2 */
5663 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5664
5665 /* Feedback refclk divider - n and m1 */
5666 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5667 DPIO_CHV_M1_DIV_BY_2 |
5668 1 << DPIO_CHV_N_DIV_SHIFT);
5669
5670 /* M2 fraction division */
5671 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5672
5673 /* M2 fraction division enable */
5674 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5675 DPIO_CHV_FRAC_DIV_EN |
5676 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5677
5678 /* Loop filter */
5679 refclk = i9xx_get_refclk(&crtc->base, 0);
5680 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5681 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5682 if (refclk == 100000)
5683 intcoeff = 11;
5684 else if (refclk == 38400)
5685 intcoeff = 10;
5686 else
5687 intcoeff = 9;
5688 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5689 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5690
5691 /* AFC Recal */
5692 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5693 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5694 DPIO_AFC_RECAL);
5695
5696 mutex_unlock(&dev_priv->dpio_lock);
5697}
5698
Daniel Vetterf47709a2013-03-28 10:42:02 +01005699static void i9xx_update_pll(struct intel_crtc *crtc,
5700 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005701 int num_connectors)
5702{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005703 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005704 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005705 u32 dpll;
5706 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005707 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005708
Daniel Vetterf47709a2013-03-28 10:42:02 +01005709 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305710
Daniel Vetterf47709a2013-03-28 10:42:02 +01005711 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5712 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005713
5714 dpll = DPLL_VGA_MODE_DIS;
5715
Daniel Vetterf47709a2013-03-28 10:42:02 +01005716 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005717 dpll |= DPLLB_MODE_LVDS;
5718 else
5719 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005720
Daniel Vetteref1b4602013-06-01 17:17:04 +02005721 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02005722 dpll |= (crtc->config.pixel_multiplier - 1)
5723 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005724 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02005725
5726 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02005727 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005728
Daniel Vetterf47709a2013-03-28 10:42:02 +01005729 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02005730 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005731
5732 /* compute bitmask from p1 value */
5733 if (IS_PINEVIEW(dev))
5734 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5735 else {
5736 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5737 if (IS_G4X(dev) && reduced_clock)
5738 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5739 }
5740 switch (clock->p2) {
5741 case 5:
5742 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5743 break;
5744 case 7:
5745 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5746 break;
5747 case 10:
5748 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5749 break;
5750 case 14:
5751 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5752 break;
5753 }
5754 if (INTEL_INFO(dev)->gen >= 4)
5755 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5756
Daniel Vetter09ede542013-04-30 14:01:45 +02005757 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005758 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005759 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005760 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5761 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5762 else
5763 dpll |= PLL_REF_INPUT_DREFCLK;
5764
5765 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005766 crtc->config.dpll_hw_state.dpll = dpll;
5767
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005768 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005769 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5770 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005771 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005772 }
5773}
5774
Daniel Vetterf47709a2013-03-28 10:42:02 +01005775static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005776 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005777 int num_connectors)
5778{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005779 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005780 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005781 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005782 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005783
Daniel Vetterf47709a2013-03-28 10:42:02 +01005784 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305785
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005786 dpll = DPLL_VGA_MODE_DIS;
5787
Daniel Vetterf47709a2013-03-28 10:42:02 +01005788 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005789 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5790 } else {
5791 if (clock->p1 == 2)
5792 dpll |= PLL_P1_DIVIDE_BY_TWO;
5793 else
5794 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5795 if (clock->p2 == 4)
5796 dpll |= PLL_P2_DIVIDE_BY_4;
5797 }
5798
Daniel Vetter4a33e482013-07-06 12:52:05 +02005799 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5800 dpll |= DPLL_DVO_2X_MODE;
5801
Daniel Vetterf47709a2013-03-28 10:42:02 +01005802 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005803 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5804 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5805 else
5806 dpll |= PLL_REF_INPUT_DREFCLK;
5807
5808 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005809 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005810}
5811
Daniel Vetter8a654f32013-06-01 17:16:22 +02005812static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005813{
5814 struct drm_device *dev = intel_crtc->base.dev;
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005817 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005818 struct drm_display_mode *adjusted_mode =
5819 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005820 uint32_t crtc_vtotal, crtc_vblank_end;
5821 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005822
5823 /* We need to be careful not to changed the adjusted mode, for otherwise
5824 * the hw state checker will get angry at the mismatch. */
5825 crtc_vtotal = adjusted_mode->crtc_vtotal;
5826 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005827
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005828 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005829 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005830 crtc_vtotal -= 1;
5831 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005832
5833 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5834 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5835 else
5836 vsyncshift = adjusted_mode->crtc_hsync_start -
5837 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005838 if (vsyncshift < 0)
5839 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005840 }
5841
5842 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005843 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005844
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005845 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005846 (adjusted_mode->crtc_hdisplay - 1) |
5847 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005848 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005849 (adjusted_mode->crtc_hblank_start - 1) |
5850 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005851 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005852 (adjusted_mode->crtc_hsync_start - 1) |
5853 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5854
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005855 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005856 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005857 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005858 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005859 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005860 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005861 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005862 (adjusted_mode->crtc_vsync_start - 1) |
5863 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5864
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005865 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5866 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5867 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5868 * bits. */
5869 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5870 (pipe == PIPE_B || pipe == PIPE_C))
5871 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5872
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005873 /* pipesrc controls the size that is scaled from, which should
5874 * always be the user's requested size.
5875 */
5876 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005877 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5878 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005879}
5880
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005881static void intel_get_pipe_timings(struct intel_crtc *crtc,
5882 struct intel_crtc_config *pipe_config)
5883{
5884 struct drm_device *dev = crtc->base.dev;
5885 struct drm_i915_private *dev_priv = dev->dev_private;
5886 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5887 uint32_t tmp;
5888
5889 tmp = I915_READ(HTOTAL(cpu_transcoder));
5890 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5891 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5892 tmp = I915_READ(HBLANK(cpu_transcoder));
5893 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5894 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5895 tmp = I915_READ(HSYNC(cpu_transcoder));
5896 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5897 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5898
5899 tmp = I915_READ(VTOTAL(cpu_transcoder));
5900 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5901 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5902 tmp = I915_READ(VBLANK(cpu_transcoder));
5903 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5904 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5905 tmp = I915_READ(VSYNC(cpu_transcoder));
5906 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5907 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5908
5909 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5910 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5911 pipe_config->adjusted_mode.crtc_vtotal += 1;
5912 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5913 }
5914
5915 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005916 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5917 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5918
5919 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5920 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005921}
5922
Daniel Vetterf6a83282014-02-11 15:28:57 -08005923void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5924 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03005925{
Daniel Vetterf6a83282014-02-11 15:28:57 -08005926 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5927 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5928 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5929 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005930
Daniel Vetterf6a83282014-02-11 15:28:57 -08005931 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5932 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5933 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5934 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005935
Daniel Vetterf6a83282014-02-11 15:28:57 -08005936 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03005937
Daniel Vetterf6a83282014-02-11 15:28:57 -08005938 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5939 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03005940}
5941
Daniel Vetter84b046f2013-02-19 18:48:54 +01005942static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5943{
5944 struct drm_device *dev = intel_crtc->base.dev;
5945 struct drm_i915_private *dev_priv = dev->dev_private;
5946 uint32_t pipeconf;
5947
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005948 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005949
Daniel Vetter67c72a12013-09-24 11:46:14 +02005950 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5951 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5952 pipeconf |= PIPECONF_ENABLE;
5953
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005954 if (intel_crtc->config.double_wide)
5955 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005956
Daniel Vetterff9ce462013-04-24 14:57:17 +02005957 /* only g4x and later have fancy bpc/dither controls */
5958 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02005959 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5960 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5961 pipeconf |= PIPECONF_DITHER_EN |
5962 PIPECONF_DITHER_TYPE_SP;
5963
5964 switch (intel_crtc->config.pipe_bpp) {
5965 case 18:
5966 pipeconf |= PIPECONF_6BPC;
5967 break;
5968 case 24:
5969 pipeconf |= PIPECONF_8BPC;
5970 break;
5971 case 30:
5972 pipeconf |= PIPECONF_10BPC;
5973 break;
5974 default:
5975 /* Case prevented by intel_choose_pipe_bpp_dither. */
5976 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01005977 }
5978 }
5979
5980 if (HAS_PIPE_CXSR(dev)) {
5981 if (intel_crtc->lowfreq_avail) {
5982 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5983 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5984 } else {
5985 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01005986 }
5987 }
5988
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02005989 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5990 if (INTEL_INFO(dev)->gen < 4 ||
5991 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5992 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5993 else
5994 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5995 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01005996 pipeconf |= PIPECONF_PROGRESSIVE;
5997
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005998 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5999 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03006000
Daniel Vetter84b046f2013-02-19 18:48:54 +01006001 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6002 POSTING_READ(PIPECONF(intel_crtc->pipe));
6003}
6004
Eric Anholtf564048e2011-03-30 13:01:02 -07006005static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07006006 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006007 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006008{
6009 struct drm_device *dev = crtc->dev;
6010 struct drm_i915_private *dev_priv = dev->dev_private;
6011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Eric Anholtc751ce42010-03-25 11:48:48 -07006012 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07006013 intel_clock_t clock, reduced_clock;
Daniel Vettera16af7212013-04-30 14:01:44 +02006014 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006015 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01006016 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08006017 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08006018
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02006019 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01006020 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006021 case INTEL_OUTPUT_LVDS:
6022 is_lvds = true;
6023 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006024 case INTEL_OUTPUT_DSI:
6025 is_dsi = true;
6026 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006027 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006028
Eric Anholtc751ce42010-03-25 11:48:48 -07006029 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08006030 }
6031
Jani Nikulaf2335332013-09-13 11:03:09 +03006032 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02006033 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006034
Jani Nikulaf2335332013-09-13 11:03:09 +03006035 if (!intel_crtc->config.clock_set) {
6036 refclk = i9xx_get_refclk(crtc, num_connectors);
6037
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006038 /*
6039 * Returns a set of divisors for the desired target clock with
6040 * the given refclk, or FALSE. The returned values represent
6041 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6042 * 2) / p1 / p2.
6043 */
6044 limit = intel_limit(crtc, refclk);
6045 ok = dev_priv->display.find_dpll(limit, crtc,
6046 intel_crtc->config.port_clock,
6047 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03006048 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006049 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6050 return -EINVAL;
6051 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006052
Jani Nikulaf2335332013-09-13 11:03:09 +03006053 if (is_lvds && dev_priv->lvds_downclock_avail) {
6054 /*
6055 * Ensure we match the reduced clock's P to the target
6056 * clock. If the clocks don't match, we can't switch
6057 * the display clock by using the FP0/FP1. In such case
6058 * we will disable the LVDS downclock feature.
6059 */
6060 has_reduced_clock =
6061 dev_priv->display.find_dpll(limit, crtc,
6062 dev_priv->lvds_downclock,
6063 refclk, &clock,
6064 &reduced_clock);
6065 }
6066 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01006067 intel_crtc->config.dpll.n = clock.n;
6068 intel_crtc->config.dpll.m1 = clock.m1;
6069 intel_crtc->config.dpll.m2 = clock.m2;
6070 intel_crtc->config.dpll.p1 = clock.p1;
6071 intel_crtc->config.dpll.p2 = clock.p2;
6072 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006073
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006074 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02006075 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306076 has_reduced_clock ? &reduced_clock : NULL,
6077 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006078 } else if (IS_CHERRYVIEW(dev)) {
6079 chv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006080 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03006081 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006082 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01006083 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006084 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006085 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006086 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006087
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006088 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006089}
6090
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006091static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6092 struct intel_crtc_config *pipe_config)
6093{
6094 struct drm_device *dev = crtc->base.dev;
6095 struct drm_i915_private *dev_priv = dev->dev_private;
6096 uint32_t tmp;
6097
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006098 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6099 return;
6100
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006101 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006102 if (!(tmp & PFIT_ENABLE))
6103 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006104
Daniel Vetter06922822013-07-11 13:35:40 +02006105 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006106 if (INTEL_INFO(dev)->gen < 4) {
6107 if (crtc->pipe != PIPE_B)
6108 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006109 } else {
6110 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6111 return;
6112 }
6113
Daniel Vetter06922822013-07-11 13:35:40 +02006114 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006115 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6116 if (INTEL_INFO(dev)->gen < 5)
6117 pipe_config->gmch_pfit.lvds_border_bits =
6118 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6119}
6120
Jesse Barnesacbec812013-09-20 11:29:32 -07006121static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6122 struct intel_crtc_config *pipe_config)
6123{
6124 struct drm_device *dev = crtc->base.dev;
6125 struct drm_i915_private *dev_priv = dev->dev_private;
6126 int pipe = pipe_config->cpu_transcoder;
6127 intel_clock_t clock;
6128 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006129 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006130
6131 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006132 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006133 mutex_unlock(&dev_priv->dpio_lock);
6134
6135 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6136 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6137 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6138 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6139 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6140
Ville Syrjäläf6466282013-10-14 14:50:31 +03006141 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006142
Ville Syrjäläf6466282013-10-14 14:50:31 +03006143 /* clock.dot is the fast clock */
6144 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006145}
6146
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006147static void i9xx_get_plane_config(struct intel_crtc *crtc,
6148 struct intel_plane_config *plane_config)
6149{
6150 struct drm_device *dev = crtc->base.dev;
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152 u32 val, base, offset;
6153 int pipe = crtc->pipe, plane = crtc->plane;
6154 int fourcc, pixel_format;
6155 int aligned_height;
6156
Dave Airlie66e514c2014-04-03 07:51:54 +10006157 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6158 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006159 DRM_DEBUG_KMS("failed to alloc fb\n");
6160 return;
6161 }
6162
6163 val = I915_READ(DSPCNTR(plane));
6164
6165 if (INTEL_INFO(dev)->gen >= 4)
6166 if (val & DISPPLANE_TILED)
6167 plane_config->tiled = true;
6168
6169 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6170 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006171 crtc->base.primary->fb->pixel_format = fourcc;
6172 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006173 drm_format_plane_cpp(fourcc, 0) * 8;
6174
6175 if (INTEL_INFO(dev)->gen >= 4) {
6176 if (plane_config->tiled)
6177 offset = I915_READ(DSPTILEOFF(plane));
6178 else
6179 offset = I915_READ(DSPLINOFF(plane));
6180 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6181 } else {
6182 base = I915_READ(DSPADDR(plane));
6183 }
6184 plane_config->base = base;
6185
6186 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006187 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6188 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006189
6190 val = I915_READ(DSPSTRIDE(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006191 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006192
Dave Airlie66e514c2014-04-03 07:51:54 +10006193 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006194 plane_config->tiled);
6195
Fabian Frederick1267a262014-07-01 20:39:41 +02006196 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6197 aligned_height);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006198
6199 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006200 pipe, plane, crtc->base.primary->fb->width,
6201 crtc->base.primary->fb->height,
6202 crtc->base.primary->fb->bits_per_pixel, base,
6203 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006204 plane_config->size);
6205
6206}
6207
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006208static void chv_crtc_clock_get(struct intel_crtc *crtc,
6209 struct intel_crtc_config *pipe_config)
6210{
6211 struct drm_device *dev = crtc->base.dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 int pipe = pipe_config->cpu_transcoder;
6214 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6215 intel_clock_t clock;
6216 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6217 int refclk = 100000;
6218
6219 mutex_lock(&dev_priv->dpio_lock);
6220 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6221 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6222 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6223 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6224 mutex_unlock(&dev_priv->dpio_lock);
6225
6226 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6227 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6228 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6229 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6230 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6231
6232 chv_clock(refclk, &clock);
6233
6234 /* clock.dot is the fast clock */
6235 pipe_config->port_clock = clock.dot / 5;
6236}
6237
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006238static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6239 struct intel_crtc_config *pipe_config)
6240{
6241 struct drm_device *dev = crtc->base.dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 uint32_t tmp;
6244
Imre Deakb5482bd2014-03-05 16:20:55 +02006245 if (!intel_display_power_enabled(dev_priv,
6246 POWER_DOMAIN_PIPE(crtc->pipe)))
6247 return false;
6248
Daniel Vettere143a212013-07-04 12:01:15 +02006249 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006250 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006251
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006252 tmp = I915_READ(PIPECONF(crtc->pipe));
6253 if (!(tmp & PIPECONF_ENABLE))
6254 return false;
6255
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006256 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6257 switch (tmp & PIPECONF_BPC_MASK) {
6258 case PIPECONF_6BPC:
6259 pipe_config->pipe_bpp = 18;
6260 break;
6261 case PIPECONF_8BPC:
6262 pipe_config->pipe_bpp = 24;
6263 break;
6264 case PIPECONF_10BPC:
6265 pipe_config->pipe_bpp = 30;
6266 break;
6267 default:
6268 break;
6269 }
6270 }
6271
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006272 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6273 pipe_config->limited_color_range = true;
6274
Ville Syrjälä282740f2013-09-04 18:30:03 +03006275 if (INTEL_INFO(dev)->gen < 4)
6276 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6277
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006278 intel_get_pipe_timings(crtc, pipe_config);
6279
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006280 i9xx_get_pfit_config(crtc, pipe_config);
6281
Daniel Vetter6c49f242013-06-06 12:45:25 +02006282 if (INTEL_INFO(dev)->gen >= 4) {
6283 tmp = I915_READ(DPLL_MD(crtc->pipe));
6284 pipe_config->pixel_multiplier =
6285 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6286 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006287 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006288 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6289 tmp = I915_READ(DPLL(crtc->pipe));
6290 pipe_config->pixel_multiplier =
6291 ((tmp & SDVO_MULTIPLIER_MASK)
6292 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6293 } else {
6294 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6295 * port and will be fixed up in the encoder->get_config
6296 * function. */
6297 pipe_config->pixel_multiplier = 1;
6298 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006299 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6300 if (!IS_VALLEYVIEW(dev)) {
6301 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6302 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006303 } else {
6304 /* Mask out read-only status bits. */
6305 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6306 DPLL_PORTC_READY_MASK |
6307 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006308 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006309
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006310 if (IS_CHERRYVIEW(dev))
6311 chv_crtc_clock_get(crtc, pipe_config);
6312 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006313 vlv_crtc_clock_get(crtc, pipe_config);
6314 else
6315 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006316
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006317 return true;
6318}
6319
Paulo Zanonidde86e22012-12-01 12:04:25 -02006320static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006321{
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6323 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006324 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006325 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006326 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006327 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006328 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006329 bool has_ck505 = false;
6330 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006331
6332 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07006333 list_for_each_entry(encoder, &mode_config->encoder_list,
6334 base.head) {
6335 switch (encoder->type) {
6336 case INTEL_OUTPUT_LVDS:
6337 has_panel = true;
6338 has_lvds = true;
6339 break;
6340 case INTEL_OUTPUT_EDP:
6341 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006342 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006343 has_cpu_edp = true;
6344 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006345 }
6346 }
6347
Keith Packard99eb6a02011-09-26 14:29:12 -07006348 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006349 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006350 can_ssc = has_ck505;
6351 } else {
6352 has_ck505 = false;
6353 can_ssc = true;
6354 }
6355
Imre Deak2de69052013-05-08 13:14:04 +03006356 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6357 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006358
6359 /* Ironlake: try to setup display ref clock before DPLL
6360 * enabling. This is only under driver's control after
6361 * PCH B stepping, previous chipset stepping should be
6362 * ignoring this setting.
6363 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006364 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006365
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006366 /* As we must carefully and slowly disable/enable each source in turn,
6367 * compute the final state we want first and check if we need to
6368 * make any changes at all.
6369 */
6370 final = val;
6371 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006372 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006373 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006374 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006375 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6376
6377 final &= ~DREF_SSC_SOURCE_MASK;
6378 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6379 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006380
Keith Packard199e5d72011-09-22 12:01:57 -07006381 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006382 final |= DREF_SSC_SOURCE_ENABLE;
6383
6384 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6385 final |= DREF_SSC1_ENABLE;
6386
6387 if (has_cpu_edp) {
6388 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6389 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6390 else
6391 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6392 } else
6393 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6394 } else {
6395 final |= DREF_SSC_SOURCE_DISABLE;
6396 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6397 }
6398
6399 if (final == val)
6400 return;
6401
6402 /* Always enable nonspread source */
6403 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6404
6405 if (has_ck505)
6406 val |= DREF_NONSPREAD_CK505_ENABLE;
6407 else
6408 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6409
6410 if (has_panel) {
6411 val &= ~DREF_SSC_SOURCE_MASK;
6412 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006413
Keith Packard199e5d72011-09-22 12:01:57 -07006414 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006415 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006416 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006417 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006418 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006419 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006420
6421 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006422 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006423 POSTING_READ(PCH_DREF_CONTROL);
6424 udelay(200);
6425
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006426 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006427
6428 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006429 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006430 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006431 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006432 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006433 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006434 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006435 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006436 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006437
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006438 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006439 POSTING_READ(PCH_DREF_CONTROL);
6440 udelay(200);
6441 } else {
6442 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6443
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006444 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006445
6446 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006447 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006448
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006449 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006450 POSTING_READ(PCH_DREF_CONTROL);
6451 udelay(200);
6452
6453 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006454 val &= ~DREF_SSC_SOURCE_MASK;
6455 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006456
6457 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006458 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006459
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006460 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006461 POSTING_READ(PCH_DREF_CONTROL);
6462 udelay(200);
6463 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006464
6465 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006466}
6467
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006468static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006469{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006470 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006471
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006472 tmp = I915_READ(SOUTH_CHICKEN2);
6473 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6474 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006475
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006476 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6477 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6478 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006479
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006480 tmp = I915_READ(SOUTH_CHICKEN2);
6481 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6482 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006483
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006484 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6485 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6486 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006487}
6488
6489/* WaMPhyProgramming:hsw */
6490static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6491{
6492 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006493
6494 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6495 tmp &= ~(0xFF << 24);
6496 tmp |= (0x12 << 24);
6497 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6498
Paulo Zanonidde86e22012-12-01 12:04:25 -02006499 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6500 tmp |= (1 << 11);
6501 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6502
6503 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6504 tmp |= (1 << 11);
6505 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6506
Paulo Zanonidde86e22012-12-01 12:04:25 -02006507 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6508 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6509 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6510
6511 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6512 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6513 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6514
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006515 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6516 tmp &= ~(7 << 13);
6517 tmp |= (5 << 13);
6518 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006519
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006520 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6521 tmp &= ~(7 << 13);
6522 tmp |= (5 << 13);
6523 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006524
6525 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6526 tmp &= ~0xFF;
6527 tmp |= 0x1C;
6528 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6529
6530 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6531 tmp &= ~0xFF;
6532 tmp |= 0x1C;
6533 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6534
6535 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6536 tmp &= ~(0xFF << 16);
6537 tmp |= (0x1C << 16);
6538 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6539
6540 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6541 tmp &= ~(0xFF << 16);
6542 tmp |= (0x1C << 16);
6543 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6544
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006545 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6546 tmp |= (1 << 27);
6547 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006548
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006549 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6550 tmp |= (1 << 27);
6551 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006552
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006553 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6554 tmp &= ~(0xF << 28);
6555 tmp |= (4 << 28);
6556 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006557
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006558 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6559 tmp &= ~(0xF << 28);
6560 tmp |= (4 << 28);
6561 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006562}
6563
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006564/* Implements 3 different sequences from BSpec chapter "Display iCLK
6565 * Programming" based on the parameters passed:
6566 * - Sequence to enable CLKOUT_DP
6567 * - Sequence to enable CLKOUT_DP without spread
6568 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6569 */
6570static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6571 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006572{
6573 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006574 uint32_t reg, tmp;
6575
6576 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6577 with_spread = true;
6578 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6579 with_fdi, "LP PCH doesn't have FDI\n"))
6580 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006581
6582 mutex_lock(&dev_priv->dpio_lock);
6583
6584 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6585 tmp &= ~SBI_SSCCTL_DISABLE;
6586 tmp |= SBI_SSCCTL_PATHALT;
6587 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6588
6589 udelay(24);
6590
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006591 if (with_spread) {
6592 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6593 tmp &= ~SBI_SSCCTL_PATHALT;
6594 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006595
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006596 if (with_fdi) {
6597 lpt_reset_fdi_mphy(dev_priv);
6598 lpt_program_fdi_mphy(dev_priv);
6599 }
6600 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02006601
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006602 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6603 SBI_GEN0 : SBI_DBUFF0;
6604 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6605 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6606 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01006607
6608 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006609}
6610
Paulo Zanoni47701c32013-07-23 11:19:25 -03006611/* Sequence to disable CLKOUT_DP */
6612static void lpt_disable_clkout_dp(struct drm_device *dev)
6613{
6614 struct drm_i915_private *dev_priv = dev->dev_private;
6615 uint32_t reg, tmp;
6616
6617 mutex_lock(&dev_priv->dpio_lock);
6618
6619 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6620 SBI_GEN0 : SBI_DBUFF0;
6621 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6622 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6623 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6624
6625 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6626 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6627 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6628 tmp |= SBI_SSCCTL_PATHALT;
6629 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6630 udelay(32);
6631 }
6632 tmp |= SBI_SSCCTL_DISABLE;
6633 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6634 }
6635
6636 mutex_unlock(&dev_priv->dpio_lock);
6637}
6638
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006639static void lpt_init_pch_refclk(struct drm_device *dev)
6640{
6641 struct drm_mode_config *mode_config = &dev->mode_config;
6642 struct intel_encoder *encoder;
6643 bool has_vga = false;
6644
6645 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6646 switch (encoder->type) {
6647 case INTEL_OUTPUT_ANALOG:
6648 has_vga = true;
6649 break;
6650 }
6651 }
6652
Paulo Zanoni47701c32013-07-23 11:19:25 -03006653 if (has_vga)
6654 lpt_enable_clkout_dp(dev, true, true);
6655 else
6656 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006657}
6658
Paulo Zanonidde86e22012-12-01 12:04:25 -02006659/*
6660 * Initialize reference clocks when the driver loads
6661 */
6662void intel_init_pch_refclk(struct drm_device *dev)
6663{
6664 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6665 ironlake_init_pch_refclk(dev);
6666 else if (HAS_PCH_LPT(dev))
6667 lpt_init_pch_refclk(dev);
6668}
6669
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006670static int ironlake_get_refclk(struct drm_crtc *crtc)
6671{
6672 struct drm_device *dev = crtc->dev;
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006675 int num_connectors = 0;
6676 bool is_lvds = false;
6677
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02006678 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006679 switch (encoder->type) {
6680 case INTEL_OUTPUT_LVDS:
6681 is_lvds = true;
6682 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006683 }
6684 num_connectors++;
6685 }
6686
6687 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006688 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006689 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006690 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006691 }
6692
6693 return 120000;
6694}
6695
Daniel Vetter6ff93602013-04-19 11:24:36 +02006696static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03006697{
6698 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6700 int pipe = intel_crtc->pipe;
6701 uint32_t val;
6702
Daniel Vetter78114072013-06-13 00:54:57 +02006703 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03006704
Daniel Vetter965e0c42013-03-27 00:44:57 +01006705 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03006706 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006707 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006708 break;
6709 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006710 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006711 break;
6712 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006713 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006714 break;
6715 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006716 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006717 break;
6718 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03006719 /* Case prevented by intel_choose_pipe_bpp_dither. */
6720 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03006721 }
6722
Daniel Vetterd8b32242013-04-25 17:54:44 +02006723 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03006724 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6725
Daniel Vetter6ff93602013-04-19 11:24:36 +02006726 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03006727 val |= PIPECONF_INTERLACED_ILK;
6728 else
6729 val |= PIPECONF_PROGRESSIVE;
6730
Daniel Vetter50f3b012013-03-27 00:44:56 +01006731 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006732 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006733
Paulo Zanonic8203562012-09-12 10:06:29 -03006734 I915_WRITE(PIPECONF(pipe), val);
6735 POSTING_READ(PIPECONF(pipe));
6736}
6737
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006738/*
6739 * Set up the pipe CSC unit.
6740 *
6741 * Currently only full range RGB to limited range RGB conversion
6742 * is supported, but eventually this should handle various
6743 * RGB<->YCbCr scenarios as well.
6744 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01006745static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006746{
6747 struct drm_device *dev = crtc->dev;
6748 struct drm_i915_private *dev_priv = dev->dev_private;
6749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6750 int pipe = intel_crtc->pipe;
6751 uint16_t coeff = 0x7800; /* 1.0 */
6752
6753 /*
6754 * TODO: Check what kind of values actually come out of the pipe
6755 * with these coeff/postoff values and adjust to get the best
6756 * accuracy. Perhaps we even need to take the bpc value into
6757 * consideration.
6758 */
6759
Daniel Vetter50f3b012013-03-27 00:44:56 +01006760 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006761 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6762
6763 /*
6764 * GY/GU and RY/RU should be the other way around according
6765 * to BSpec, but reality doesn't agree. Just set them up in
6766 * a way that results in the correct picture.
6767 */
6768 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6769 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6770
6771 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6772 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6773
6774 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6775 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6776
6777 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6778 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6779 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6780
6781 if (INTEL_INFO(dev)->gen > 6) {
6782 uint16_t postoff = 0;
6783
Daniel Vetter50f3b012013-03-27 00:44:56 +01006784 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02006785 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006786
6787 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6788 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6789 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6790
6791 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6792 } else {
6793 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6794
Daniel Vetter50f3b012013-03-27 00:44:56 +01006795 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006796 mode |= CSC_BLACK_SCREEN_OFFSET;
6797
6798 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6799 }
6800}
6801
Daniel Vetter6ff93602013-04-19 11:24:36 +02006802static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006803{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006804 struct drm_device *dev = crtc->dev;
6805 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006807 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006808 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006809 uint32_t val;
6810
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006811 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006812
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006813 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006814 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6815
Daniel Vetter6ff93602013-04-19 11:24:36 +02006816 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006817 val |= PIPECONF_INTERLACED_ILK;
6818 else
6819 val |= PIPECONF_PROGRESSIVE;
6820
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006821 I915_WRITE(PIPECONF(cpu_transcoder), val);
6822 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006823
6824 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6825 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006826
6827 if (IS_BROADWELL(dev)) {
6828 val = 0;
6829
6830 switch (intel_crtc->config.pipe_bpp) {
6831 case 18:
6832 val |= PIPEMISC_DITHER_6_BPC;
6833 break;
6834 case 24:
6835 val |= PIPEMISC_DITHER_8_BPC;
6836 break;
6837 case 30:
6838 val |= PIPEMISC_DITHER_10_BPC;
6839 break;
6840 case 36:
6841 val |= PIPEMISC_DITHER_12_BPC;
6842 break;
6843 default:
6844 /* Case prevented by pipe_config_set_bpp. */
6845 BUG();
6846 }
6847
6848 if (intel_crtc->config.dither)
6849 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6850
6851 I915_WRITE(PIPEMISC(pipe), val);
6852 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006853}
6854
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006855static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006856 intel_clock_t *clock,
6857 bool *has_reduced_clock,
6858 intel_clock_t *reduced_clock)
6859{
6860 struct drm_device *dev = crtc->dev;
6861 struct drm_i915_private *dev_priv = dev->dev_private;
6862 struct intel_encoder *intel_encoder;
6863 int refclk;
6864 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02006865 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006866
6867 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6868 switch (intel_encoder->type) {
6869 case INTEL_OUTPUT_LVDS:
6870 is_lvds = true;
6871 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006872 }
6873 }
6874
6875 refclk = ironlake_get_refclk(crtc);
6876
6877 /*
6878 * Returns a set of divisors for the desired target clock with the given
6879 * refclk, or FALSE. The returned values represent the clock equation:
6880 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6881 */
6882 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006883 ret = dev_priv->display.find_dpll(limit, crtc,
6884 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006885 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006886 if (!ret)
6887 return false;
6888
6889 if (is_lvds && dev_priv->lvds_downclock_avail) {
6890 /*
6891 * Ensure we match the reduced clock's P to the target clock.
6892 * If the clocks don't match, we can't switch the display clock
6893 * by using the FP0/FP1. In such case we will disable the LVDS
6894 * downclock feature.
6895 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006896 *has_reduced_clock =
6897 dev_priv->display.find_dpll(limit, crtc,
6898 dev_priv->lvds_downclock,
6899 refclk, clock,
6900 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006901 }
6902
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006903 return true;
6904}
6905
Paulo Zanonid4b19312012-11-29 11:29:32 -02006906int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6907{
6908 /*
6909 * Account for spread spectrum to avoid
6910 * oversubscribing the link. Max center spread
6911 * is 2.5%; use 5% for safety's sake.
6912 */
6913 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02006914 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02006915}
6916
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006917static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02006918{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006919 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006920}
6921
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006922static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006923 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006924 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006925{
6926 struct drm_crtc *crtc = &intel_crtc->base;
6927 struct drm_device *dev = crtc->dev;
6928 struct drm_i915_private *dev_priv = dev->dev_private;
6929 struct intel_encoder *intel_encoder;
6930 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006931 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02006932 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006933
6934 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6935 switch (intel_encoder->type) {
6936 case INTEL_OUTPUT_LVDS:
6937 is_lvds = true;
6938 break;
6939 case INTEL_OUTPUT_SDVO:
6940 case INTEL_OUTPUT_HDMI:
6941 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006942 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006943 }
6944
6945 num_connectors++;
6946 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006947
Chris Wilsonc1858122010-12-03 21:35:48 +00006948 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07006949 factor = 21;
6950 if (is_lvds) {
6951 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006952 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02006953 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07006954 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02006955 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07006956 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00006957
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006958 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02006959 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00006960
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006961 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6962 *fp2 |= FP_CB_TUNE;
6963
Chris Wilson5eddb702010-09-11 13:48:45 +01006964 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08006965
Eric Anholta07d6782011-03-30 13:01:08 -07006966 if (is_lvds)
6967 dpll |= DPLLB_MODE_LVDS;
6968 else
6969 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006970
Daniel Vetteref1b4602013-06-01 17:17:04 +02006971 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6972 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006973
6974 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006975 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02006976 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006977 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08006978
Eric Anholta07d6782011-03-30 13:01:08 -07006979 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006980 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006981 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006982 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006983
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006984 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07006985 case 5:
6986 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6987 break;
6988 case 7:
6989 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6990 break;
6991 case 10:
6992 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6993 break;
6994 case 14:
6995 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6996 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006997 }
6998
Daniel Vetterb4c09f32013-04-30 14:01:42 +02006999 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05007000 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08007001 else
7002 dpll |= PLL_REF_INPUT_DREFCLK;
7003
Daniel Vetter959e16d2013-06-05 13:34:21 +02007004 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007005}
7006
Jesse Barnes79e53942008-11-07 14:24:08 -08007007static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08007008 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02007009 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08007010{
7011 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007013 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007014 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007015 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03007016 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01007017 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007018 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02007019 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007020
7021 for_each_encoder_on_crtc(dev, crtc, encoder) {
7022 switch (encoder->type) {
7023 case INTEL_OUTPUT_LVDS:
7024 is_lvds = true;
7025 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007026 }
7027
7028 num_connectors++;
7029 }
7030
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007031 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7032 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7033
Daniel Vetterff9a6752013-06-01 17:16:21 +02007034 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007035 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02007036 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007037 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7038 return -EINVAL;
7039 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01007040 /* Compat-code for transition, will disappear. */
7041 if (!intel_crtc->config.clock_set) {
7042 intel_crtc->config.dpll.n = clock.n;
7043 intel_crtc->config.dpll.m1 = clock.m1;
7044 intel_crtc->config.dpll.m2 = clock.m2;
7045 intel_crtc->config.dpll.p1 = clock.p1;
7046 intel_crtc->config.dpll.p2 = clock.p2;
7047 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007048
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007049 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01007050 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007051 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007052 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007053 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007054
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007055 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007056 &fp, &reduced_clock,
7057 has_reduced_clock ? &fp2 : NULL);
7058
Daniel Vetter959e16d2013-06-05 13:34:21 +02007059 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007060 intel_crtc->config.dpll_hw_state.fp0 = fp;
7061 if (has_reduced_clock)
7062 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7063 else
7064 intel_crtc->config.dpll_hw_state.fp1 = fp;
7065
Daniel Vetterb89a1d32013-06-05 13:34:24 +02007066 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007067 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03007068 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Daniel Vetter29407aa2014-04-24 23:55:08 +02007069 pipe_name(intel_crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07007070 return -EINVAL;
7071 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007072 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02007073 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007074
Jani Nikulad330a952014-01-21 11:24:25 +02007075 if (is_lvds && has_reduced_clock && i915.powersave)
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007076 intel_crtc->lowfreq_avail = true;
7077 else
7078 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007079
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007080 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007081}
7082
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007083static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7084 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007085{
7086 struct drm_device *dev = crtc->base.dev;
7087 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007088 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007089
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007090 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7091 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7092 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7093 & ~TU_SIZE_MASK;
7094 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7095 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7096 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7097}
7098
7099static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7100 enum transcoder transcoder,
7101 struct intel_link_m_n *m_n)
7102{
7103 struct drm_device *dev = crtc->base.dev;
7104 struct drm_i915_private *dev_priv = dev->dev_private;
7105 enum pipe pipe = crtc->pipe;
7106
7107 if (INTEL_INFO(dev)->gen >= 5) {
7108 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7109 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7110 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7111 & ~TU_SIZE_MASK;
7112 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7113 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7114 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7115 } else {
7116 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7117 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7118 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7119 & ~TU_SIZE_MASK;
7120 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7121 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7122 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7123 }
7124}
7125
7126void intel_dp_get_m_n(struct intel_crtc *crtc,
7127 struct intel_crtc_config *pipe_config)
7128{
7129 if (crtc->config.has_pch_encoder)
7130 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7131 else
7132 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7133 &pipe_config->dp_m_n);
7134}
7135
Daniel Vetter72419202013-04-04 13:28:53 +02007136static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7137 struct intel_crtc_config *pipe_config)
7138{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007139 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7140 &pipe_config->fdi_m_n);
Daniel Vetter72419202013-04-04 13:28:53 +02007141}
7142
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007143static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7144 struct intel_crtc_config *pipe_config)
7145{
7146 struct drm_device *dev = crtc->base.dev;
7147 struct drm_i915_private *dev_priv = dev->dev_private;
7148 uint32_t tmp;
7149
7150 tmp = I915_READ(PF_CTL(crtc->pipe));
7151
7152 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007153 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007154 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7155 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007156
7157 /* We currently do not free assignements of panel fitters on
7158 * ivb/hsw (since we don't use the higher upscaling modes which
7159 * differentiates them) so just WARN about this case for now. */
7160 if (IS_GEN7(dev)) {
7161 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7162 PF_PIPE_SEL_IVB(crtc->pipe));
7163 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007164 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007165}
7166
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007167static void ironlake_get_plane_config(struct intel_crtc *crtc,
7168 struct intel_plane_config *plane_config)
7169{
7170 struct drm_device *dev = crtc->base.dev;
7171 struct drm_i915_private *dev_priv = dev->dev_private;
7172 u32 val, base, offset;
7173 int pipe = crtc->pipe, plane = crtc->plane;
7174 int fourcc, pixel_format;
7175 int aligned_height;
7176
Dave Airlie66e514c2014-04-03 07:51:54 +10007177 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7178 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007179 DRM_DEBUG_KMS("failed to alloc fb\n");
7180 return;
7181 }
7182
7183 val = I915_READ(DSPCNTR(plane));
7184
7185 if (INTEL_INFO(dev)->gen >= 4)
7186 if (val & DISPPLANE_TILED)
7187 plane_config->tiled = true;
7188
7189 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7190 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007191 crtc->base.primary->fb->pixel_format = fourcc;
7192 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007193 drm_format_plane_cpp(fourcc, 0) * 8;
7194
7195 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7196 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7197 offset = I915_READ(DSPOFFSET(plane));
7198 } else {
7199 if (plane_config->tiled)
7200 offset = I915_READ(DSPTILEOFF(plane));
7201 else
7202 offset = I915_READ(DSPLINOFF(plane));
7203 }
7204 plane_config->base = base;
7205
7206 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007207 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7208 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007209
7210 val = I915_READ(DSPSTRIDE(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007211 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007212
Dave Airlie66e514c2014-04-03 07:51:54 +10007213 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007214 plane_config->tiled);
7215
Fabian Frederick1267a262014-07-01 20:39:41 +02007216 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7217 aligned_height);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007218
7219 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007220 pipe, plane, crtc->base.primary->fb->width,
7221 crtc->base.primary->fb->height,
7222 crtc->base.primary->fb->bits_per_pixel, base,
7223 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007224 plane_config->size);
7225}
7226
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007227static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7228 struct intel_crtc_config *pipe_config)
7229{
7230 struct drm_device *dev = crtc->base.dev;
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232 uint32_t tmp;
7233
Paulo Zanoni930e8c92014-07-04 13:38:34 -03007234 if (!intel_display_power_enabled(dev_priv,
7235 POWER_DOMAIN_PIPE(crtc->pipe)))
7236 return false;
7237
Daniel Vettere143a212013-07-04 12:01:15 +02007238 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007239 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007240
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007241 tmp = I915_READ(PIPECONF(crtc->pipe));
7242 if (!(tmp & PIPECONF_ENABLE))
7243 return false;
7244
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007245 switch (tmp & PIPECONF_BPC_MASK) {
7246 case PIPECONF_6BPC:
7247 pipe_config->pipe_bpp = 18;
7248 break;
7249 case PIPECONF_8BPC:
7250 pipe_config->pipe_bpp = 24;
7251 break;
7252 case PIPECONF_10BPC:
7253 pipe_config->pipe_bpp = 30;
7254 break;
7255 case PIPECONF_12BPC:
7256 pipe_config->pipe_bpp = 36;
7257 break;
7258 default:
7259 break;
7260 }
7261
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007262 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7263 pipe_config->limited_color_range = true;
7264
Daniel Vetterab9412b2013-05-03 11:49:46 +02007265 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007266 struct intel_shared_dpll *pll;
7267
Daniel Vetter88adfff2013-03-28 10:42:01 +01007268 pipe_config->has_pch_encoder = true;
7269
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007270 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7271 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7272 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007273
7274 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007275
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007276 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007277 pipe_config->shared_dpll =
7278 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007279 } else {
7280 tmp = I915_READ(PCH_DPLL_SEL);
7281 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7282 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7283 else
7284 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7285 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007286
7287 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7288
7289 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7290 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007291
7292 tmp = pipe_config->dpll_hw_state.dpll;
7293 pipe_config->pixel_multiplier =
7294 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7295 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007296
7297 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007298 } else {
7299 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007300 }
7301
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007302 intel_get_pipe_timings(crtc, pipe_config);
7303
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007304 ironlake_get_pfit_config(crtc, pipe_config);
7305
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007306 return true;
7307}
7308
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007309static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7310{
7311 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007312 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007313
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007314 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007315 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007316 pipe_name(crtc->pipe));
7317
7318 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
Daniel Vetter8cc3e162014-06-25 22:01:46 +03007319 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7320 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7321 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007322 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7323 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7324 "CPU PWM1 enabled\n");
7325 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7326 "CPU PWM2 enabled\n");
7327 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7328 "PCH PWM1 enabled\n");
7329 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7330 "Utility pin enabled\n");
7331 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7332
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007333 /*
7334 * In theory we can still leave IRQs enabled, as long as only the HPD
7335 * interrupts remain enabled. We used to check for that, but since it's
7336 * gen-specific and since we only disable LCPLL after we fully disable
7337 * the interrupts, the check below should be enough.
7338 */
7339 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007340}
7341
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007342static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7343{
7344 struct drm_device *dev = dev_priv->dev;
7345
7346 if (IS_HASWELL(dev))
7347 return I915_READ(D_COMP_HSW);
7348 else
7349 return I915_READ(D_COMP_BDW);
7350}
7351
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007352static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7353{
7354 struct drm_device *dev = dev_priv->dev;
7355
7356 if (IS_HASWELL(dev)) {
7357 mutex_lock(&dev_priv->rps.hw_lock);
7358 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7359 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03007360 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007361 mutex_unlock(&dev_priv->rps.hw_lock);
7362 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007363 I915_WRITE(D_COMP_BDW, val);
7364 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007365 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007366}
7367
7368/*
7369 * This function implements pieces of two sequences from BSpec:
7370 * - Sequence for display software to disable LCPLL
7371 * - Sequence for display software to allow package C8+
7372 * The steps implemented here are just the steps that actually touch the LCPLL
7373 * register. Callers should take care of disabling all the display engine
7374 * functions, doing the mode unset, fixing interrupts, etc.
7375 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007376static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7377 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007378{
7379 uint32_t val;
7380
7381 assert_can_disable_lcpll(dev_priv);
7382
7383 val = I915_READ(LCPLL_CTL);
7384
7385 if (switch_to_fclk) {
7386 val |= LCPLL_CD_SOURCE_FCLK;
7387 I915_WRITE(LCPLL_CTL, val);
7388
7389 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7390 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7391 DRM_ERROR("Switching to FCLK failed\n");
7392
7393 val = I915_READ(LCPLL_CTL);
7394 }
7395
7396 val |= LCPLL_PLL_DISABLE;
7397 I915_WRITE(LCPLL_CTL, val);
7398 POSTING_READ(LCPLL_CTL);
7399
7400 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7401 DRM_ERROR("LCPLL still locked\n");
7402
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007403 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007404 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007405 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007406 ndelay(100);
7407
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007408 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7409 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007410 DRM_ERROR("D_COMP RCOMP still in progress\n");
7411
7412 if (allow_power_down) {
7413 val = I915_READ(LCPLL_CTL);
7414 val |= LCPLL_POWER_DOWN_ALLOW;
7415 I915_WRITE(LCPLL_CTL, val);
7416 POSTING_READ(LCPLL_CTL);
7417 }
7418}
7419
7420/*
7421 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7422 * source.
7423 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007424static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007425{
7426 uint32_t val;
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007427 unsigned long irqflags;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007428
7429 val = I915_READ(LCPLL_CTL);
7430
7431 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7432 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7433 return;
7434
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007435 /*
7436 * Make sure we're not on PC8 state before disabling PC8, otherwise
7437 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7438 *
7439 * The other problem is that hsw_restore_lcpll() is called as part of
7440 * the runtime PM resume sequence, so we can't just call
7441 * gen6_gt_force_wake_get() because that function calls
7442 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7443 * while we are on the resume sequence. So to solve this problem we have
7444 * to call special forcewake code that doesn't touch runtime PM and
7445 * doesn't enable the forcewake delayed work.
7446 */
7447 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7448 if (dev_priv->uncore.forcewake_count++ == 0)
7449 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7450 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007451
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007452 if (val & LCPLL_POWER_DOWN_ALLOW) {
7453 val &= ~LCPLL_POWER_DOWN_ALLOW;
7454 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007455 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007456 }
7457
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007458 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007459 val |= D_COMP_COMP_FORCE;
7460 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007461 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007462
7463 val = I915_READ(LCPLL_CTL);
7464 val &= ~LCPLL_PLL_DISABLE;
7465 I915_WRITE(LCPLL_CTL, val);
7466
7467 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7468 DRM_ERROR("LCPLL not locked yet\n");
7469
7470 if (val & LCPLL_CD_SOURCE_FCLK) {
7471 val = I915_READ(LCPLL_CTL);
7472 val &= ~LCPLL_CD_SOURCE_FCLK;
7473 I915_WRITE(LCPLL_CTL, val);
7474
7475 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7476 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7477 DRM_ERROR("Switching back to LCPLL failed\n");
7478 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007479
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007480 /* See the big comment above. */
7481 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7482 if (--dev_priv->uncore.forcewake_count == 0)
7483 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7484 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007485}
7486
Paulo Zanoni765dab62014-03-07 20:08:18 -03007487/*
7488 * Package states C8 and deeper are really deep PC states that can only be
7489 * reached when all the devices on the system allow it, so even if the graphics
7490 * device allows PC8+, it doesn't mean the system will actually get to these
7491 * states. Our driver only allows PC8+ when going into runtime PM.
7492 *
7493 * The requirements for PC8+ are that all the outputs are disabled, the power
7494 * well is disabled and most interrupts are disabled, and these are also
7495 * requirements for runtime PM. When these conditions are met, we manually do
7496 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7497 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7498 * hang the machine.
7499 *
7500 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7501 * the state of some registers, so when we come back from PC8+ we need to
7502 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7503 * need to take care of the registers kept by RC6. Notice that this happens even
7504 * if we don't put the device in PCI D3 state (which is what currently happens
7505 * because of the runtime PM support).
7506 *
7507 * For more, read "Display Sequences for Package C8" on the hardware
7508 * documentation.
7509 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007510void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007511{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007512 struct drm_device *dev = dev_priv->dev;
7513 uint32_t val;
7514
Paulo Zanonic67a4702013-08-19 13:18:09 -03007515 DRM_DEBUG_KMS("Enabling package C8+\n");
7516
Paulo Zanonic67a4702013-08-19 13:18:09 -03007517 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7518 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7519 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7520 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7521 }
7522
7523 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007524 hsw_disable_lcpll(dev_priv, true, true);
7525}
7526
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007527void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007528{
7529 struct drm_device *dev = dev_priv->dev;
7530 uint32_t val;
7531
Paulo Zanonic67a4702013-08-19 13:18:09 -03007532 DRM_DEBUG_KMS("Disabling package C8+\n");
7533
7534 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007535 lpt_init_pch_refclk(dev);
7536
7537 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7538 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7539 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7540 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7541 }
7542
7543 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007544}
7545
Paulo Zanoni9a952a02014-03-07 20:12:34 -03007546static void snb_modeset_global_resources(struct drm_device *dev)
7547{
7548 modeset_update_crtc_power_domains(dev);
7549}
7550
Imre Deak4f074122013-10-16 17:25:51 +03007551static void haswell_modeset_global_resources(struct drm_device *dev)
7552{
Paulo Zanonida723562013-12-19 11:54:51 -02007553 modeset_update_crtc_power_domains(dev);
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02007554}
7555
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007556static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007557 int x, int y,
7558 struct drm_framebuffer *fb)
7559{
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007561
Paulo Zanoni566b7342013-11-25 15:27:08 -02007562 if (!intel_ddi_pll_select(intel_crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007563 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03007564
Daniel Vetter644cef32014-04-24 23:55:07 +02007565 intel_crtc->lowfreq_avail = false;
7566
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007567 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007568}
7569
Daniel Vetter26804af2014-06-25 22:01:55 +03007570static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7571 struct intel_crtc_config *pipe_config)
7572{
7573 struct drm_device *dev = crtc->base.dev;
7574 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007575 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03007576 enum port port;
7577 uint32_t tmp;
7578
7579 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7580
7581 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7582
7583 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
Daniel Vetter9cd86932014-06-25 22:01:57 +03007584
7585 switch (pipe_config->ddi_pll_sel) {
7586 case PORT_CLK_SEL_WRPLL1:
7587 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7588 break;
7589 case PORT_CLK_SEL_WRPLL2:
7590 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7591 break;
7592 }
7593
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007594 if (pipe_config->shared_dpll >= 0) {
7595 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7596
7597 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7598 &pipe_config->dpll_hw_state));
7599 }
7600
Daniel Vetter26804af2014-06-25 22:01:55 +03007601 /*
7602 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7603 * DDI E. So just check whether this pipe is wired to DDI E and whether
7604 * the PCH transcoder is on.
7605 */
7606 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7607 pipe_config->has_pch_encoder = true;
7608
7609 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7610 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7611 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7612
7613 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7614 }
7615}
7616
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007617static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7618 struct intel_crtc_config *pipe_config)
7619{
7620 struct drm_device *dev = crtc->base.dev;
7621 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007622 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007623 uint32_t tmp;
7624
Imre Deakb5482bd2014-03-05 16:20:55 +02007625 if (!intel_display_power_enabled(dev_priv,
7626 POWER_DOMAIN_PIPE(crtc->pipe)))
7627 return false;
7628
Daniel Vettere143a212013-07-04 12:01:15 +02007629 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007630 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7631
Daniel Vettereccb1402013-05-22 00:50:22 +02007632 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7633 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7634 enum pipe trans_edp_pipe;
7635 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7636 default:
7637 WARN(1, "unknown pipe linked to edp transcoder\n");
7638 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7639 case TRANS_DDI_EDP_INPUT_A_ON:
7640 trans_edp_pipe = PIPE_A;
7641 break;
7642 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7643 trans_edp_pipe = PIPE_B;
7644 break;
7645 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7646 trans_edp_pipe = PIPE_C;
7647 break;
7648 }
7649
7650 if (trans_edp_pipe == crtc->pipe)
7651 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7652 }
7653
Imre Deakda7e29b2014-02-18 00:02:02 +02007654 if (!intel_display_power_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02007655 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03007656 return false;
7657
Daniel Vettereccb1402013-05-22 00:50:22 +02007658 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007659 if (!(tmp & PIPECONF_ENABLE))
7660 return false;
7661
Daniel Vetter26804af2014-06-25 22:01:55 +03007662 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007663
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007664 intel_get_pipe_timings(crtc, pipe_config);
7665
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007666 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Imre Deakda7e29b2014-02-18 00:02:02 +02007667 if (intel_display_power_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007668 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01007669
Jesse Barnese59150d2014-01-07 13:30:45 -08007670 if (IS_HASWELL(dev))
7671 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7672 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007673
Daniel Vetter6c49f242013-06-06 12:45:25 +02007674 pipe_config->pixel_multiplier = 1;
7675
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007676 return true;
7677}
7678
Jani Nikula1a915102013-10-16 12:34:48 +03007679static struct {
7680 int clock;
7681 u32 config;
7682} hdmi_audio_clock[] = {
7683 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7684 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7685 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7686 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7687 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7688 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7689 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7690 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7691 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7692 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7693};
7694
7695/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7696static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7697{
7698 int i;
7699
7700 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7701 if (mode->clock == hdmi_audio_clock[i].clock)
7702 break;
7703 }
7704
7705 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7706 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7707 i = 1;
7708 }
7709
7710 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7711 hdmi_audio_clock[i].clock,
7712 hdmi_audio_clock[i].config);
7713
7714 return hdmi_audio_clock[i].config;
7715}
7716
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007717static bool intel_eld_uptodate(struct drm_connector *connector,
7718 int reg_eldv, uint32_t bits_eldv,
7719 int reg_elda, uint32_t bits_elda,
7720 int reg_edid)
7721{
7722 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7723 uint8_t *eld = connector->eld;
7724 uint32_t i;
7725
7726 i = I915_READ(reg_eldv);
7727 i &= bits_eldv;
7728
7729 if (!eld[0])
7730 return !i;
7731
7732 if (!i)
7733 return false;
7734
7735 i = I915_READ(reg_elda);
7736 i &= ~bits_elda;
7737 I915_WRITE(reg_elda, i);
7738
7739 for (i = 0; i < eld[2]; i++)
7740 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7741 return false;
7742
7743 return true;
7744}
7745
Wu Fengguange0dac652011-09-05 14:25:34 +08007746static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007747 struct drm_crtc *crtc,
7748 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007749{
7750 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7751 uint8_t *eld = connector->eld;
7752 uint32_t eldv;
7753 uint32_t len;
7754 uint32_t i;
7755
7756 i = I915_READ(G4X_AUD_VID_DID);
7757
7758 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7759 eldv = G4X_ELDV_DEVCL_DEVBLC;
7760 else
7761 eldv = G4X_ELDV_DEVCTG;
7762
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007763 if (intel_eld_uptodate(connector,
7764 G4X_AUD_CNTL_ST, eldv,
7765 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7766 G4X_HDMIW_HDMIEDID))
7767 return;
7768
Wu Fengguange0dac652011-09-05 14:25:34 +08007769 i = I915_READ(G4X_AUD_CNTL_ST);
7770 i &= ~(eldv | G4X_ELD_ADDR);
7771 len = (i >> 9) & 0x1f; /* ELD buffer size */
7772 I915_WRITE(G4X_AUD_CNTL_ST, i);
7773
7774 if (!eld[0])
7775 return;
7776
7777 len = min_t(uint8_t, eld[2], len);
7778 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7779 for (i = 0; i < len; i++)
7780 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7781
7782 i = I915_READ(G4X_AUD_CNTL_ST);
7783 i |= eldv;
7784 I915_WRITE(G4X_AUD_CNTL_ST, i);
7785}
7786
Wang Xingchao83358c852012-08-16 22:43:37 +08007787static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007788 struct drm_crtc *crtc,
7789 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007790{
7791 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7792 uint8_t *eld = connector->eld;
Wang Xingchao83358c852012-08-16 22:43:37 +08007793 uint32_t eldv;
7794 uint32_t i;
7795 int len;
7796 int pipe = to_intel_crtc(crtc)->pipe;
7797 int tmp;
7798
7799 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7800 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7801 int aud_config = HSW_AUD_CFG(pipe);
7802 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7803
Wang Xingchao83358c852012-08-16 22:43:37 +08007804 /* Audio output enable */
7805 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7806 tmp = I915_READ(aud_cntrl_st2);
7807 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7808 I915_WRITE(aud_cntrl_st2, tmp);
Daniel Vetterc7905792014-04-16 16:56:09 +02007809 POSTING_READ(aud_cntrl_st2);
Wang Xingchao83358c852012-08-16 22:43:37 +08007810
Daniel Vetterc7905792014-04-16 16:56:09 +02007811 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Wang Xingchao83358c852012-08-16 22:43:37 +08007812
7813 /* Set ELD valid state */
7814 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007815 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007816 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7817 I915_WRITE(aud_cntrl_st2, tmp);
7818 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007819 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007820
7821 /* Enable HDMI mode */
7822 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007823 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007824 /* clear N_programing_enable and N_value_index */
7825 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7826 I915_WRITE(aud_config, tmp);
7827
7828 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7829
7830 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7831
7832 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7833 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7834 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7835 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007836 } else {
7837 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7838 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007839
7840 if (intel_eld_uptodate(connector,
7841 aud_cntrl_st2, eldv,
7842 aud_cntl_st, IBX_ELD_ADDRESS,
7843 hdmiw_hdmiedid))
7844 return;
7845
7846 i = I915_READ(aud_cntrl_st2);
7847 i &= ~eldv;
7848 I915_WRITE(aud_cntrl_st2, i);
7849
7850 if (!eld[0])
7851 return;
7852
7853 i = I915_READ(aud_cntl_st);
7854 i &= ~IBX_ELD_ADDRESS;
7855 I915_WRITE(aud_cntl_st, i);
7856 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7857 DRM_DEBUG_DRIVER("port num:%d\n", i);
7858
7859 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7860 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7861 for (i = 0; i < len; i++)
7862 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7863
7864 i = I915_READ(aud_cntrl_st2);
7865 i |= eldv;
7866 I915_WRITE(aud_cntrl_st2, i);
7867
7868}
7869
Wu Fengguange0dac652011-09-05 14:25:34 +08007870static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007871 struct drm_crtc *crtc,
7872 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007873{
7874 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7875 uint8_t *eld = connector->eld;
7876 uint32_t eldv;
7877 uint32_t i;
7878 int len;
7879 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007880 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007881 int aud_cntl_st;
7882 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007883 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007884
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007885 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007886 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7887 aud_config = IBX_AUD_CFG(pipe);
7888 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007889 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007890 } else if (IS_VALLEYVIEW(connector->dev)) {
7891 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7892 aud_config = VLV_AUD_CFG(pipe);
7893 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7894 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007895 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007896 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7897 aud_config = CPT_AUD_CFG(pipe);
7898 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007899 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007900 }
7901
Wang Xingchao9b138a82012-08-09 16:52:18 +08007902 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08007903
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007904 if (IS_VALLEYVIEW(connector->dev)) {
7905 struct intel_encoder *intel_encoder;
7906 struct intel_digital_port *intel_dig_port;
7907
7908 intel_encoder = intel_attached_encoder(connector);
7909 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7910 i = intel_dig_port->port;
7911 } else {
7912 i = I915_READ(aud_cntl_st);
7913 i = (i >> 29) & DIP_PORT_SEL_MASK;
7914 /* DIP_Port_Select, 0x1 = PortB */
7915 }
7916
Wu Fengguange0dac652011-09-05 14:25:34 +08007917 if (!i) {
7918 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7919 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007920 eldv = IBX_ELD_VALIDB;
7921 eldv |= IBX_ELD_VALIDB << 4;
7922 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08007923 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03007924 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007925 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08007926 }
7927
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007928 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7929 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7930 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06007931 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007932 } else {
7933 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7934 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007935
7936 if (intel_eld_uptodate(connector,
7937 aud_cntrl_st2, eldv,
7938 aud_cntl_st, IBX_ELD_ADDRESS,
7939 hdmiw_hdmiedid))
7940 return;
7941
Wu Fengguange0dac652011-09-05 14:25:34 +08007942 i = I915_READ(aud_cntrl_st2);
7943 i &= ~eldv;
7944 I915_WRITE(aud_cntrl_st2, i);
7945
7946 if (!eld[0])
7947 return;
7948
Wu Fengguange0dac652011-09-05 14:25:34 +08007949 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007950 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08007951 I915_WRITE(aud_cntl_st, i);
7952
7953 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7954 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7955 for (i = 0; i < len; i++)
7956 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7957
7958 i = I915_READ(aud_cntrl_st2);
7959 i |= eldv;
7960 I915_WRITE(aud_cntrl_st2, i);
7961}
7962
7963void intel_write_eld(struct drm_encoder *encoder,
7964 struct drm_display_mode *mode)
7965{
7966 struct drm_crtc *crtc = encoder->crtc;
7967 struct drm_connector *connector;
7968 struct drm_device *dev = encoder->dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7970
7971 connector = drm_select_eld(encoder, mode);
7972 if (!connector)
7973 return;
7974
7975 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7976 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03007977 connector->name,
Wu Fengguange0dac652011-09-05 14:25:34 +08007978 connector->encoder->base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +03007979 connector->encoder->name);
Wu Fengguange0dac652011-09-05 14:25:34 +08007980
7981 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7982
7983 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03007984 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08007985}
7986
Chris Wilson560b85b2010-08-07 11:01:38 +01007987static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7988{
7989 struct drm_device *dev = crtc->dev;
7990 struct drm_i915_private *dev_priv = dev->dev_private;
7991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson4b0e3332014-05-30 16:35:26 +03007992 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01007993
Chris Wilson4b0e3332014-05-30 16:35:26 +03007994 if (base != intel_crtc->cursor_base) {
Chris Wilson560b85b2010-08-07 11:01:38 +01007995 /* On these chipsets we can only modify the base whilst
7996 * the cursor is disabled.
7997 */
Chris Wilson4b0e3332014-05-30 16:35:26 +03007998 if (intel_crtc->cursor_cntl) {
7999 I915_WRITE(_CURACNTR, 0);
8000 POSTING_READ(_CURACNTR);
8001 intel_crtc->cursor_cntl = 0;
8002 }
8003
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008004 I915_WRITE(_CURABASE, base);
Chris Wilson4b0e3332014-05-30 16:35:26 +03008005 POSTING_READ(_CURABASE);
8006 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008007
Chris Wilson4b0e3332014-05-30 16:35:26 +03008008 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8009 cntl = 0;
8010 if (base)
8011 cntl = (CURSOR_ENABLE |
Chris Wilson560b85b2010-08-07 11:01:38 +01008012 CURSOR_GAMMA_ENABLE |
Chris Wilson4b0e3332014-05-30 16:35:26 +03008013 CURSOR_FORMAT_ARGB);
8014 if (intel_crtc->cursor_cntl != cntl) {
8015 I915_WRITE(_CURACNTR, cntl);
8016 POSTING_READ(_CURACNTR);
8017 intel_crtc->cursor_cntl = cntl;
8018 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008019}
8020
8021static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8022{
8023 struct drm_device *dev = crtc->dev;
8024 struct drm_i915_private *dev_priv = dev->dev_private;
8025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8026 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008027 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01008028
Chris Wilson4b0e3332014-05-30 16:35:26 +03008029 cntl = 0;
8030 if (base) {
8031 cntl = MCURSOR_GAMMA_ENABLE;
8032 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308033 case 64:
8034 cntl |= CURSOR_MODE_64_ARGB_AX;
8035 break;
8036 case 128:
8037 cntl |= CURSOR_MODE_128_ARGB_AX;
8038 break;
8039 case 256:
8040 cntl |= CURSOR_MODE_256_ARGB_AX;
8041 break;
8042 default:
8043 WARN_ON(1);
8044 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01008045 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008046 cntl |= pipe << 28; /* Connect to correct pipe */
Chris Wilson560b85b2010-08-07 11:01:38 +01008047 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008048 if (intel_crtc->cursor_cntl != cntl) {
8049 I915_WRITE(CURCNTR(pipe), cntl);
8050 POSTING_READ(CURCNTR(pipe));
8051 intel_crtc->cursor_cntl = cntl;
8052 }
8053
Chris Wilson560b85b2010-08-07 11:01:38 +01008054 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008055 I915_WRITE(CURBASE(pipe), base);
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01008056 POSTING_READ(CURBASE(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01008057}
8058
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008059static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8060{
8061 struct drm_device *dev = crtc->dev;
8062 struct drm_i915_private *dev_priv = dev->dev_private;
8063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8064 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008065 uint32_t cntl;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008066
Chris Wilson4b0e3332014-05-30 16:35:26 +03008067 cntl = 0;
8068 if (base) {
8069 cntl = MCURSOR_GAMMA_ENABLE;
8070 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308071 case 64:
8072 cntl |= CURSOR_MODE_64_ARGB_AX;
8073 break;
8074 case 128:
8075 cntl |= CURSOR_MODE_128_ARGB_AX;
8076 break;
8077 case 256:
8078 cntl |= CURSOR_MODE_256_ARGB_AX;
8079 break;
8080 default:
8081 WARN_ON(1);
8082 return;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008083 }
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008084 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008085 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8086 cntl |= CURSOR_PIPE_CSC_ENABLE;
8087
8088 if (intel_crtc->cursor_cntl != cntl) {
8089 I915_WRITE(CURCNTR(pipe), cntl);
8090 POSTING_READ(CURCNTR(pipe));
8091 intel_crtc->cursor_cntl = cntl;
8092 }
8093
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008094 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008095 I915_WRITE(CURBASE(pipe), base);
8096 POSTING_READ(CURBASE(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008097}
8098
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008099/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01008100static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8101 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008102{
8103 struct drm_device *dev = crtc->dev;
8104 struct drm_i915_private *dev_priv = dev->dev_private;
8105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8106 int pipe = intel_crtc->pipe;
Matt Roper3d7d6512014-06-10 08:28:13 -07008107 int x = crtc->cursor_x;
8108 int y = crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008109 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008110
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008111 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008112 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008113
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008114 if (x >= intel_crtc->config.pipe_src_w)
8115 base = 0;
8116
8117 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008118 base = 0;
8119
8120 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008121 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008122 base = 0;
8123
8124 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8125 x = -x;
8126 }
8127 pos |= x << CURSOR_X_SHIFT;
8128
8129 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008130 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008131 base = 0;
8132
8133 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8134 y = -y;
8135 }
8136 pos |= y << CURSOR_Y_SHIFT;
8137
Chris Wilson4b0e3332014-05-30 16:35:26 +03008138 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008139 return;
8140
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008141 I915_WRITE(CURPOS(pipe), pos);
8142
8143 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008144 ivb_update_cursor(crtc, base);
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008145 else if (IS_845G(dev) || IS_I865G(dev))
8146 i845_update_cursor(crtc, base);
8147 else
8148 i9xx_update_cursor(crtc, base);
Chris Wilson4b0e3332014-05-30 16:35:26 +03008149 intel_crtc->cursor_base = base;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008150}
8151
Matt Ropere3287952014-06-10 08:28:12 -07008152/*
8153 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8154 *
8155 * Note that the object's reference will be consumed if the update fails. If
8156 * the update succeeds, the reference of the old object (if any) will be
8157 * consumed.
8158 */
8159static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8160 struct drm_i915_gem_object *obj,
8161 uint32_t width, uint32_t height)
Jesse Barnes79e53942008-11-07 14:24:08 -08008162{
8163 struct drm_device *dev = crtc->dev;
8164 struct drm_i915_private *dev_priv = dev->dev_private;
8165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02008166 enum pipe pipe = intel_crtc->pipe;
Chris Wilson64f962e2014-03-26 12:38:15 +00008167 unsigned old_width;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008168 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008169 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008170
Jesse Barnes79e53942008-11-07 14:24:08 -08008171 /* if we want to turn off the cursor ignore width and height */
Matt Ropere3287952014-06-10 08:28:12 -07008172 if (!obj) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008173 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008174 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00008175 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008176 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008177 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008178 }
8179
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308180 /* Check for which cursor types we support */
8181 if (!((width == 64 && height == 64) ||
8182 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8183 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8184 DRM_DEBUG("Cursor dimension not supported\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08008185 return -EINVAL;
8186 }
8187
Chris Wilson05394f32010-11-08 19:18:58 +00008188 if (obj->base.size < width * height * 4) {
Matt Ropere3287952014-06-10 08:28:12 -07008189 DRM_DEBUG_KMS("buffer is too small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10008190 ret = -ENOMEM;
8191 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008192 }
8193
Dave Airlie71acb5e2008-12-30 20:31:46 +10008194 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008195 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008196 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008197 unsigned alignment;
8198
Chris Wilsond9e86c02010-11-10 16:40:20 +00008199 if (obj->tiling_mode) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008200 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008201 ret = -EINVAL;
8202 goto fail_locked;
8203 }
8204
Chris Wilson693db182013-03-05 14:52:39 +00008205 /* Note that the w/a also requires 2 PTE of padding following
8206 * the bo. We currently fill all unused PTE with the shadow
8207 * page and so we should always have valid PTE following the
8208 * cursor preventing the VT-d warning.
8209 */
8210 alignment = 0;
8211 if (need_vtd_wa(dev))
8212 alignment = 64*1024;
8213
8214 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008215 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008216 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008217 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008218 }
8219
Chris Wilsond9e86c02010-11-10 16:40:20 +00008220 ret = i915_gem_object_put_fence(obj);
8221 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008222 DRM_DEBUG_KMS("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008223 goto fail_unpin;
8224 }
8225
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008226 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008227 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008228 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson00731152014-05-21 12:42:56 +01008229 ret = i915_gem_object_attach_phys(obj, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008230 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008231 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008232 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008233 }
Chris Wilson00731152014-05-21 12:42:56 +01008234 addr = obj->phys_handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008235 }
8236
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008237 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04008238 I915_WRITE(CURSIZE, (height << 12) | width);
8239
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008240 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008241 if (intel_crtc->cursor_bo) {
Chris Wilson00731152014-05-21 12:42:56 +01008242 if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilsoncc98b412013-08-09 12:25:09 +01008243 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008244 }
Jesse Barnes80824002009-09-10 15:28:06 -07008245
Daniel Vettera071fa02014-06-18 23:28:09 +02008246 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8247 INTEL_FRONTBUFFER_CURSOR(pipe));
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008248 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008249
Chris Wilson64f962e2014-03-26 12:38:15 +00008250 old_width = intel_crtc->cursor_width;
8251
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008252 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008253 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008254 intel_crtc->cursor_width = width;
8255 intel_crtc->cursor_height = height;
8256
Chris Wilson64f962e2014-03-26 12:38:15 +00008257 if (intel_crtc->active) {
8258 if (old_width != width)
8259 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008260 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Chris Wilson64f962e2014-03-26 12:38:15 +00008261 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008262
Daniel Vetterf99d7062014-06-19 16:01:59 +02008263 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8264
Jesse Barnes79e53942008-11-07 14:24:08 -08008265 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008266fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008267 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008268fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008269 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00008270fail:
Chris Wilson05394f32010-11-08 19:18:58 +00008271 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10008272 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008273}
8274
Jesse Barnes79e53942008-11-07 14:24:08 -08008275static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008276 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008277{
James Simmons72034252010-08-03 01:33:19 +01008278 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008280
James Simmons72034252010-08-03 01:33:19 +01008281 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008282 intel_crtc->lut_r[i] = red[i] >> 8;
8283 intel_crtc->lut_g[i] = green[i] >> 8;
8284 intel_crtc->lut_b[i] = blue[i] >> 8;
8285 }
8286
8287 intel_crtc_load_lut(crtc);
8288}
8289
Jesse Barnes79e53942008-11-07 14:24:08 -08008290/* VESA 640x480x72Hz mode to set on the pipe */
8291static struct drm_display_mode load_detect_mode = {
8292 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8293 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8294};
8295
Daniel Vettera8bb6812014-02-10 18:00:39 +01008296struct drm_framebuffer *
8297__intel_framebuffer_create(struct drm_device *dev,
8298 struct drm_mode_fb_cmd2 *mode_cmd,
8299 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008300{
8301 struct intel_framebuffer *intel_fb;
8302 int ret;
8303
8304 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8305 if (!intel_fb) {
8306 drm_gem_object_unreference_unlocked(&obj->base);
8307 return ERR_PTR(-ENOMEM);
8308 }
8309
8310 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008311 if (ret)
8312 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008313
8314 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008315err:
8316 drm_gem_object_unreference_unlocked(&obj->base);
8317 kfree(intel_fb);
8318
8319 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008320}
8321
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008322static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008323intel_framebuffer_create(struct drm_device *dev,
8324 struct drm_mode_fb_cmd2 *mode_cmd,
8325 struct drm_i915_gem_object *obj)
8326{
8327 struct drm_framebuffer *fb;
8328 int ret;
8329
8330 ret = i915_mutex_lock_interruptible(dev);
8331 if (ret)
8332 return ERR_PTR(ret);
8333 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8334 mutex_unlock(&dev->struct_mutex);
8335
8336 return fb;
8337}
8338
Chris Wilsond2dff872011-04-19 08:36:26 +01008339static u32
8340intel_framebuffer_pitch_for_width(int width, int bpp)
8341{
8342 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8343 return ALIGN(pitch, 64);
8344}
8345
8346static u32
8347intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8348{
8349 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +02008350 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +01008351}
8352
8353static struct drm_framebuffer *
8354intel_framebuffer_create_for_mode(struct drm_device *dev,
8355 struct drm_display_mode *mode,
8356 int depth, int bpp)
8357{
8358 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008359 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008360
8361 obj = i915_gem_alloc_object(dev,
8362 intel_framebuffer_size_for_mode(mode, bpp));
8363 if (obj == NULL)
8364 return ERR_PTR(-ENOMEM);
8365
8366 mode_cmd.width = mode->hdisplay;
8367 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008368 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8369 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008370 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008371
8372 return intel_framebuffer_create(dev, &mode_cmd, obj);
8373}
8374
8375static struct drm_framebuffer *
8376mode_fits_in_fbdev(struct drm_device *dev,
8377 struct drm_display_mode *mode)
8378{
Daniel Vetter4520f532013-10-09 09:18:51 +02008379#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008380 struct drm_i915_private *dev_priv = dev->dev_private;
8381 struct drm_i915_gem_object *obj;
8382 struct drm_framebuffer *fb;
8383
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008384 if (!dev_priv->fbdev)
8385 return NULL;
8386
8387 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008388 return NULL;
8389
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008390 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008391 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008392
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008393 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008394 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8395 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008396 return NULL;
8397
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008398 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008399 return NULL;
8400
8401 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008402#else
8403 return NULL;
8404#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008405}
8406
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008407bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008408 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05008409 struct intel_load_detect_pipe *old,
8410 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008411{
8412 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008413 struct intel_encoder *intel_encoder =
8414 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008415 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008416 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008417 struct drm_crtc *crtc = NULL;
8418 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008419 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05008420 struct drm_mode_config *config = &dev->mode_config;
8421 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008422
Chris Wilsond2dff872011-04-19 08:36:26 +01008423 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008424 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008425 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008426
Rob Clark51fd3712013-11-19 12:10:12 -05008427 drm_modeset_acquire_init(ctx, 0);
8428
8429retry:
8430 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8431 if (ret)
8432 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008433
Jesse Barnes79e53942008-11-07 14:24:08 -08008434 /*
8435 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008436 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008437 * - if the connector already has an assigned crtc, use it (but make
8438 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008439 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008440 * - try to find the first unused crtc that can drive this connector,
8441 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008442 */
8443
8444 /* See if we already have a CRTC for this connector */
8445 if (encoder->crtc) {
8446 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008447
Rob Clark51fd3712013-11-19 12:10:12 -05008448 ret = drm_modeset_lock(&crtc->mutex, ctx);
8449 if (ret)
8450 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01008451
Daniel Vetter24218aa2012-08-12 19:27:11 +02008452 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008453 old->load_detect_temp = false;
8454
8455 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008456 if (connector->dpms != DRM_MODE_DPMS_ON)
8457 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008458
Chris Wilson71731882011-04-19 23:10:58 +01008459 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008460 }
8461
8462 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008463 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008464 i++;
8465 if (!(encoder->possible_crtcs & (1 << i)))
8466 continue;
8467 if (!possible_crtc->enabled) {
8468 crtc = possible_crtc;
8469 break;
8470 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008471 }
8472
8473 /*
8474 * If we didn't find an unused CRTC, don't use any.
8475 */
8476 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008477 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05008478 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08008479 }
8480
Rob Clark51fd3712013-11-19 12:10:12 -05008481 ret = drm_modeset_lock(&crtc->mutex, ctx);
8482 if (ret)
8483 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02008484 intel_encoder->new_crtc = to_intel_crtc(crtc);
8485 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008486
8487 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008488 intel_crtc->new_enabled = true;
8489 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008490 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008491 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008492 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008493
Chris Wilson64927112011-04-20 07:25:26 +01008494 if (!mode)
8495 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008496
Chris Wilsond2dff872011-04-19 08:36:26 +01008497 /* We need a framebuffer large enough to accommodate all accesses
8498 * that the plane may generate whilst we perform load detection.
8499 * We can not rely on the fbcon either being present (we get called
8500 * during its initialisation to detect all boot displays, or it may
8501 * not even exist) or that it is large enough to satisfy the
8502 * requested mode.
8503 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008504 fb = mode_fits_in_fbdev(dev, mode);
8505 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008506 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008507 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8508 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008509 } else
8510 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008511 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008512 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008513 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008514 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008515
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008516 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008517 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008518 if (old->release_fb)
8519 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008520 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008521 }
Chris Wilson71731882011-04-19 23:10:58 +01008522
Jesse Barnes79e53942008-11-07 14:24:08 -08008523 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008524 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008525 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008526
8527 fail:
8528 intel_crtc->new_enabled = crtc->enabled;
8529 if (intel_crtc->new_enabled)
8530 intel_crtc->new_config = &intel_crtc->config;
8531 else
8532 intel_crtc->new_config = NULL;
Rob Clark51fd3712013-11-19 12:10:12 -05008533fail_unlock:
8534 if (ret == -EDEADLK) {
8535 drm_modeset_backoff(ctx);
8536 goto retry;
8537 }
8538
8539 drm_modeset_drop_locks(ctx);
8540 drm_modeset_acquire_fini(ctx);
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008541
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008542 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008543}
8544
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008545void intel_release_load_detect_pipe(struct drm_connector *connector,
Rob Clark51fd3712013-11-19 12:10:12 -05008546 struct intel_load_detect_pipe *old,
8547 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008548{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008549 struct intel_encoder *intel_encoder =
8550 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008551 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008552 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008554
Chris Wilsond2dff872011-04-19 08:36:26 +01008555 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008556 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008557 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008558
Chris Wilson8261b192011-04-19 23:18:09 +01008559 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008560 to_intel_connector(connector)->new_encoder = NULL;
8561 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008562 intel_crtc->new_enabled = false;
8563 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008564 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008565
Daniel Vetter36206362012-12-10 20:42:17 +01008566 if (old->release_fb) {
8567 drm_framebuffer_unregister_private(old->release_fb);
8568 drm_framebuffer_unreference(old->release_fb);
8569 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008570
Rob Clark51fd3712013-11-19 12:10:12 -05008571 goto unlock;
Chris Wilson0622a532011-04-21 09:32:11 +01008572 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008573 }
8574
Eric Anholtc751ce42010-03-25 11:48:48 -07008575 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008576 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8577 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01008578
Rob Clark51fd3712013-11-19 12:10:12 -05008579unlock:
8580 drm_modeset_drop_locks(ctx);
8581 drm_modeset_acquire_fini(ctx);
Jesse Barnes79e53942008-11-07 14:24:08 -08008582}
8583
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008584static int i9xx_pll_refclk(struct drm_device *dev,
8585 const struct intel_crtc_config *pipe_config)
8586{
8587 struct drm_i915_private *dev_priv = dev->dev_private;
8588 u32 dpll = pipe_config->dpll_hw_state.dpll;
8589
8590 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008591 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008592 else if (HAS_PCH_SPLIT(dev))
8593 return 120000;
8594 else if (!IS_GEN2(dev))
8595 return 96000;
8596 else
8597 return 48000;
8598}
8599
Jesse Barnes79e53942008-11-07 14:24:08 -08008600/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008601static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8602 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008603{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008604 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008605 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008606 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008607 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008608 u32 fp;
8609 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008610 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008611
8612 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008613 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008614 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008615 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008616
8617 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008618 if (IS_PINEVIEW(dev)) {
8619 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8620 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008621 } else {
8622 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8623 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8624 }
8625
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008626 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008627 if (IS_PINEVIEW(dev))
8628 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8629 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008630 else
8631 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008632 DPLL_FPA01_P1_POST_DIV_SHIFT);
8633
8634 switch (dpll & DPLL_MODE_MASK) {
8635 case DPLLB_MODE_DAC_SERIAL:
8636 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8637 5 : 10;
8638 break;
8639 case DPLLB_MODE_LVDS:
8640 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8641 7 : 14;
8642 break;
8643 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008644 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008645 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008646 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008647 }
8648
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008649 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008650 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008651 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008652 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008653 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008654 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008655 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008656
8657 if (is_lvds) {
8658 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8659 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008660
8661 if (lvds & LVDS_CLKB_POWER_UP)
8662 clock.p2 = 7;
8663 else
8664 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008665 } else {
8666 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8667 clock.p1 = 2;
8668 else {
8669 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8670 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8671 }
8672 if (dpll & PLL_P2_DIVIDE_BY_4)
8673 clock.p2 = 4;
8674 else
8675 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008676 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008677
8678 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008679 }
8680
Ville Syrjälä18442d02013-09-13 16:00:08 +03008681 /*
8682 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008683 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008684 * encoder's get_config() function.
8685 */
8686 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008687}
8688
Ville Syrjälä6878da02013-09-13 15:59:11 +03008689int intel_dotclock_calculate(int link_freq,
8690 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008691{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008692 /*
8693 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008694 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008695 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008696 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008697 *
8698 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008699 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008700 */
8701
Ville Syrjälä6878da02013-09-13 15:59:11 +03008702 if (!m_n->link_n)
8703 return 0;
8704
8705 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8706}
8707
Ville Syrjälä18442d02013-09-13 16:00:08 +03008708static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8709 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008710{
8711 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008712
8713 /* read out port_clock from the DPLL */
8714 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008715
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008716 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008717 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008718 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008719 * agree once we know their relationship in the encoder's
8720 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008721 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008722 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008723 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8724 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008725}
8726
8727/** Returns the currently programmed mode of the given pipe. */
8728struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8729 struct drm_crtc *crtc)
8730{
Jesse Barnes548f2452011-02-17 10:40:53 -08008731 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008733 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008734 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008735 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008736 int htot = I915_READ(HTOTAL(cpu_transcoder));
8737 int hsync = I915_READ(HSYNC(cpu_transcoder));
8738 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8739 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008740 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008741
8742 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8743 if (!mode)
8744 return NULL;
8745
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008746 /*
8747 * Construct a pipe_config sufficient for getting the clock info
8748 * back out of crtc_clock_get.
8749 *
8750 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8751 * to use a real value here instead.
8752 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008753 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008754 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008755 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8756 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8757 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008758 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8759
Ville Syrjälä773ae032013-09-23 17:48:20 +03008760 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008761 mode->hdisplay = (htot & 0xffff) + 1;
8762 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8763 mode->hsync_start = (hsync & 0xffff) + 1;
8764 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8765 mode->vdisplay = (vtot & 0xffff) + 1;
8766 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8767 mode->vsync_start = (vsync & 0xffff) + 1;
8768 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8769
8770 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008771
8772 return mode;
8773}
8774
Daniel Vettercc365132014-06-18 13:59:13 +02008775static void intel_increase_pllclock(struct drm_device *dev,
8776 enum pipe pipe)
Jesse Barnes652c3932009-08-17 13:31:43 -07008777{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008778 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008779 int dpll_reg = DPLL(pipe);
8780 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07008781
Eric Anholtbad720f2009-10-22 16:11:14 -07008782 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008783 return;
8784
8785 if (!dev_priv->lvds_downclock_avail)
8786 return;
8787
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008788 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008789 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08008790 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008791
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008792 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008793
8794 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8795 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008796 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008797
Jesse Barnes652c3932009-08-17 13:31:43 -07008798 dpll = I915_READ(dpll_reg);
8799 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08008800 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008801 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008802}
8803
8804static void intel_decrease_pllclock(struct drm_crtc *crtc)
8805{
8806 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008807 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008809
Eric Anholtbad720f2009-10-22 16:11:14 -07008810 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008811 return;
8812
8813 if (!dev_priv->lvds_downclock_avail)
8814 return;
8815
8816 /*
8817 * Since this is called by a timer, we should never get here in
8818 * the manual case.
8819 */
8820 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008821 int pipe = intel_crtc->pipe;
8822 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008823 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008824
Zhao Yakui44d98a62009-10-09 11:39:40 +08008825 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008826
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008827 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008828
Chris Wilson074b5e12012-05-02 12:07:06 +01008829 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008830 dpll |= DISPLAY_RATE_SELECT_FPA1;
8831 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008832 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008833 dpll = I915_READ(dpll_reg);
8834 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008835 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008836 }
8837
8838}
8839
Chris Wilsonf047e392012-07-21 12:31:41 +01008840void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008841{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008842 struct drm_i915_private *dev_priv = dev->dev_private;
8843
Chris Wilsonf62a0072014-02-21 17:55:39 +00008844 if (dev_priv->mm.busy)
8845 return;
8846
Paulo Zanoni43694d62014-03-07 20:08:08 -03008847 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008848 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008849 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008850}
8851
8852void intel_mark_idle(struct drm_device *dev)
8853{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008854 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008855 struct drm_crtc *crtc;
8856
Chris Wilsonf62a0072014-02-21 17:55:39 +00008857 if (!dev_priv->mm.busy)
8858 return;
8859
8860 dev_priv->mm.busy = false;
8861
Jani Nikulad330a952014-01-21 11:24:25 +02008862 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008863 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008864
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008865 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008866 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008867 continue;
8868
8869 intel_decrease_pllclock(crtc);
8870 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008871
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008872 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008873 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008874
8875out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03008876 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008877}
8878
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07008879
Daniel Vetterf99d7062014-06-19 16:01:59 +02008880/**
8881 * intel_mark_fb_busy - mark given planes as busy
8882 * @dev: DRM device
8883 * @frontbuffer_bits: bits for the affected planes
8884 * @ring: optional ring for asynchronous commands
8885 *
8886 * This function gets called every time the screen contents change. It can be
8887 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8888 */
8889static void intel_mark_fb_busy(struct drm_device *dev,
8890 unsigned frontbuffer_bits,
8891 struct intel_engine_cs *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01008892{
Daniel Vettercc365132014-06-18 13:59:13 +02008893 enum pipe pipe;
Jesse Barnes652c3932009-08-17 13:31:43 -07008894
Jani Nikulad330a952014-01-21 11:24:25 +02008895 if (!i915.powersave)
Jesse Barnes652c3932009-08-17 13:31:43 -07008896 return;
8897
Daniel Vettercc365132014-06-18 13:59:13 +02008898 for_each_pipe(pipe) {
Daniel Vetterf99d7062014-06-19 16:01:59 +02008899 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
Jesse Barnes652c3932009-08-17 13:31:43 -07008900 continue;
8901
Daniel Vettercc365132014-06-18 13:59:13 +02008902 intel_increase_pllclock(dev, pipe);
Chris Wilsonc65355b2013-06-06 16:53:41 -03008903 if (ring && intel_fbc_enabled(dev))
8904 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07008905 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008906}
8907
Daniel Vetterf99d7062014-06-19 16:01:59 +02008908/**
8909 * intel_fb_obj_invalidate - invalidate frontbuffer object
8910 * @obj: GEM object to invalidate
8911 * @ring: set for asynchronous rendering
8912 *
8913 * This function gets called every time rendering on the given object starts and
8914 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8915 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8916 * until the rendering completes or a flip on this frontbuffer plane is
8917 * scheduled.
8918 */
8919void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8920 struct intel_engine_cs *ring)
8921{
8922 struct drm_device *dev = obj->base.dev;
8923 struct drm_i915_private *dev_priv = dev->dev_private;
8924
8925 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8926
8927 if (!obj->frontbuffer_bits)
8928 return;
8929
8930 if (ring) {
8931 mutex_lock(&dev_priv->fb_tracking.lock);
8932 dev_priv->fb_tracking.busy_bits
8933 |= obj->frontbuffer_bits;
8934 dev_priv->fb_tracking.flip_bits
8935 &= ~obj->frontbuffer_bits;
8936 mutex_unlock(&dev_priv->fb_tracking.lock);
8937 }
8938
8939 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8940
8941 intel_edp_psr_exit(dev);
8942}
8943
8944/**
8945 * intel_frontbuffer_flush - flush frontbuffer
8946 * @dev: DRM device
8947 * @frontbuffer_bits: frontbuffer plane tracking bits
8948 *
8949 * This function gets called every time rendering on the given planes has
8950 * completed and frontbuffer caching can be started again. Flushes will get
8951 * delayed if they're blocked by some oustanding asynchronous rendering.
8952 *
8953 * Can be called without any locks held.
8954 */
8955void intel_frontbuffer_flush(struct drm_device *dev,
8956 unsigned frontbuffer_bits)
8957{
8958 struct drm_i915_private *dev_priv = dev->dev_private;
8959
8960 /* Delay flushing when rings are still busy.*/
8961 mutex_lock(&dev_priv->fb_tracking.lock);
8962 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8963 mutex_unlock(&dev_priv->fb_tracking.lock);
8964
8965 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8966
8967 intel_edp_psr_exit(dev);
8968}
8969
8970/**
8971 * intel_fb_obj_flush - flush frontbuffer object
8972 * @obj: GEM object to flush
8973 * @retire: set when retiring asynchronous rendering
8974 *
8975 * This function gets called every time rendering on the given object has
8976 * completed and frontbuffer caching can be started again. If @retire is true
8977 * then any delayed flushes will be unblocked.
8978 */
8979void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
8980 bool retire)
8981{
8982 struct drm_device *dev = obj->base.dev;
8983 struct drm_i915_private *dev_priv = dev->dev_private;
8984 unsigned frontbuffer_bits;
8985
8986 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8987
8988 if (!obj->frontbuffer_bits)
8989 return;
8990
8991 frontbuffer_bits = obj->frontbuffer_bits;
8992
8993 if (retire) {
8994 mutex_lock(&dev_priv->fb_tracking.lock);
8995 /* Filter out new bits since rendering started. */
8996 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
8997
8998 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
8999 mutex_unlock(&dev_priv->fb_tracking.lock);
9000 }
9001
9002 intel_frontbuffer_flush(dev, frontbuffer_bits);
9003}
9004
9005/**
9006 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9007 * @dev: DRM device
9008 * @frontbuffer_bits: frontbuffer plane tracking bits
9009 *
9010 * This function gets called after scheduling a flip on @obj. The actual
9011 * frontbuffer flushing will be delayed until completion is signalled with
9012 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9013 * flush will be cancelled.
9014 *
9015 * Can be called without any locks held.
9016 */
9017void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9018 unsigned frontbuffer_bits)
9019{
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021
9022 mutex_lock(&dev_priv->fb_tracking.lock);
9023 dev_priv->fb_tracking.flip_bits
9024 |= frontbuffer_bits;
9025 mutex_unlock(&dev_priv->fb_tracking.lock);
9026}
9027
9028/**
9029 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9030 * @dev: DRM device
9031 * @frontbuffer_bits: frontbuffer plane tracking bits
9032 *
9033 * This function gets called after the flip has been latched and will complete
9034 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9035 *
9036 * Can be called without any locks held.
9037 */
9038void intel_frontbuffer_flip_complete(struct drm_device *dev,
9039 unsigned frontbuffer_bits)
9040{
9041 struct drm_i915_private *dev_priv = dev->dev_private;
9042
9043 mutex_lock(&dev_priv->fb_tracking.lock);
9044 /* Mask any cancelled flips. */
9045 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9046 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9047 mutex_unlock(&dev_priv->fb_tracking.lock);
9048
9049 intel_frontbuffer_flush(dev, frontbuffer_bits);
9050}
9051
Jesse Barnes79e53942008-11-07 14:24:08 -08009052static void intel_crtc_destroy(struct drm_crtc *crtc)
9053{
9054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009055 struct drm_device *dev = crtc->dev;
9056 struct intel_unpin_work *work;
9057 unsigned long flags;
9058
9059 spin_lock_irqsave(&dev->event_lock, flags);
9060 work = intel_crtc->unpin_work;
9061 intel_crtc->unpin_work = NULL;
9062 spin_unlock_irqrestore(&dev->event_lock, flags);
9063
9064 if (work) {
9065 cancel_work_sync(&work->work);
9066 kfree(work);
9067 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009068
9069 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009070
Jesse Barnes79e53942008-11-07 14:24:08 -08009071 kfree(intel_crtc);
9072}
9073
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009074static void intel_unpin_work_fn(struct work_struct *__work)
9075{
9076 struct intel_unpin_work *work =
9077 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009078 struct drm_device *dev = work->crtc->dev;
Daniel Vetterf99d7062014-06-19 16:01:59 +02009079 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009080
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009081 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01009082 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00009083 drm_gem_object_unreference(&work->pending_flip_obj->base);
9084 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00009085
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009086 intel_update_fbc(dev);
9087 mutex_unlock(&dev->struct_mutex);
9088
Daniel Vetterf99d7062014-06-19 16:01:59 +02009089 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9090
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009091 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9092 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9093
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009094 kfree(work);
9095}
9096
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009097static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01009098 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009099{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009100 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9102 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009103 unsigned long flags;
9104
9105 /* Ignore early vblank irqs */
9106 if (intel_crtc == NULL)
9107 return;
9108
9109 spin_lock_irqsave(&dev->event_lock, flags);
9110 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00009111
9112 /* Ensure we don't miss a work->pending update ... */
9113 smp_rmb();
9114
9115 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009116 spin_unlock_irqrestore(&dev->event_lock, flags);
9117 return;
9118 }
9119
Chris Wilsone7d841c2012-12-03 11:36:30 +00009120 /* and that the unpin work is consistent wrt ->pending. */
9121 smp_rmb();
9122
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009123 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009124
Rob Clark45a066e2012-10-08 14:50:40 -05009125 if (work->event)
9126 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009127
Daniel Vetter87b6b102014-05-15 15:33:46 +02009128 drm_crtc_vblank_put(crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01009129
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009130 spin_unlock_irqrestore(&dev->event_lock, flags);
9131
Daniel Vetter2c10d572012-12-20 21:24:07 +01009132 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009133
9134 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07009135
9136 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009137}
9138
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009139void intel_finish_page_flip(struct drm_device *dev, int pipe)
9140{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009141 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009142 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9143
Mario Kleiner49b14a52010-12-09 07:00:07 +01009144 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009145}
9146
9147void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9148{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009149 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009150 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9151
Mario Kleiner49b14a52010-12-09 07:00:07 +01009152 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009153}
9154
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009155/* Is 'a' after or equal to 'b'? */
9156static bool g4x_flip_count_after_eq(u32 a, u32 b)
9157{
9158 return !((a - b) & 0x80000000);
9159}
9160
9161static bool page_flip_finished(struct intel_crtc *crtc)
9162{
9163 struct drm_device *dev = crtc->base.dev;
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165
9166 /*
9167 * The relevant registers doen't exist on pre-ctg.
9168 * As the flip done interrupt doesn't trigger for mmio
9169 * flips on gmch platforms, a flip count check isn't
9170 * really needed there. But since ctg has the registers,
9171 * include it in the check anyway.
9172 */
9173 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9174 return true;
9175
9176 /*
9177 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9178 * used the same base address. In that case the mmio flip might
9179 * have completed, but the CS hasn't even executed the flip yet.
9180 *
9181 * A flip count check isn't enough as the CS might have updated
9182 * the base address just after start of vblank, but before we
9183 * managed to process the interrupt. This means we'd complete the
9184 * CS flip too soon.
9185 *
9186 * Combining both checks should get us a good enough result. It may
9187 * still happen that the CS flip has been executed, but has not
9188 * yet actually completed. But in case the base address is the same
9189 * anyway, we don't really care.
9190 */
9191 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9192 crtc->unpin_work->gtt_offset &&
9193 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9194 crtc->unpin_work->flip_count);
9195}
9196
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009197void intel_prepare_page_flip(struct drm_device *dev, int plane)
9198{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009199 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009200 struct intel_crtc *intel_crtc =
9201 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9202 unsigned long flags;
9203
Chris Wilsone7d841c2012-12-03 11:36:30 +00009204 /* NB: An MMIO update of the plane base pointer will also
9205 * generate a page-flip completion irq, i.e. every modeset
9206 * is also accompanied by a spurious intel_prepare_page_flip().
9207 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009208 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009209 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00009210 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009211 spin_unlock_irqrestore(&dev->event_lock, flags);
9212}
9213
Robin Schroereba905b2014-05-18 02:24:50 +02009214static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00009215{
9216 /* Ensure that the work item is consistent when activating it ... */
9217 smp_wmb();
9218 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9219 /* and that it is marked active as soon as the irq could fire. */
9220 smp_wmb();
9221}
9222
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009223static int intel_gen2_queue_flip(struct drm_device *dev,
9224 struct drm_crtc *crtc,
9225 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009226 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009227 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009228 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009229{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009231 u32 flip_mask;
9232 int ret;
9233
Daniel Vetter6d90c952012-04-26 23:28:05 +02009234 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009235 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009236 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009237
9238 /* Can't queue multiple flips, so wait for the previous
9239 * one to finish before executing the next.
9240 */
9241 if (intel_crtc->plane)
9242 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9243 else
9244 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009245 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9246 intel_ring_emit(ring, MI_NOOP);
9247 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9248 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9249 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009250 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009251 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00009252
9253 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009254 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009255 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009256}
9257
9258static int intel_gen3_queue_flip(struct drm_device *dev,
9259 struct drm_crtc *crtc,
9260 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009261 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009262 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009263 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009264{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009266 u32 flip_mask;
9267 int ret;
9268
Daniel Vetter6d90c952012-04-26 23:28:05 +02009269 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009270 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009271 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009272
9273 if (intel_crtc->plane)
9274 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9275 else
9276 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009277 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9278 intel_ring_emit(ring, MI_NOOP);
9279 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9280 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9281 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009282 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009283 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009284
Chris Wilsone7d841c2012-12-03 11:36:30 +00009285 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009286 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009287 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009288}
9289
9290static int intel_gen4_queue_flip(struct drm_device *dev,
9291 struct drm_crtc *crtc,
9292 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009293 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009294 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009295 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009296{
9297 struct drm_i915_private *dev_priv = dev->dev_private;
9298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9299 uint32_t pf, pipesrc;
9300 int ret;
9301
Daniel Vetter6d90c952012-04-26 23:28:05 +02009302 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009303 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009304 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009305
9306 /* i965+ uses the linear or tiled offsets from the
9307 * Display Registers (which do not change across a page-flip)
9308 * so we need only reprogram the base address.
9309 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009310 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9311 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9312 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009313 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009314 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009315
9316 /* XXX Enabling the panel-fitter across page-flip is so far
9317 * untested on non-native modes, so ignore it for now.
9318 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9319 */
9320 pf = 0;
9321 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009322 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009323
9324 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009325 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009326 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009327}
9328
9329static int intel_gen6_queue_flip(struct drm_device *dev,
9330 struct drm_crtc *crtc,
9331 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009332 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009333 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009334 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009335{
9336 struct drm_i915_private *dev_priv = dev->dev_private;
9337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9338 uint32_t pf, pipesrc;
9339 int ret;
9340
Daniel Vetter6d90c952012-04-26 23:28:05 +02009341 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009342 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009343 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009344
Daniel Vetter6d90c952012-04-26 23:28:05 +02009345 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9346 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9347 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009348 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009349
Chris Wilson99d9acd2012-04-17 20:37:00 +01009350 /* Contrary to the suggestions in the documentation,
9351 * "Enable Panel Fitter" does not seem to be required when page
9352 * flipping with a non-native mode, and worse causes a normal
9353 * modeset to fail.
9354 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9355 */
9356 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009357 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009358 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009359
9360 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009361 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009362 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009363}
9364
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009365static int intel_gen7_queue_flip(struct drm_device *dev,
9366 struct drm_crtc *crtc,
9367 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009368 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009369 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009370 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009371{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009373 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009374 int len, ret;
9375
Robin Schroereba905b2014-05-18 02:24:50 +02009376 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009377 case PLANE_A:
9378 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9379 break;
9380 case PLANE_B:
9381 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9382 break;
9383 case PLANE_C:
9384 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9385 break;
9386 default:
9387 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009388 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009389 }
9390
Chris Wilsonffe74d72013-08-26 20:58:12 +01009391 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009392 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009393 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009394 /*
9395 * On Gen 8, SRM is now taking an extra dword to accommodate
9396 * 48bits addresses, and we need a NOOP for the batch size to
9397 * stay even.
9398 */
9399 if (IS_GEN8(dev))
9400 len += 2;
9401 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009402
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009403 /*
9404 * BSpec MI_DISPLAY_FLIP for IVB:
9405 * "The full packet must be contained within the same cache line."
9406 *
9407 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9408 * cacheline, if we ever start emitting more commands before
9409 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9410 * then do the cacheline alignment, and finally emit the
9411 * MI_DISPLAY_FLIP.
9412 */
9413 ret = intel_ring_cacheline_align(ring);
9414 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009415 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009416
Chris Wilsonffe74d72013-08-26 20:58:12 +01009417 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009418 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009419 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009420
Chris Wilsonffe74d72013-08-26 20:58:12 +01009421 /* Unmask the flip-done completion message. Note that the bspec says that
9422 * we should do this for both the BCS and RCS, and that we must not unmask
9423 * more than one flip event at any time (or ensure that one flip message
9424 * can be sent by waiting for flip-done prior to queueing new flips).
9425 * Experimentation says that BCS works despite DERRMR masking all
9426 * flip-done completion events and that unmasking all planes at once
9427 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9428 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9429 */
9430 if (ring->id == RCS) {
9431 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9432 intel_ring_emit(ring, DERRMR);
9433 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9434 DERRMR_PIPEB_PRI_FLIP_DONE |
9435 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009436 if (IS_GEN8(dev))
9437 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9438 MI_SRM_LRM_GLOBAL_GTT);
9439 else
9440 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9441 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009442 intel_ring_emit(ring, DERRMR);
9443 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009444 if (IS_GEN8(dev)) {
9445 intel_ring_emit(ring, 0);
9446 intel_ring_emit(ring, MI_NOOP);
9447 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009448 }
9449
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009450 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009451 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009452 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009453 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009454
9455 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009456 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009457 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009458}
9459
Sourab Gupta84c33a62014-06-02 16:47:17 +05309460static bool use_mmio_flip(struct intel_engine_cs *ring,
9461 struct drm_i915_gem_object *obj)
9462{
9463 /*
9464 * This is not being used for older platforms, because
9465 * non-availability of flip done interrupt forces us to use
9466 * CS flips. Older platforms derive flip done using some clever
9467 * tricks involving the flip_pending status bits and vblank irqs.
9468 * So using MMIO flips there would disrupt this mechanism.
9469 */
9470
Chris Wilson8e09bf82014-07-08 10:40:30 +01009471 if (ring == NULL)
9472 return true;
9473
Sourab Gupta84c33a62014-06-02 16:47:17 +05309474 if (INTEL_INFO(ring->dev)->gen < 5)
9475 return false;
9476
9477 if (i915.use_mmio_flip < 0)
9478 return false;
9479 else if (i915.use_mmio_flip > 0)
9480 return true;
9481 else
9482 return ring != obj->ring;
9483}
9484
9485static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9486{
9487 struct drm_device *dev = intel_crtc->base.dev;
9488 struct drm_i915_private *dev_priv = dev->dev_private;
9489 struct intel_framebuffer *intel_fb =
9490 to_intel_framebuffer(intel_crtc->base.primary->fb);
9491 struct drm_i915_gem_object *obj = intel_fb->obj;
9492 u32 dspcntr;
9493 u32 reg;
9494
9495 intel_mark_page_flip_active(intel_crtc);
9496
9497 reg = DSPCNTR(intel_crtc->plane);
9498 dspcntr = I915_READ(reg);
9499
9500 if (INTEL_INFO(dev)->gen >= 4) {
9501 if (obj->tiling_mode != I915_TILING_NONE)
9502 dspcntr |= DISPPLANE_TILED;
9503 else
9504 dspcntr &= ~DISPPLANE_TILED;
9505 }
9506 I915_WRITE(reg, dspcntr);
9507
9508 I915_WRITE(DSPSURF(intel_crtc->plane),
9509 intel_crtc->unpin_work->gtt_offset);
9510 POSTING_READ(DSPSURF(intel_crtc->plane));
9511}
9512
9513static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9514{
9515 struct intel_engine_cs *ring;
9516 int ret;
9517
9518 lockdep_assert_held(&obj->base.dev->struct_mutex);
9519
9520 if (!obj->last_write_seqno)
9521 return 0;
9522
9523 ring = obj->ring;
9524
9525 if (i915_seqno_passed(ring->get_seqno(ring, true),
9526 obj->last_write_seqno))
9527 return 0;
9528
9529 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9530 if (ret)
9531 return ret;
9532
9533 if (WARN_ON(!ring->irq_get(ring)))
9534 return 0;
9535
9536 return 1;
9537}
9538
9539void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9540{
9541 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9542 struct intel_crtc *intel_crtc;
9543 unsigned long irq_flags;
9544 u32 seqno;
9545
9546 seqno = ring->get_seqno(ring, false);
9547
9548 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9549 for_each_intel_crtc(ring->dev, intel_crtc) {
9550 struct intel_mmio_flip *mmio_flip;
9551
9552 mmio_flip = &intel_crtc->mmio_flip;
9553 if (mmio_flip->seqno == 0)
9554 continue;
9555
9556 if (ring->id != mmio_flip->ring_id)
9557 continue;
9558
9559 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9560 intel_do_mmio_flip(intel_crtc);
9561 mmio_flip->seqno = 0;
9562 ring->irq_put(ring);
9563 }
9564 }
9565 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9566}
9567
9568static int intel_queue_mmio_flip(struct drm_device *dev,
9569 struct drm_crtc *crtc,
9570 struct drm_framebuffer *fb,
9571 struct drm_i915_gem_object *obj,
9572 struct intel_engine_cs *ring,
9573 uint32_t flags)
9574{
9575 struct drm_i915_private *dev_priv = dev->dev_private;
9576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9577 unsigned long irq_flags;
9578 int ret;
9579
9580 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9581 return -EBUSY;
9582
9583 ret = intel_postpone_flip(obj);
9584 if (ret < 0)
9585 return ret;
9586 if (ret == 0) {
9587 intel_do_mmio_flip(intel_crtc);
9588 return 0;
9589 }
9590
9591 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9592 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9593 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9594 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9595
9596 /*
9597 * Double check to catch cases where irq fired before
9598 * mmio flip data was ready
9599 */
9600 intel_notify_mmio_flip(obj->ring);
9601 return 0;
9602}
9603
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009604static int intel_default_queue_flip(struct drm_device *dev,
9605 struct drm_crtc *crtc,
9606 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009607 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009608 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009609 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009610{
9611 return -ENODEV;
9612}
9613
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009614static int intel_crtc_page_flip(struct drm_crtc *crtc,
9615 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009616 struct drm_pending_vblank_event *event,
9617 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009618{
9619 struct drm_device *dev = crtc->dev;
9620 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009621 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009622 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02009624 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009625 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009626 struct intel_engine_cs *ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009627 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01009628 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009629
Matt Roper2ff8fde2014-07-08 07:50:07 -07009630 /*
9631 * drm_mode_page_flip_ioctl() should already catch this, but double
9632 * check to be safe. In the future we may enable pageflipping from
9633 * a disabled primary plane.
9634 */
9635 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9636 return -EBUSY;
9637
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009638 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009639 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009640 return -EINVAL;
9641
9642 /*
9643 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9644 * Note that pitch changes could also affect these register.
9645 */
9646 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009647 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9648 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009649 return -EINVAL;
9650
Chris Wilsonf900db42014-02-20 09:26:13 +00009651 if (i915_terminally_wedged(&dev_priv->gpu_error))
9652 goto out_hang;
9653
Daniel Vetterb14c5672013-09-19 12:18:32 +02009654 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009655 if (work == NULL)
9656 return -ENOMEM;
9657
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009658 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009659 work->crtc = crtc;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009660 work->old_fb_obj = intel_fb_obj(old_fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009661 INIT_WORK(&work->work, intel_unpin_work_fn);
9662
Daniel Vetter87b6b102014-05-15 15:33:46 +02009663 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009664 if (ret)
9665 goto free_work;
9666
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009667 /* We borrow the event spin lock for protecting unpin_work */
9668 spin_lock_irqsave(&dev->event_lock, flags);
9669 if (intel_crtc->unpin_work) {
9670 spin_unlock_irqrestore(&dev->event_lock, flags);
9671 kfree(work);
Daniel Vetter87b6b102014-05-15 15:33:46 +02009672 drm_crtc_vblank_put(crtc);
Chris Wilson468f0b42010-05-27 13:18:13 +01009673
9674 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009675 return -EBUSY;
9676 }
9677 intel_crtc->unpin_work = work;
9678 spin_unlock_irqrestore(&dev->event_lock, flags);
9679
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009680 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9681 flush_workqueue(dev_priv->wq);
9682
Chris Wilson79158102012-05-23 11:13:58 +01009683 ret = i915_mutex_lock_interruptible(dev);
9684 if (ret)
9685 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009686
Jesse Barnes75dfca82010-02-10 15:09:44 -08009687 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009688 drm_gem_object_reference(&work->old_fb_obj->base);
9689 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009690
Matt Roperf4510a22014-04-01 15:22:40 -07009691 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009692
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009693 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009694
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01009695 work->enable_stall_check = true;
9696
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009697 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009698 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009699
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009700 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Daniel Vettera071fa02014-06-18 23:28:09 +02009701 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009702
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009703 if (IS_VALLEYVIEW(dev)) {
9704 ring = &dev_priv->ring[BCS];
Chris Wilson8e09bf82014-07-08 10:40:30 +01009705 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9706 /* vlv: DISPLAY_FLIP fails to change tiling */
9707 ring = NULL;
Chris Wilson2a92d5b2014-07-08 10:40:29 +01009708 } else if (IS_IVYBRIDGE(dev)) {
9709 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009710 } else if (INTEL_INFO(dev)->gen >= 7) {
9711 ring = obj->ring;
9712 if (ring == NULL || ring->id != RCS)
9713 ring = &dev_priv->ring[BCS];
9714 } else {
9715 ring = &dev_priv->ring[RCS];
9716 }
9717
9718 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009719 if (ret)
9720 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009721
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009722 work->gtt_offset =
9723 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9724
Sourab Gupta84c33a62014-06-02 16:47:17 +05309725 if (use_mmio_flip(ring, obj))
9726 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9727 page_flip_flags);
9728 else
9729 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9730 page_flip_flags);
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009731 if (ret)
9732 goto cleanup_unpin;
9733
Daniel Vettera071fa02014-06-18 23:28:09 +02009734 i915_gem_track_fb(work->old_fb_obj, obj,
9735 INTEL_FRONTBUFFER_PRIMARY(pipe));
9736
Chris Wilson7782de32011-07-08 12:22:41 +01009737 intel_disable_fbc(dev);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009738 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009739 mutex_unlock(&dev->struct_mutex);
9740
Jesse Barnese5510fa2010-07-01 16:48:37 -07009741 trace_i915_flip_request(intel_crtc->plane, obj);
9742
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009743 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009744
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009745cleanup_unpin:
9746 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009747cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009748 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009749 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009750 drm_gem_object_unreference(&work->old_fb_obj->base);
9751 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009752 mutex_unlock(&dev->struct_mutex);
9753
Chris Wilson79158102012-05-23 11:13:58 +01009754cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01009755 spin_lock_irqsave(&dev->event_lock, flags);
9756 intel_crtc->unpin_work = NULL;
9757 spin_unlock_irqrestore(&dev->event_lock, flags);
9758
Daniel Vetter87b6b102014-05-15 15:33:46 +02009759 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009760free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009761 kfree(work);
9762
Chris Wilsonf900db42014-02-20 09:26:13 +00009763 if (ret == -EIO) {
9764out_hang:
9765 intel_crtc_wait_for_pending_flips(crtc);
9766 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9767 if (ret == 0 && event)
Daniel Vettera071fa02014-06-18 23:28:09 +02009768 drm_send_vblank_event(dev, pipe, event);
Chris Wilsonf900db42014-02-20 09:26:13 +00009769 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009770 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009771}
9772
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009773static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009774 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9775 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009776};
9777
Daniel Vetter9a935852012-07-05 22:34:27 +02009778/**
9779 * intel_modeset_update_staged_output_state
9780 *
9781 * Updates the staged output configuration state, e.g. after we've read out the
9782 * current hw state.
9783 */
9784static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9785{
Ville Syrjälä76688512014-01-10 11:28:06 +02009786 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009787 struct intel_encoder *encoder;
9788 struct intel_connector *connector;
9789
9790 list_for_each_entry(connector, &dev->mode_config.connector_list,
9791 base.head) {
9792 connector->new_encoder =
9793 to_intel_encoder(connector->base.encoder);
9794 }
9795
9796 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9797 base.head) {
9798 encoder->new_crtc =
9799 to_intel_crtc(encoder->base.crtc);
9800 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009801
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009802 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009803 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009804
9805 if (crtc->new_enabled)
9806 crtc->new_config = &crtc->config;
9807 else
9808 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009809 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009810}
9811
9812/**
9813 * intel_modeset_commit_output_state
9814 *
9815 * This function copies the stage display pipe configuration to the real one.
9816 */
9817static void intel_modeset_commit_output_state(struct drm_device *dev)
9818{
Ville Syrjälä76688512014-01-10 11:28:06 +02009819 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009820 struct intel_encoder *encoder;
9821 struct intel_connector *connector;
9822
9823 list_for_each_entry(connector, &dev->mode_config.connector_list,
9824 base.head) {
9825 connector->base.encoder = &connector->new_encoder->base;
9826 }
9827
9828 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9829 base.head) {
9830 encoder->base.crtc = &encoder->new_crtc->base;
9831 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009832
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009833 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009834 crtc->base.enabled = crtc->new_enabled;
9835 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009836}
9837
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009838static void
Robin Schroereba905b2014-05-18 02:24:50 +02009839connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009840 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009841{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009842 int bpp = pipe_config->pipe_bpp;
9843
9844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9845 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009846 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009847
9848 /* Don't use an invalid EDID bpc value */
9849 if (connector->base.display_info.bpc &&
9850 connector->base.display_info.bpc * 3 < bpp) {
9851 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9852 bpp, connector->base.display_info.bpc*3);
9853 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9854 }
9855
9856 /* Clamp bpp to 8 on screens without EDID 1.4 */
9857 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9858 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9859 bpp);
9860 pipe_config->pipe_bpp = 24;
9861 }
9862}
9863
9864static int
9865compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9866 struct drm_framebuffer *fb,
9867 struct intel_crtc_config *pipe_config)
9868{
9869 struct drm_device *dev = crtc->base.dev;
9870 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009871 int bpp;
9872
Daniel Vetterd42264b2013-03-28 16:38:08 +01009873 switch (fb->pixel_format) {
9874 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009875 bpp = 8*3; /* since we go through a colormap */
9876 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009877 case DRM_FORMAT_XRGB1555:
9878 case DRM_FORMAT_ARGB1555:
9879 /* checked in intel_framebuffer_init already */
9880 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9881 return -EINVAL;
9882 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009883 bpp = 6*3; /* min is 18bpp */
9884 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009885 case DRM_FORMAT_XBGR8888:
9886 case DRM_FORMAT_ABGR8888:
9887 /* checked in intel_framebuffer_init already */
9888 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9889 return -EINVAL;
9890 case DRM_FORMAT_XRGB8888:
9891 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009892 bpp = 8*3;
9893 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009894 case DRM_FORMAT_XRGB2101010:
9895 case DRM_FORMAT_ARGB2101010:
9896 case DRM_FORMAT_XBGR2101010:
9897 case DRM_FORMAT_ABGR2101010:
9898 /* checked in intel_framebuffer_init already */
9899 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01009900 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009901 bpp = 10*3;
9902 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01009903 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009904 default:
9905 DRM_DEBUG_KMS("unsupported depth\n");
9906 return -EINVAL;
9907 }
9908
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009909 pipe_config->pipe_bpp = bpp;
9910
9911 /* Clamp display bpp to EDID value */
9912 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009913 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02009914 if (!connector->new_encoder ||
9915 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009916 continue;
9917
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009918 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009919 }
9920
9921 return bpp;
9922}
9923
Daniel Vetter644db712013-09-19 14:53:58 +02009924static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9925{
9926 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9927 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +01009928 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +02009929 mode->crtc_hdisplay, mode->crtc_hsync_start,
9930 mode->crtc_hsync_end, mode->crtc_htotal,
9931 mode->crtc_vdisplay, mode->crtc_vsync_start,
9932 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9933}
9934
Daniel Vetterc0b03412013-05-28 12:05:54 +02009935static void intel_dump_pipe_config(struct intel_crtc *crtc,
9936 struct intel_crtc_config *pipe_config,
9937 const char *context)
9938{
9939 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9940 context, pipe_name(crtc->pipe));
9941
9942 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9943 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9944 pipe_config->pipe_bpp, pipe_config->dither);
9945 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9946 pipe_config->has_pch_encoder,
9947 pipe_config->fdi_lanes,
9948 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9949 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9950 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009951 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9952 pipe_config->has_dp_encoder,
9953 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9954 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9955 pipe_config->dp_m_n.tu);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009956 DRM_DEBUG_KMS("requested mode:\n");
9957 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9958 DRM_DEBUG_KMS("adjusted mode:\n");
9959 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +02009960 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009961 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009962 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9963 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009964 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9965 pipe_config->gmch_pfit.control,
9966 pipe_config->gmch_pfit.pgm_ratios,
9967 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009968 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +02009969 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009970 pipe_config->pch_pfit.size,
9971 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009972 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03009973 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009974}
9975
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009976static bool encoders_cloneable(const struct intel_encoder *a,
9977 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009978{
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009979 /* masks could be asymmetric, so check both ways */
9980 return a == b || (a->cloneable & (1 << b->type) &&
9981 b->cloneable & (1 << a->type));
9982}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009983
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009984static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9985 struct intel_encoder *encoder)
9986{
9987 struct drm_device *dev = crtc->base.dev;
9988 struct intel_encoder *source_encoder;
9989
9990 list_for_each_entry(source_encoder,
9991 &dev->mode_config.encoder_list, base.head) {
9992 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009993 continue;
9994
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009995 if (!encoders_cloneable(encoder, source_encoder))
9996 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009997 }
9998
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009999 return true;
10000}
10001
10002static bool check_encoder_cloning(struct intel_crtc *crtc)
10003{
10004 struct drm_device *dev = crtc->base.dev;
10005 struct intel_encoder *encoder;
10006
10007 list_for_each_entry(encoder,
10008 &dev->mode_config.encoder_list, base.head) {
10009 if (encoder->new_crtc != crtc)
10010 continue;
10011
10012 if (!check_single_encoder_cloning(crtc, encoder))
10013 return false;
10014 }
10015
10016 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010017}
10018
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010019static struct intel_crtc_config *
10020intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010021 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010022 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +020010023{
10024 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +020010025 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010026 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +010010027 int plane_bpp, ret = -EINVAL;
10028 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020010029
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010030 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010031 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10032 return ERR_PTR(-EINVAL);
10033 }
10034
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010035 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10036 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020010037 return ERR_PTR(-ENOMEM);
10038
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010039 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10040 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010041
Daniel Vettere143a212013-07-04 12:01:15 +020010042 pipe_config->cpu_transcoder =
10043 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010044 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010045
Imre Deak2960bc92013-07-30 13:36:32 +030010046 /*
10047 * Sanitize sync polarity flags based on requested ones. If neither
10048 * positive or negative polarity is requested, treat this as meaning
10049 * negative polarity.
10050 */
10051 if (!(pipe_config->adjusted_mode.flags &
10052 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10053 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10054
10055 if (!(pipe_config->adjusted_mode.flags &
10056 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10057 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10058
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010059 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10060 * plane pixel format and any sink constraints into account. Returns the
10061 * source plane bpp so that dithering can be selected on mismatches
10062 * after encoders and crtc also have had their say. */
10063 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10064 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010065 if (plane_bpp < 0)
10066 goto fail;
10067
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030010068 /*
10069 * Determine the real pipe dimensions. Note that stereo modes can
10070 * increase the actual pipe size due to the frame doubling and
10071 * insertion of additional space for blanks between the frame. This
10072 * is stored in the crtc timings. We use the requested mode to do this
10073 * computation to clearly distinguish it from the adjusted mode, which
10074 * can be changed by the connectors in the below retry loop.
10075 */
10076 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10077 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10078 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10079
Daniel Vettere29c22c2013-02-21 00:00:16 +010010080encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020010081 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020010082 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020010083 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010084
Daniel Vetter135c81b2013-07-21 21:37:09 +020010085 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +010010086 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020010087
Daniel Vetter7758a112012-07-08 19:40:39 +020010088 /* Pass our mode to the connectors and the CRTC to give them a chance to
10089 * adjust it according to limitations or connector properties, and also
10090 * a chance to reject the mode entirely.
10091 */
10092 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10093 base.head) {
10094
10095 if (&encoder->new_crtc->base != crtc)
10096 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +010010097
Daniel Vetterefea6e82013-07-21 21:36:59 +020010098 if (!(encoder->compute_config(encoder, pipe_config))) {
10099 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020010100 goto fail;
10101 }
10102 }
10103
Daniel Vetterff9a6752013-06-01 17:16:21 +020010104 /* Set default port clock if not overwritten by the encoder. Needs to be
10105 * done afterwards in case the encoder adjusts the mode. */
10106 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +010010107 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10108 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010109
Daniel Vettera43f6e02013-06-07 23:10:32 +020010110 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010111 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010112 DRM_DEBUG_KMS("CRTC fixup failed\n");
10113 goto fail;
10114 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010010115
10116 if (ret == RETRY) {
10117 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10118 ret = -EINVAL;
10119 goto fail;
10120 }
10121
10122 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10123 retry = false;
10124 goto encoder_retry;
10125 }
10126
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010127 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10128 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10129 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10130
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010131 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +020010132fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010133 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010134 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +020010135}
10136
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010137/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10138 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10139static void
10140intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10141 unsigned *prepare_pipes, unsigned *disable_pipes)
10142{
10143 struct intel_crtc *intel_crtc;
10144 struct drm_device *dev = crtc->dev;
10145 struct intel_encoder *encoder;
10146 struct intel_connector *connector;
10147 struct drm_crtc *tmp_crtc;
10148
10149 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10150
10151 /* Check which crtcs have changed outputs connected to them, these need
10152 * to be part of the prepare_pipes mask. We don't (yet) support global
10153 * modeset across multiple crtcs, so modeset_pipes will only have one
10154 * bit set at most. */
10155 list_for_each_entry(connector, &dev->mode_config.connector_list,
10156 base.head) {
10157 if (connector->base.encoder == &connector->new_encoder->base)
10158 continue;
10159
10160 if (connector->base.encoder) {
10161 tmp_crtc = connector->base.encoder->crtc;
10162
10163 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10164 }
10165
10166 if (connector->new_encoder)
10167 *prepare_pipes |=
10168 1 << connector->new_encoder->new_crtc->pipe;
10169 }
10170
10171 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10172 base.head) {
10173 if (encoder->base.crtc == &encoder->new_crtc->base)
10174 continue;
10175
10176 if (encoder->base.crtc) {
10177 tmp_crtc = encoder->base.crtc;
10178
10179 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10180 }
10181
10182 if (encoder->new_crtc)
10183 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10184 }
10185
Ville Syrjälä76688512014-01-10 11:28:06 +020010186 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010187 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010188 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010189 continue;
10190
Ville Syrjälä76688512014-01-10 11:28:06 +020010191 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010192 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +020010193 else
10194 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010195 }
10196
10197
10198 /* set_mode is also used to update properties on life display pipes. */
10199 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +020010200 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010201 *prepare_pipes |= 1 << intel_crtc->pipe;
10202
Daniel Vetterb6c51642013-04-12 18:48:43 +020010203 /*
10204 * For simplicity do a full modeset on any pipe where the output routing
10205 * changed. We could be more clever, but that would require us to be
10206 * more careful with calling the relevant encoder->mode_set functions.
10207 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010208 if (*prepare_pipes)
10209 *modeset_pipes = *prepare_pipes;
10210
10211 /* ... and mask these out. */
10212 *modeset_pipes &= ~(*disable_pipes);
10213 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +020010214
10215 /*
10216 * HACK: We don't (yet) fully support global modesets. intel_set_config
10217 * obies this rule, but the modeset restore mode of
10218 * intel_modeset_setup_hw_state does not.
10219 */
10220 *modeset_pipes &= 1 << intel_crtc->pipe;
10221 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +020010222
10223 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10224 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010225}
10226
Daniel Vetterea9d7582012-07-10 10:42:52 +020010227static bool intel_crtc_in_use(struct drm_crtc *crtc)
10228{
10229 struct drm_encoder *encoder;
10230 struct drm_device *dev = crtc->dev;
10231
10232 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10233 if (encoder->crtc == crtc)
10234 return true;
10235
10236 return false;
10237}
10238
10239static void
10240intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10241{
10242 struct intel_encoder *intel_encoder;
10243 struct intel_crtc *intel_crtc;
10244 struct drm_connector *connector;
10245
10246 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10247 base.head) {
10248 if (!intel_encoder->base.crtc)
10249 continue;
10250
10251 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10252
10253 if (prepare_pipes & (1 << intel_crtc->pipe))
10254 intel_encoder->connectors_active = false;
10255 }
10256
10257 intel_modeset_commit_output_state(dev);
10258
Ville Syrjälä76688512014-01-10 11:28:06 +020010259 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010260 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010261 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010262 WARN_ON(intel_crtc->new_config &&
10263 intel_crtc->new_config != &intel_crtc->config);
10264 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010265 }
10266
10267 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10268 if (!connector->encoder || !connector->encoder->crtc)
10269 continue;
10270
10271 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10272
10273 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +020010274 struct drm_property *dpms_property =
10275 dev->mode_config.dpms_property;
10276
Daniel Vetterea9d7582012-07-10 10:42:52 +020010277 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -050010278 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +020010279 dpms_property,
10280 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010281
10282 intel_encoder = to_intel_encoder(connector->encoder);
10283 intel_encoder->connectors_active = true;
10284 }
10285 }
10286
10287}
10288
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010289static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010290{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010291 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010292
10293 if (clock1 == clock2)
10294 return true;
10295
10296 if (!clock1 || !clock2)
10297 return false;
10298
10299 diff = abs(clock1 - clock2);
10300
10301 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10302 return true;
10303
10304 return false;
10305}
10306
Daniel Vetter25c5b262012-07-08 22:08:04 +020010307#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10308 list_for_each_entry((intel_crtc), \
10309 &(dev)->mode_config.crtc_list, \
10310 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +020010311 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020010312
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010313static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010314intel_pipe_config_compare(struct drm_device *dev,
10315 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010316 struct intel_crtc_config *pipe_config)
10317{
Daniel Vetter66e985c2013-06-05 13:34:20 +020010318#define PIPE_CONF_CHECK_X(name) \
10319 if (current_config->name != pipe_config->name) { \
10320 DRM_ERROR("mismatch in " #name " " \
10321 "(expected 0x%08x, found 0x%08x)\n", \
10322 current_config->name, \
10323 pipe_config->name); \
10324 return false; \
10325 }
10326
Daniel Vetter08a24032013-04-19 11:25:34 +020010327#define PIPE_CONF_CHECK_I(name) \
10328 if (current_config->name != pipe_config->name) { \
10329 DRM_ERROR("mismatch in " #name " " \
10330 "(expected %i, found %i)\n", \
10331 current_config->name, \
10332 pipe_config->name); \
10333 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010010334 }
10335
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010336#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10337 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -070010338 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010339 "(expected %i, found %i)\n", \
10340 current_config->name & (mask), \
10341 pipe_config->name & (mask)); \
10342 return false; \
10343 }
10344
Ville Syrjälä5e550652013-09-06 23:29:07 +030010345#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10346 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10347 DRM_ERROR("mismatch in " #name " " \
10348 "(expected %i, found %i)\n", \
10349 current_config->name, \
10350 pipe_config->name); \
10351 return false; \
10352 }
10353
Daniel Vetterbb760062013-06-06 14:55:52 +020010354#define PIPE_CONF_QUIRK(quirk) \
10355 ((current_config->quirks | pipe_config->quirks) & (quirk))
10356
Daniel Vettereccb1402013-05-22 00:50:22 +020010357 PIPE_CONF_CHECK_I(cpu_transcoder);
10358
Daniel Vetter08a24032013-04-19 11:25:34 +020010359 PIPE_CONF_CHECK_I(has_pch_encoder);
10360 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +020010361 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10362 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10363 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10364 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10365 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +020010366
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010367 PIPE_CONF_CHECK_I(has_dp_encoder);
10368 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10369 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10370 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10371 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10372 PIPE_CONF_CHECK_I(dp_m_n.tu);
10373
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010374 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10375 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10376 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10377 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10378 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10379 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10380
10381 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10382 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10383 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10384 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10385 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10386 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10387
Daniel Vetterc93f54c2013-06-27 19:47:19 +020010388 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +020010389 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020010390 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10391 IS_VALLEYVIEW(dev))
10392 PIPE_CONF_CHECK_I(limited_color_range);
Daniel Vetter6c49f242013-06-06 12:45:25 +020010393
Daniel Vetter9ed109a2014-04-24 23:54:52 +020010394 PIPE_CONF_CHECK_I(has_audio);
10395
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010396 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10397 DRM_MODE_FLAG_INTERLACE);
10398
Daniel Vetterbb760062013-06-06 14:55:52 +020010399 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10400 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10401 DRM_MODE_FLAG_PHSYNC);
10402 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10403 DRM_MODE_FLAG_NHSYNC);
10404 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10405 DRM_MODE_FLAG_PVSYNC);
10406 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10407 DRM_MODE_FLAG_NVSYNC);
10408 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010409
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010410 PIPE_CONF_CHECK_I(pipe_src_w);
10411 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010412
Daniel Vetter99535992014-04-13 12:00:33 +020010413 /*
10414 * FIXME: BIOS likes to set up a cloned config with lvds+external
10415 * screen. Since we don't yet re-compute the pipe config when moving
10416 * just the lvds port away to another pipe the sw tracking won't match.
10417 *
10418 * Proper atomic modesets with recomputed global state will fix this.
10419 * Until then just don't check gmch state for inherited modes.
10420 */
10421 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10422 PIPE_CONF_CHECK_I(gmch_pfit.control);
10423 /* pfit ratios are autocomputed by the hw on gen4+ */
10424 if (INTEL_INFO(dev)->gen < 4)
10425 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10426 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10427 }
10428
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010429 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10430 if (current_config->pch_pfit.enabled) {
10431 PIPE_CONF_CHECK_I(pch_pfit.pos);
10432 PIPE_CONF_CHECK_I(pch_pfit.size);
10433 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010434
Jesse Barnese59150d2014-01-07 13:30:45 -080010435 /* BDW+ don't expose a synchronous way to read the state */
10436 if (IS_HASWELL(dev))
10437 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010438
Ville Syrjälä282740f2013-09-04 18:30:03 +030010439 PIPE_CONF_CHECK_I(double_wide);
10440
Daniel Vetter26804af2014-06-25 22:01:55 +030010441 PIPE_CONF_CHECK_X(ddi_pll_sel);
10442
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010443 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010444 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010445 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010446 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10447 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010448 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010449
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010450 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10451 PIPE_CONF_CHECK_I(pipe_bpp);
10452
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010453 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10454 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010455
Daniel Vetter66e985c2013-06-05 13:34:20 +020010456#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010457#undef PIPE_CONF_CHECK_I
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010458#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010459#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010460#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010461
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010462 return true;
10463}
10464
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010465static void
10466check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010467{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010468 struct intel_connector *connector;
10469
10470 list_for_each_entry(connector, &dev->mode_config.connector_list,
10471 base.head) {
10472 /* This also checks the encoder/connector hw state with the
10473 * ->get_hw_state callbacks. */
10474 intel_connector_check_state(connector);
10475
10476 WARN(&connector->new_encoder->base != connector->base.encoder,
10477 "connector's staged encoder doesn't match current encoder\n");
10478 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010479}
10480
10481static void
10482check_encoder_state(struct drm_device *dev)
10483{
10484 struct intel_encoder *encoder;
10485 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010486
10487 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10488 base.head) {
10489 bool enabled = false;
10490 bool active = false;
10491 enum pipe pipe, tracked_pipe;
10492
10493 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10494 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030010495 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010496
10497 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10498 "encoder's stage crtc doesn't match current crtc\n");
10499 WARN(encoder->connectors_active && !encoder->base.crtc,
10500 "encoder's active_connectors set, but no crtc\n");
10501
10502 list_for_each_entry(connector, &dev->mode_config.connector_list,
10503 base.head) {
10504 if (connector->base.encoder != &encoder->base)
10505 continue;
10506 enabled = true;
10507 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10508 active = true;
10509 }
10510 WARN(!!encoder->base.crtc != enabled,
10511 "encoder's enabled state mismatch "
10512 "(expected %i, found %i)\n",
10513 !!encoder->base.crtc, enabled);
10514 WARN(active && !encoder->base.crtc,
10515 "active encoder with no crtc\n");
10516
10517 WARN(encoder->connectors_active != active,
10518 "encoder's computed active state doesn't match tracked active state "
10519 "(expected %i, found %i)\n", active, encoder->connectors_active);
10520
10521 active = encoder->get_hw_state(encoder, &pipe);
10522 WARN(active != encoder->connectors_active,
10523 "encoder's hw state doesn't match sw tracking "
10524 "(expected %i, found %i)\n",
10525 encoder->connectors_active, active);
10526
10527 if (!encoder->base.crtc)
10528 continue;
10529
10530 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10531 WARN(active && pipe != tracked_pipe,
10532 "active encoder's pipe doesn't match"
10533 "(expected %i, found %i)\n",
10534 tracked_pipe, pipe);
10535
10536 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010537}
10538
10539static void
10540check_crtc_state(struct drm_device *dev)
10541{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010542 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010543 struct intel_crtc *crtc;
10544 struct intel_encoder *encoder;
10545 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010546
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010547 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010548 bool enabled = false;
10549 bool active = false;
10550
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010551 memset(&pipe_config, 0, sizeof(pipe_config));
10552
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010553 DRM_DEBUG_KMS("[CRTC:%d]\n",
10554 crtc->base.base.id);
10555
10556 WARN(crtc->active && !crtc->base.enabled,
10557 "active crtc, but not enabled in sw tracking\n");
10558
10559 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10560 base.head) {
10561 if (encoder->base.crtc != &crtc->base)
10562 continue;
10563 enabled = true;
10564 if (encoder->connectors_active)
10565 active = true;
10566 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010567
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010568 WARN(active != crtc->active,
10569 "crtc's computed active state doesn't match tracked active state "
10570 "(expected %i, found %i)\n", active, crtc->active);
10571 WARN(enabled != crtc->base.enabled,
10572 "crtc's computed enabled state doesn't match tracked enabled state "
10573 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10574
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010575 active = dev_priv->display.get_pipe_config(crtc,
10576 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010577
10578 /* hw state is inconsistent with the pipe A quirk */
10579 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10580 active = crtc->active;
10581
Daniel Vetter6c49f242013-06-06 12:45:25 +020010582 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10583 base.head) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010584 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010585 if (encoder->base.crtc != &crtc->base)
10586 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010587 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010588 encoder->get_config(encoder, &pipe_config);
10589 }
10590
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010591 WARN(crtc->active != active,
10592 "crtc active state doesn't match with hw state "
10593 "(expected %i, found %i)\n", crtc->active, active);
10594
Daniel Vetterc0b03412013-05-28 12:05:54 +020010595 if (active &&
10596 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10597 WARN(1, "pipe state doesn't match!\n");
10598 intel_dump_pipe_config(crtc, &pipe_config,
10599 "[hw state]");
10600 intel_dump_pipe_config(crtc, &crtc->config,
10601 "[sw state]");
10602 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010603 }
10604}
10605
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010606static void
10607check_shared_dpll_state(struct drm_device *dev)
10608{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010609 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010610 struct intel_crtc *crtc;
10611 struct intel_dpll_hw_state dpll_hw_state;
10612 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010613
10614 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10615 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10616 int enabled_crtcs = 0, active_crtcs = 0;
10617 bool active;
10618
10619 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10620
10621 DRM_DEBUG_KMS("%s\n", pll->name);
10622
10623 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10624
10625 WARN(pll->active > pll->refcount,
10626 "more active pll users than references: %i vs %i\n",
10627 pll->active, pll->refcount);
10628 WARN(pll->active && !pll->on,
10629 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010630 WARN(pll->on && !pll->active,
10631 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010632 WARN(pll->on != active,
10633 "pll on state mismatch (expected %i, found %i)\n",
10634 pll->on, active);
10635
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010636 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010637 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10638 enabled_crtcs++;
10639 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10640 active_crtcs++;
10641 }
10642 WARN(pll->active != active_crtcs,
10643 "pll active crtcs mismatch (expected %i, found %i)\n",
10644 pll->active, active_crtcs);
10645 WARN(pll->refcount != enabled_crtcs,
10646 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10647 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010648
10649 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10650 sizeof(dpll_hw_state)),
10651 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010652 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010653}
10654
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010655void
10656intel_modeset_check_state(struct drm_device *dev)
10657{
10658 check_connector_state(dev);
10659 check_encoder_state(dev);
10660 check_crtc_state(dev);
10661 check_shared_dpll_state(dev);
10662}
10663
Ville Syrjälä18442d02013-09-13 16:00:08 +030010664void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10665 int dotclock)
10666{
10667 /*
10668 * FDI already provided one idea for the dotclock.
10669 * Yell if the encoder disagrees.
10670 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010671 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010672 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010673 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010674}
10675
Ville Syrjälä80715b22014-05-15 20:23:23 +030010676static void update_scanline_offset(struct intel_crtc *crtc)
10677{
10678 struct drm_device *dev = crtc->base.dev;
10679
10680 /*
10681 * The scanline counter increments at the leading edge of hsync.
10682 *
10683 * On most platforms it starts counting from vtotal-1 on the
10684 * first active line. That means the scanline counter value is
10685 * always one less than what we would expect. Ie. just after
10686 * start of vblank, which also occurs at start of hsync (on the
10687 * last active line), the scanline counter will read vblank_start-1.
10688 *
10689 * On gen2 the scanline counter starts counting from 1 instead
10690 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10691 * to keep the value positive), instead of adding one.
10692 *
10693 * On HSW+ the behaviour of the scanline counter depends on the output
10694 * type. For DP ports it behaves like most other platforms, but on HDMI
10695 * there's an extra 1 line difference. So we need to add two instead of
10696 * one to the value.
10697 */
10698 if (IS_GEN2(dev)) {
10699 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10700 int vtotal;
10701
10702 vtotal = mode->crtc_vtotal;
10703 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10704 vtotal /= 2;
10705
10706 crtc->scanline_offset = vtotal - 1;
10707 } else if (HAS_DDI(dev) &&
10708 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10709 crtc->scanline_offset = 2;
10710 } else
10711 crtc->scanline_offset = 1;
10712}
10713
Daniel Vetterf30da182013-04-11 20:22:50 +020010714static int __intel_set_mode(struct drm_crtc *crtc,
10715 struct drm_display_mode *mode,
10716 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +020010717{
10718 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010719 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010720 struct drm_display_mode *saved_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010721 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010722 struct intel_crtc *intel_crtc;
10723 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010724 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010725
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010726 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010727 if (!saved_mode)
10728 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010729
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010730 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +020010731 &prepare_pipes, &disable_pipes);
10732
Tim Gardner3ac18232012-12-07 07:54:26 -070010733 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010734
Daniel Vetter25c5b262012-07-08 22:08:04 +020010735 /* Hack: Because we don't (yet) support global modeset on multiple
10736 * crtcs, we don't keep track of the new mode for more than one crtc.
10737 * Hence simply check whether any bit is set in modeset_pipes in all the
10738 * pieces of code that are not yet converted to deal with mutliple crtcs
10739 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010740 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010741 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010742 if (IS_ERR(pipe_config)) {
10743 ret = PTR_ERR(pipe_config);
10744 pipe_config = NULL;
10745
Tim Gardner3ac18232012-12-07 07:54:26 -070010746 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010747 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020010748 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10749 "[modeset]");
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010750 to_intel_crtc(crtc)->new_config = pipe_config;
Daniel Vettera6778b32012-07-02 09:56:42 +020010751 }
10752
Jesse Barnes30a970c2013-11-04 13:48:12 -080010753 /*
10754 * See if the config requires any additional preparation, e.g.
10755 * to adjust global state with pipes off. We need to do this
10756 * here so we can get the modeset_pipe updated config for the new
10757 * mode set on this crtc. For other crtcs we need to use the
10758 * adjusted_mode bits in the crtc directly.
10759 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010760 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010761 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010762
Ville Syrjäläc164f832013-11-05 22:34:12 +020010763 /* may have added more to prepare_pipes than we should */
10764 prepare_pipes &= ~disable_pipes;
10765 }
10766
Daniel Vetter460da9162013-03-27 00:44:51 +010010767 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10768 intel_crtc_disable(&intel_crtc->base);
10769
Daniel Vetterea9d7582012-07-10 10:42:52 +020010770 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10771 if (intel_crtc->base.enabled)
10772 dev_priv->display.crtc_disable(&intel_crtc->base);
10773 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010774
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010775 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10776 * to set it here already despite that we pass it down the callchain.
10777 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010778 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010779 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010780 /* mode_set/enable/disable functions rely on a correct pipe
10781 * config. */
10782 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010783 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010784
10785 /*
10786 * Calculate and store various constants which
10787 * are later needed by vblank and swap-completion
10788 * timestamping. They are derived from true hwmode.
10789 */
10790 drm_calc_timestamping_constants(crtc,
10791 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010792 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010793
Daniel Vetterea9d7582012-07-10 10:42:52 +020010794 /* Only after disabling all output pipelines that will be changed can we
10795 * update the the output configuration. */
10796 intel_modeset_update_state(dev, prepare_pipes);
10797
Daniel Vetter47fab732012-10-26 10:58:18 +020010798 if (dev_priv->display.modeset_global_resources)
10799 dev_priv->display.modeset_global_resources(dev);
10800
Daniel Vettera6778b32012-07-02 09:56:42 +020010801 /* Set up the DPLL and any encoders state that needs to adjust or depend
10802 * on the DPLL.
10803 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010804 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070010805 struct drm_framebuffer *old_fb = crtc->primary->fb;
10806 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10807 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Daniel Vetter4c107942014-04-24 23:55:05 +020010808
10809 mutex_lock(&dev->struct_mutex);
10810 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vettera071fa02014-06-18 23:28:09 +020010811 obj,
Daniel Vetter4c107942014-04-24 23:55:05 +020010812 NULL);
10813 if (ret != 0) {
10814 DRM_ERROR("pin & fence failed\n");
10815 mutex_unlock(&dev->struct_mutex);
10816 goto done;
10817 }
Matt Roper2ff8fde2014-07-08 07:50:07 -070010818 if (old_fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020010819 intel_unpin_fb_obj(old_obj);
Daniel Vettera071fa02014-06-18 23:28:09 +020010820 i915_gem_track_fb(old_obj, obj,
10821 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Daniel Vetter4c107942014-04-24 23:55:05 +020010822 mutex_unlock(&dev->struct_mutex);
10823
10824 crtc->primary->fb = fb;
10825 crtc->x = x;
10826 crtc->y = y;
10827
Daniel Vetter4271b752014-04-24 23:55:00 +020010828 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10829 x, y, fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010830 if (ret)
10831 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +020010832 }
10833
10834 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030010835 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10836 update_scanline_offset(intel_crtc);
10837
Daniel Vetter25c5b262012-07-08 22:08:04 +020010838 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030010839 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010840
Daniel Vettera6778b32012-07-02 09:56:42 +020010841 /* FIXME: add subpixel order */
10842done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010843 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070010844 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010845
Tim Gardner3ac18232012-12-07 07:54:26 -070010846out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010847 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070010848 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020010849 return ret;
10850}
10851
Damien Lespiaue7457a92013-08-08 22:28:59 +010010852static int intel_set_mode(struct drm_crtc *crtc,
10853 struct drm_display_mode *mode,
10854 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020010855{
10856 int ret;
10857
10858 ret = __intel_set_mode(crtc, mode, x, y, fb);
10859
10860 if (ret == 0)
10861 intel_modeset_check_state(crtc->dev);
10862
10863 return ret;
10864}
10865
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010866void intel_crtc_restore_mode(struct drm_crtc *crtc)
10867{
Matt Roperf4510a22014-04-01 15:22:40 -070010868 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010869}
10870
Daniel Vetter25c5b262012-07-08 22:08:04 +020010871#undef for_each_intel_crtc_masked
10872
Daniel Vetterd9e55602012-07-04 22:16:09 +020010873static void intel_set_config_free(struct intel_set_config *config)
10874{
10875 if (!config)
10876 return;
10877
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010878 kfree(config->save_connector_encoders);
10879 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020010880 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020010881 kfree(config);
10882}
10883
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010884static int intel_set_config_save_state(struct drm_device *dev,
10885 struct intel_set_config *config)
10886{
Ville Syrjälä76688512014-01-10 11:28:06 +020010887 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010888 struct drm_encoder *encoder;
10889 struct drm_connector *connector;
10890 int count;
10891
Ville Syrjälä76688512014-01-10 11:28:06 +020010892 config->save_crtc_enabled =
10893 kcalloc(dev->mode_config.num_crtc,
10894 sizeof(bool), GFP_KERNEL);
10895 if (!config->save_crtc_enabled)
10896 return -ENOMEM;
10897
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010898 config->save_encoder_crtcs =
10899 kcalloc(dev->mode_config.num_encoder,
10900 sizeof(struct drm_crtc *), GFP_KERNEL);
10901 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010902 return -ENOMEM;
10903
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010904 config->save_connector_encoders =
10905 kcalloc(dev->mode_config.num_connector,
10906 sizeof(struct drm_encoder *), GFP_KERNEL);
10907 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010908 return -ENOMEM;
10909
10910 /* Copy data. Note that driver private data is not affected.
10911 * Should anything bad happen only the expected state is
10912 * restored, not the drivers personal bookkeeping.
10913 */
10914 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010010915 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010916 config->save_crtc_enabled[count++] = crtc->enabled;
10917 }
10918
10919 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010920 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010921 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010922 }
10923
10924 count = 0;
10925 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010926 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010927 }
10928
10929 return 0;
10930}
10931
10932static void intel_set_config_restore_state(struct drm_device *dev,
10933 struct intel_set_config *config)
10934{
Ville Syrjälä76688512014-01-10 11:28:06 +020010935 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020010936 struct intel_encoder *encoder;
10937 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010938 int count;
10939
10940 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010941 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010942 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010943
10944 if (crtc->new_enabled)
10945 crtc->new_config = &crtc->config;
10946 else
10947 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020010948 }
10949
10950 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010951 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10952 encoder->new_crtc =
10953 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010954 }
10955
10956 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010957 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10958 connector->new_encoder =
10959 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010960 }
10961}
10962
Imre Deake3de42b2013-05-03 19:44:07 +020010963static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010010964is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020010965{
10966 int i;
10967
Chris Wilson2e57f472013-07-17 12:14:40 +010010968 if (set->num_connectors == 0)
10969 return false;
10970
10971 if (WARN_ON(set->connectors == NULL))
10972 return false;
10973
10974 for (i = 0; i < set->num_connectors; i++)
10975 if (set->connectors[i]->encoder &&
10976 set->connectors[i]->encoder->crtc == set->crtc &&
10977 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020010978 return true;
10979
10980 return false;
10981}
10982
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010983static void
10984intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10985 struct intel_set_config *config)
10986{
10987
10988 /* We should be able to check here if the fb has the same properties
10989 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010010990 if (is_crtc_connector_off(set)) {
10991 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070010992 } else if (set->crtc->primary->fb != set->fb) {
Matt Roper3b150f02014-05-29 08:06:53 -070010993 /*
10994 * If we have no fb, we can only flip as long as the crtc is
10995 * active, otherwise we need a full mode set. The crtc may
10996 * be active if we've only disabled the primary plane, or
10997 * in fastboot situations.
10998 */
Matt Roperf4510a22014-04-01 15:22:40 -070010999 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011000 struct intel_crtc *intel_crtc =
11001 to_intel_crtc(set->crtc);
11002
Matt Roper3b150f02014-05-29 08:06:53 -070011003 if (intel_crtc->active) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011004 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11005 config->fb_changed = true;
11006 } else {
11007 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11008 config->mode_changed = true;
11009 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011010 } else if (set->fb == NULL) {
11011 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010011012 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070011013 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011014 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011015 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011016 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011017 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011018 }
11019
Daniel Vetter835c5872012-07-10 18:11:08 +020011020 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011021 config->fb_changed = true;
11022
11023 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11024 DRM_DEBUG_KMS("modes are different, full mode set\n");
11025 drm_mode_debug_printmodeline(&set->crtc->mode);
11026 drm_mode_debug_printmodeline(set->mode);
11027 config->mode_changed = true;
11028 }
Chris Wilsona1d95702013-08-13 18:48:47 +010011029
11030 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11031 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011032}
11033
Daniel Vetter2e431052012-07-04 22:42:15 +020011034static int
Daniel Vetter9a935852012-07-05 22:34:27 +020011035intel_modeset_stage_output_state(struct drm_device *dev,
11036 struct drm_mode_set *set,
11037 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020011038{
Daniel Vetter9a935852012-07-05 22:34:27 +020011039 struct intel_connector *connector;
11040 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020011041 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030011042 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020011043
Damien Lespiau9abdda72013-02-13 13:29:23 +000011044 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020011045 * of connectors. For paranoia, double-check this. */
11046 WARN_ON(!set->fb && (set->num_connectors != 0));
11047 WARN_ON(set->fb && (set->num_connectors == 0));
11048
Daniel Vetter9a935852012-07-05 22:34:27 +020011049 list_for_each_entry(connector, &dev->mode_config.connector_list,
11050 base.head) {
11051 /* Otherwise traverse passed in connector list and get encoders
11052 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020011053 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011054 if (set->connectors[ro] == &connector->base) {
11055 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +020011056 break;
11057 }
11058 }
11059
Daniel Vetter9a935852012-07-05 22:34:27 +020011060 /* If we disable the crtc, disable all its connectors. Also, if
11061 * the connector is on the changing crtc but not on the new
11062 * connector list, disable it. */
11063 if ((!set->fb || ro == set->num_connectors) &&
11064 connector->base.encoder &&
11065 connector->base.encoder->crtc == set->crtc) {
11066 connector->new_encoder = NULL;
11067
11068 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11069 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011070 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020011071 }
11072
11073
11074 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011075 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011076 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011077 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011078 }
11079 /* connector->new_encoder is now updated for all connectors. */
11080
11081 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020011082 list_for_each_entry(connector, &dev->mode_config.connector_list,
11083 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011084 struct drm_crtc *new_crtc;
11085
Daniel Vetter9a935852012-07-05 22:34:27 +020011086 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020011087 continue;
11088
Daniel Vetter9a935852012-07-05 22:34:27 +020011089 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020011090
11091 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011092 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020011093 new_crtc = set->crtc;
11094 }
11095
11096 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010011097 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11098 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011099 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020011100 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011101 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
11102
11103 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11104 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011105 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020011106 new_crtc->base.id);
11107 }
11108
11109 /* Check for any encoders that needs to be disabled. */
11110 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11111 base.head) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011112 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011113 list_for_each_entry(connector,
11114 &dev->mode_config.connector_list,
11115 base.head) {
11116 if (connector->new_encoder == encoder) {
11117 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011118 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020011119 }
11120 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011121
11122 if (num_connectors == 0)
11123 encoder->new_crtc = NULL;
11124 else if (num_connectors > 1)
11125 return -EINVAL;
11126
Daniel Vetter9a935852012-07-05 22:34:27 +020011127 /* Only now check for crtc changes so we don't miss encoders
11128 * that will be disabled. */
11129 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011130 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011131 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011132 }
11133 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011134 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +020011135
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011136 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011137 crtc->new_enabled = false;
11138
11139 list_for_each_entry(encoder,
11140 &dev->mode_config.encoder_list,
11141 base.head) {
11142 if (encoder->new_crtc == crtc) {
11143 crtc->new_enabled = true;
11144 break;
11145 }
11146 }
11147
11148 if (crtc->new_enabled != crtc->base.enabled) {
11149 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11150 crtc->new_enabled ? "en" : "dis");
11151 config->mode_changed = true;
11152 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011153
11154 if (crtc->new_enabled)
11155 crtc->new_config = &crtc->config;
11156 else
11157 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011158 }
11159
Daniel Vetter2e431052012-07-04 22:42:15 +020011160 return 0;
11161}
11162
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011163static void disable_crtc_nofb(struct intel_crtc *crtc)
11164{
11165 struct drm_device *dev = crtc->base.dev;
11166 struct intel_encoder *encoder;
11167 struct intel_connector *connector;
11168
11169 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11170 pipe_name(crtc->pipe));
11171
11172 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11173 if (connector->new_encoder &&
11174 connector->new_encoder->new_crtc == crtc)
11175 connector->new_encoder = NULL;
11176 }
11177
11178 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11179 if (encoder->new_crtc == crtc)
11180 encoder->new_crtc = NULL;
11181 }
11182
11183 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011184 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011185}
11186
Daniel Vetter2e431052012-07-04 22:42:15 +020011187static int intel_crtc_set_config(struct drm_mode_set *set)
11188{
11189 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020011190 struct drm_mode_set save_set;
11191 struct intel_set_config *config;
11192 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020011193
Daniel Vetter8d3e3752012-07-05 16:09:09 +020011194 BUG_ON(!set);
11195 BUG_ON(!set->crtc);
11196 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020011197
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010011198 /* Enforce sane interface api - has been abused by the fb helper. */
11199 BUG_ON(!set->mode && set->fb);
11200 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020011201
Daniel Vetter2e431052012-07-04 22:42:15 +020011202 if (set->fb) {
11203 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11204 set->crtc->base.id, set->fb->base.id,
11205 (int)set->num_connectors, set->x, set->y);
11206 } else {
11207 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020011208 }
11209
11210 dev = set->crtc->dev;
11211
11212 ret = -ENOMEM;
11213 config = kzalloc(sizeof(*config), GFP_KERNEL);
11214 if (!config)
11215 goto out_config;
11216
11217 ret = intel_set_config_save_state(dev, config);
11218 if (ret)
11219 goto out_config;
11220
11221 save_set.crtc = set->crtc;
11222 save_set.mode = &set->crtc->mode;
11223 save_set.x = set->crtc->x;
11224 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070011225 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020011226
11227 /* Compute whether we need a full modeset, only an fb base update or no
11228 * change at all. In the future we might also check whether only the
11229 * mode changed, e.g. for LVDS where we only change the panel fitter in
11230 * such cases. */
11231 intel_set_config_compute_mode_changes(set, config);
11232
Daniel Vetter9a935852012-07-05 22:34:27 +020011233 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020011234 if (ret)
11235 goto fail;
11236
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011237 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011238 ret = intel_set_mode(set->crtc, set->mode,
11239 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011240 } else if (config->fb_changed) {
Matt Roper3b150f02014-05-29 08:06:53 -070011241 struct drm_i915_private *dev_priv = dev->dev_private;
11242 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11243
Ville Syrjälä4878cae2013-02-18 19:08:48 +020011244 intel_crtc_wait_for_pending_flips(set->crtc);
11245
Daniel Vetter4f660f42012-07-02 09:47:37 +020011246 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020011247 set->x, set->y, set->fb);
Matt Roper3b150f02014-05-29 08:06:53 -070011248
11249 /*
11250 * We need to make sure the primary plane is re-enabled if it
11251 * has previously been turned off.
11252 */
11253 if (!intel_crtc->primary_enabled && ret == 0) {
11254 WARN_ON(!intel_crtc->active);
11255 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11256 intel_crtc->pipe);
11257 }
11258
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011259 /*
11260 * In the fastboot case this may be our only check of the
11261 * state after boot. It would be better to only do it on
11262 * the first update, but we don't have a nice way of doing that
11263 * (and really, set_config isn't used much for high freq page
11264 * flipping, so increasing its cost here shouldn't be a big
11265 * deal).
11266 */
Jani Nikulad330a952014-01-21 11:24:25 +020011267 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011268 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020011269 }
11270
Chris Wilson2d05eae2013-05-03 17:36:25 +010011271 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020011272 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11273 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020011274fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010011275 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011276
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011277 /*
11278 * HACK: if the pipe was on, but we didn't have a framebuffer,
11279 * force the pipe off to avoid oopsing in the modeset code
11280 * due to fb==NULL. This should only happen during boot since
11281 * we don't yet reconstruct the FB from the hardware state.
11282 */
11283 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11284 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11285
Chris Wilson2d05eae2013-05-03 17:36:25 +010011286 /* Try to restore the config */
11287 if (config->mode_changed &&
11288 intel_set_mode(save_set.crtc, save_set.mode,
11289 save_set.x, save_set.y, save_set.fb))
11290 DRM_ERROR("failed to restore config after modeset failure\n");
11291 }
Daniel Vetter50f56112012-07-02 09:35:43 +020011292
Daniel Vetterd9e55602012-07-04 22:16:09 +020011293out_config:
11294 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011295 return ret;
11296}
11297
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011298static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011299 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020011300 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011301 .destroy = intel_crtc_destroy,
11302 .page_flip = intel_crtc_page_flip,
11303};
11304
Daniel Vetter53589012013-06-05 13:34:16 +020011305static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11306 struct intel_shared_dpll *pll,
11307 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011308{
Daniel Vetter53589012013-06-05 13:34:16 +020011309 uint32_t val;
11310
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030011311 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11312 return false;
11313
Daniel Vetter53589012013-06-05 13:34:16 +020011314 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020011315 hw_state->dpll = val;
11316 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11317 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020011318
11319 return val & DPLL_VCO_ENABLE;
11320}
11321
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011322static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11323 struct intel_shared_dpll *pll)
11324{
11325 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11326 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11327}
11328
Daniel Vettere7b903d2013-06-05 13:34:14 +020011329static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11330 struct intel_shared_dpll *pll)
11331{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011332 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020011333 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020011334
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011335 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11336
11337 /* Wait for the clocks to stabilize. */
11338 POSTING_READ(PCH_DPLL(pll->id));
11339 udelay(150);
11340
11341 /* The pixel multiplier can only be updated once the
11342 * DPLL is enabled and the clocks are stable.
11343 *
11344 * So write it again.
11345 */
11346 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11347 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011348 udelay(200);
11349}
11350
11351static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11352 struct intel_shared_dpll *pll)
11353{
11354 struct drm_device *dev = dev_priv->dev;
11355 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011356
11357 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011358 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020011359 if (intel_crtc_to_shared_dpll(crtc) == pll)
11360 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11361 }
11362
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011363 I915_WRITE(PCH_DPLL(pll->id), 0);
11364 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011365 udelay(200);
11366}
11367
Daniel Vetter46edb022013-06-05 13:34:12 +020011368static char *ibx_pch_dpll_names[] = {
11369 "PCH DPLL A",
11370 "PCH DPLL B",
11371};
11372
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011373static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011374{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011375 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011376 int i;
11377
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011378 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011379
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020011381 dev_priv->shared_dplls[i].id = i;
11382 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011383 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011384 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11385 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020011386 dev_priv->shared_dplls[i].get_hw_state =
11387 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011388 }
11389}
11390
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011391static void intel_shared_dpll_init(struct drm_device *dev)
11392{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011393 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011394
Daniel Vetter9cd86932014-06-25 22:01:57 +030011395 if (HAS_DDI(dev))
11396 intel_ddi_pll_init(dev);
11397 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011398 ibx_pch_dpll_init(dev);
11399 else
11400 dev_priv->num_shared_dpll = 0;
11401
11402 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011403}
11404
Matt Roper465c1202014-05-29 08:06:54 -070011405static int
11406intel_primary_plane_disable(struct drm_plane *plane)
11407{
11408 struct drm_device *dev = plane->dev;
11409 struct drm_i915_private *dev_priv = dev->dev_private;
11410 struct intel_plane *intel_plane = to_intel_plane(plane);
11411 struct intel_crtc *intel_crtc;
11412
11413 if (!plane->fb)
11414 return 0;
11415
11416 BUG_ON(!plane->crtc);
11417
11418 intel_crtc = to_intel_crtc(plane->crtc);
11419
11420 /*
11421 * Even though we checked plane->fb above, it's still possible that
11422 * the primary plane has been implicitly disabled because the crtc
11423 * coordinates given weren't visible, or because we detected
11424 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11425 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11426 * In either case, we need to unpin the FB and let the fb pointer get
11427 * updated, but otherwise we don't need to touch the hardware.
11428 */
11429 if (!intel_crtc->primary_enabled)
11430 goto disable_unpin;
11431
11432 intel_crtc_wait_for_pending_flips(plane->crtc);
11433 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11434 intel_plane->pipe);
Matt Roper465c1202014-05-29 08:06:54 -070011435disable_unpin:
Matt Roper4c345742014-07-09 16:22:10 -070011436 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011437 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
Daniel Vettera071fa02014-06-18 23:28:09 +020011438 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper2ff8fde2014-07-08 07:50:07 -070011439 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
Matt Roper4c345742014-07-09 16:22:10 -070011440 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011441 plane->fb = NULL;
11442
11443 return 0;
11444}
11445
11446static int
11447intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11448 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11449 unsigned int crtc_w, unsigned int crtc_h,
11450 uint32_t src_x, uint32_t src_y,
11451 uint32_t src_w, uint32_t src_h)
11452{
11453 struct drm_device *dev = crtc->dev;
11454 struct drm_i915_private *dev_priv = dev->dev_private;
11455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11456 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011457 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11458 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
Matt Roper465c1202014-05-29 08:06:54 -070011459 struct drm_rect dest = {
11460 /* integer pixels */
11461 .x1 = crtc_x,
11462 .y1 = crtc_y,
11463 .x2 = crtc_x + crtc_w,
11464 .y2 = crtc_y + crtc_h,
11465 };
11466 struct drm_rect src = {
11467 /* 16.16 fixed point */
11468 .x1 = src_x,
11469 .y1 = src_y,
11470 .x2 = src_x + src_w,
11471 .y2 = src_y + src_h,
11472 };
11473 const struct drm_rect clip = {
11474 /* integer pixels */
11475 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11476 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11477 };
11478 bool visible;
11479 int ret;
11480
11481 ret = drm_plane_helper_check_update(plane, crtc, fb,
11482 &src, &dest, &clip,
11483 DRM_PLANE_HELPER_NO_SCALING,
11484 DRM_PLANE_HELPER_NO_SCALING,
11485 false, true, &visible);
11486
11487 if (ret)
11488 return ret;
11489
11490 /*
11491 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11492 * updating the fb pointer, and returning without touching the
11493 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11494 * turn on the display with all planes setup as desired.
11495 */
11496 if (!crtc->enabled) {
Matt Roper4c345742014-07-09 16:22:10 -070011497 mutex_lock(&dev->struct_mutex);
11498
Matt Roper465c1202014-05-29 08:06:54 -070011499 /*
11500 * If we already called setplane while the crtc was disabled,
11501 * we may have an fb pinned; unpin it.
11502 */
11503 if (plane->fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011504 intel_unpin_fb_obj(old_obj);
11505
11506 i915_gem_track_fb(old_obj, obj,
11507 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper465c1202014-05-29 08:06:54 -070011508
11509 /* Pin and return without programming hardware */
Matt Roper4c345742014-07-09 16:22:10 -070011510 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11511 mutex_unlock(&dev->struct_mutex);
11512
11513 return ret;
Matt Roper465c1202014-05-29 08:06:54 -070011514 }
11515
11516 intel_crtc_wait_for_pending_flips(crtc);
11517
11518 /*
11519 * If clipping results in a non-visible primary plane, we'll disable
11520 * the primary plane. Note that this is a bit different than what
11521 * happens if userspace explicitly disables the plane by passing fb=0
11522 * because plane->fb still gets set and pinned.
11523 */
11524 if (!visible) {
Matt Roper4c345742014-07-09 16:22:10 -070011525 mutex_lock(&dev->struct_mutex);
11526
Matt Roper465c1202014-05-29 08:06:54 -070011527 /*
11528 * Try to pin the new fb first so that we can bail out if we
11529 * fail.
11530 */
11531 if (plane->fb != fb) {
Daniel Vettera071fa02014-06-18 23:28:09 +020011532 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
Matt Roper4c345742014-07-09 16:22:10 -070011533 if (ret) {
11534 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011535 return ret;
Matt Roper4c345742014-07-09 16:22:10 -070011536 }
Matt Roper465c1202014-05-29 08:06:54 -070011537 }
11538
Daniel Vettera071fa02014-06-18 23:28:09 +020011539 i915_gem_track_fb(old_obj, obj,
11540 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11541
Matt Roper465c1202014-05-29 08:06:54 -070011542 if (intel_crtc->primary_enabled)
11543 intel_disable_primary_hw_plane(dev_priv,
11544 intel_plane->plane,
11545 intel_plane->pipe);
11546
11547
11548 if (plane->fb != fb)
11549 if (plane->fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011550 intel_unpin_fb_obj(old_obj);
Matt Roper465c1202014-05-29 08:06:54 -070011551
Matt Roper4c345742014-07-09 16:22:10 -070011552 mutex_unlock(&dev->struct_mutex);
11553
Matt Roper465c1202014-05-29 08:06:54 -070011554 return 0;
11555 }
11556
11557 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11558 if (ret)
11559 return ret;
11560
11561 if (!intel_crtc->primary_enabled)
11562 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11563 intel_crtc->pipe);
11564
11565 return 0;
11566}
11567
Matt Roper3d7d6512014-06-10 08:28:13 -070011568/* Common destruction function for both primary and cursor planes */
11569static void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070011570{
11571 struct intel_plane *intel_plane = to_intel_plane(plane);
11572 drm_plane_cleanup(plane);
11573 kfree(intel_plane);
11574}
11575
11576static const struct drm_plane_funcs intel_primary_plane_funcs = {
11577 .update_plane = intel_primary_plane_setplane,
11578 .disable_plane = intel_primary_plane_disable,
Matt Roper3d7d6512014-06-10 08:28:13 -070011579 .destroy = intel_plane_destroy,
Matt Roper465c1202014-05-29 08:06:54 -070011580};
11581
11582static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11583 int pipe)
11584{
11585 struct intel_plane *primary;
11586 const uint32_t *intel_primary_formats;
11587 int num_formats;
11588
11589 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11590 if (primary == NULL)
11591 return NULL;
11592
11593 primary->can_scale = false;
11594 primary->max_downscale = 1;
11595 primary->pipe = pipe;
11596 primary->plane = pipe;
11597 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11598 primary->plane = !pipe;
11599
11600 if (INTEL_INFO(dev)->gen <= 3) {
11601 intel_primary_formats = intel_primary_formats_gen2;
11602 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11603 } else {
11604 intel_primary_formats = intel_primary_formats_gen4;
11605 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11606 }
11607
11608 drm_universal_plane_init(dev, &primary->base, 0,
11609 &intel_primary_plane_funcs,
11610 intel_primary_formats, num_formats,
11611 DRM_PLANE_TYPE_PRIMARY);
11612 return &primary->base;
11613}
11614
Matt Roper3d7d6512014-06-10 08:28:13 -070011615static int
11616intel_cursor_plane_disable(struct drm_plane *plane)
11617{
11618 if (!plane->fb)
11619 return 0;
11620
11621 BUG_ON(!plane->crtc);
11622
11623 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11624}
11625
11626static int
11627intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11628 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11629 unsigned int crtc_w, unsigned int crtc_h,
11630 uint32_t src_x, uint32_t src_y,
11631 uint32_t src_w, uint32_t src_h)
11632{
11633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11634 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11635 struct drm_i915_gem_object *obj = intel_fb->obj;
11636 struct drm_rect dest = {
11637 /* integer pixels */
11638 .x1 = crtc_x,
11639 .y1 = crtc_y,
11640 .x2 = crtc_x + crtc_w,
11641 .y2 = crtc_y + crtc_h,
11642 };
11643 struct drm_rect src = {
11644 /* 16.16 fixed point */
11645 .x1 = src_x,
11646 .y1 = src_y,
11647 .x2 = src_x + src_w,
11648 .y2 = src_y + src_h,
11649 };
11650 const struct drm_rect clip = {
11651 /* integer pixels */
11652 .x2 = intel_crtc->config.pipe_src_w,
11653 .y2 = intel_crtc->config.pipe_src_h,
11654 };
11655 bool visible;
11656 int ret;
11657
11658 ret = drm_plane_helper_check_update(plane, crtc, fb,
11659 &src, &dest, &clip,
11660 DRM_PLANE_HELPER_NO_SCALING,
11661 DRM_PLANE_HELPER_NO_SCALING,
11662 true, true, &visible);
11663 if (ret)
11664 return ret;
11665
11666 crtc->cursor_x = crtc_x;
11667 crtc->cursor_y = crtc_y;
11668 if (fb != crtc->cursor->fb) {
11669 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11670 } else {
11671 intel_crtc_update_cursor(crtc, visible);
11672 return 0;
11673 }
11674}
11675static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11676 .update_plane = intel_cursor_plane_update,
11677 .disable_plane = intel_cursor_plane_disable,
11678 .destroy = intel_plane_destroy,
11679};
11680
11681static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11682 int pipe)
11683{
11684 struct intel_plane *cursor;
11685
11686 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11687 if (cursor == NULL)
11688 return NULL;
11689
11690 cursor->can_scale = false;
11691 cursor->max_downscale = 1;
11692 cursor->pipe = pipe;
11693 cursor->plane = pipe;
11694
11695 drm_universal_plane_init(dev, &cursor->base, 0,
11696 &intel_cursor_plane_funcs,
11697 intel_cursor_formats,
11698 ARRAY_SIZE(intel_cursor_formats),
11699 DRM_PLANE_TYPE_CURSOR);
11700 return &cursor->base;
11701}
11702
Hannes Ederb358d0a2008-12-18 21:18:47 +010011703static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080011704{
Jani Nikulafbee40d2014-03-31 14:27:18 +030011705 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080011706 struct intel_crtc *intel_crtc;
Matt Roper3d7d6512014-06-10 08:28:13 -070011707 struct drm_plane *primary = NULL;
11708 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070011709 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080011710
Daniel Vetter955382f2013-09-19 14:05:45 +020011711 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080011712 if (intel_crtc == NULL)
11713 return;
11714
Matt Roper465c1202014-05-29 08:06:54 -070011715 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011716 if (!primary)
11717 goto fail;
11718
11719 cursor = intel_cursor_plane_create(dev, pipe);
11720 if (!cursor)
11721 goto fail;
11722
Matt Roper465c1202014-05-29 08:06:54 -070011723 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070011724 cursor, &intel_crtc_funcs);
11725 if (ret)
11726 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011727
11728 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080011729 for (i = 0; i < 256; i++) {
11730 intel_crtc->lut_r[i] = i;
11731 intel_crtc->lut_g[i] = i;
11732 intel_crtc->lut_b[i] = i;
11733 }
11734
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011735 /*
11736 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020011737 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011738 */
Jesse Barnes80824002009-09-10 15:28:06 -070011739 intel_crtc->pipe = pipe;
11740 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010011741 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080011742 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010011743 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070011744 }
11745
Chris Wilson4b0e3332014-05-30 16:35:26 +030011746 intel_crtc->cursor_base = ~0;
11747 intel_crtc->cursor_cntl = ~0;
11748
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030011749 init_waitqueue_head(&intel_crtc->vbl_wait);
11750
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080011751 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11752 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11753 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11754 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11755
Jesse Barnes79e53942008-11-07 14:24:08 -080011756 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020011757
11758 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011759 return;
11760
11761fail:
11762 if (primary)
11763 drm_plane_cleanup(primary);
11764 if (cursor)
11765 drm_plane_cleanup(cursor);
11766 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080011767}
11768
Jesse Barnes752aa882013-10-31 18:55:49 +020011769enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11770{
11771 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011772 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020011773
Rob Clark51fd3712013-11-19 12:10:12 -050011774 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020011775
11776 if (!encoder)
11777 return INVALID_PIPE;
11778
11779 return to_intel_crtc(encoder->crtc)->pipe;
11780}
11781
Carl Worth08d7b3d2009-04-29 14:43:54 -070011782int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000011783 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070011784{
Carl Worth08d7b3d2009-04-29 14:43:54 -070011785 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +020011786 struct drm_mode_object *drmmode_obj;
11787 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011788
Daniel Vetter1cff8f62012-04-24 09:55:08 +020011789 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11790 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011791
Daniel Vetterc05422d2009-08-11 16:05:30 +020011792 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11793 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -070011794
Daniel Vetterc05422d2009-08-11 16:05:30 +020011795 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070011796 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030011797 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011798 }
11799
Daniel Vetterc05422d2009-08-11 16:05:30 +020011800 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11801 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011802
Daniel Vetterc05422d2009-08-11 16:05:30 +020011803 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011804}
11805
Daniel Vetter66a92782012-07-12 20:08:18 +020011806static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080011807{
Daniel Vetter66a92782012-07-12 20:08:18 +020011808 struct drm_device *dev = encoder->base.dev;
11809 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080011810 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080011811 int entry = 0;
11812
Daniel Vetter66a92782012-07-12 20:08:18 +020011813 list_for_each_entry(source_encoder,
11814 &dev->mode_config.encoder_list, base.head) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011815 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020011816 index_mask |= (1 << entry);
11817
Jesse Barnes79e53942008-11-07 14:24:08 -080011818 entry++;
11819 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010011820
Jesse Barnes79e53942008-11-07 14:24:08 -080011821 return index_mask;
11822}
11823
Chris Wilson4d302442010-12-14 19:21:29 +000011824static bool has_edp_a(struct drm_device *dev)
11825{
11826 struct drm_i915_private *dev_priv = dev->dev_private;
11827
11828 if (!IS_MOBILE(dev))
11829 return false;
11830
11831 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11832 return false;
11833
Damien Lespiaue3589902014-02-07 19:12:50 +000011834 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000011835 return false;
11836
11837 return true;
11838}
11839
Damien Lespiauba0fbca2014-01-08 14:18:23 +000011840const char *intel_output_name(int output)
11841{
11842 static const char *names[] = {
11843 [INTEL_OUTPUT_UNUSED] = "Unused",
11844 [INTEL_OUTPUT_ANALOG] = "Analog",
11845 [INTEL_OUTPUT_DVO] = "DVO",
11846 [INTEL_OUTPUT_SDVO] = "SDVO",
11847 [INTEL_OUTPUT_LVDS] = "LVDS",
11848 [INTEL_OUTPUT_TVOUT] = "TV",
11849 [INTEL_OUTPUT_HDMI] = "HDMI",
11850 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11851 [INTEL_OUTPUT_EDP] = "eDP",
11852 [INTEL_OUTPUT_DSI] = "DSI",
11853 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11854 };
11855
11856 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11857 return "Invalid";
11858
11859 return names[output];
11860}
11861
Jesse Barnes84b4e042014-06-25 08:24:29 -070011862static bool intel_crt_present(struct drm_device *dev)
11863{
11864 struct drm_i915_private *dev_priv = dev->dev_private;
11865
11866 if (IS_ULT(dev))
11867 return false;
11868
11869 if (IS_CHERRYVIEW(dev))
11870 return false;
11871
11872 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11873 return false;
11874
11875 return true;
11876}
11877
Jesse Barnes79e53942008-11-07 14:24:08 -080011878static void intel_setup_outputs(struct drm_device *dev)
11879{
Eric Anholt725e30a2009-01-22 13:01:02 -080011880 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010011881 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011882 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080011883
Daniel Vetterc9093352013-06-06 22:22:47 +020011884 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011885
Jesse Barnes84b4e042014-06-25 08:24:29 -070011886 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020011887 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011888
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011889 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030011890 int found;
11891
11892 /* Haswell uses DDI functions to detect digital outputs */
11893 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11894 /* DDI A only supports eDP */
11895 if (found)
11896 intel_ddi_init(dev, PORT_A);
11897
11898 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11899 * register */
11900 found = I915_READ(SFUSE_STRAP);
11901
11902 if (found & SFUSE_STRAP_DDIB_DETECTED)
11903 intel_ddi_init(dev, PORT_B);
11904 if (found & SFUSE_STRAP_DDIC_DETECTED)
11905 intel_ddi_init(dev, PORT_C);
11906 if (found & SFUSE_STRAP_DDID_DETECTED)
11907 intel_ddi_init(dev, PORT_D);
11908 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011909 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020011910 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020011911
11912 if (has_edp_a(dev))
11913 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011914
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011915 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080011916 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010011917 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011918 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011919 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011920 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011921 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011922 }
11923
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011924 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011925 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011926
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011927 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011928 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011929
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011930 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011931 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011932
Daniel Vetter270b3042012-10-27 15:52:05 +020011933 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011934 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070011935 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030011936 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11937 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11938 PORT_B);
11939 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11940 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11941 }
11942
Jesse Barnes6f6005a2013-08-09 09:34:35 -070011943 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11944 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11945 PORT_C);
11946 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020011947 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Jesse Barnes6f6005a2013-08-09 09:34:35 -070011948 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053011949
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030011950 if (IS_CHERRYVIEW(dev)) {
11951 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11952 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11953 PORT_D);
11954 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11955 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11956 }
11957 }
11958
Jani Nikula3cfca972013-08-27 15:12:26 +030011959 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080011960 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080011961 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080011962
Paulo Zanonie2debe92013-02-18 19:00:27 -030011963 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011964 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011965 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011966 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11967 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011968 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011969 }
Ma Ling27185ae2009-08-24 13:50:23 +080011970
Imre Deake7281ea2013-05-08 13:14:08 +030011971 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011972 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080011973 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040011974
11975 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040011976
Paulo Zanonie2debe92013-02-18 19:00:27 -030011977 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011978 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011979 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011980 }
Ma Ling27185ae2009-08-24 13:50:23 +080011981
Paulo Zanonie2debe92013-02-18 19:00:27 -030011982 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080011983
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011984 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11985 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011986 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011987 }
Imre Deake7281ea2013-05-08 13:14:08 +030011988 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011989 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080011990 }
Ma Ling27185ae2009-08-24 13:50:23 +080011991
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011992 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030011993 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011994 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070011995 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080011996 intel_dvo_init(dev);
11997
Zhenyu Wang103a1962009-11-27 11:44:36 +080011998 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080011999 intel_tv_init(dev);
12000
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070012001 intel_edp_psr_init(dev);
12002
Chris Wilson4ef69c72010-09-09 15:14:28 +010012003 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12004 encoder->base.possible_crtcs = encoder->crtc_mask;
12005 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020012006 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080012007 }
Chris Wilson47356eb2011-01-11 17:06:04 +000012008
Paulo Zanonidde86e22012-12-01 12:04:25 -020012009 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020012010
12011 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012012}
12013
12014static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12015{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012016 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080012017 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080012018
Daniel Vetteref2d6332014-02-10 18:00:38 +010012019 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012020 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010012021 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012022 drm_gem_object_unreference(&intel_fb->obj->base);
12023 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012024 kfree(intel_fb);
12025}
12026
12027static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000012028 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080012029 unsigned int *handle)
12030{
12031 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000012032 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012033
Chris Wilson05394f32010-11-08 19:18:58 +000012034 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080012035}
12036
12037static const struct drm_framebuffer_funcs intel_fb_funcs = {
12038 .destroy = intel_user_framebuffer_destroy,
12039 .create_handle = intel_user_framebuffer_create_handle,
12040};
12041
Daniel Vetterb5ea6422014-03-02 21:18:00 +010012042static int intel_framebuffer_init(struct drm_device *dev,
12043 struct intel_framebuffer *intel_fb,
12044 struct drm_mode_fb_cmd2 *mode_cmd,
12045 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080012046{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012047 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012048 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080012049 int ret;
12050
Daniel Vetterdd4916c2013-10-09 21:23:51 +020012051 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12052
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012053 if (obj->tiling_mode == I915_TILING_Y) {
12054 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010012055 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012056 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012057
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012058 if (mode_cmd->pitches[0] & 63) {
12059 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12060 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010012061 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012062 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012063
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012064 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12065 pitch_limit = 32*1024;
12066 } else if (INTEL_INFO(dev)->gen >= 4) {
12067 if (obj->tiling_mode)
12068 pitch_limit = 16*1024;
12069 else
12070 pitch_limit = 32*1024;
12071 } else if (INTEL_INFO(dev)->gen >= 3) {
12072 if (obj->tiling_mode)
12073 pitch_limit = 8*1024;
12074 else
12075 pitch_limit = 16*1024;
12076 } else
12077 /* XXX DSPC is limited to 4k tiled */
12078 pitch_limit = 8*1024;
12079
12080 if (mode_cmd->pitches[0] > pitch_limit) {
12081 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12082 obj->tiling_mode ? "tiled" : "linear",
12083 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012084 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012085 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012086
12087 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012088 mode_cmd->pitches[0] != obj->stride) {
12089 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12090 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012091 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012092 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012093
Ville Syrjälä57779d02012-10-31 17:50:14 +020012094 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012095 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020012096 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012097 case DRM_FORMAT_RGB565:
12098 case DRM_FORMAT_XRGB8888:
12099 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012100 break;
12101 case DRM_FORMAT_XRGB1555:
12102 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012103 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012104 DRM_DEBUG("unsupported pixel format: %s\n",
12105 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012106 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012107 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020012108 break;
12109 case DRM_FORMAT_XBGR8888:
12110 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012111 case DRM_FORMAT_XRGB2101010:
12112 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012113 case DRM_FORMAT_XBGR2101010:
12114 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012115 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012116 DRM_DEBUG("unsupported pixel format: %s\n",
12117 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012118 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012119 }
Jesse Barnesb5626742011-06-24 12:19:27 -070012120 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020012121 case DRM_FORMAT_YUYV:
12122 case DRM_FORMAT_UYVY:
12123 case DRM_FORMAT_YVYU:
12124 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012125 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012126 DRM_DEBUG("unsupported pixel format: %s\n",
12127 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012128 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012129 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012130 break;
12131 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012132 DRM_DEBUG("unsupported pixel format: %s\n",
12133 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010012134 return -EINVAL;
12135 }
12136
Ville Syrjälä90f9a332012-10-31 17:50:19 +020012137 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12138 if (mode_cmd->offsets[0] != 0)
12139 return -EINVAL;
12140
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012141 aligned_height = intel_align_height(dev, mode_cmd->height,
12142 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020012143 /* FIXME drm helper for size checks (especially planar formats)? */
12144 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12145 return -EINVAL;
12146
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012147 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12148 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020012149 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012150
Jesse Barnes79e53942008-11-07 14:24:08 -080012151 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12152 if (ret) {
12153 DRM_ERROR("framebuffer init failed %d\n", ret);
12154 return ret;
12155 }
12156
Jesse Barnes79e53942008-11-07 14:24:08 -080012157 return 0;
12158}
12159
Jesse Barnes79e53942008-11-07 14:24:08 -080012160static struct drm_framebuffer *
12161intel_user_framebuffer_create(struct drm_device *dev,
12162 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012163 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080012164{
Chris Wilson05394f32010-11-08 19:18:58 +000012165 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012166
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012167 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12168 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000012169 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010012170 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080012171
Chris Wilsond2dff872011-04-19 08:36:26 +010012172 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080012173}
12174
Daniel Vetter4520f532013-10-09 09:18:51 +020012175#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020012176static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020012177{
12178}
12179#endif
12180
Jesse Barnes79e53942008-11-07 14:24:08 -080012181static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080012182 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020012183 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080012184};
12185
Jesse Barnese70236a2009-09-21 10:42:27 -070012186/* Set up chip specific display functions */
12187static void intel_init_display(struct drm_device *dev)
12188{
12189 struct drm_i915_private *dev_priv = dev->dev_private;
12190
Daniel Vetteree9300b2013-06-03 22:40:22 +020012191 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12192 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030012193 else if (IS_CHERRYVIEW(dev))
12194 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020012195 else if (IS_VALLEYVIEW(dev))
12196 dev_priv->display.find_dpll = vlv_find_best_dpll;
12197 else if (IS_PINEVIEW(dev))
12198 dev_priv->display.find_dpll = pnv_find_best_dpll;
12199 else
12200 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12201
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012202 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012203 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012204 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012205 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020012206 dev_priv->display.crtc_enable = haswell_crtc_enable;
12207 dev_priv->display.crtc_disable = haswell_crtc_disable;
Daniel Vetterdf8ad702014-06-25 22:02:03 +030012208 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012209 dev_priv->display.update_primary_plane =
12210 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012211 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012212 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012213 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070012214 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012215 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12216 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012217 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012218 dev_priv->display.update_primary_plane =
12219 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012220 } else if (IS_VALLEYVIEW(dev)) {
12221 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012222 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012223 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12224 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12225 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12226 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012227 dev_priv->display.update_primary_plane =
12228 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012229 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012230 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012231 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070012232 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012233 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12234 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012235 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012236 dev_priv->display.update_primary_plane =
12237 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012238 }
Jesse Barnese70236a2009-09-21 10:42:27 -070012239
Jesse Barnese70236a2009-09-21 10:42:27 -070012240 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070012241 if (IS_VALLEYVIEW(dev))
12242 dev_priv->display.get_display_clock_speed =
12243 valleyview_get_display_clock_speed;
12244 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070012245 dev_priv->display.get_display_clock_speed =
12246 i945_get_display_clock_speed;
12247 else if (IS_I915G(dev))
12248 dev_priv->display.get_display_clock_speed =
12249 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012250 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012251 dev_priv->display.get_display_clock_speed =
12252 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012253 else if (IS_PINEVIEW(dev))
12254 dev_priv->display.get_display_clock_speed =
12255 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070012256 else if (IS_I915GM(dev))
12257 dev_priv->display.get_display_clock_speed =
12258 i915gm_get_display_clock_speed;
12259 else if (IS_I865G(dev))
12260 dev_priv->display.get_display_clock_speed =
12261 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020012262 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012263 dev_priv->display.get_display_clock_speed =
12264 i855_get_display_clock_speed;
12265 else /* 852, 830 */
12266 dev_priv->display.get_display_clock_speed =
12267 i830_get_display_clock_speed;
12268
Zhenyu Wang7f8a8562010-04-01 13:07:53 +080012269 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +010012270 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070012271 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080012272 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +080012273 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070012274 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080012275 dev_priv->display.write_eld = ironlake_write_eld;
Paulo Zanoni9a952a02014-03-07 20:12:34 -030012276 dev_priv->display.modeset_global_resources =
12277 snb_modeset_global_resources;
Jesse Barnes357555c2011-04-28 15:09:55 -070012278 } else if (IS_IVYBRIDGE(dev)) {
12279 /* FIXME: detect B0+ stepping and use auto training */
12280 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080012281 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +020012282 dev_priv->display.modeset_global_resources =
12283 ivb_modeset_global_resources;
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012284 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -030012285 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +080012286 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -020012287 dev_priv->display.modeset_global_resources =
12288 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -020012289 }
Jesse Barnes6067aae2011-04-28 15:04:31 -070012290 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080012291 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnes30a970c2013-11-04 13:48:12 -080012292 } else if (IS_VALLEYVIEW(dev)) {
12293 dev_priv->display.modeset_global_resources =
12294 valleyview_modeset_global_resources;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -040012295 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -070012296 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012297
12298 /* Default just returns -ENODEV to indicate unsupported */
12299 dev_priv->display.queue_flip = intel_default_queue_flip;
12300
12301 switch (INTEL_INFO(dev)->gen) {
12302 case 2:
12303 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12304 break;
12305
12306 case 3:
12307 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12308 break;
12309
12310 case 4:
12311 case 5:
12312 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12313 break;
12314
12315 case 6:
12316 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12317 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012318 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012319 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012320 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12321 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012322 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020012323
12324 intel_panel_init_backlight_funcs(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012325}
12326
Jesse Barnesb690e962010-07-19 13:53:12 -070012327/*
12328 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12329 * resume, or other times. This quirk makes sure that's the case for
12330 * affected systems.
12331 */
Akshay Joshi0206e352011-08-16 15:34:10 -040012332static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070012333{
12334 struct drm_i915_private *dev_priv = dev->dev_private;
12335
12336 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012337 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012338}
12339
Keith Packard435793d2011-07-12 14:56:22 -070012340/*
12341 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12342 */
12343static void quirk_ssc_force_disable(struct drm_device *dev)
12344{
12345 struct drm_i915_private *dev_priv = dev->dev_private;
12346 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012347 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070012348}
12349
Carsten Emde4dca20e2012-03-15 15:56:26 +010012350/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010012351 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12352 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010012353 */
12354static void quirk_invert_brightness(struct drm_device *dev)
12355{
12356 struct drm_i915_private *dev_priv = dev->dev_private;
12357 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012358 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012359}
12360
12361struct intel_quirk {
12362 int device;
12363 int subsystem_vendor;
12364 int subsystem_device;
12365 void (*hook)(struct drm_device *dev);
12366};
12367
Egbert Eich5f85f1762012-10-14 15:46:38 +020012368/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12369struct intel_dmi_quirk {
12370 void (*hook)(struct drm_device *dev);
12371 const struct dmi_system_id (*dmi_id_list)[];
12372};
12373
12374static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12375{
12376 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12377 return 1;
12378}
12379
12380static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12381 {
12382 .dmi_id_list = &(const struct dmi_system_id[]) {
12383 {
12384 .callback = intel_dmi_reverse_brightness,
12385 .ident = "NCR Corporation",
12386 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12387 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12388 },
12389 },
12390 { } /* terminating entry */
12391 },
12392 .hook = quirk_invert_brightness,
12393 },
12394};
12395
Ben Widawskyc43b5632012-04-16 14:07:40 -070012396static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070012397 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040012398 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070012399
Jesse Barnesb690e962010-07-19 13:53:12 -070012400 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12401 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12402
Jesse Barnesb690e962010-07-19 13:53:12 -070012403 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12404 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12405
Keith Packard435793d2011-07-12 14:56:22 -070012406 /* Lenovo U160 cannot use SSC on LVDS */
12407 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020012408
12409 /* Sony Vaio Y cannot use SSC on LVDS */
12410 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010012411
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010012412 /* Acer Aspire 5734Z must invert backlight brightness */
12413 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12414
12415 /* Acer/eMachines G725 */
12416 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12417
12418 /* Acer/eMachines e725 */
12419 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12420
12421 /* Acer/Packard Bell NCL20 */
12422 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12423
12424 /* Acer Aspire 4736Z */
12425 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020012426
12427 /* Acer Aspire 5336 */
12428 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -070012429};
12430
12431static void intel_init_quirks(struct drm_device *dev)
12432{
12433 struct pci_dev *d = dev->pdev;
12434 int i;
12435
12436 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12437 struct intel_quirk *q = &intel_quirks[i];
12438
12439 if (d->device == q->device &&
12440 (d->subsystem_vendor == q->subsystem_vendor ||
12441 q->subsystem_vendor == PCI_ANY_ID) &&
12442 (d->subsystem_device == q->subsystem_device ||
12443 q->subsystem_device == PCI_ANY_ID))
12444 q->hook(dev);
12445 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020012446 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12447 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12448 intel_dmi_quirks[i].hook(dev);
12449 }
Jesse Barnesb690e962010-07-19 13:53:12 -070012450}
12451
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012452/* Disable the VGA plane that we never use */
12453static void i915_disable_vga(struct drm_device *dev)
12454{
12455 struct drm_i915_private *dev_priv = dev->dev_private;
12456 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012457 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012458
Ville Syrjälä2b37c612014-01-22 21:32:38 +020012459 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012460 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070012461 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012462 sr1 = inb(VGA_SR_DATA);
12463 outb(sr1 | 1<<5, VGA_SR_DATA);
12464 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12465 udelay(300);
12466
12467 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12468 POSTING_READ(vga_reg);
12469}
12470
Daniel Vetterf8175862012-04-10 15:50:11 +020012471void intel_modeset_init_hw(struct drm_device *dev)
12472{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030012473 intel_prepare_ddi(dev);
12474
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +030012475 if (IS_VALLEYVIEW(dev))
12476 vlv_update_cdclk(dev);
12477
Daniel Vetterf8175862012-04-10 15:50:11 +020012478 intel_init_clock_gating(dev);
12479
Jesse Barnes5382f5f352013-12-16 16:34:24 -080012480 intel_reset_dpio(dev);
Jesse Barnes40e9cf62013-10-03 11:35:46 -070012481
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012482 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020012483}
12484
Imre Deak7d708ee2013-04-17 14:04:50 +030012485void intel_modeset_suspend_hw(struct drm_device *dev)
12486{
12487 intel_suspend_hw(dev);
12488}
12489
Jesse Barnes79e53942008-11-07 14:24:08 -080012490void intel_modeset_init(struct drm_device *dev)
12491{
Jesse Barnes652c3932009-08-17 13:31:43 -070012492 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000012493 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012494 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080012495 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080012496
12497 drm_mode_config_init(dev);
12498
12499 dev->mode_config.min_width = 0;
12500 dev->mode_config.min_height = 0;
12501
Dave Airlie019d96c2011-09-29 16:20:42 +010012502 dev->mode_config.preferred_depth = 24;
12503 dev->mode_config.prefer_shadow = 1;
12504
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020012505 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080012506
Jesse Barnesb690e962010-07-19 13:53:12 -070012507 intel_init_quirks(dev);
12508
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030012509 intel_init_pm(dev);
12510
Ben Widawskye3c74752013-04-05 13:12:39 -070012511 if (INTEL_INFO(dev)->num_pipes == 0)
12512 return;
12513
Jesse Barnese70236a2009-09-21 10:42:27 -070012514 intel_init_display(dev);
12515
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012516 if (IS_GEN2(dev)) {
12517 dev->mode_config.max_width = 2048;
12518 dev->mode_config.max_height = 2048;
12519 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070012520 dev->mode_config.max_width = 4096;
12521 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080012522 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012523 dev->mode_config.max_width = 8192;
12524 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080012525 }
Damien Lespiau068be562014-03-28 14:17:49 +000012526
12527 if (IS_GEN2(dev)) {
12528 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12529 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12530 } else {
12531 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12532 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12533 }
12534
Ben Widawsky5d4545a2013-01-17 12:45:15 -080012535 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080012536
Zhao Yakui28c97732009-10-09 11:39:41 +080012537 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012538 INTEL_INFO(dev)->num_pipes,
12539 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080012540
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012541 for_each_pipe(pipe) {
12542 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000012543 for_each_sprite(pipe, sprite) {
12544 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012545 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030012546 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000012547 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012548 }
Jesse Barnes79e53942008-11-07 14:24:08 -080012549 }
12550
Jesse Barnesf42bb702013-12-16 16:34:23 -080012551 intel_init_dpio(dev);
Jesse Barnes5382f5f352013-12-16 16:34:24 -080012552 intel_reset_dpio(dev);
Jesse Barnesf42bb702013-12-16 16:34:23 -080012553
Daniel Vettere72f9fb2013-06-05 13:34:06 +020012554 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012555
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012556 /* Just disable it once at startup */
12557 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012558 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000012559
12560 /* Just in case the BIOS is doing something questionable. */
12561 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012562
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012563 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012564 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012565 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012566
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012567 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080012568 if (!crtc->active)
12569 continue;
12570
Jesse Barnes46f297f2014-03-07 08:57:48 -080012571 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080012572 * Note that reserving the BIOS fb up front prevents us
12573 * from stuffing other stolen allocations like the ring
12574 * on top. This prevents some ugliness at boot time, and
12575 * can even allow for smooth boot transitions if the BIOS
12576 * fb is large enough for the active pipe configuration.
12577 */
12578 if (dev_priv->display.get_plane_config) {
12579 dev_priv->display.get_plane_config(crtc,
12580 &crtc->plane_config);
12581 /*
12582 * If the fb is shared between multiple heads, we'll
12583 * just get the first one.
12584 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080012585 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012586 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080012587 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010012588}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080012589
Daniel Vetter7fad7982012-07-04 17:51:47 +020012590static void intel_enable_pipe_a(struct drm_device *dev)
12591{
12592 struct intel_connector *connector;
12593 struct drm_connector *crt = NULL;
12594 struct intel_load_detect_pipe load_detect_temp;
Rob Clark51fd3712013-11-19 12:10:12 -050012595 struct drm_modeset_acquire_ctx ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020012596
12597 /* We can't just switch on the pipe A, we need to set things up with a
12598 * proper mode and output configuration. As a gross hack, enable pipe A
12599 * by enabling the load detect pipe once. */
12600 list_for_each_entry(connector,
12601 &dev->mode_config.connector_list,
12602 base.head) {
12603 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12604 crt = &connector->base;
12605 break;
12606 }
12607 }
12608
12609 if (!crt)
12610 return;
12611
Rob Clark51fd3712013-11-19 12:10:12 -050012612 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12613 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
Daniel Vetter7fad7982012-07-04 17:51:47 +020012614
12615
12616}
12617
Daniel Vetterfa555832012-10-10 23:14:00 +020012618static bool
12619intel_check_plane_mapping(struct intel_crtc *crtc)
12620{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012621 struct drm_device *dev = crtc->base.dev;
12622 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012623 u32 reg, val;
12624
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012625 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020012626 return true;
12627
12628 reg = DSPCNTR(!crtc->plane);
12629 val = I915_READ(reg);
12630
12631 if ((val & DISPLAY_PLANE_ENABLE) &&
12632 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12633 return false;
12634
12635 return true;
12636}
12637
Daniel Vetter24929352012-07-02 20:28:59 +020012638static void intel_sanitize_crtc(struct intel_crtc *crtc)
12639{
12640 struct drm_device *dev = crtc->base.dev;
12641 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012642 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020012643
Daniel Vetter24929352012-07-02 20:28:59 +020012644 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020012645 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020012646 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12647
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012648 /* restore vblank interrupts to correct state */
12649 if (crtc->active)
12650 drm_vblank_on(dev, crtc->pipe);
12651 else
12652 drm_vblank_off(dev, crtc->pipe);
12653
Daniel Vetter24929352012-07-02 20:28:59 +020012654 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020012655 * disable the crtc (and hence change the state) if it is wrong. Note
12656 * that gen4+ has a fixed plane -> pipe mapping. */
12657 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020012658 struct intel_connector *connector;
12659 bool plane;
12660
Daniel Vetter24929352012-07-02 20:28:59 +020012661 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12662 crtc->base.base.id);
12663
12664 /* Pipe has the wrong plane attached and the plane is active.
12665 * Temporarily change the plane mapping and disable everything
12666 * ... */
12667 plane = crtc->plane;
12668 crtc->plane = !plane;
12669 dev_priv->display.crtc_disable(&crtc->base);
12670 crtc->plane = plane;
12671
12672 /* ... and break all links. */
12673 list_for_each_entry(connector, &dev->mode_config.connector_list,
12674 base.head) {
12675 if (connector->encoder->base.crtc != &crtc->base)
12676 continue;
12677
Egbert Eich7f1950f2014-04-25 10:56:22 +020012678 connector->base.dpms = DRM_MODE_DPMS_OFF;
12679 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020012680 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020012681 /* multiple connectors may have the same encoder:
12682 * handle them and break crtc link separately */
12683 list_for_each_entry(connector, &dev->mode_config.connector_list,
12684 base.head)
12685 if (connector->encoder->base.crtc == &crtc->base) {
12686 connector->encoder->base.crtc = NULL;
12687 connector->encoder->connectors_active = false;
12688 }
Daniel Vetter24929352012-07-02 20:28:59 +020012689
12690 WARN_ON(crtc->active);
12691 crtc->base.enabled = false;
12692 }
Daniel Vetter24929352012-07-02 20:28:59 +020012693
Daniel Vetter7fad7982012-07-04 17:51:47 +020012694 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12695 crtc->pipe == PIPE_A && !crtc->active) {
12696 /* BIOS forgot to enable pipe A, this mostly happens after
12697 * resume. Force-enable the pipe to fix this, the update_dpms
12698 * call below we restore the pipe to the right state, but leave
12699 * the required bits on. */
12700 intel_enable_pipe_a(dev);
12701 }
12702
Daniel Vetter24929352012-07-02 20:28:59 +020012703 /* Adjust the state of the output pipe according to whether we
12704 * have active connectors/encoders. */
12705 intel_crtc_update_dpms(&crtc->base);
12706
12707 if (crtc->active != crtc->base.enabled) {
12708 struct intel_encoder *encoder;
12709
12710 /* This can happen either due to bugs in the get_hw_state
12711 * functions or because the pipe is force-enabled due to the
12712 * pipe A quirk. */
12713 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12714 crtc->base.base.id,
12715 crtc->base.enabled ? "enabled" : "disabled",
12716 crtc->active ? "enabled" : "disabled");
12717
12718 crtc->base.enabled = crtc->active;
12719
12720 /* Because we only establish the connector -> encoder ->
12721 * crtc links if something is active, this means the
12722 * crtc is now deactivated. Break the links. connector
12723 * -> encoder links are only establish when things are
12724 * actually up, hence no need to break them. */
12725 WARN_ON(crtc->active);
12726
12727 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12728 WARN_ON(encoder->connectors_active);
12729 encoder->base.crtc = NULL;
12730 }
12731 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020012732
12733 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010012734 /*
12735 * We start out with underrun reporting disabled to avoid races.
12736 * For correct bookkeeping mark this on active crtcs.
12737 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020012738 * Also on gmch platforms we dont have any hardware bits to
12739 * disable the underrun reporting. Which means we need to start
12740 * out with underrun reporting disabled also on inactive pipes,
12741 * since otherwise we'll complain about the garbage we read when
12742 * e.g. coming up after runtime pm.
12743 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010012744 * No protection against concurrent access is required - at
12745 * worst a fifo underrun happens which also sets this to false.
12746 */
12747 crtc->cpu_fifo_underrun_disabled = true;
12748 crtc->pch_fifo_underrun_disabled = true;
Ville Syrjälä80715b22014-05-15 20:23:23 +030012749
12750 update_scanline_offset(crtc);
Daniel Vetter4cc31482014-03-24 00:01:41 +010012751 }
Daniel Vetter24929352012-07-02 20:28:59 +020012752}
12753
12754static void intel_sanitize_encoder(struct intel_encoder *encoder)
12755{
12756 struct intel_connector *connector;
12757 struct drm_device *dev = encoder->base.dev;
12758
12759 /* We need to check both for a crtc link (meaning that the
12760 * encoder is active and trying to read from a pipe) and the
12761 * pipe itself being active. */
12762 bool has_active_crtc = encoder->base.crtc &&
12763 to_intel_crtc(encoder->base.crtc)->active;
12764
12765 if (encoder->connectors_active && !has_active_crtc) {
12766 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12767 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012768 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020012769
12770 /* Connector is active, but has no active pipe. This is
12771 * fallout from our resume register restoring. Disable
12772 * the encoder manually again. */
12773 if (encoder->base.crtc) {
12774 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12775 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012776 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020012777 encoder->disable(encoder);
12778 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020012779 encoder->base.crtc = NULL;
12780 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020012781
12782 /* Inconsistent output/port/pipe state happens presumably due to
12783 * a bug in one of the get_hw_state functions. Or someplace else
12784 * in our code, like the register restore mess on resume. Clamp
12785 * things to off as a safer default. */
12786 list_for_each_entry(connector,
12787 &dev->mode_config.connector_list,
12788 base.head) {
12789 if (connector->encoder != encoder)
12790 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020012791 connector->base.dpms = DRM_MODE_DPMS_OFF;
12792 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020012793 }
12794 }
12795 /* Enabled encoders without active connectors will be fixed in
12796 * the crtc fixup. */
12797}
12798
Imre Deak04098752014-02-18 00:02:16 +020012799void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012800{
12801 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012802 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012803
Imre Deak04098752014-02-18 00:02:16 +020012804 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12805 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12806 i915_disable_vga(dev);
12807 }
12808}
12809
12810void i915_redisable_vga(struct drm_device *dev)
12811{
12812 struct drm_i915_private *dev_priv = dev->dev_private;
12813
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030012814 /* This function can be called both from intel_modeset_setup_hw_state or
12815 * at a very early point in our resume sequence, where the power well
12816 * structures are not yet restored. Since this function is at a very
12817 * paranoid "someone might have enabled VGA while we were not looking"
12818 * level, just check if the power well is enabled instead of trying to
12819 * follow the "don't touch the power well if we don't need it" policy
12820 * the rest of the driver uses. */
Imre Deak04098752014-02-18 00:02:16 +020012821 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030012822 return;
12823
Imre Deak04098752014-02-18 00:02:16 +020012824 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012825}
12826
Ville Syrjälä98ec7732014-04-30 17:43:01 +030012827static bool primary_get_hw_state(struct intel_crtc *crtc)
12828{
12829 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12830
12831 if (!crtc->active)
12832 return false;
12833
12834 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12835}
12836
Daniel Vetter30e984d2013-06-05 13:34:17 +020012837static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020012838{
12839 struct drm_i915_private *dev_priv = dev->dev_private;
12840 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020012841 struct intel_crtc *crtc;
12842 struct intel_encoder *encoder;
12843 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020012844 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020012845
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012846 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010012847 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020012848
Daniel Vetter99535992014-04-13 12:00:33 +020012849 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12850
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012851 crtc->active = dev_priv->display.get_pipe_config(crtc,
12852 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020012853
12854 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030012855 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020012856
12857 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12858 crtc->base.base.id,
12859 crtc->active ? "enabled" : "disabled");
12860 }
12861
Daniel Vetter53589012013-06-05 13:34:16 +020012862 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12863 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12864
12865 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12866 pll->active = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012867 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020012868 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12869 pll->active++;
12870 }
12871 pll->refcount = pll->active;
12872
Daniel Vetter35c95372013-07-17 06:55:04 +020012873 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12874 pll->name, pll->refcount, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030012875
12876 if (pll->refcount)
12877 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020012878 }
12879
Daniel Vetter24929352012-07-02 20:28:59 +020012880 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12881 base.head) {
12882 pipe = 0;
12883
12884 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070012885 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12886 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010012887 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020012888 } else {
12889 encoder->base.crtc = NULL;
12890 }
12891
12892 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010012893 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020012894 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012895 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020012896 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010012897 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020012898 }
12899
12900 list_for_each_entry(connector, &dev->mode_config.connector_list,
12901 base.head) {
12902 if (connector->get_hw_state(connector)) {
12903 connector->base.dpms = DRM_MODE_DPMS_ON;
12904 connector->encoder->connectors_active = true;
12905 connector->base.encoder = &connector->encoder->base;
12906 } else {
12907 connector->base.dpms = DRM_MODE_DPMS_OFF;
12908 connector->base.encoder = NULL;
12909 }
12910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12911 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030012912 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020012913 connector->base.encoder ? "enabled" : "disabled");
12914 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020012915}
12916
12917/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12918 * and i915 state tracking structures. */
12919void intel_modeset_setup_hw_state(struct drm_device *dev,
12920 bool force_restore)
12921{
12922 struct drm_i915_private *dev_priv = dev->dev_private;
12923 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020012924 struct intel_crtc *crtc;
12925 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020012926 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020012927
12928 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020012929
Jesse Barnesbabea612013-06-26 18:57:38 +030012930 /*
12931 * Now that we have the config, copy it to each CRTC struct
12932 * Note that this could go away if we move to using crtc_config
12933 * checking everywhere.
12934 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012935 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020012936 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080012937 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030012938 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12939 crtc->base.base.id);
12940 drm_mode_debug_printmodeline(&crtc->base.mode);
12941 }
12942 }
12943
Daniel Vetter24929352012-07-02 20:28:59 +020012944 /* HW state is read out, now we need to sanitize this mess. */
12945 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12946 base.head) {
12947 intel_sanitize_encoder(encoder);
12948 }
12949
12950 for_each_pipe(pipe) {
12951 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12952 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020012953 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020012954 }
Daniel Vetter9a935852012-07-05 22:34:27 +020012955
Daniel Vetter35c95372013-07-17 06:55:04 +020012956 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12957 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12958
12959 if (!pll->on || pll->active)
12960 continue;
12961
12962 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12963
12964 pll->disable(dev_priv, pll);
12965 pll->on = false;
12966 }
12967
Ville Syrjälä96f90c52013-12-05 15:51:38 +020012968 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030012969 ilk_wm_get_hw_state(dev);
12970
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012971 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030012972 i915_redisable_vga(dev);
12973
Daniel Vetterf30da182013-04-11 20:22:50 +020012974 /*
12975 * We need to use raw interfaces for restoring state to avoid
12976 * checking (bogus) intermediate states.
12977 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012978 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070012979 struct drm_crtc *crtc =
12980 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020012981
12982 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
Matt Roperf4510a22014-04-01 15:22:40 -070012983 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012984 }
12985 } else {
12986 intel_modeset_update_staged_output_state(dev);
12987 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012988
12989 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010012990}
12991
12992void intel_modeset_gem_init(struct drm_device *dev)
12993{
Jesse Barnes484b41d2014-03-07 08:57:55 -080012994 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070012995 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -080012996
Imre Deakae484342014-03-31 15:10:44 +030012997 mutex_lock(&dev->struct_mutex);
12998 intel_init_gt_powersave(dev);
12999 mutex_unlock(&dev->struct_mutex);
13000
Chris Wilson1833b132012-05-09 11:56:28 +010013001 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020013002
13003 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080013004
13005 /*
13006 * Make sure any fbs we allocated at startup are properly
13007 * pinned & fenced. When we do the allocation it's too early
13008 * for this.
13009 */
13010 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010013011 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070013012 obj = intel_fb_obj(c->primary->fb);
13013 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080013014 continue;
13015
Matt Roper2ff8fde2014-07-08 07:50:07 -070013016 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080013017 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13018 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100013019 drm_framebuffer_unreference(c->primary->fb);
13020 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013021 }
13022 }
13023 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013024}
13025
Imre Deak4932e2c2014-02-11 17:12:48 +020013026void intel_connector_unregister(struct intel_connector *intel_connector)
13027{
13028 struct drm_connector *connector = &intel_connector->base;
13029
13030 intel_panel_destroy_backlight(connector);
13031 drm_sysfs_connector_remove(connector);
13032}
13033
Jesse Barnes79e53942008-11-07 14:24:08 -080013034void intel_modeset_cleanup(struct drm_device *dev)
13035{
Jesse Barnes652c3932009-08-17 13:31:43 -070013036 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid9255d52013-09-26 20:05:59 -030013037 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070013038
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013039 /*
13040 * Interrupts and polling as the first thing to avoid creating havoc.
13041 * Too much stuff here (turning of rps, connectors, ...) would
13042 * experience fancy races otherwise.
13043 */
13044 drm_irq_uninstall(dev);
13045 cancel_work_sync(&dev_priv->hotplug_work);
13046 /*
13047 * Due to the hpd irq storm handling the hotplug work can re-arm the
13048 * poll handlers. Hence disable polling after hpd handling is shut down.
13049 */
Keith Packardf87ea762010-10-03 19:36:26 -070013050 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013051
Jesse Barnes652c3932009-08-17 13:31:43 -070013052 mutex_lock(&dev->struct_mutex);
13053
Jesse Barnes723bfd72010-10-07 16:01:13 -070013054 intel_unregister_dsm_handler();
13055
Chris Wilson973d04f2011-07-08 12:22:37 +010013056 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070013057
Daniel Vetter8090c6b2012-06-24 16:42:32 +020013058 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000013059
Daniel Vetter930ebb42012-06-29 23:32:16 +020013060 ironlake_teardown_rc6(dev);
13061
Kristian Høgsberg69341a52009-11-11 12:19:17 -050013062 mutex_unlock(&dev->struct_mutex);
13063
Chris Wilson1630fe72011-07-08 12:22:42 +010013064 /* flush any delayed tasks or pending work */
13065 flush_scheduled_work();
13066
Jani Nikuladb31af12013-11-08 16:48:53 +020013067 /* destroy the backlight and sysfs files before encoders/connectors */
13068 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020013069 struct intel_connector *intel_connector;
13070
13071 intel_connector = to_intel_connector(connector);
13072 intel_connector->unregister(intel_connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020013073 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030013074
Jesse Barnes79e53942008-11-07 14:24:08 -080013075 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010013076
13077 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030013078
13079 mutex_lock(&dev->struct_mutex);
13080 intel_cleanup_gt_powersave(dev);
13081 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013082}
13083
Dave Airlie28d52042009-09-21 14:33:58 +100013084/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080013085 * Return which encoder is currently attached for connector.
13086 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010013087struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080013088{
Chris Wilsondf0e9242010-09-09 16:20:55 +010013089 return &intel_attached_encoder(connector)->base;
13090}
Jesse Barnes79e53942008-11-07 14:24:08 -080013091
Chris Wilsondf0e9242010-09-09 16:20:55 +010013092void intel_connector_attach_encoder(struct intel_connector *connector,
13093 struct intel_encoder *encoder)
13094{
13095 connector->encoder = encoder;
13096 drm_mode_connector_attach_encoder(&connector->base,
13097 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080013098}
Dave Airlie28d52042009-09-21 14:33:58 +100013099
13100/*
13101 * set vga decode state - true == enable VGA decode
13102 */
13103int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13104{
13105 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000013106 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100013107 u16 gmch_ctrl;
13108
Chris Wilson75fa0412014-02-07 18:37:02 -020013109 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13110 DRM_ERROR("failed to read control word\n");
13111 return -EIO;
13112 }
13113
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020013114 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13115 return 0;
13116
Dave Airlie28d52042009-09-21 14:33:58 +100013117 if (state)
13118 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13119 else
13120 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020013121
13122 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13123 DRM_ERROR("failed to write control word\n");
13124 return -EIO;
13125 }
13126
Dave Airlie28d52042009-09-21 14:33:58 +100013127 return 0;
13128}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013129
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013130struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013131
13132 u32 power_well_driver;
13133
Chris Wilson63b66e52013-08-08 15:12:06 +020013134 int num_transcoders;
13135
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013136 struct intel_cursor_error_state {
13137 u32 control;
13138 u32 position;
13139 u32 base;
13140 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010013141 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013142
13143 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013144 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013145 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030013146 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010013147 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013148
13149 struct intel_plane_error_state {
13150 u32 control;
13151 u32 stride;
13152 u32 size;
13153 u32 pos;
13154 u32 addr;
13155 u32 surface;
13156 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010013157 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020013158
13159 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013160 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020013161 enum transcoder cpu_transcoder;
13162
13163 u32 conf;
13164
13165 u32 htotal;
13166 u32 hblank;
13167 u32 hsync;
13168 u32 vtotal;
13169 u32 vblank;
13170 u32 vsync;
13171 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013172};
13173
13174struct intel_display_error_state *
13175intel_display_capture_error_state(struct drm_device *dev)
13176{
Jani Nikulafbee40d2014-03-31 14:27:18 +030013177 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013178 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020013179 int transcoders[] = {
13180 TRANSCODER_A,
13181 TRANSCODER_B,
13182 TRANSCODER_C,
13183 TRANSCODER_EDP,
13184 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013185 int i;
13186
Chris Wilson63b66e52013-08-08 15:12:06 +020013187 if (INTEL_INFO(dev)->num_pipes == 0)
13188 return NULL;
13189
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013190 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013191 if (error == NULL)
13192 return NULL;
13193
Imre Deak190be112013-11-25 17:15:31 +020013194 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013195 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13196
Damien Lespiau52331302012-08-15 19:23:25 +010013197 for_each_pipe(i) {
Imre Deakddf9c532013-11-27 22:02:02 +020013198 error->pipe[i].power_domain_on =
Imre Deakbfafe932014-06-05 20:31:47 +030013199 intel_display_power_enabled_unlocked(dev_priv,
13200 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020013201 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013202 continue;
13203
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030013204 error->cursor[i].control = I915_READ(CURCNTR(i));
13205 error->cursor[i].position = I915_READ(CURPOS(i));
13206 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013207
13208 error->plane[i].control = I915_READ(DSPCNTR(i));
13209 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013210 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030013211 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013212 error->plane[i].pos = I915_READ(DSPPOS(i));
13213 }
Paulo Zanonica291362013-03-06 20:03:14 -030013214 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13215 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013216 if (INTEL_INFO(dev)->gen >= 4) {
13217 error->plane[i].surface = I915_READ(DSPSURF(i));
13218 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13219 }
13220
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013221 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030013222
13223 if (!HAS_PCH_SPLIT(dev))
13224 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020013225 }
13226
13227 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13228 if (HAS_DDI(dev_priv->dev))
13229 error->num_transcoders++; /* Account for eDP. */
13230
13231 for (i = 0; i < error->num_transcoders; i++) {
13232 enum transcoder cpu_transcoder = transcoders[i];
13233
Imre Deakddf9c532013-11-27 22:02:02 +020013234 error->transcoder[i].power_domain_on =
Imre Deakbfafe932014-06-05 20:31:47 +030013235 intel_display_power_enabled_unlocked(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020013236 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013237 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013238 continue;
13239
Chris Wilson63b66e52013-08-08 15:12:06 +020013240 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13241
13242 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13243 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13244 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13245 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13246 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13247 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13248 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013249 }
13250
13251 return error;
13252}
13253
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013254#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13255
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013256void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013257intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013258 struct drm_device *dev,
13259 struct intel_display_error_state *error)
13260{
13261 int i;
13262
Chris Wilson63b66e52013-08-08 15:12:06 +020013263 if (!error)
13264 return;
13265
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013266 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020013267 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013268 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013269 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010013270 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013271 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020013272 err_printf(m, " Power: %s\n",
13273 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013274 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030013275 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013276
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013277 err_printf(m, "Plane [%d]:\n", i);
13278 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13279 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013280 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013281 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13282 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013283 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030013284 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013285 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013286 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013287 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13288 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013289 }
13290
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013291 err_printf(m, "Cursor [%d]:\n", i);
13292 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13293 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13294 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013295 }
Chris Wilson63b66e52013-08-08 15:12:06 +020013296
13297 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010013298 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020013299 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013300 err_printf(m, " Power: %s\n",
13301 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020013302 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13303 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13304 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13305 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13306 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13307 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13308 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13309 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013310}