blob: 0c16a2b39b411229755e3e673cf06f175fb17454 [file] [log] [blame]
Kumar Galaccf06992006-05-20 15:00:15 -07001/*
2 * MPC83xx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/completion.h>
18#include <linux/interrupt.h>
19#include <linux/delay.h>
20#include <linux/irq.h>
21#include <linux/device.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/spi_bitbang.h>
24#include <linux/platform_device.h>
25#include <linux/fsl_devices.h>
26
27#include <asm/irq.h>
28#include <asm/io.h>
29
30/* SPI Controller registers */
31struct mpc83xx_spi_reg {
32 u8 res1[0x20];
33 __be32 mode;
34 __be32 event;
35 __be32 mask;
36 __be32 command;
37 __be32 transmit;
38 __be32 receive;
39};
40
41/* SPI Controller mode register definitions */
Anton Vorontsov2a485d72007-07-31 00:38:45 -070042#define SPMODE_LOOP (1 << 30)
Kumar Galaccf06992006-05-20 15:00:15 -070043#define SPMODE_CI_INACTIVEHIGH (1 << 29)
44#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
45#define SPMODE_DIV16 (1 << 27)
46#define SPMODE_REV (1 << 26)
47#define SPMODE_MS (1 << 25)
48#define SPMODE_ENABLE (1 << 24)
49#define SPMODE_LEN(x) ((x) << 20)
50#define SPMODE_PM(x) ((x) << 16)
Joakim Tjernlundf29ba282007-07-17 04:04:12 -070051#define SPMODE_OP (1 << 14)
Kumar Galaccf06992006-05-20 15:00:15 -070052
53/*
54 * Default for SPI Mode:
55 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
56 */
57#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
58 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
59
60/* SPIE register values */
61#define SPIE_NE 0x00000200 /* Not empty */
62#define SPIE_NF 0x00000100 /* Not full */
63
64/* SPIM register values */
65#define SPIM_NE 0x00000200 /* Not empty */
66#define SPIM_NF 0x00000100 /* Not full */
67
68/* SPI Controller driver's private data. */
69struct mpc83xx_spi {
70 /* bitbang has to be first */
71 struct spi_bitbang bitbang;
72 struct completion done;
73
74 struct mpc83xx_spi_reg __iomem *base;
75
76 /* rx & tx bufs from the spi_transfer */
77 const void *tx;
78 void *rx;
79
80 /* functions to deal with different sized buffers */
81 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
82 u32(*get_tx) (struct mpc83xx_spi *);
83
84 unsigned int count;
85 u32 irq;
86
87 unsigned nsecs; /* (clock cycle time)/2 */
88
89 u32 sysclk;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -070090 u32 rx_shift; /* RX data reg shift when in qe mode */
91 u32 tx_shift; /* TX data reg shift when in qe mode */
92
93 bool qe_mode;
94
Kumar Galaccf06992006-05-20 15:00:15 -070095 void (*activate_cs) (u8 cs, u8 polarity);
96 void (*deactivate_cs) (u8 cs, u8 polarity);
97};
98
99static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
100{
101 out_be32(reg, val);
102}
103
104static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
105{
106 return in_be32(reg);
107}
108
109#define MPC83XX_SPI_RX_BUF(type) \
110void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
111{ \
112 type * rx = mpc83xx_spi->rx; \
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700113 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
Kumar Galaccf06992006-05-20 15:00:15 -0700114 mpc83xx_spi->rx = rx; \
115}
116
117#define MPC83XX_SPI_TX_BUF(type) \
118u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
119{ \
120 u32 data; \
121 const type * tx = mpc83xx_spi->tx; \
David Brownell4b1badf2006-12-29 16:48:39 -0800122 if (!tx) \
123 return 0; \
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700124 data = *tx++ << mpc83xx_spi->tx_shift; \
Kumar Galaccf06992006-05-20 15:00:15 -0700125 mpc83xx_spi->tx = tx; \
126 return data; \
127}
128
129MPC83XX_SPI_RX_BUF(u8)
130MPC83XX_SPI_RX_BUF(u16)
131MPC83XX_SPI_RX_BUF(u32)
132MPC83XX_SPI_TX_BUF(u8)
133MPC83XX_SPI_TX_BUF(u16)
134MPC83XX_SPI_TX_BUF(u32)
135
136static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
137{
138 struct mpc83xx_spi *mpc83xx_spi;
139 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
140
141 mpc83xx_spi = spi_master_get_devdata(spi->master);
142
143 if (value == BITBANG_CS_INACTIVE) {
144 if (mpc83xx_spi->deactivate_cs)
145 mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
146 }
147
148 if (value == BITBANG_CS_ACTIVE) {
149 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
150 u32 len = spi->bits_per_word;
151 if (len == 32)
152 len = 0;
153 else
154 len = len - 1;
155
156 /* mask out bits we are going to set */
Anton Vorontsov32421da2007-07-31 00:38:41 -0700157 regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
158 | SPMODE_LEN(0xF) | SPMODE_DIV16
Anton Vorontsov2a485d72007-07-31 00:38:45 -0700159 | SPMODE_PM(0xF) | SPMODE_REV | SPMODE_LOOP);
Kumar Galaccf06992006-05-20 15:00:15 -0700160
161 if (spi->mode & SPI_CPHA)
162 regval |= SPMODE_CP_BEGIN_EDGECLK;
163 if (spi->mode & SPI_CPOL)
164 regval |= SPMODE_CI_INACTIVEHIGH;
Anton Vorontsov32421da2007-07-31 00:38:41 -0700165 if (!(spi->mode & SPI_LSB_FIRST))
166 regval |= SPMODE_REV;
Anton Vorontsov2a485d72007-07-31 00:38:45 -0700167 if (spi->mode & SPI_LOOP)
168 regval |= SPMODE_LOOP;
Kumar Galaccf06992006-05-20 15:00:15 -0700169
170 regval |= SPMODE_LEN(len);
171
172 if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
173 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
Clifford Wolf698ca472007-07-17 04:04:06 -0700174 if (pm > 0x0f) {
175 printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
176 "Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
177 spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
178 pm = 0x0f;
179 }
Kumar Galaccf06992006-05-20 15:00:15 -0700180 regval |= SPMODE_PM(pm) | SPMODE_DIV16;
181 } else {
182 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
183 regval |= SPMODE_PM(pm);
184 }
185
Anton Vorontsov49bb2302007-07-31 00:38:40 -0700186 /* Turn off SPI unit prior changing mode */
187 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
Kumar Galaccf06992006-05-20 15:00:15 -0700188 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
189 if (mpc83xx_spi->activate_cs)
190 mpc83xx_spi->activate_cs(spi->chip_select, pol);
191 }
192}
193
194static
195int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
196{
197 struct mpc83xx_spi *mpc83xx_spi;
198 u32 regval;
199 u8 bits_per_word;
200 u32 hz;
201
202 mpc83xx_spi = spi_master_get_devdata(spi->master);
203
204 if (t) {
205 bits_per_word = t->bits_per_word;
206 hz = t->speed_hz;
207 } else {
208 bits_per_word = 0;
209 hz = 0;
210 }
211
212 /* spi_transfer level calls that work per-word */
213 if (!bits_per_word)
214 bits_per_word = spi->bits_per_word;
215
216 /* Make sure its a bit width we support [4..16, 32] */
217 if ((bits_per_word < 4)
218 || ((bits_per_word > 16) && (bits_per_word != 32)))
219 return -EINVAL;
220
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700221 mpc83xx_spi->rx_shift = 0;
222 mpc83xx_spi->tx_shift = 0;
Kumar Galaccf06992006-05-20 15:00:15 -0700223 if (bits_per_word <= 8) {
224 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
225 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700226 if (mpc83xx_spi->qe_mode) {
227 mpc83xx_spi->rx_shift = 16;
228 mpc83xx_spi->tx_shift = 24;
229 }
Kumar Galaccf06992006-05-20 15:00:15 -0700230 } else if (bits_per_word <= 16) {
231 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
232 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700233 if (mpc83xx_spi->qe_mode) {
234 mpc83xx_spi->rx_shift = 16;
235 mpc83xx_spi->tx_shift = 16;
236 }
Kumar Galaccf06992006-05-20 15:00:15 -0700237 } else if (bits_per_word <= 32) {
238 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
239 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
240 } else
241 return -EINVAL;
242
Anton Vorontsov35cc0b92007-07-31 00:38:42 -0700243 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
244 mpc83xx_spi->tx_shift = 0;
245 if (bits_per_word <= 8)
246 mpc83xx_spi->rx_shift = 8;
247 else
248 mpc83xx_spi->rx_shift = 0;
249 }
250
Kumar Galaccf06992006-05-20 15:00:15 -0700251 /* nsecs = (clock period)/2 */
252 if (!hz)
253 hz = spi->max_speed_hz;
254 mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
255 if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
256 return -EINVAL;
257
258 if (bits_per_word == 32)
259 bits_per_word = 0;
260 else
261 bits_per_word = bits_per_word - 1;
262
263 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
264
Anton Vorontsov32421da2007-07-31 00:38:41 -0700265 /* mask out bits we are going to set */
266 regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV);
Kumar Galaccf06992006-05-20 15:00:15 -0700267 regval |= SPMODE_LEN(bits_per_word);
Anton Vorontsov32421da2007-07-31 00:38:41 -0700268 if (!(spi->mode & SPI_LSB_FIRST))
269 regval |= SPMODE_REV;
Kumar Galaccf06992006-05-20 15:00:15 -0700270
Anton Vorontsov49bb2302007-07-31 00:38:40 -0700271 /* Turn off SPI unit prior changing mode */
272 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
Kumar Galaccf06992006-05-20 15:00:15 -0700273 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
274
275 return 0;
276}
277
David Brownelldccd5732007-07-17 04:04:02 -0700278/* the spi->mode bits understood by this driver: */
Anton Vorontsov2a485d72007-07-31 00:38:45 -0700279#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
280 | SPI_LSB_FIRST | SPI_LOOP)
David Brownelldccd5732007-07-17 04:04:02 -0700281
Kumar Galaccf06992006-05-20 15:00:15 -0700282static int mpc83xx_spi_setup(struct spi_device *spi)
283{
284 struct spi_bitbang *bitbang;
285 struct mpc83xx_spi *mpc83xx_spi;
286 int retval;
287
David Brownelldccd5732007-07-17 04:04:02 -0700288 if (spi->mode & ~MODEBITS) {
289 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
290 spi->mode & ~MODEBITS);
291 return -EINVAL;
292 }
293
Kumar Galaccf06992006-05-20 15:00:15 -0700294 if (!spi->max_speed_hz)
295 return -EINVAL;
296
297 bitbang = spi_master_get_devdata(spi->master);
298 mpc83xx_spi = spi_master_get_devdata(spi->master);
299
300 if (!spi->bits_per_word)
301 spi->bits_per_word = 8;
302
303 retval = mpc83xx_spi_setup_transfer(spi, NULL);
304 if (retval < 0)
305 return retval;
306
307 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
308 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
309 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
310
311 /* NOTE we _need_ to call chipselect() early, ideally with adapter
312 * setup, unless the hardware defaults cooperate to avoid confusion
313 * between normal (active low) and inverted chipselects.
314 */
315
316 /* deselect chip (low or high) */
317 spin_lock(&bitbang->lock);
318 if (!bitbang->busy) {
319 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
320 ndelay(mpc83xx_spi->nsecs);
321 }
322 spin_unlock(&bitbang->lock);
323
324 return 0;
325}
326
327static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
328{
329 struct mpc83xx_spi *mpc83xx_spi;
330 u32 word;
331
332 mpc83xx_spi = spi_master_get_devdata(spi->master);
333
334 mpc83xx_spi->tx = t->tx_buf;
335 mpc83xx_spi->rx = t->rx_buf;
336 mpc83xx_spi->count = t->len;
337 INIT_COMPLETION(mpc83xx_spi->done);
338
339 /* enable rx ints */
340 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
341
342 /* transmit word */
343 word = mpc83xx_spi->get_tx(mpc83xx_spi);
344 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
345
346 wait_for_completion(&mpc83xx_spi->done);
347
348 /* disable rx ints */
349 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
350
351 return t->len - mpc83xx_spi->count;
352}
353
David Howells7d12e782006-10-05 14:55:46 +0100354irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
Kumar Galaccf06992006-05-20 15:00:15 -0700355{
356 struct mpc83xx_spi *mpc83xx_spi = context_data;
357 u32 event;
358 irqreturn_t ret = IRQ_NONE;
359
360 /* Get interrupt events(tx/rx) */
361 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
362
363 /* We need handle RX first */
364 if (event & SPIE_NE) {
365 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
366
367 if (mpc83xx_spi->rx)
368 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
369
370 ret = IRQ_HANDLED;
371 }
372
373 if ((event & SPIE_NF) == 0)
374 /* spin until TX is done */
375 while (((event =
376 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
377 SPIE_NF) == 0)
378 cpu_relax();
379
380 mpc83xx_spi->count -= 1;
381 if (mpc83xx_spi->count) {
382 if (mpc83xx_spi->tx) {
383 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
384 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
385 word);
386 }
387 } else {
388 complete(&mpc83xx_spi->done);
389 }
390
391 /* Clear the events */
392 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
393
394 return ret;
395}
396
397static int __init mpc83xx_spi_probe(struct platform_device *dev)
398{
399 struct spi_master *master;
400 struct mpc83xx_spi *mpc83xx_spi;
401 struct fsl_spi_platform_data *pdata;
402 struct resource *r;
403 u32 regval;
404 int ret = 0;
405
406 /* Get resources(memory, IRQ) associated with the device */
407 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
408
409 if (master == NULL) {
410 ret = -ENOMEM;
411 goto err;
412 }
413
414 platform_set_drvdata(dev, master);
415 pdata = dev->dev.platform_data;
416
417 if (pdata == NULL) {
418 ret = -ENODEV;
419 goto free_master;
420 }
421
422 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
423 if (r == NULL) {
424 ret = -ENODEV;
425 goto free_master;
426 }
Kumar Galaccf06992006-05-20 15:00:15 -0700427 mpc83xx_spi = spi_master_get_devdata(master);
428 mpc83xx_spi->bitbang.master = spi_master_get(master);
429 mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
430 mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
431 mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
432 mpc83xx_spi->sysclk = pdata->sysclk;
433 mpc83xx_spi->activate_cs = pdata->activate_cs;
434 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700435 mpc83xx_spi->qe_mode = pdata->qe_mode;
Kumar Galaccf06992006-05-20 15:00:15 -0700436 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
437 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
438
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700439 mpc83xx_spi->rx_shift = 0;
440 mpc83xx_spi->tx_shift = 0;
441 if (mpc83xx_spi->qe_mode) {
442 mpc83xx_spi->rx_shift = 16;
443 mpc83xx_spi->tx_shift = 24;
444 }
445
Kumar Galaccf06992006-05-20 15:00:15 -0700446 mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
447 init_completion(&mpc83xx_spi->done);
448
449 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
450 if (mpc83xx_spi->base == NULL) {
451 ret = -ENOMEM;
452 goto put_master;
453 }
454
455 mpc83xx_spi->irq = platform_get_irq(dev, 0);
456
457 if (mpc83xx_spi->irq < 0) {
458 ret = -ENXIO;
459 goto unmap_io;
460 }
461
462 /* Register for SPI Interrupt */
463 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
464 0, "mpc83xx_spi", mpc83xx_spi);
465
466 if (ret != 0)
467 goto unmap_io;
468
469 master->bus_num = pdata->bus_num;
470 master->num_chipselect = pdata->max_chipselect;
471
472 /* SPI controller initializations */
473 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
474 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
475 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
476 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
477
478 /* Enable SPI interface */
479 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700480 if (pdata->qe_mode)
481 regval |= SPMODE_OP;
482
Kumar Galaccf06992006-05-20 15:00:15 -0700483 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
484
485 ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
486
487 if (ret != 0)
488 goto free_irq;
489
490 printk(KERN_INFO
491 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
492 dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
493
494 return ret;
495
496free_irq:
497 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
498unmap_io:
499 iounmap(mpc83xx_spi->base);
500put_master:
501 spi_master_put(master);
502free_master:
503 kfree(master);
504err:
505 return ret;
506}
507
508static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
509{
510 struct mpc83xx_spi *mpc83xx_spi;
511 struct spi_master *master;
512
513 master = platform_get_drvdata(dev);
514 mpc83xx_spi = spi_master_get_devdata(master);
515
516 spi_bitbang_stop(&mpc83xx_spi->bitbang);
517 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
518 iounmap(mpc83xx_spi->base);
519 spi_master_put(mpc83xx_spi->bitbang.master);
520
521 return 0;
522}
523
524static struct platform_driver mpc83xx_spi_driver = {
525 .probe = mpc83xx_spi_probe,
526 .remove = __devexit_p(mpc83xx_spi_remove),
527 .driver = {
528 .name = "mpc83xx_spi",
529 },
530};
531
532static int __init mpc83xx_spi_init(void)
533{
534 return platform_driver_register(&mpc83xx_spi_driver);
535}
536
537static void __exit mpc83xx_spi_exit(void)
538{
539 platform_driver_unregister(&mpc83xx_spi_driver);
540}
541
542module_init(mpc83xx_spi_init);
543module_exit(mpc83xx_spi_exit);
544
545MODULE_AUTHOR("Kumar Gala");
546MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
547MODULE_LICENSE("GPL");