blob: 0038dc4c06c7dbd89b7cef8f424f374fc250da42 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
Sergei Shtylyovd8178982009-12-07 23:39:38 +040014 * Look into engine reset on timeout errors. Should not be required.
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 */
16
Joe Perches8d7b1c72011-01-31 08:39:24 -080017#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
Jeff Garzik669a5db2006-08-29 18:12:40 -040018
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
Jeff Garzik669a5db2006-08-29 18:12:40 -040022#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt366"
Joe Perches8d7b1c72011-01-31 08:39:24 -080028#define DRV_VERSION "0.6.11"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30struct hpt_clock {
Tejun Heo6ecb6f22009-01-08 16:29:20 -050031 u8 xfer_mode;
Jeff Garzik669a5db2006-08-29 18:12:40 -040032 u32 timing;
33};
34
35/* key for bus clock timings
36 * bit
Sergei Shtylyov82beb5d2009-11-25 00:17:31 +040037 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
38 * cycles = value + 1
39 * 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
40 * cycles = value + 1
41 * 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040042 * register access.
Sergei Shtylyov82beb5d2009-11-25 00:17:31 +040043 * 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040044 * register access.
Sergei Shtylyov82beb5d2009-11-25 00:17:31 +040045 * 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
46 * 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
47 * 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040048 * register access.
Sergei Shtylyov82beb5d2009-11-25 00:17:31 +040049 * 28 UDMA enable.
50 * 29 DMA enable.
51 * 30 PIO_MST enable. If set, the chip is in bus master mode during
52 * PIO xfer.
Jeff Garzik669a5db2006-08-29 18:12:40 -040053 * 31 FIFO enable.
54 */
55
56static const struct hpt_clock hpt366_40[] = {
57 { XFER_UDMA_4, 0x900fd943 },
58 { XFER_UDMA_3, 0x900ad943 },
59 { XFER_UDMA_2, 0x900bd943 },
60 { XFER_UDMA_1, 0x9008d943 },
61 { XFER_UDMA_0, 0x9008d943 },
62
63 { XFER_MW_DMA_2, 0xa008d943 },
64 { XFER_MW_DMA_1, 0xa010d955 },
65 { XFER_MW_DMA_0, 0xa010d9fc },
66
67 { XFER_PIO_4, 0xc008d963 },
68 { XFER_PIO_3, 0xc010d974 },
69 { XFER_PIO_2, 0xc010d997 },
70 { XFER_PIO_1, 0xc010d9c7 },
71 { XFER_PIO_0, 0xc018d9d9 },
72 { 0, 0x0120d9d9 }
73};
74
75static const struct hpt_clock hpt366_33[] = {
76 { XFER_UDMA_4, 0x90c9a731 },
77 { XFER_UDMA_3, 0x90cfa731 },
78 { XFER_UDMA_2, 0x90caa731 },
79 { XFER_UDMA_1, 0x90cba731 },
80 { XFER_UDMA_0, 0x90c8a731 },
81
82 { XFER_MW_DMA_2, 0xa0c8a731 },
83 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
84 { XFER_MW_DMA_0, 0xa0c8a797 },
85
86 { XFER_PIO_4, 0xc0c8a731 },
87 { XFER_PIO_3, 0xc0c8a742 },
88 { XFER_PIO_2, 0xc0d0a753 },
89 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
90 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
91 { 0, 0x0120a7a7 }
92};
93
94static const struct hpt_clock hpt366_25[] = {
95 { XFER_UDMA_4, 0x90c98521 },
96 { XFER_UDMA_3, 0x90cf8521 },
97 { XFER_UDMA_2, 0x90cf8521 },
98 { XFER_UDMA_1, 0x90cb8521 },
99 { XFER_UDMA_0, 0x90cb8521 },
100
101 { XFER_MW_DMA_2, 0xa0ca8521 },
102 { XFER_MW_DMA_1, 0xa0ca8532 },
103 { XFER_MW_DMA_0, 0xa0ca8575 },
104
105 { XFER_PIO_4, 0xc0ca8521 },
106 { XFER_PIO_3, 0xc0ca8532 },
107 { XFER_PIO_2, 0xc0ca8542 },
108 { XFER_PIO_1, 0xc0d08572 },
109 { XFER_PIO_0, 0xc0d08585 },
110 { 0, 0x01208585 }
111};
112
Bartlomiej Zolnierkiewiczdc5e44e2011-10-11 19:52:31 +0200113/**
114 * hpt36x_find_mode - find the hpt36x timing
115 * @ap: ATA port
116 * @speed: transfer mode
117 *
118 * Return the 32bit register programming information for this channel
119 * that matches the speed provided.
120 */
121
122static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
123{
124 struct hpt_clock *clocks = ap->host->private_data;
125
126 while (clocks->xfer_mode) {
127 if (clocks->xfer_mode == speed)
128 return clocks->timing;
129 clocks++;
130 }
131 BUG();
132 return 0xffffffffU; /* silence compiler warning */
133}
134
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300135static const char * const bad_ata33[] = {
136 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
137 "Maxtor 90845U3", "Maxtor 90650U2",
138 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
139 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
140 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
141 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400142 "Maxtor 90510D4",
143 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300144 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
145 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
146 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
147 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400148 NULL
149};
150
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300151static const char * const bad_ata66_4[] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400152 "IBM-DTLA-307075",
153 "IBM-DTLA-307060",
154 "IBM-DTLA-307045",
155 "IBM-DTLA-307030",
156 "IBM-DTLA-307020",
157 "IBM-DTLA-307015",
158 "IBM-DTLA-305040",
159 "IBM-DTLA-305030",
160 "IBM-DTLA-305020",
161 "IC35L010AVER07-0",
162 "IC35L020AVER07-0",
163 "IC35L030AVER07-0",
164 "IC35L040AVER07-0",
165 "IC35L060AVER07-0",
166 "WDC AC310200R",
167 NULL
168};
169
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300170static const char * const bad_ata66_3[] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400171 "WDC AC310200R",
172 NULL
173};
174
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300175static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
176 const char * const list[])
Jeff Garzik669a5db2006-08-29 18:12:40 -0400177{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900178 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400179 int i = 0;
180
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900181 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400182
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900183 while (list[i] != NULL) {
184 if (!strcmp(list[i], model_num)) {
Joe Perches8d7b1c72011-01-31 08:39:24 -0800185 pr_warn("%s is not supported for %s\n",
186 modestr, list[i]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400187 return 1;
188 }
189 i++;
190 }
191 return 0;
192}
193
194/**
195 * hpt366_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400196 * @adev: ATA device
197 *
198 * Block UDMA on devices that cause trouble with this controller.
199 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400200
Alan Coxa76b62c2007-03-09 09:34:07 -0500201static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400202{
203 if (adev->class == ATA_DEV_ATA) {
204 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
205 mask &= ~ATA_MASK_UDMA;
206 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
Alan Cox6ddd6862008-02-26 13:35:54 -0800207 mask &= ~(0xF8 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400208 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
Alan Cox6ddd6862008-02-26 13:35:54 -0800209 mask &= ~(0xF0 << ATA_SHIFT_UDMA);
Tejun Heo3ee89f12008-12-09 17:14:04 +0900210 } else if (adev->class == ATA_DEV_ATAPI)
211 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
212
Tejun Heoc7087652010-05-10 21:41:34 +0200213 return mask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400214}
215
Alan Coxfecfda52007-03-08 19:34:28 +0000216static int hpt36x_cable_detect(struct ata_port *ap)
217{
Alan Coxfecfda52007-03-08 19:34:28 +0000218 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heobab5b322008-12-09 17:13:19 +0900219 u8 ata66;
Alan Coxfecfda52007-03-08 19:34:28 +0000220
Tejun Heobab5b322008-12-09 17:13:19 +0900221 /*
222 * Each channel of pata_hpt366 occupies separate PCI function
223 * as the primary channel and bit1 indicates the cable type.
224 */
Alan Coxfecfda52007-03-08 19:34:28 +0000225 pci_read_config_byte(pdev, 0x5A, &ata66);
Tejun Heobab5b322008-12-09 17:13:19 +0900226 if (ata66 & 2)
Alan Coxfecfda52007-03-08 19:34:28 +0000227 return ATA_CBL_PATA40;
228 return ATA_CBL_PATA80;
229}
230
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500231static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
232 u8 mode)
233{
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500234 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Sergei Shtylyov859faa82009-12-07 23:36:15 +0400235 u32 addr = 0x40 + 4 * adev->devno;
Bartlomiej Zolnierkiewiczdc5e44e2011-10-11 19:52:31 +0200236 u32 mask, reg, t;
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500237
238 /* determine timing mask and find matching clock entry */
239 if (mode < XFER_MW_DMA_0)
240 mask = 0xc1f8ffff;
241 else if (mode < XFER_UDMA_0)
242 mask = 0x303800ff;
243 else
244 mask = 0x30070000;
245
Bartlomiej Zolnierkiewiczdc5e44e2011-10-11 19:52:31 +0200246 t = hpt36x_find_mode(ap, mode);
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500247
248 /*
249 * Combine new mode bits with old config bits and disable
250 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
251 * problems handling I/O errors later.
252 */
Sergei Shtylyov859faa82009-12-07 23:36:15 +0400253 pci_read_config_dword(pdev, addr, &reg);
Bartlomiej Zolnierkiewiczdc5e44e2011-10-11 19:52:31 +0200254 reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
Sergei Shtylyov859faa82009-12-07 23:36:15 +0400255 pci_write_config_dword(pdev, addr, reg);
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500256}
257
Jeff Garzik669a5db2006-08-29 18:12:40 -0400258/**
259 * hpt366_set_piomode - PIO setup
260 * @ap: ATA interface
261 * @adev: device on the interface
262 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400263 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400264 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400265
Jeff Garzik669a5db2006-08-29 18:12:40 -0400266static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
267{
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500268 hpt366_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400269}
270
271/**
272 * hpt366_set_dmamode - DMA timing setup
273 * @ap: ATA interface
274 * @adev: Device being configured
275 *
276 * Set up the channel for MWDMA or UDMA modes. Much the same as with
277 * PIO, load the mode number and then set MWDMA or UDMA flag.
278 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400279
Jeff Garzik669a5db2006-08-29 18:12:40 -0400280static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
281{
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500282 hpt366_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400283}
284
285static struct scsi_host_template hpt36x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900286 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287};
288
289/*
290 * Configuration for HPT366/68
291 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400292
Jeff Garzik669a5db2006-08-29 18:12:40 -0400293static struct ata_port_operations hpt366_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900294 .inherits = &ata_bmdma_port_ops,
295 .cable_detect = hpt36x_cable_detect,
296 .mode_filter = hpt366_filter,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400297 .set_piomode = hpt366_set_piomode,
298 .set_dmamode = hpt366_set_dmamode,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400299};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400300
301/**
Alanaa54ab12006-11-27 16:24:15 +0000302 * hpt36x_init_chipset - common chip setup
303 * @dev: PCI device
304 *
305 * Perform the chip setup work that must be done at both init and
306 * resume time
307 */
308
309static void hpt36x_init_chipset(struct pci_dev *dev)
310{
311 u8 drive_fast;
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300312
Alanaa54ab12006-11-27 16:24:15 +0000313 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
314 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
315 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
316 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
317
318 pci_read_config_byte(dev, 0x51, &drive_fast);
319 if (drive_fast & 0x80)
320 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
321}
322
323/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400324 * hpt36x_init_one - Initialise an HPT366/368
325 * @dev: PCI device
326 * @id: Entry in match table
327 *
328 * Initialise an HPT36x device. There are some interesting complications
329 * here. Firstly the chip may report 366 and be one of several variants.
330 * Secondly all the timings depend on the clock for the chip which we must
331 * detect and look up
332 *
333 * This is the known chip mappings. It may be missing a couple of later
334 * releases.
335 *
336 * Chip version PCI Rev Notes
337 * HPT366 4 (HPT366) 0 UDMA66
338 * HPT366 4 (HPT366) 1 UDMA66
339 * HPT368 4 (HPT366) 2 UDMA66
340 * HPT37x/30x 4 (HPT366) 3+ Other driver
341 *
342 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400343
Jeff Garzik669a5db2006-08-29 18:12:40 -0400344static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
345{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200346 static const struct ata_port_info info_hpt366 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400347 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100348 .pio_mask = ATA_PIO4,
349 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400350 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400351 .port_ops = &hpt366_port_ops
352 };
Tejun Heo887125e2008-03-25 12:22:49 +0900353 const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400354
Arnd Bergmann6ec0a862015-05-19 16:34:05 +0200355 const void *hpriv = NULL;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400356 u32 reg1;
Tejun Heof08048e2008-03-25 12:22:47 +0900357 int rc;
358
359 rc = pcim_enable_device(dev);
360 if (rc)
361 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400362
Jeff Garzik669a5db2006-08-29 18:12:40 -0400363 /* May be a later chip in disguise. Check */
364 /* Newer chips are not in the HPT36x driver. Ignore them */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400365 if (dev->revision > 2)
366 return -ENODEV;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400367
Alanaa54ab12006-11-27 16:24:15 +0000368 hpt36x_init_chipset(dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400369
370 pci_read_config_dword(dev, 0x40, &reg1);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400371
Jeff Garzik669a5db2006-08-29 18:12:40 -0400372 /* PCI clocking determines the ATA timing values to use */
373 /* info_hpt366 is safe against re-entry so we can scribble on it */
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300374 switch ((reg1 & 0x700) >> 8) {
375 case 9:
376 hpriv = &hpt366_40;
377 break;
378 case 5:
379 hpriv = &hpt366_25;
380 break;
381 default:
382 hpriv = &hpt366_33;
383 break;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400384 }
385 /* Now kick off ATA set up */
Arnd Bergmann6ec0a862015-05-19 16:34:05 +0200386 return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400387}
388
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +0200389#ifdef CONFIG_PM_SLEEP
Alanaa54ab12006-11-27 16:24:15 +0000390static int hpt36x_reinit_one(struct pci_dev *dev)
391{
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900392 struct ata_host *host = pci_get_drvdata(dev);
Tejun Heof08048e2008-03-25 12:22:47 +0900393 int rc;
394
395 rc = ata_pci_device_do_resume(dev);
396 if (rc)
397 return rc;
Alanaa54ab12006-11-27 16:24:15 +0000398 hpt36x_init_chipset(dev);
Tejun Heof08048e2008-03-25 12:22:47 +0900399 ata_host_resume(host);
400 return 0;
Alanaa54ab12006-11-27 16:24:15 +0000401}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900402#endif
Alanaa54ab12006-11-27 16:24:15 +0000403
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400404static const struct pci_device_id hpt36x[] = {
405 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400406 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400407};
408
409static struct pci_driver hpt36x_pci_driver = {
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300410 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400411 .id_table = hpt36x,
Sergei Shtylyov28cd4b62010-12-28 23:06:38 +0300412 .probe = hpt36x_init_one,
Alanaa54ab12006-11-27 16:24:15 +0000413 .remove = ata_pci_remove_one,
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +0200414#ifdef CONFIG_PM_SLEEP
Alanaa54ab12006-11-27 16:24:15 +0000415 .suspend = ata_pci_device_suspend,
416 .resume = hpt36x_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900417#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400418};
419
Axel Lin2fc75da2012-04-19 13:43:05 +0800420module_pci_driver(hpt36x_pci_driver);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400421
Jeff Garzik669a5db2006-08-29 18:12:40 -0400422MODULE_AUTHOR("Alan Cox");
423MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
424MODULE_LICENSE("GPL");
425MODULE_DEVICE_TABLE(pci, hpt36x);
426MODULE_VERSION(DRV_VERSION);