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Linus Walleij6c009ab2010-09-13 00:35:22 +02001/*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19#include <linux/clk.h>
Vipin Kumar4774fb02012-03-14 11:47:18 +053020#include <linux/completion.h>
21#include <linux/dmaengine.h>
22#include <linux/dma-direction.h>
23#include <linux/dma-mapping.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020024#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/resource.h>
28#include <linux/sched.h>
29#include <linux/types.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/nand_ecc.h>
33#include <linux/platform_device.h>
Stefan Roeseeea62812012-03-16 10:19:31 +010034#include <linux/of.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020035#include <linux/mtd/partitions.h>
36#include <linux/io.h>
37#include <linux/slab.h>
38#include <linux/mtd/fsmc.h>
Linus Walleij593cd872010-11-29 13:52:19 +010039#include <linux/amba/bus.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020040#include <mtd/mtd-abi.h>
41
Bhavna Yadave29ee572012-03-07 17:00:50 +053042static struct nand_ecclayout fsmc_ecc1_128_layout = {
Linus Walleij6c009ab2010-09-13 00:35:22 +020043 .eccbytes = 24,
44 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
45 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
46 .oobfree = {
47 {.offset = 8, .length = 8},
48 {.offset = 24, .length = 8},
49 {.offset = 40, .length = 8},
50 {.offset = 56, .length = 8},
51 {.offset = 72, .length = 8},
52 {.offset = 88, .length = 8},
53 {.offset = 104, .length = 8},
54 {.offset = 120, .length = 8}
55 }
56};
57
Bhavna Yadave29ee572012-03-07 17:00:50 +053058static struct nand_ecclayout fsmc_ecc1_64_layout = {
59 .eccbytes = 12,
60 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
61 .oobfree = {
62 {.offset = 8, .length = 8},
63 {.offset = 24, .length = 8},
64 {.offset = 40, .length = 8},
65 {.offset = 56, .length = 8},
66 }
67};
68
69static struct nand_ecclayout fsmc_ecc1_16_layout = {
70 .eccbytes = 3,
71 .eccpos = {2, 3, 4},
72 .oobfree = {
73 {.offset = 8, .length = 8},
74 }
75};
76
77/*
78 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
79 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
80 * bytes are free for use.
81 */
82static struct nand_ecclayout fsmc_ecc4_256_layout = {
83 .eccbytes = 208,
84 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
85 9, 10, 11, 12, 13, 14,
86 18, 19, 20, 21, 22, 23, 24,
87 25, 26, 27, 28, 29, 30,
88 34, 35, 36, 37, 38, 39, 40,
89 41, 42, 43, 44, 45, 46,
90 50, 51, 52, 53, 54, 55, 56,
91 57, 58, 59, 60, 61, 62,
92 66, 67, 68, 69, 70, 71, 72,
93 73, 74, 75, 76, 77, 78,
94 82, 83, 84, 85, 86, 87, 88,
95 89, 90, 91, 92, 93, 94,
96 98, 99, 100, 101, 102, 103, 104,
97 105, 106, 107, 108, 109, 110,
98 114, 115, 116, 117, 118, 119, 120,
99 121, 122, 123, 124, 125, 126,
100 130, 131, 132, 133, 134, 135, 136,
101 137, 138, 139, 140, 141, 142,
102 146, 147, 148, 149, 150, 151, 152,
103 153, 154, 155, 156, 157, 158,
104 162, 163, 164, 165, 166, 167, 168,
105 169, 170, 171, 172, 173, 174,
106 178, 179, 180, 181, 182, 183, 184,
107 185, 186, 187, 188, 189, 190,
108 194, 195, 196, 197, 198, 199, 200,
109 201, 202, 203, 204, 205, 206,
110 210, 211, 212, 213, 214, 215, 216,
111 217, 218, 219, 220, 221, 222,
112 226, 227, 228, 229, 230, 231, 232,
113 233, 234, 235, 236, 237, 238,
114 242, 243, 244, 245, 246, 247, 248,
115 249, 250, 251, 252, 253, 254
116 },
117 .oobfree = {
118 {.offset = 15, .length = 3},
119 {.offset = 31, .length = 3},
120 {.offset = 47, .length = 3},
121 {.offset = 63, .length = 3},
122 {.offset = 79, .length = 3},
123 {.offset = 95, .length = 3},
124 {.offset = 111, .length = 3},
125 {.offset = 127, .length = 3},
126 {.offset = 143, .length = 3},
127 {.offset = 159, .length = 3},
128 {.offset = 175, .length = 3},
129 {.offset = 191, .length = 3},
130 {.offset = 207, .length = 3},
131 {.offset = 223, .length = 3},
132 {.offset = 239, .length = 3},
133 {.offset = 255, .length = 1}
134 }
135};
136
137/*
Armando Visconti0c78e932012-03-07 17:00:55 +0530138 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140 * bytes are free for use.
141 */
142static struct nand_ecclayout fsmc_ecc4_224_layout = {
143 .eccbytes = 104,
144 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
145 9, 10, 11, 12, 13, 14,
146 18, 19, 20, 21, 22, 23, 24,
147 25, 26, 27, 28, 29, 30,
148 34, 35, 36, 37, 38, 39, 40,
149 41, 42, 43, 44, 45, 46,
150 50, 51, 52, 53, 54, 55, 56,
151 57, 58, 59, 60, 61, 62,
152 66, 67, 68, 69, 70, 71, 72,
153 73, 74, 75, 76, 77, 78,
154 82, 83, 84, 85, 86, 87, 88,
155 89, 90, 91, 92, 93, 94,
156 98, 99, 100, 101, 102, 103, 104,
157 105, 106, 107, 108, 109, 110,
158 114, 115, 116, 117, 118, 119, 120,
159 121, 122, 123, 124, 125, 126
160 },
161 .oobfree = {
162 {.offset = 15, .length = 3},
163 {.offset = 31, .length = 3},
164 {.offset = 47, .length = 3},
165 {.offset = 63, .length = 3},
166 {.offset = 79, .length = 3},
167 {.offset = 95, .length = 3},
168 {.offset = 111, .length = 3},
169 {.offset = 127, .length = 97}
170 }
171};
172
173/*
Bhavna Yadave29ee572012-03-07 17:00:50 +0530174 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176 * bytes are free for use.
177 */
178static struct nand_ecclayout fsmc_ecc4_128_layout = {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200179 .eccbytes = 104,
180 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
181 9, 10, 11, 12, 13, 14,
182 18, 19, 20, 21, 22, 23, 24,
183 25, 26, 27, 28, 29, 30,
184 34, 35, 36, 37, 38, 39, 40,
185 41, 42, 43, 44, 45, 46,
186 50, 51, 52, 53, 54, 55, 56,
187 57, 58, 59, 60, 61, 62,
188 66, 67, 68, 69, 70, 71, 72,
189 73, 74, 75, 76, 77, 78,
190 82, 83, 84, 85, 86, 87, 88,
191 89, 90, 91, 92, 93, 94,
192 98, 99, 100, 101, 102, 103, 104,
193 105, 106, 107, 108, 109, 110,
194 114, 115, 116, 117, 118, 119, 120,
195 121, 122, 123, 124, 125, 126
196 },
197 .oobfree = {
198 {.offset = 15, .length = 3},
199 {.offset = 31, .length = 3},
200 {.offset = 47, .length = 3},
201 {.offset = 63, .length = 3},
202 {.offset = 79, .length = 3},
203 {.offset = 95, .length = 3},
204 {.offset = 111, .length = 3},
205 {.offset = 127, .length = 1}
206 }
207};
208
209/*
Bhavna Yadave29ee572012-03-07 17:00:50 +0530210 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212 * bytes are free for use.
213 */
214static struct nand_ecclayout fsmc_ecc4_64_layout = {
215 .eccbytes = 52,
216 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
217 9, 10, 11, 12, 13, 14,
218 18, 19, 20, 21, 22, 23, 24,
219 25, 26, 27, 28, 29, 30,
220 34, 35, 36, 37, 38, 39, 40,
221 41, 42, 43, 44, 45, 46,
222 50, 51, 52, 53, 54, 55, 56,
223 57, 58, 59, 60, 61, 62,
224 },
225 .oobfree = {
226 {.offset = 15, .length = 3},
227 {.offset = 31, .length = 3},
228 {.offset = 47, .length = 3},
229 {.offset = 63, .length = 1},
230 }
231};
232
233/*
234 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236 * byte is free for use.
237 */
238static struct nand_ecclayout fsmc_ecc4_16_layout = {
239 .eccbytes = 13,
240 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
241 9, 10, 11, 12, 13, 14
242 },
243 .oobfree = {
244 {.offset = 15, .length = 1},
245 }
246};
247
248/*
Linus Walleij6c009ab2010-09-13 00:35:22 +0200249 * ECC placement definitions in oobfree type format.
250 * There are 13 bytes of ecc for every 512 byte block and it has to be read
251 * consecutively and immediately after the 512 byte data block for hardware to
252 * generate the error bit offsets in 512 byte data.
253 * Managing the ecc bytes in the following way makes it easier for software to
254 * read ecc bytes consecutive to data bytes. This way is similar to
255 * oobfree structure maintained already in generic nand driver
256 */
257static struct fsmc_eccplace fsmc_ecc4_lp_place = {
258 .eccplace = {
259 {.offset = 2, .length = 13},
260 {.offset = 18, .length = 13},
261 {.offset = 34, .length = 13},
262 {.offset = 50, .length = 13},
263 {.offset = 66, .length = 13},
264 {.offset = 82, .length = 13},
265 {.offset = 98, .length = 13},
266 {.offset = 114, .length = 13}
267 }
268};
269
Linus Walleij6c009ab2010-09-13 00:35:22 +0200270static struct fsmc_eccplace fsmc_ecc4_sp_place = {
271 .eccplace = {
272 {.offset = 0, .length = 4},
273 {.offset = 6, .length = 9}
274 }
275};
276
Linus Walleij6c009ab2010-09-13 00:35:22 +0200277/**
Linus Walleij593cd872010-11-29 13:52:19 +0100278 * struct fsmc_nand_data - structure for FSMC NAND device state
Linus Walleij6c009ab2010-09-13 00:35:22 +0200279 *
Linus Walleij593cd872010-11-29 13:52:19 +0100280 * @pid: Part ID on the AMBA PrimeCell format
Linus Walleij6c009ab2010-09-13 00:35:22 +0200281 * @mtd: MTD info for a NAND flash.
282 * @nand: Chip related info for a NAND flash.
Vipin Kumar71470322012-03-14 11:47:07 +0530283 * @partitions: Partition info for a NAND Flash.
284 * @nr_partitions: Total number of partition of a NAND flash.
Linus Walleij6c009ab2010-09-13 00:35:22 +0200285 *
286 * @ecc_place: ECC placing locations in oobfree type format.
287 * @bank: Bank number for probed device.
288 * @clk: Clock structure for FSMC.
289 *
Vipin Kumar4774fb02012-03-14 11:47:18 +0530290 * @read_dma_chan: DMA channel for read access
291 * @write_dma_chan: DMA channel for write access to NAND
292 * @dma_access_complete: Completion structure
293 *
294 * @data_pa: NAND Physical port for Data.
Linus Walleij6c009ab2010-09-13 00:35:22 +0200295 * @data_va: NAND port for Data.
296 * @cmd_va: NAND port for Command.
297 * @addr_va: NAND port for Address.
298 * @regs_va: FSMC regs base address.
299 */
300struct fsmc_nand_data {
Linus Walleij593cd872010-11-29 13:52:19 +0100301 u32 pid;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200302 struct mtd_info mtd;
303 struct nand_chip nand;
Vipin Kumar71470322012-03-14 11:47:07 +0530304 struct mtd_partition *partitions;
305 unsigned int nr_partitions;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200306
307 struct fsmc_eccplace *ecc_place;
308 unsigned int bank;
Vipin Kumar712c4ad2012-03-14 11:47:16 +0530309 struct device *dev;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530310 enum access_mode mode;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200311 struct clk *clk;
312
Vipin Kumar4774fb02012-03-14 11:47:18 +0530313 /* DMA related objects */
314 struct dma_chan *read_dma_chan;
315 struct dma_chan *write_dma_chan;
316 struct completion dma_access_complete;
317
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530318 struct fsmc_nand_timings *dev_timings;
319
Vipin Kumar4774fb02012-03-14 11:47:18 +0530320 dma_addr_t data_pa;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200321 void __iomem *data_va;
322 void __iomem *cmd_va;
323 void __iomem *addr_va;
324 void __iomem *regs_va;
325
326 void (*select_chip)(uint32_t bank, uint32_t busw);
327};
328
329/* Assert CS signal based on chipnr */
330static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
331{
332 struct nand_chip *chip = mtd->priv;
333 struct fsmc_nand_data *host;
334
335 host = container_of(mtd, struct fsmc_nand_data, mtd);
336
337 switch (chipnr) {
338 case -1:
339 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
340 break;
341 case 0:
342 case 1:
343 case 2:
344 case 3:
345 if (host->select_chip)
346 host->select_chip(chipnr,
347 chip->options & NAND_BUSWIDTH_16);
348 break;
349
350 default:
351 BUG();
352 }
353}
354
355/*
356 * fsmc_cmd_ctrl - For facilitaing Hardware access
357 * This routine allows hardware specific access to control-lines(ALE,CLE)
358 */
359static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
360{
361 struct nand_chip *this = mtd->priv;
362 struct fsmc_nand_data *host = container_of(mtd,
363 struct fsmc_nand_data, mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530364 void *__iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200365 unsigned int bank = host->bank;
366
367 if (ctrl & NAND_CTRL_CHANGE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530368 u32 pc;
369
Linus Walleij6c009ab2010-09-13 00:35:22 +0200370 if (ctrl & NAND_CLE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530371 this->IO_ADDR_R = host->cmd_va;
372 this->IO_ADDR_W = host->cmd_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200373 } else if (ctrl & NAND_ALE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530374 this->IO_ADDR_R = host->addr_va;
375 this->IO_ADDR_W = host->addr_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200376 } else {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530377 this->IO_ADDR_R = host->data_va;
378 this->IO_ADDR_W = host->data_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200379 }
380
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530381 pc = readl(FSMC_NAND_REG(regs, bank, PC));
382 if (ctrl & NAND_NCE)
383 pc |= FSMC_ENABLE;
384 else
385 pc &= ~FSMC_ENABLE;
386 writel(pc, FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200387 }
388
389 mb();
390
391 if (cmd != NAND_CMD_NONE)
392 writeb(cmd, this->IO_ADDR_W);
393}
394
395/*
396 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
397 *
398 * This routine initializes timing parameters related to NAND memory access in
399 * FSMC registers
400 */
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530401static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530402 uint32_t busw, struct fsmc_nand_timings *timings)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200403{
404 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530405 uint32_t tclr, tar, thiz, thold, twait, tset;
406 struct fsmc_nand_timings *tims;
407 struct fsmc_nand_timings default_timings = {
408 .tclr = FSMC_TCLR_1,
409 .tar = FSMC_TAR_1,
410 .thiz = FSMC_THIZ_1,
411 .thold = FSMC_THOLD_4,
412 .twait = FSMC_TWAIT_6,
413 .tset = FSMC_TSET_0,
414 };
415
416 if (timings)
417 tims = timings;
418 else
419 tims = &default_timings;
420
421 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
422 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
423 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
424 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
425 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
426 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200427
428 if (busw)
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530429 writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200430 else
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530431 writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200432
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530433 writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
434 FSMC_NAND_REG(regs, bank, PC));
435 writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM));
436 writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200437}
438
439/*
440 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
441 */
442static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
443{
444 struct fsmc_nand_data *host = container_of(mtd,
445 struct fsmc_nand_data, mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530446 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200447 uint32_t bank = host->bank;
448
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530449 writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
450 FSMC_NAND_REG(regs, bank, PC));
451 writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
452 FSMC_NAND_REG(regs, bank, PC));
453 writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
454 FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200455}
456
457/*
458 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300459 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
Linus Walleij6c009ab2010-09-13 00:35:22 +0200460 * max of 8-bits)
461 */
462static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
463 uint8_t *ecc)
464{
465 struct fsmc_nand_data *host = container_of(mtd,
466 struct fsmc_nand_data, mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530467 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200468 uint32_t bank = host->bank;
469 uint32_t ecc_tmp;
470 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
471
472 do {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530473 if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200474 break;
475 else
476 cond_resched();
477 } while (!time_after_eq(jiffies, deadline));
478
Vipin Kumar712c4ad2012-03-14 11:47:16 +0530479 if (time_after_eq(jiffies, deadline)) {
480 dev_err(host->dev, "calculate ecc timed out\n");
481 return -ETIMEDOUT;
482 }
483
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530484 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200485 ecc[0] = (uint8_t) (ecc_tmp >> 0);
486 ecc[1] = (uint8_t) (ecc_tmp >> 8);
487 ecc[2] = (uint8_t) (ecc_tmp >> 16);
488 ecc[3] = (uint8_t) (ecc_tmp >> 24);
489
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530490 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200491 ecc[4] = (uint8_t) (ecc_tmp >> 0);
492 ecc[5] = (uint8_t) (ecc_tmp >> 8);
493 ecc[6] = (uint8_t) (ecc_tmp >> 16);
494 ecc[7] = (uint8_t) (ecc_tmp >> 24);
495
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530496 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200497 ecc[8] = (uint8_t) (ecc_tmp >> 0);
498 ecc[9] = (uint8_t) (ecc_tmp >> 8);
499 ecc[10] = (uint8_t) (ecc_tmp >> 16);
500 ecc[11] = (uint8_t) (ecc_tmp >> 24);
501
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530502 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200503 ecc[12] = (uint8_t) (ecc_tmp >> 16);
504
505 return 0;
506}
507
508/*
509 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300510 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
Linus Walleij6c009ab2010-09-13 00:35:22 +0200511 * max of 1-bit)
512 */
513static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
514 uint8_t *ecc)
515{
516 struct fsmc_nand_data *host = container_of(mtd,
517 struct fsmc_nand_data, mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530518 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200519 uint32_t bank = host->bank;
520 uint32_t ecc_tmp;
521
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530522 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200523 ecc[0] = (uint8_t) (ecc_tmp >> 0);
524 ecc[1] = (uint8_t) (ecc_tmp >> 8);
525 ecc[2] = (uint8_t) (ecc_tmp >> 16);
526
527 return 0;
528}
529
Vipin Kumar519300c2012-03-07 17:00:49 +0530530/* Count the number of 0's in buff upto a max of max_bits */
531static int count_written_bits(uint8_t *buff, int size, int max_bits)
532{
533 int k, written_bits = 0;
534
535 for (k = 0; k < size; k++) {
536 written_bits += hweight8(~buff[k]);
537 if (written_bits > max_bits)
538 break;
539 }
540
541 return written_bits;
542}
543
Vipin Kumar4774fb02012-03-14 11:47:18 +0530544static void dma_complete(void *param)
545{
546 struct fsmc_nand_data *host = param;
547
548 complete(&host->dma_access_complete);
549}
550
551static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
552 enum dma_data_direction direction)
553{
554 struct dma_chan *chan;
555 struct dma_device *dma_dev;
556 struct dma_async_tx_descriptor *tx;
557 dma_addr_t dma_dst, dma_src, dma_addr;
558 dma_cookie_t cookie;
559 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
560 int ret;
561
562 if (direction == DMA_TO_DEVICE)
563 chan = host->write_dma_chan;
564 else if (direction == DMA_FROM_DEVICE)
565 chan = host->read_dma_chan;
566 else
567 return -EINVAL;
568
569 dma_dev = chan->device;
570 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
571
572 if (direction == DMA_TO_DEVICE) {
573 dma_src = dma_addr;
574 dma_dst = host->data_pa;
575 flags |= DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_SKIP_DEST_UNMAP;
576 } else {
577 dma_src = host->data_pa;
578 dma_dst = dma_addr;
579 flags |= DMA_COMPL_DEST_UNMAP_SINGLE | DMA_COMPL_SKIP_SRC_UNMAP;
580 }
581
582 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
583 len, flags);
584
585 if (!tx) {
586 dev_err(host->dev, "device_prep_dma_memcpy error\n");
587 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
588 return -EIO;
589 }
590
591 tx->callback = dma_complete;
592 tx->callback_param = host;
593 cookie = tx->tx_submit(tx);
594
595 ret = dma_submit_error(cookie);
596 if (ret) {
597 dev_err(host->dev, "dma_submit_error %d\n", cookie);
598 return ret;
599 }
600
601 dma_async_issue_pending(chan);
602
603 ret =
604 wait_for_completion_interruptible_timeout(&host->dma_access_complete,
605 msecs_to_jiffies(3000));
606 if (ret <= 0) {
607 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
608 dev_err(host->dev, "wait_for_completion_timeout\n");
609 return ret ? ret : -ETIMEDOUT;
610 }
611
612 return 0;
613}
614
Linus Walleij6c009ab2010-09-13 00:35:22 +0200615/*
Vipin Kumar604e7542012-03-14 11:47:17 +0530616 * fsmc_write_buf - write buffer to chip
617 * @mtd: MTD device structure
618 * @buf: data buffer
619 * @len: number of bytes to write
620 */
621static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
622{
623 int i;
624 struct nand_chip *chip = mtd->priv;
625
626 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
627 IS_ALIGNED(len, sizeof(uint32_t))) {
628 uint32_t *p = (uint32_t *)buf;
629 len = len >> 2;
630 for (i = 0; i < len; i++)
631 writel(p[i], chip->IO_ADDR_W);
632 } else {
633 for (i = 0; i < len; i++)
634 writeb(buf[i], chip->IO_ADDR_W);
635 }
636}
637
638/*
639 * fsmc_read_buf - read chip data into buffer
640 * @mtd: MTD device structure
641 * @buf: buffer to store date
642 * @len: number of bytes to read
643 */
644static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
645{
646 int i;
647 struct nand_chip *chip = mtd->priv;
648
649 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
650 IS_ALIGNED(len, sizeof(uint32_t))) {
651 uint32_t *p = (uint32_t *)buf;
652 len = len >> 2;
653 for (i = 0; i < len; i++)
654 p[i] = readl(chip->IO_ADDR_R);
655 } else {
656 for (i = 0; i < len; i++)
657 buf[i] = readb(chip->IO_ADDR_R);
658 }
659}
660
661/*
Vipin Kumar4774fb02012-03-14 11:47:18 +0530662 * fsmc_read_buf_dma - read chip data into buffer
663 * @mtd: MTD device structure
664 * @buf: buffer to store date
665 * @len: number of bytes to read
666 */
667static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
668{
669 struct fsmc_nand_data *host;
670
671 host = container_of(mtd, struct fsmc_nand_data, mtd);
672 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
673}
674
675/*
676 * fsmc_write_buf_dma - write buffer to chip
677 * @mtd: MTD device structure
678 * @buf: data buffer
679 * @len: number of bytes to write
680 */
681static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
682 int len)
683{
684 struct fsmc_nand_data *host;
685
686 host = container_of(mtd, struct fsmc_nand_data, mtd);
687 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
688}
689
690/*
Linus Walleij6c009ab2010-09-13 00:35:22 +0200691 * fsmc_read_page_hwecc
692 * @mtd: mtd info structure
693 * @chip: nand chip info structure
694 * @buf: buffer to store read data
695 * @page: page number to read
696 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300697 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
Linus Walleij6c009ab2010-09-13 00:35:22 +0200698 * performed in a strict sequence as follows:
699 * data(512 byte) -> ecc(13 byte)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300700 * After this read, fsmc hardware generates and reports error data bits(up to a
Linus Walleij6c009ab2010-09-13 00:35:22 +0200701 * max of 8 bits)
702 */
703static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
704 uint8_t *buf, int page)
705{
706 struct fsmc_nand_data *host = container_of(mtd,
707 struct fsmc_nand_data, mtd);
708 struct fsmc_eccplace *ecc_place = host->ecc_place;
709 int i, j, s, stat, eccsize = chip->ecc.size;
710 int eccbytes = chip->ecc.bytes;
711 int eccsteps = chip->ecc.steps;
712 uint8_t *p = buf;
713 uint8_t *ecc_calc = chip->buffers->ecccalc;
714 uint8_t *ecc_code = chip->buffers->ecccode;
715 int off, len, group = 0;
716 /*
717 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
718 * end up reading 14 bytes (7 words) from oob. The local array is
719 * to maintain word alignment
720 */
721 uint16_t ecc_oob[7];
722 uint8_t *oob = (uint8_t *)&ecc_oob[0];
723
724 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200725 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
726 chip->ecc.hwctl(mtd, NAND_ECC_READ);
727 chip->read_buf(mtd, p, eccsize);
728
729 for (j = 0; j < eccbytes;) {
730 off = ecc_place->eccplace[group].offset;
731 len = ecc_place->eccplace[group].length;
732 group++;
733
734 /*
Vipin Kumar4cbe1bf02012-03-14 11:47:09 +0530735 * length is intentionally kept a higher multiple of 2
736 * to read at least 13 bytes even in case of 16 bit NAND
737 * devices
738 */
Vipin Kumaraea686b2012-03-14 11:47:10 +0530739 if (chip->options & NAND_BUSWIDTH_16)
740 len = roundup(len, 2);
741
Linus Walleij6c009ab2010-09-13 00:35:22 +0200742 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
743 chip->read_buf(mtd, oob + j, len);
744 j += len;
745 }
746
Vipin Kumar519300c2012-03-07 17:00:49 +0530747 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200748 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
749
750 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
751 if (stat < 0)
752 mtd->ecc_stats.failed++;
753 else
754 mtd->ecc_stats.corrected += stat;
755 }
756
757 return 0;
758}
759
760/*
Armando Visconti753e0132012-03-07 17:00:54 +0530761 * fsmc_bch8_correct_data
Linus Walleij6c009ab2010-09-13 00:35:22 +0200762 * @mtd: mtd info structure
763 * @dat: buffer of read data
764 * @read_ecc: ecc read from device spare area
765 * @calc_ecc: ecc calculated from read data
766 *
767 * calc_ecc is a 104 bit information containing maximum of 8 error
768 * offset informations of 13 bits each in 512 bytes of read data.
769 */
Armando Visconti753e0132012-03-07 17:00:54 +0530770static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
Linus Walleij6c009ab2010-09-13 00:35:22 +0200771 uint8_t *read_ecc, uint8_t *calc_ecc)
772{
773 struct fsmc_nand_data *host = container_of(mtd,
774 struct fsmc_nand_data, mtd);
Vipin Kumar519300c2012-03-07 17:00:49 +0530775 struct nand_chip *chip = mtd->priv;
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530776 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200777 unsigned int bank = host->bank;
Armando Viscontia612c2a2012-03-07 17:00:53 +0530778 uint32_t err_idx[8];
Linus Walleij6c009ab2010-09-13 00:35:22 +0200779 uint32_t num_err, i;
Armando Visconti753e0132012-03-07 17:00:54 +0530780 uint32_t ecc1, ecc2, ecc3, ecc4;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200781
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530782 num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
Vipin Kumar519300c2012-03-07 17:00:49 +0530783
784 /* no bit flipping */
785 if (likely(num_err == 0))
786 return 0;
787
788 /* too many errors */
789 if (unlikely(num_err > 8)) {
790 /*
791 * This is a temporary erase check. A newly erased page read
792 * would result in an ecc error because the oob data is also
793 * erased to FF and the calculated ecc for an FF data is not
794 * FF..FF.
795 * This is a workaround to skip performing correction in case
796 * data is FF..FF
797 *
798 * Logic:
799 * For every page, each bit written as 0 is counted until these
800 * number of bits are greater than 8 (the maximum correction
801 * capability of FSMC for each 512 + 13 bytes)
802 */
803
804 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
805 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
806
807 if ((bits_ecc + bits_data) <= 8) {
808 if (bits_data)
809 memset(dat, 0xff, chip->ecc.size);
810 return bits_data;
811 }
812
813 return -EBADMSG;
814 }
815
Linus Walleij6c009ab2010-09-13 00:35:22 +0200816 /*
817 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
818 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
819 *
820 * calc_ecc is a 104 bit information containing maximum of 8 error
821 * offset informations of 13 bits each. calc_ecc is copied into a
822 * uint64_t array and error offset indexes are populated in err_idx
823 * array
824 */
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530825 ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1));
826 ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2));
827 ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3));
828 ecc4 = readl(FSMC_NAND_REG(regs, bank, STS));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200829
Armando Visconti753e0132012-03-07 17:00:54 +0530830 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
831 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
832 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
833 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
834 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
835 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
836 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
837 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200838
839 i = 0;
840 while (num_err--) {
841 change_bit(0, (unsigned long *)&err_idx[i]);
842 change_bit(1, (unsigned long *)&err_idx[i]);
843
Vipin Kumarb533f8d2012-03-14 11:47:11 +0530844 if (err_idx[i] < chip->ecc.size * 8) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200845 change_bit(err_idx[i], (unsigned long *)dat);
846 i++;
847 }
848 }
849 return i;
850}
851
Vipin Kumar4774fb02012-03-14 11:47:18 +0530852static bool filter(struct dma_chan *chan, void *slave)
853{
854 chan->private = slave;
855 return true;
856}
857
Stefan Roeseeea62812012-03-16 10:19:31 +0100858#ifdef CONFIG_OF
859static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
860 struct device_node *np)
861{
862 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
863 u32 val;
864
865 /* Set default NAND width to 8 bits */
866 pdata->width = 8;
867 if (!of_property_read_u32(np, "bank-width", &val)) {
868 if (val == 2) {
869 pdata->width = 16;
870 } else if (val != 1) {
871 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
872 return -EINVAL;
873 }
874 }
875 of_property_read_u32(np, "st,ale-off", &pdata->ale_off);
876 of_property_read_u32(np, "st,cle-off", &pdata->cle_off);
877 if (of_get_property(np, "nand-skip-bbtscan", NULL))
878 pdata->options = NAND_SKIP_BBTSCAN;
879
880 return 0;
881}
882#else
883static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
884 struct device_node *np)
885{
886 return -ENOSYS;
887}
888#endif
889
Linus Walleij6c009ab2010-09-13 00:35:22 +0200890/*
891 * fsmc_nand_probe - Probe function
892 * @pdev: platform device structure
893 */
894static int __init fsmc_nand_probe(struct platform_device *pdev)
895{
896 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
Stefan Roeseeea62812012-03-16 10:19:31 +0100897 struct device_node __maybe_unused *np = pdev->dev.of_node;
898 struct mtd_part_parser_data ppdata = {};
Linus Walleij6c009ab2010-09-13 00:35:22 +0200899 struct fsmc_nand_data *host;
900 struct mtd_info *mtd;
901 struct nand_chip *nand;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200902 struct resource *res;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530903 dma_cap_mask_t mask;
Linus Walleij4ad916b2010-11-29 13:52:06 +0100904 int ret = 0;
Linus Walleij593cd872010-11-29 13:52:19 +0100905 u32 pid;
906 int i;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200907
Stefan Roeseeea62812012-03-16 10:19:31 +0100908 if (np) {
909 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
910 pdev->dev.platform_data = pdata;
911 ret = fsmc_nand_probe_config_dt(pdev, np);
912 if (ret) {
913 dev_err(&pdev->dev, "no platform data\n");
914 return -ENODEV;
915 }
916 }
917
Linus Walleij6c009ab2010-09-13 00:35:22 +0200918 if (!pdata) {
919 dev_err(&pdev->dev, "platform data is NULL\n");
920 return -EINVAL;
921 }
922
923 /* Allocate memory for the device structure (and zero it) */
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530924 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200925 if (!host) {
926 dev_err(&pdev->dev, "failed to allocate device structure\n");
927 return -ENOMEM;
928 }
929
930 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530931 if (!res)
932 return -EINVAL;
933
934 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
935 pdev->name)) {
936 dev_err(&pdev->dev, "Failed to get memory data resourse\n");
937 return -ENOENT;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200938 }
939
Vipin Kumar4774fb02012-03-14 11:47:18 +0530940 host->data_pa = (dma_addr_t)res->start;
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530941 host->data_va = devm_ioremap(&pdev->dev, res->start,
942 resource_size(res));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200943 if (!host->data_va) {
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530944 dev_err(&pdev->dev, "data ioremap failed\n");
945 return -ENOMEM;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200946 }
947
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530948 if (!devm_request_mem_region(&pdev->dev, res->start + pdata->ale_off,
949 resource_size(res), pdev->name)) {
950 dev_err(&pdev->dev, "Failed to get memory ale resourse\n");
951 return -ENOENT;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200952 }
953
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530954 host->addr_va = devm_ioremap(&pdev->dev, res->start + pdata->ale_off,
Shiraz Hashimb2acc922012-03-07 17:00:51 +0530955 resource_size(res));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200956 if (!host->addr_va) {
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530957 dev_err(&pdev->dev, "ale ioremap failed\n");
958 return -ENOMEM;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200959 }
960
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530961 if (!devm_request_mem_region(&pdev->dev, res->start + pdata->cle_off,
962 resource_size(res), pdev->name)) {
963 dev_err(&pdev->dev, "Failed to get memory cle resourse\n");
964 return -ENOENT;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200965 }
966
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530967 host->cmd_va = devm_ioremap(&pdev->dev, res->start + pdata->cle_off,
968 resource_size(res));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200969 if (!host->cmd_va) {
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530970 dev_err(&pdev->dev, "ale ioremap failed\n");
971 return -ENOMEM;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200972 }
973
974 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530975 if (!res)
976 return -EINVAL;
977
978 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
979 pdev->name)) {
980 dev_err(&pdev->dev, "Failed to get memory regs resourse\n");
981 return -ENOENT;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200982 }
983
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530984 host->regs_va = devm_ioremap(&pdev->dev, res->start,
985 resource_size(res));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200986 if (!host->regs_va) {
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530987 dev_err(&pdev->dev, "regs ioremap failed\n");
988 return -ENOMEM;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200989 }
990
991 host->clk = clk_get(&pdev->dev, NULL);
992 if (IS_ERR(host->clk)) {
993 dev_err(&pdev->dev, "failed to fetch block clock\n");
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530994 return PTR_ERR(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200995 }
996
997 ret = clk_enable(host->clk);
998 if (ret)
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530999 goto err_clk_enable;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001000
Linus Walleij593cd872010-11-29 13:52:19 +01001001 /*
1002 * This device ID is actually a common AMBA ID as used on the
1003 * AMBA PrimeCell bus. However it is not a PrimeCell.
1004 */
1005 for (pid = 0, i = 0; i < 4; i++)
1006 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
1007 host->pid = pid;
1008 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
1009 "revision %02x, config %02x\n",
1010 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1011 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1012
Linus Walleij6c009ab2010-09-13 00:35:22 +02001013 host->bank = pdata->bank;
1014 host->select_chip = pdata->select_bank;
Vipin Kumar71470322012-03-14 11:47:07 +05301015 host->partitions = pdata->partitions;
1016 host->nr_partitions = pdata->nr_partitions;
Vipin Kumar712c4ad2012-03-14 11:47:16 +05301017 host->dev = &pdev->dev;
Vipin Kumare2f6bce2012-03-14 11:47:14 +05301018 host->dev_timings = pdata->nand_timings;
Vipin Kumar4774fb02012-03-14 11:47:18 +05301019 host->mode = pdata->mode;
1020
1021 if (host->mode == USE_DMA_ACCESS)
1022 init_completion(&host->dma_access_complete);
1023
Linus Walleij6c009ab2010-09-13 00:35:22 +02001024 /* Link all private pointers */
1025 mtd = &host->mtd;
1026 nand = &host->nand;
1027 mtd->priv = nand;
1028 nand->priv = host;
1029
1030 host->mtd.owner = THIS_MODULE;
1031 nand->IO_ADDR_R = host->data_va;
1032 nand->IO_ADDR_W = host->data_va;
1033 nand->cmd_ctrl = fsmc_cmd_ctrl;
1034 nand->chip_delay = 30;
1035
1036 nand->ecc.mode = NAND_ECC_HW;
1037 nand->ecc.hwctl = fsmc_enable_hwecc;
1038 nand->ecc.size = 512;
1039 nand->options = pdata->options;
1040 nand->select_chip = fsmc_select_chip;
Vipin Kumar467e6e72012-03-14 11:47:12 +05301041 nand->badblockbits = 7;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001042
1043 if (pdata->width == FSMC_NAND_BW16)
1044 nand->options |= NAND_BUSWIDTH_16;
1045
Vipin Kumar4774fb02012-03-14 11:47:18 +05301046 switch (host->mode) {
1047 case USE_DMA_ACCESS:
1048 dma_cap_zero(mask);
1049 dma_cap_set(DMA_MEMCPY, mask);
1050 host->read_dma_chan = dma_request_channel(mask, filter,
1051 pdata->read_dma_priv);
1052 if (!host->read_dma_chan) {
1053 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1054 goto err_req_read_chnl;
1055 }
1056 host->write_dma_chan = dma_request_channel(mask, filter,
1057 pdata->write_dma_priv);
1058 if (!host->write_dma_chan) {
1059 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1060 goto err_req_write_chnl;
1061 }
1062 nand->read_buf = fsmc_read_buf_dma;
1063 nand->write_buf = fsmc_write_buf_dma;
1064 break;
1065
1066 default:
1067 case USE_WORD_ACCESS:
Vipin Kumar604e7542012-03-14 11:47:17 +05301068 nand->read_buf = fsmc_read_buf;
1069 nand->write_buf = fsmc_write_buf;
Vipin Kumar4774fb02012-03-14 11:47:18 +05301070 break;
Vipin Kumar604e7542012-03-14 11:47:17 +05301071 }
1072
Vipin Kumar2a5dbead2012-03-14 11:47:19 +05301073 fsmc_nand_setup(host->regs_va, host->bank,
1074 nand->options & NAND_BUSWIDTH_16,
Vipin Kumare2f6bce2012-03-14 11:47:14 +05301075 host->dev_timings);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001076
Linus Walleij593cd872010-11-29 13:52:19 +01001077 if (AMBA_REV_BITS(host->pid) >= 8) {
Linus Walleij6c009ab2010-09-13 00:35:22 +02001078 nand->ecc.read_page = fsmc_read_page_hwecc;
1079 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
Armando Visconti753e0132012-03-07 17:00:54 +05301080 nand->ecc.correct = fsmc_bch8_correct_data;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001081 nand->ecc.bytes = 13;
Mike Dunn6a918ba2012-03-11 14:21:11 -07001082 nand->ecc.strength = 8;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001083 } else {
1084 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1085 nand->ecc.correct = nand_correct_data;
1086 nand->ecc.bytes = 3;
Mike Dunn6a918ba2012-03-11 14:21:11 -07001087 nand->ecc.strength = 1;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001088 }
1089
1090 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001091 * Scan to find existence of the device
Linus Walleij6c009ab2010-09-13 00:35:22 +02001092 */
1093 if (nand_scan_ident(&host->mtd, 1, NULL)) {
1094 ret = -ENXIO;
1095 dev_err(&pdev->dev, "No NAND Device found!\n");
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301096 goto err_scan_ident;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001097 }
1098
Linus Walleij593cd872010-11-29 13:52:19 +01001099 if (AMBA_REV_BITS(host->pid) >= 8) {
Bhavna Yadave29ee572012-03-07 17:00:50 +05301100 switch (host->mtd.oobsize) {
1101 case 16:
1102 nand->ecc.layout = &fsmc_ecc4_16_layout;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001103 host->ecc_place = &fsmc_ecc4_sp_place;
Bhavna Yadave29ee572012-03-07 17:00:50 +05301104 break;
1105 case 64:
1106 nand->ecc.layout = &fsmc_ecc4_64_layout;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001107 host->ecc_place = &fsmc_ecc4_lp_place;
Bhavna Yadave29ee572012-03-07 17:00:50 +05301108 break;
1109 case 128:
1110 nand->ecc.layout = &fsmc_ecc4_128_layout;
1111 host->ecc_place = &fsmc_ecc4_lp_place;
1112 break;
Armando Visconti0c78e932012-03-07 17:00:55 +05301113 case 224:
1114 nand->ecc.layout = &fsmc_ecc4_224_layout;
1115 host->ecc_place = &fsmc_ecc4_lp_place;
1116 break;
Bhavna Yadave29ee572012-03-07 17:00:50 +05301117 case 256:
1118 nand->ecc.layout = &fsmc_ecc4_256_layout;
1119 host->ecc_place = &fsmc_ecc4_lp_place;
1120 break;
1121 default:
1122 printk(KERN_WARNING "No oob scheme defined for "
1123 "oobsize %d\n", mtd->oobsize);
1124 BUG();
Linus Walleij6c009ab2010-09-13 00:35:22 +02001125 }
1126 } else {
Bhavna Yadave29ee572012-03-07 17:00:50 +05301127 switch (host->mtd.oobsize) {
1128 case 16:
1129 nand->ecc.layout = &fsmc_ecc1_16_layout;
1130 break;
1131 case 64:
1132 nand->ecc.layout = &fsmc_ecc1_64_layout;
1133 break;
1134 case 128:
1135 nand->ecc.layout = &fsmc_ecc1_128_layout;
1136 break;
1137 default:
1138 printk(KERN_WARNING "No oob scheme defined for "
1139 "oobsize %d\n", mtd->oobsize);
1140 BUG();
1141 }
Linus Walleij6c009ab2010-09-13 00:35:22 +02001142 }
1143
1144 /* Second stage of scan to fill MTD data-structures */
1145 if (nand_scan_tail(&host->mtd)) {
1146 ret = -ENXIO;
1147 goto err_probe;
1148 }
1149
1150 /*
1151 * The partition information can is accessed by (in the same precedence)
1152 *
1153 * command line through Bootloader,
1154 * platform data,
1155 * default partition information present in driver.
1156 */
Linus Walleij6c009ab2010-09-13 00:35:22 +02001157 /*
Dmitry Eremin-Solenikov8d3f8bb2011-05-29 20:16:57 +04001158 * Check for partition info passed
Linus Walleij6c009ab2010-09-13 00:35:22 +02001159 */
1160 host->mtd.name = "nand";
Stefan Roeseeea62812012-03-16 10:19:31 +01001161 ppdata.of_node = np;
1162 ret = mtd_device_parse_register(&host->mtd, NULL, &ppdata,
Vipin Kumar71470322012-03-14 11:47:07 +05301163 host->partitions, host->nr_partitions);
Jamie Iles99335d02011-05-23 10:23:23 +01001164 if (ret)
Linus Walleij6c009ab2010-09-13 00:35:22 +02001165 goto err_probe;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001166
1167 platform_set_drvdata(pdev, host);
1168 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1169 return 0;
1170
1171err_probe:
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301172err_scan_ident:
Vipin Kumar4774fb02012-03-14 11:47:18 +05301173 if (host->mode == USE_DMA_ACCESS)
1174 dma_release_channel(host->write_dma_chan);
1175err_req_write_chnl:
1176 if (host->mode == USE_DMA_ACCESS)
1177 dma_release_channel(host->read_dma_chan);
1178err_req_read_chnl:
Linus Walleij6c009ab2010-09-13 00:35:22 +02001179 clk_disable(host->clk);
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301180err_clk_enable:
1181 clk_put(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001182 return ret;
1183}
1184
1185/*
1186 * Clean up routine
1187 */
1188static int fsmc_nand_remove(struct platform_device *pdev)
1189{
1190 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1191
1192 platform_set_drvdata(pdev, NULL);
1193
1194 if (host) {
Axel Lin82e023a2011-06-03 13:15:30 +08001195 nand_release(&host->mtd);
Vipin Kumar4774fb02012-03-14 11:47:18 +05301196
1197 if (host->mode == USE_DMA_ACCESS) {
1198 dma_release_channel(host->write_dma_chan);
1199 dma_release_channel(host->read_dma_chan);
1200 }
Linus Walleij6c009ab2010-09-13 00:35:22 +02001201 clk_disable(host->clk);
1202 clk_put(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001203 }
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301204
Linus Walleij6c009ab2010-09-13 00:35:22 +02001205 return 0;
1206}
1207
1208#ifdef CONFIG_PM
1209static int fsmc_nand_suspend(struct device *dev)
1210{
1211 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1212 if (host)
1213 clk_disable(host->clk);
1214 return 0;
1215}
1216
1217static int fsmc_nand_resume(struct device *dev)
1218{
1219 struct fsmc_nand_data *host = dev_get_drvdata(dev);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301220 if (host) {
Linus Walleij6c009ab2010-09-13 00:35:22 +02001221 clk_enable(host->clk);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301222 fsmc_nand_setup(host->regs_va, host->bank,
Vipin Kumare2f6bce2012-03-14 11:47:14 +05301223 host->nand.options & NAND_BUSWIDTH_16,
1224 host->dev_timings);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301225 }
Linus Walleij6c009ab2010-09-13 00:35:22 +02001226 return 0;
1227}
1228
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301229static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001230#endif
1231
Stefan Roeseeea62812012-03-16 10:19:31 +01001232#ifdef CONFIG_OF
1233static const struct of_device_id fsmc_nand_id_table[] = {
1234 { .compatible = "st,spear600-fsmc-nand" },
1235 {}
1236};
1237MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1238#endif
1239
Linus Walleij6c009ab2010-09-13 00:35:22 +02001240static struct platform_driver fsmc_nand_driver = {
1241 .remove = fsmc_nand_remove,
1242 .driver = {
1243 .owner = THIS_MODULE,
1244 .name = "fsmc-nand",
Stefan Roeseeea62812012-03-16 10:19:31 +01001245 .of_match_table = of_match_ptr(fsmc_nand_id_table),
Linus Walleij6c009ab2010-09-13 00:35:22 +02001246#ifdef CONFIG_PM
1247 .pm = &fsmc_nand_pm_ops,
1248#endif
1249 },
1250};
1251
1252static int __init fsmc_nand_init(void)
1253{
1254 return platform_driver_probe(&fsmc_nand_driver,
1255 fsmc_nand_probe);
1256}
1257module_init(fsmc_nand_init);
1258
1259static void __exit fsmc_nand_exit(void)
1260{
1261 platform_driver_unregister(&fsmc_nand_driver);
1262}
1263module_exit(fsmc_nand_exit);
1264
1265MODULE_LICENSE("GPL");
1266MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1267MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");