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Viresh Kumar5df33a62012-04-10 09:02:35 +05301/*
2 * SPEAr6xx machines clock framework source file
3 *
4 * Copyright (C) 2012 ST Microelectronics
Viresh Kumar10d89352012-06-20 12:53:02 -07005 * Viresh Kumar <viresh.linux@gmail.com>
Viresh Kumar5df33a62012-04-10 09:02:35 +05306 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/io.h>
15#include <linux/spinlock_types.h>
Viresh Kumar5df33a62012-04-10 09:02:35 +053016#include "clk.h"
17
18static DEFINE_SPINLOCK(_lock);
19
Arnd Bergmannd9909eb2012-12-02 17:59:57 +010020#define PLL1_CTR (misc_base + 0x008)
21#define PLL1_FRQ (misc_base + 0x00C)
22#define PLL2_CTR (misc_base + 0x014)
23#define PLL2_FRQ (misc_base + 0x018)
24#define PLL_CLK_CFG (misc_base + 0x020)
Viresh Kumar5df33a62012-04-10 09:02:35 +053025 /* PLL_CLK_CFG register masks */
26 #define MCTR_CLK_SHIFT 28
27 #define MCTR_CLK_MASK 3
28
Arnd Bergmannd9909eb2012-12-02 17:59:57 +010029#define CORE_CLK_CFG (misc_base + 0x024)
Viresh Kumar5df33a62012-04-10 09:02:35 +053030 /* CORE CLK CFG register masks */
31 #define HCLK_RATIO_SHIFT 10
32 #define HCLK_RATIO_MASK 2
33 #define PCLK_RATIO_SHIFT 8
34 #define PCLK_RATIO_MASK 2
35
Arnd Bergmannd9909eb2012-12-02 17:59:57 +010036#define PERIP_CLK_CFG (misc_base + 0x028)
Viresh Kumar5df33a62012-04-10 09:02:35 +053037 /* PERIP_CLK_CFG register masks */
38 #define CLCD_CLK_SHIFT 2
39 #define CLCD_CLK_MASK 2
40 #define UART_CLK_SHIFT 4
41 #define UART_CLK_MASK 1
42 #define FIRDA_CLK_SHIFT 5
43 #define FIRDA_CLK_MASK 2
44 #define GPT0_CLK_SHIFT 8
45 #define GPT1_CLK_SHIFT 10
46 #define GPT2_CLK_SHIFT 11
47 #define GPT3_CLK_SHIFT 12
48 #define GPT_CLK_MASK 1
49
Arnd Bergmannd9909eb2012-12-02 17:59:57 +010050#define PERIP1_CLK_ENB (misc_base + 0x02C)
Viresh Kumar5df33a62012-04-10 09:02:35 +053051 /* PERIP1_CLK_ENB register masks */
52 #define UART0_CLK_ENB 3
53 #define UART1_CLK_ENB 4
54 #define SSP0_CLK_ENB 5
55 #define SSP1_CLK_ENB 6
56 #define I2C_CLK_ENB 7
57 #define JPEG_CLK_ENB 8
58 #define FSMC_CLK_ENB 9
59 #define FIRDA_CLK_ENB 10
60 #define GPT2_CLK_ENB 11
61 #define GPT3_CLK_ENB 12
62 #define GPIO2_CLK_ENB 13
63 #define SSP2_CLK_ENB 14
64 #define ADC_CLK_ENB 15
65 #define GPT1_CLK_ENB 11
66 #define RTC_CLK_ENB 17
67 #define GPIO1_CLK_ENB 18
68 #define DMA_CLK_ENB 19
69 #define SMI_CLK_ENB 21
70 #define CLCD_CLK_ENB 22
71 #define GMAC_CLK_ENB 23
72 #define USBD_CLK_ENB 24
73 #define USBH0_CLK_ENB 25
74 #define USBH1_CLK_ENB 26
75
Arnd Bergmannd9909eb2012-12-02 17:59:57 +010076#define PRSC0_CLK_CFG (misc_base + 0x044)
77#define PRSC1_CLK_CFG (misc_base + 0x048)
78#define PRSC2_CLK_CFG (misc_base + 0x04C)
Viresh Kumar5df33a62012-04-10 09:02:35 +053079
Arnd Bergmannd9909eb2012-12-02 17:59:57 +010080#define CLCD_CLK_SYNT (misc_base + 0x05C)
81#define FIRDA_CLK_SYNT (misc_base + 0x060)
82#define UART_CLK_SYNT (misc_base + 0x064)
Viresh Kumar5df33a62012-04-10 09:02:35 +053083
84/* vco rate configuration table, in ascending order of rates */
85static struct pll_rate_tbl pll_rtbl[] = {
86 {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
87 {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
88 {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
89};
90
91/* aux rate configuration table, in ascending order of rates */
92static struct aux_rate_tbl aux_rtbl[] = {
93 /* For PLL1 = 332 MHz */
Deepak Sikrief0fd0a2012-11-10 12:13:45 +053094 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
Viresh Kumar5df33a62012-04-10 09:02:35 +053095 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
96 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
97 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
98};
99
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530100static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
101static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
102static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
103static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
104static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
105static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
Viresh Kumar5df33a62012-04-10 09:02:35 +0530106static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
107 "pll2_clk", };
108
109/* gpt rate configuration table, in ascending order of rates */
110static struct gpt_rate_tbl gpt_rtbl[] = {
111 /* For pll1 = 332 MHz */
112 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
113 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
114 {.mscale = 1, .nscale = 0}, /* 83 MHz */
115};
116
Arnd Bergmannd9909eb2012-12-02 17:59:57 +0100117void __init spear6xx_clk_init(void __iomem *misc_base)
Viresh Kumar5df33a62012-04-10 09:02:35 +0530118{
119 struct clk *clk, *clk1;
120
Viresh Kumar5df33a62012-04-10 09:02:35 +0530121 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
122 32000);
123 clk_register_clkdev(clk, "osc_32k_clk", NULL);
124
125 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
126 30000000);
127 clk_register_clkdev(clk, "osc_30m_clk", NULL);
128
129 /* clock derived from 32 KHz osc clk */
130 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
131 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
132 clk_register_clkdev(clk, NULL, "rtc-spear");
133
134 /* clock derived from 30 MHz osc clk */
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530135 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530136 48000000);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530137 clk_register_clkdev(clk, "pll3_clk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530138
139 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
140 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
141 &_lock, &clk1, NULL);
142 clk_register_clkdev(clk, "vco1_clk", NULL);
143 clk_register_clkdev(clk1, "pll1_clk", NULL);
144
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530145 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
146 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
147 &_lock, &clk1, NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530148 clk_register_clkdev(clk, "vco2_clk", NULL);
149 clk_register_clkdev(clk1, "pll2_clk", NULL);
150
151 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
152 1);
153 clk_register_clkdev(clk, NULL, "wdt");
154
155 /* clock derived from pll1 clk */
Vipul Kumar Samar12499792012-11-10 12:13:43 +0530156 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
157 CLK_SET_RATE_PARENT, 1, 1);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530158 clk_register_clkdev(clk, "cpu_clk", NULL);
159
160 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
161 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
162 HCLK_RATIO_MASK, 0, &_lock);
163 clk_register_clkdev(clk, "ahb_clk", NULL);
164
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530165 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
166 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
167 &_lock, &clk1);
168 clk_register_clkdev(clk, "uart_syn_clk", NULL);
169 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530170
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530171 clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100172 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
173 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
174 &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530175 clk_register_clkdev(clk, "uart_mclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530176
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530177 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
178 UART0_CLK_ENB, 0, &_lock);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530179 clk_register_clkdev(clk, NULL, "d0000000.serial");
180
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530181 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
182 UART1_CLK_ENB, 0, &_lock);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530183 clk_register_clkdev(clk, NULL, "d0080000.serial");
184
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530185 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
186 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
187 &_lock, &clk1);
188 clk_register_clkdev(clk, "firda_syn_clk", NULL);
189 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530190
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530191 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100192 ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
193 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
194 &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530195 clk_register_clkdev(clk, "firda_mclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530196
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530197 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530198 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
199 clk_register_clkdev(clk, NULL, "firda");
200
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530201 clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
202 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
203 &_lock, &clk1);
204 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
205 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530206
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530207 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100208 ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
209 PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
210 &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530211 clk_register_clkdev(clk, "clcd_mclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530212
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530213 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530214 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
215 clk_register_clkdev(clk, NULL, "clcd");
216
217 /* gpt clocks */
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530218 clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530219 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530220 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530221
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530222 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100223 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
224 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530225 clk_register_clkdev(clk, NULL, "gpt0");
226
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530227 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100228 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
229 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530230 clk_register_clkdev(clk, "gpt1_mclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530231
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530232 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530233 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
234 clk_register_clkdev(clk, NULL, "gpt1");
235
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530236 clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530237 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530238 clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530239
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530240 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100241 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
242 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530243 clk_register_clkdev(clk, "gpt2_mclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530244
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530245 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530246 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
247 clk_register_clkdev(clk, NULL, "gpt2");
248
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530249 clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530250 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530251 clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530252
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530253 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100254 ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
255 PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530256 clk_register_clkdev(clk, "gpt3_mclk", NULL);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530257
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530258 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530259 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
260 clk_register_clkdev(clk, NULL, "gpt3");
261
262 /* clock derived from pll3 clk */
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530263 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530264 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
Rajeev Kumardf2449a2012-11-10 12:13:40 +0530265 clk_register_clkdev(clk, NULL, "e1800000.ehci");
266 clk_register_clkdev(clk, NULL, "e1900000.ohci");
Viresh Kumar5df33a62012-04-10 09:02:35 +0530267
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530268 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
Viresh Kumar5df33a62012-04-10 09:02:35 +0530269 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
Rajeev Kumardf2449a2012-11-10 12:13:40 +0530270 clk_register_clkdev(clk, NULL, "e2000000.ehci");
271 clk_register_clkdev(clk, NULL, "e2100000.ohci");
Viresh Kumar5df33a62012-04-10 09:02:35 +0530272
Vipul Kumar Samara8f4bf02012-07-10 17:12:46 +0530273 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
274 USBD_CLK_ENB, 0, &_lock);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530275 clk_register_clkdev(clk, NULL, "designware_udc");
276
277 /* clock derived from ahb clk */
278 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
279 1);
280 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
281
282 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100283 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
284 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
Viresh Kumar5df33a62012-04-10 09:02:35 +0530285 clk_register_clkdev(clk, "ddr_clk", NULL);
286
287 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
288 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
289 PCLK_RATIO_MASK, 0, &_lock);
290 clk_register_clkdev(clk, "apb_clk", NULL);
291
292 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
293 DMA_CLK_ENB, 0, &_lock);
294 clk_register_clkdev(clk, NULL, "fc400000.dma");
295
296 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
297 FSMC_CLK_ENB, 0, &_lock);
298 clk_register_clkdev(clk, NULL, "d1800000.flash");
299
300 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
301 GMAC_CLK_ENB, 0, &_lock);
Stefan Roese3a35fc32012-05-11 10:41:18 +0200302 clk_register_clkdev(clk, NULL, "e0800000.ethernet");
Viresh Kumar5df33a62012-04-10 09:02:35 +0530303
304 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
305 I2C_CLK_ENB, 0, &_lock);
306 clk_register_clkdev(clk, NULL, "d0200000.i2c");
307
308 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
309 JPEG_CLK_ENB, 0, &_lock);
310 clk_register_clkdev(clk, NULL, "jpeg");
311
312 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
313 SMI_CLK_ENB, 0, &_lock);
314 clk_register_clkdev(clk, NULL, "fc000000.flash");
315
316 /* clock derived from apb clk */
317 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
318 ADC_CLK_ENB, 0, &_lock);
319 clk_register_clkdev(clk, NULL, "adc");
320
321 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
322 clk_register_clkdev(clk, NULL, "f0100000.gpio");
323
324 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
325 GPIO1_CLK_ENB, 0, &_lock);
326 clk_register_clkdev(clk, NULL, "fc980000.gpio");
327
328 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
329 GPIO2_CLK_ENB, 0, &_lock);
330 clk_register_clkdev(clk, NULL, "d8100000.gpio");
331
332 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
333 SSP0_CLK_ENB, 0, &_lock);
334 clk_register_clkdev(clk, NULL, "ssp-pl022.0");
335
336 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
337 SSP1_CLK_ENB, 0, &_lock);
338 clk_register_clkdev(clk, NULL, "ssp-pl022.1");
339
340 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
341 SSP2_CLK_ENB, 0, &_lock);
342 clk_register_clkdev(clk, NULL, "ssp-pl022.2");
343}