blob: 5797020864882005d760e1432623cb3d7551a1a0 [file] [log] [blame]
Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_H
17#define __ASM_PGTABLE_H
18
19#include <asm/proc-fns.h>
20
21#include <asm/memory.h>
22#include <asm/pgtable-hwdef.h>
23
24/*
25 * Software defined PTE bits definition.
26 */
Will Deacona6fadf72012-12-18 14:15:15 +000027#define PTE_VALID (_AT(pteval_t, 1) << 0)
Catalin Marinas3676f9e2013-11-27 16:59:27 +000028#define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000029#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
30#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
Steve Capperc2c93e52014-01-15 14:07:13 +000031#define PTE_WRITE (_AT(pteval_t, 1) << 57)
Catalin Marinas3676f9e2013-11-27 16:59:27 +000032#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000033
34/*
35 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
36 */
Catalin Marinas847264fb2013-10-23 16:50:07 +010037#define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000038#define VMALLOC_END (PAGE_OFFSET - UL(0x400000000) - SZ_64K)
39
40#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
41
42#define FIRST_USER_ADDRESS 0
43
44#ifndef __ASSEMBLY__
45extern void __pte_error(const char *file, int line, unsigned long val);
46extern void __pmd_error(const char *file, int line, unsigned long val);
47extern void __pgd_error(const char *file, int line, unsigned long val);
48
49#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
50#ifndef CONFIG_ARM64_64K_PAGES
51#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
52#endif
53#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
54
Catalin Marinasa501e322014-04-03 15:57:15 +010055#ifdef CONFIG_SMP
56#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
57#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
58#else
59#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF)
60#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF)
61#endif
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000062
Catalin Marinasa501e322014-04-03 15:57:15 +010063#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
64#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
65#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000066
Catalin Marinasa501e322014-04-03 15:57:15 +010067#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
68#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
69#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000070
Catalin Marinasa501e322014-04-03 15:57:15 +010071#define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
Will Deacona6fadf72012-12-18 14:15:15 +000072
Catalin Marinasa501e322014-04-03 15:57:15 +010073#define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
74#define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000075
Catalin Marinasa501e322014-04-03 15:57:15 +010076#define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP)
Marc Zyngier36311602012-12-07 18:35:41 +000077#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
78
Catalin Marinasa501e322014-04-03 15:57:15 +010079#define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
Marc Zyngier36311602012-12-07 18:35:41 +000080#define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDWR | PTE_UXN)
81
Catalin Marinasa501e322014-04-03 15:57:15 +010082#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
83#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
84#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
85#define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
86#define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
87#define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
88#define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000089
Catalin Marinasa501e322014-04-03 15:57:15 +010090#define __P000 PAGE_NONE
91#define __P001 PAGE_READONLY
92#define __P010 PAGE_COPY
93#define __P011 PAGE_COPY
Catalin Marinas5a0fdfa2014-05-16 16:44:32 +010094#define __P100 PAGE_READONLY_EXEC
Catalin Marinasa501e322014-04-03 15:57:15 +010095#define __P101 PAGE_READONLY_EXEC
96#define __P110 PAGE_COPY_EXEC
97#define __P111 PAGE_COPY_EXEC
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000098
Catalin Marinasa501e322014-04-03 15:57:15 +010099#define __S000 PAGE_NONE
100#define __S001 PAGE_READONLY
101#define __S010 PAGE_SHARED
102#define __S011 PAGE_SHARED
Catalin Marinas5a0fdfa2014-05-16 16:44:32 +0100103#define __S100 PAGE_READONLY_EXEC
Catalin Marinasa501e322014-04-03 15:57:15 +0100104#define __S101 PAGE_READONLY_EXEC
105#define __S110 PAGE_SHARED_EXEC
106#define __S111 PAGE_SHARED_EXEC
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000107
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000108/*
109 * ZERO_PAGE is a global shared page that is always zero: used
110 * for zero-mapped memory areas etc..
111 */
112extern struct page *empty_zero_page;
113#define ZERO_PAGE(vaddr) (empty_zero_page)
114
115#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
116
117#define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
118
119#define pte_none(pte) (!pte_val(pte))
120#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
121#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
Will Deacon9ab6d022013-06-10 19:34:41 +0100122#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000123
124#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
125#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
126#define pte_unmap(pte) do { } while (0)
127#define pte_unmap_nested(pte) do { } while (0)
128
129/*
130 * The following only work if pte_present(). Undefined behaviour otherwise.
131 */
Steve Capper84fe6822014-02-25 11:38:53 +0000132#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
133#define pte_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
134#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
135#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
136#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
Catalin Marinas8e620b02012-11-15 17:21:16 +0000137#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000138
Will Deacona6fadf72012-12-18 14:15:15 +0000139#define pte_valid_user(pte) \
Will Deacon02522462013-01-09 11:08:10 +0000140 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000141
Steve Capper44b6dfc2014-01-15 14:07:12 +0000142static inline pte_t pte_wrprotect(pte_t pte)
143{
Steve Capperc2c93e52014-01-15 14:07:13 +0000144 pte_val(pte) &= ~PTE_WRITE;
Steve Capper44b6dfc2014-01-15 14:07:12 +0000145 return pte;
146}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000147
Steve Capper44b6dfc2014-01-15 14:07:12 +0000148static inline pte_t pte_mkwrite(pte_t pte)
149{
Steve Capperc2c93e52014-01-15 14:07:13 +0000150 pte_val(pte) |= PTE_WRITE;
Steve Capper44b6dfc2014-01-15 14:07:12 +0000151 return pte;
152}
153
154static inline pte_t pte_mkclean(pte_t pte)
155{
156 pte_val(pte) &= ~PTE_DIRTY;
157 return pte;
158}
159
160static inline pte_t pte_mkdirty(pte_t pte)
161{
162 pte_val(pte) |= PTE_DIRTY;
163 return pte;
164}
165
166static inline pte_t pte_mkold(pte_t pte)
167{
168 pte_val(pte) &= ~PTE_AF;
169 return pte;
170}
171
172static inline pte_t pte_mkyoung(pte_t pte)
173{
174 pte_val(pte) |= PTE_AF;
175 return pte;
176}
177
178static inline pte_t pte_mkspecial(pte_t pte)
179{
180 pte_val(pte) |= PTE_SPECIAL;
181 return pte;
182}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000183
184static inline void set_pte(pte_t *ptep, pte_t pte)
185{
186 *ptep = pte;
187}
188
189extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
190
191static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
192 pte_t *ptep, pte_t pte)
193{
Will Deacona6fadf72012-12-18 14:15:15 +0000194 if (pte_valid_user(pte)) {
Catalin Marinas71fdb6b2014-03-12 16:28:09 +0000195 if (!pte_special(pte) && pte_exec(pte))
Will Deacon02522462013-01-09 11:08:10 +0000196 __sync_icache_dcache(pte, addr);
Steve Capperc2c93e52014-01-15 14:07:13 +0000197 if (pte_dirty(pte) && pte_write(pte))
198 pte_val(pte) &= ~PTE_RDONLY;
199 else
200 pte_val(pte) |= PTE_RDONLY;
Will Deacon02522462013-01-09 11:08:10 +0000201 }
202
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000203 set_pte(ptep, pte);
204}
205
206/*
207 * Huge pte definitions.
208 */
Steve Capper084bd292013-04-10 13:48:00 +0100209#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
210#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
211
212/*
213 * Hugetlb definitions.
214 */
215#define HUGE_MAX_HSTATE 2
216#define HPAGE_SHIFT PMD_SHIFT
217#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
218#define HPAGE_MASK (~(HPAGE_SIZE - 1))
219#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000220
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000221#define __HAVE_ARCH_PTE_SPECIAL
222
Steve Capper9c7e5352014-02-25 10:02:13 +0000223static inline pte_t pmd_pte(pmd_t pmd)
224{
225 return __pte(pmd_val(pmd));
226}
Steve Capperaf074842013-04-19 16:23:57 +0100227
Steve Capper9c7e5352014-02-25 10:02:13 +0000228static inline pmd_t pte_pmd(pte_t pte)
229{
230 return __pmd(pte_val(pte));
231}
Steve Capperaf074842013-04-19 16:23:57 +0100232
233/*
234 * THP definitions.
235 */
Steve Capperaf074842013-04-19 16:23:57 +0100236
237#ifdef CONFIG_TRANSPARENT_HUGEPAGE
238#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
Steve Capper9c7e5352014-02-25 10:02:13 +0000239#define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100240#endif
241
Steve Capper9c7e5352014-02-25 10:02:13 +0000242#define pmd_young(pmd) pte_young(pmd_pte(pmd))
243#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
244#define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd)))
245#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
246#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
247#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
248#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
Will Deacone3a920a2014-06-18 14:06:27 +0100249#define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
Steve Capperaf074842013-04-19 16:23:57 +0100250
Steve Capper9c7e5352014-02-25 10:02:13 +0000251#define __HAVE_ARCH_PMD_WRITE
252#define pmd_write(pmd) pte_write(pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100253
254#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
255
256#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
257#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
258#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
259
260#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
Steve Capper206a2a72014-05-06 14:02:27 +0100261#define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
Steve Capperaf074842013-04-19 16:23:57 +0100262
Will Deaconceb21832014-05-27 19:11:58 +0100263#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100264
265static inline int has_transparent_hugepage(void)
266{
267 return 1;
268}
269
Catalin Marinasa501e322014-04-03 15:57:15 +0100270#define __pgprot_modify(prot,mask,bits) \
271 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
272
Steve Capperaf074842013-04-19 16:23:57 +0100273/*
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000274 * Mark the prot value as uncacheable and unbufferable.
275 */
276#define pgprot_noncached(prot) \
Catalin Marinasde2db742014-03-12 16:07:06 +0000277 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000278#define pgprot_writecombine(prot) \
Catalin Marinasde2db742014-03-12 16:07:06 +0000279 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000280#define __HAVE_PHYS_MEM_ACCESS_PROT
281struct file;
282extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
283 unsigned long size, pgprot_t vma_prot);
284
285#define pmd_none(pmd) (!pmd_val(pmd))
286#define pmd_present(pmd) (pmd_val(pmd))
287
288#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
289
Marc Zyngier36311602012-12-07 18:35:41 +0000290#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
291 PMD_TYPE_TABLE)
292#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
293 PMD_TYPE_SECT)
294
Steve Capper206a2a72014-05-06 14:02:27 +0100295#ifdef ARM64_64K_PAGES
296#define pud_sect(pud) (0)
297#else
298#define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
299 PUD_TYPE_SECT)
300#endif
Marc Zyngier36311602012-12-07 18:35:41 +0000301
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000302static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
303{
304 *pmdp = pmd;
Will Deacon98f76852014-05-02 16:24:10 +0100305 dsb(ishst);
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000306}
307
308static inline void pmd_clear(pmd_t *pmdp)
309{
310 set_pmd(pmdp, __pmd(0));
311}
312
313static inline pte_t *pmd_page_vaddr(pmd_t pmd)
314{
315 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
316}
317
318#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
319
320/*
321 * Conversion functions: convert a page and protection to a page entry,
322 * and a page entry and page directory to the page they refer to.
323 */
324#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
325
326#ifndef CONFIG_ARM64_64K_PAGES
327
328#define pud_none(pud) (!pud_val(pud))
329#define pud_bad(pud) (!(pud_val(pud) & 2))
330#define pud_present(pud) (pud_val(pud))
331
332static inline void set_pud(pud_t *pudp, pud_t pud)
333{
334 *pudp = pud;
Will Deacon98f76852014-05-02 16:24:10 +0100335 dsb(ishst);
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000336}
337
338static inline void pud_clear(pud_t *pudp)
339{
340 set_pud(pudp, __pud(0));
341}
342
343static inline pmd_t *pud_page_vaddr(pud_t pud)
344{
345 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
346}
347
348#endif /* CONFIG_ARM64_64K_PAGES */
349
350/* to find an entry in a page-table-directory */
351#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
352
353#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
354
355/* to find an entry in a kernel page-table-directory */
356#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
357
358/* Find an entry in the second-level page table.. */
359#ifndef CONFIG_ARM64_64K_PAGES
360#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
361static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
362{
363 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
364}
365#endif
366
367/* Find an entry in the third-level page table.. */
Will Deacon9ab6d022013-06-10 19:34:41 +0100368#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000369
370static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
371{
Will Deacona6fadf72012-12-18 14:15:15 +0000372 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
Steve Capperc2c93e52014-01-15 14:07:13 +0000373 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000374 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
375 return pte;
376}
377
Steve Capper9c7e5352014-02-25 10:02:13 +0000378static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
379{
380 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
381}
382
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000383extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
384extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
385
386#define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
387#define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
388
389/*
390 * Encode and decode a swap entry:
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000391 * bits 0-1: present (must be zero)
392 * bit 2: PTE_FILE
393 * bits 3-8: swap type
394 * bits 9-57: swap offset
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000395 */
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000396#define __SWP_TYPE_SHIFT 3
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000397#define __SWP_TYPE_BITS 6
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000398#define __SWP_OFFSET_BITS 49
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000399#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
400#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000401#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000402
403#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000404#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000405#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
406
407#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
408#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
409
410/*
411 * Ensure that there are not more swap files than can be encoded in the kernel
Geert Uytterhoevenaad90612014-03-11 11:23:39 +0100412 * PTEs.
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000413 */
414#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
415
416/*
417 * Encode and decode a file entry:
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000418 * bits 0-1: present (must be zero)
419 * bit 2: PTE_FILE
420 * bits 3-57: file offset / PAGE_SIZE
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000421 */
422#define pte_file(pte) (pte_val(pte) & PTE_FILE)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000423#define pte_to_pgoff(x) (pte_val(x) >> 3)
424#define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000425
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000426#define PTE_FILE_MAX_BITS 55
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000427
428extern int kern_addr_valid(unsigned long addr);
429
430#include <asm-generic/pgtable.h>
431
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000432#define pgtable_cache_init() do { } while (0)
433
434#endif /* !__ASSEMBLY__ */
435
436#endif /* __ASM_PGTABLE_H */