blob: 63751a28381746a7fe730c3a63ce867dc56ac8cf [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090012#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070013
14#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15#define CARDBUS_RESERVE_BUSNR 3
16#define PCI_CFG_SPACE_SIZE 256
17#define PCI_CFG_SPACE_EXP_SIZE 4096
18
19/* Ugh. Need to stop exporting this to modules. */
20LIST_HEAD(pci_root_buses);
21EXPORT_SYMBOL(pci_root_buses);
22
23LIST_HEAD(pci_devices);
24
25#ifdef HAVE_PCI_LEGACY
26/**
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
29 *
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
33 */
34static void pci_create_legacy_files(struct pci_bus *b)
35{
36 b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
37 GFP_ATOMIC);
38 if (b->legacy_io) {
39 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
40 b->legacy_io->attr.name = "legacy_io";
41 b->legacy_io->size = 0xffff;
42 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
43 b->legacy_io->attr.owner = THIS_MODULE;
44 b->legacy_io->read = pci_read_legacy_io;
45 b->legacy_io->write = pci_write_legacy_io;
46 class_device_create_bin_file(&b->class_dev, b->legacy_io);
47
48 /* Allocated above after the legacy_io struct */
49 b->legacy_mem = b->legacy_io + 1;
50 b->legacy_mem->attr.name = "legacy_mem";
51 b->legacy_mem->size = 1024*1024;
52 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
53 b->legacy_mem->attr.owner = THIS_MODULE;
54 b->legacy_mem->mmap = pci_mmap_legacy_mem;
55 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
56 }
57}
58
59void pci_remove_legacy_files(struct pci_bus *b)
60{
61 if (b->legacy_io) {
62 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
63 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
64 kfree(b->legacy_io); /* both are allocated here */
65 }
66}
67#else /* !HAVE_PCI_LEGACY */
68static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
69void pci_remove_legacy_files(struct pci_bus *bus) { return; }
70#endif /* HAVE_PCI_LEGACY */
71
72/*
73 * PCI Bus Class Devices
74 */
Alan Cox4327edf2005-09-10 00:25:49 -070075static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
76 char *buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070077{
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 int ret;
Alan Cox4327edf2005-09-10 00:25:49 -070079 cpumask_t cpumask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
Alan Cox4327edf2005-09-10 00:25:49 -070081 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -070082 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
83 if (ret < PAGE_SIZE)
84 buf[ret++] = '\n';
85 return ret;
86}
87CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
88
89/*
90 * PCI Bus Class
91 */
92static void release_pcibus_dev(struct class_device *class_dev)
93{
94 struct pci_bus *pci_bus = to_pci_bus(class_dev);
95
96 if (pci_bus->bridge)
97 put_device(pci_bus->bridge);
98 kfree(pci_bus);
99}
100
101static struct class pcibus_class = {
102 .name = "pci_bus",
103 .release = &release_pcibus_dev,
104};
105
106static int __init pcibus_class_init(void)
107{
108 return class_register(&pcibus_class);
109}
110postcore_initcall(pcibus_class_init);
111
112/*
113 * Translate the low bits of the PCI base
114 * to the resource type
115 */
116static inline unsigned int pci_calc_resource_flags(unsigned int flags)
117{
118 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
119 return IORESOURCE_IO;
120
121 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
122 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
123
124 return IORESOURCE_MEM;
125}
126
127/*
128 * Find the extent of a PCI decode..
129 */
Olof Johanssonf797f9c2005-06-13 15:52:27 -0700130static u32 pci_size(u32 base, u32 maxbase, u32 mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131{
132 u32 size = mask & maxbase; /* Find the significant bits */
133 if (!size)
134 return 0;
135
136 /* Get the lowest of them to find the decode size, and
137 from that the extent. */
138 size = (size & ~(size-1)) - 1;
139
140 /* base == maxbase can be valid only if the BAR has
141 already been programmed with all 1s. */
142 if (base == maxbase && ((base | size) & mask) != mask)
143 return 0;
144
145 return size;
146}
147
148static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
149{
150 unsigned int pos, reg, next;
151 u32 l, sz;
152 struct resource *res;
153
154 for(pos=0; pos<howmany; pos = next) {
155 next = pos+1;
156 res = &dev->resource[pos];
157 res->name = pci_name(dev);
158 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
159 pci_read_config_dword(dev, reg, &l);
160 pci_write_config_dword(dev, reg, ~0);
161 pci_read_config_dword(dev, reg, &sz);
162 pci_write_config_dword(dev, reg, l);
163 if (!sz || sz == 0xffffffff)
164 continue;
165 if (l == 0xffffffff)
166 l = 0;
167 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
Amos Waterland3c6de922005-09-22 00:48:19 -0700168 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169 if (!sz)
170 continue;
171 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
172 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
173 } else {
174 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
175 if (!sz)
176 continue;
177 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
178 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
179 }
180 res->end = res->start + (unsigned long) sz;
181 res->flags |= pci_calc_resource_flags(l);
182 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
183 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
184 pci_read_config_dword(dev, reg+4, &l);
185 next++;
186#if BITS_PER_LONG == 64
187 res->start |= ((unsigned long) l) << 32;
188 res->end = res->start + sz;
189 pci_write_config_dword(dev, reg+4, ~0);
190 pci_read_config_dword(dev, reg+4, &sz);
191 pci_write_config_dword(dev, reg+4, l);
192 sz = pci_size(l, sz, 0xffffffff);
193 if (sz) {
194 /* This BAR needs > 4GB? Wow. */
195 res->end |= (unsigned long)sz<<32;
196 }
197#else
198 if (l) {
199 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
200 res->start = 0;
201 res->flags = 0;
202 continue;
203 }
204#endif
205 }
206 }
207 if (rom) {
208 dev->rom_base_reg = rom;
209 res = &dev->resource[PCI_ROM_RESOURCE];
210 res->name = pci_name(dev);
211 pci_read_config_dword(dev, rom, &l);
212 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
213 pci_read_config_dword(dev, rom, &sz);
214 pci_write_config_dword(dev, rom, l);
215 if (l == 0xffffffff)
216 l = 0;
217 if (sz && sz != 0xffffffff) {
Amos Waterland3c6de922005-09-22 00:48:19 -0700218 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 if (sz) {
220 res->flags = (l & IORESOURCE_ROM_ENABLE) |
221 IORESOURCE_MEM | IORESOURCE_PREFETCH |
222 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
223 res->start = l & PCI_ROM_ADDRESS_MASK;
224 res->end = res->start + (unsigned long) sz;
225 }
226 }
227 }
228}
229
230void __devinit pci_read_bridge_bases(struct pci_bus *child)
231{
232 struct pci_dev *dev = child->self;
233 u8 io_base_lo, io_limit_lo;
234 u16 mem_base_lo, mem_limit_lo;
235 unsigned long base, limit;
236 struct resource *res;
237 int i;
238
239 if (!dev) /* It's a host bus, nothing to read */
240 return;
241
242 if (dev->transparent) {
243 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
Ivan Kokshaysky90b54922005-06-07 04:07:02 +0400244 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
245 child->resource[i] = child->parent->resource[i - 3];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 }
247
248 for(i=0; i<3; i++)
249 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
250
251 res = child->resource[0];
252 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
253 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
254 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
255 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
256
257 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
258 u16 io_base_hi, io_limit_hi;
259 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
260 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
261 base |= (io_base_hi << 16);
262 limit |= (io_limit_hi << 16);
263 }
264
265 if (base <= limit) {
266 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Daniel Yeisley9d265122005-12-05 07:06:43 -0500267 if (!res->start)
268 res->start = base;
269 if (!res->end)
270 res->end = limit + 0xfff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 }
272
273 res = child->resource[1];
274 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
275 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
276 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
277 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
278 if (base <= limit) {
279 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
280 res->start = base;
281 res->end = limit + 0xfffff;
282 }
283
284 res = child->resource[2];
285 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
286 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
287 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
288 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
289
290 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
291 u32 mem_base_hi, mem_limit_hi;
292 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
293 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
294
295 /*
296 * Some bridges set the base > limit by default, and some
297 * (broken) BIOSes do not initialize them. If we find
298 * this, just assume they are not being used.
299 */
300 if (mem_base_hi <= mem_limit_hi) {
301#if BITS_PER_LONG == 64
302 base |= ((long) mem_base_hi) << 32;
303 limit |= ((long) mem_limit_hi) << 32;
304#else
305 if (mem_base_hi || mem_limit_hi) {
306 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
307 return;
308 }
309#endif
310 }
311 }
312 if (base <= limit) {
313 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
314 res->start = base;
315 res->end = limit + 0xfffff;
316 }
317}
318
319static struct pci_bus * __devinit pci_alloc_bus(void)
320{
321 struct pci_bus *b;
322
323 b = kmalloc(sizeof(*b), GFP_KERNEL);
324 if (b) {
325 memset(b, 0, sizeof(*b));
326 INIT_LIST_HEAD(&b->node);
327 INIT_LIST_HEAD(&b->children);
328 INIT_LIST_HEAD(&b->devices);
329 }
330 return b;
331}
332
333static struct pci_bus * __devinit
334pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
335{
336 struct pci_bus *child;
337 int i;
338
339 /*
340 * Allocate a new bus, and inherit stuff from the parent..
341 */
342 child = pci_alloc_bus();
343 if (!child)
344 return NULL;
345
346 child->self = bridge;
347 child->parent = parent;
348 child->ops = parent->ops;
349 child->sysdata = parent->sysdata;
350 child->bridge = get_device(&bridge->dev);
351
352 child->class_dev.class = &pcibus_class;
353 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
354 class_device_register(&child->class_dev);
355 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
356
357 /*
358 * Set up the primary, secondary and subordinate
359 * bus numbers.
360 */
361 child->number = child->secondary = busnr;
362 child->primary = parent->secondary;
363 child->subordinate = 0xff;
364
365 /* Set up default resource pointers and names.. */
366 for (i = 0; i < 4; i++) {
367 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
368 child->resource[i]->name = child->name;
369 }
370 bridge->subordinate = child;
371
372 return child;
373}
374
375struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
376{
377 struct pci_bus *child;
378
379 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700380 if (child) {
381 spin_lock(&pci_bus_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 list_add_tail(&child->node, &parent->children);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700383 spin_unlock(&pci_bus_lock);
384 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 return child;
386}
387
388static void pci_enable_crs(struct pci_dev *dev)
389{
390 u16 cap, rpctl;
391 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
392 if (!rpcap)
393 return;
394
395 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
396 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
397 return;
398
399 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
400 rpctl |= PCI_EXP_RTCTL_CRSSVE;
401 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
402}
403
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700404static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
405{
406 struct pci_bus *parent = child->parent;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700407
408 /* Attempts to fix that up are really dangerous unless
409 we're going to re-assign all bus numbers. */
410 if (!pcibios_assign_all_busses())
411 return;
412
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700413 while (parent->parent && parent->subordinate < max) {
414 parent->subordinate = max;
415 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
416 parent = parent->parent;
417 }
418}
419
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
421
422/*
423 * If it's a bridge, configure it and scan the bus behind it.
424 * For CardBus bridges, we don't scan behind as the devices will
425 * be handled by the bridge driver itself.
426 *
427 * We need to process bridges in two passes -- first we scan those
428 * already configured by the BIOS and after we are done with all of
429 * them, we proceed to assigning numbers to the remaining buses in
430 * order to avoid overlaps between old and new bus numbers.
431 */
432int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
433{
434 struct pci_bus *child;
435 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100436 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437 u16 bctl;
438
439 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
440
441 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
442 pci_name(dev), buses & 0xffffff, pass);
443
444 /* Disable MasterAbortMode during probing to avoid reporting
445 of bus errors (in some architectures) */
446 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
447 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
448 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
449
450 pci_enable_crs(dev);
451
452 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
453 unsigned int cmax, busnr;
454 /*
455 * Bus already configured by firmware, process it in the first
456 * pass and just note the configuration.
457 */
458 if (pass)
459 return max;
460 busnr = (buses >> 8) & 0xFF;
461
462 /*
463 * If we already got to this bus through a different bridge,
464 * ignore it. This can happen with the i450NX chipset.
465 */
466 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
467 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
468 pci_domain_nr(bus), busnr);
469 return max;
470 }
471
Rajesh Shah6ef6f0e2005-04-28 00:25:49 -0700472 child = pci_add_new_bus(bus, dev, busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 if (!child)
474 return max;
475 child->primary = buses & 0xFF;
476 child->subordinate = (buses >> 16) & 0xFF;
477 child->bridge_ctl = bctl;
478
479 cmax = pci_scan_child_bus(child);
480 if (cmax > max)
481 max = cmax;
482 if (child->subordinate > max)
483 max = child->subordinate;
484 } else {
485 /*
486 * We need to assign a number to this bus which we always
487 * do in the second pass.
488 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700489 if (!pass) {
490 if (pcibios_assign_all_busses())
491 /* Temporarily disable forwarding of the
492 configuration cycles on all bridges in
493 this bus segment to avoid possible
494 conflicts in the second pass between two
495 bridges programmed with overlapping
496 bus ranges. */
497 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
498 buses & ~0xffffff);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 return max;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700500 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501
502 /* Clear errors */
503 pci_write_config_word(dev, PCI_STATUS, 0xffff);
504
Rajesh Shahcc574502005-04-28 00:25:47 -0700505 /* Prevent assigning a bus number that already exists.
506 * This can happen when a bridge is hot-plugged */
507 if (pci_find_bus(pci_domain_nr(bus), max+1))
508 return max;
Rajesh Shah6ef6f0e2005-04-28 00:25:49 -0700509 child = pci_add_new_bus(bus, dev, ++max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510 buses = (buses & 0xff000000)
511 | ((unsigned int)(child->primary) << 0)
512 | ((unsigned int)(child->secondary) << 8)
513 | ((unsigned int)(child->subordinate) << 16);
514
515 /*
516 * yenta.c forces a secondary latency timer of 176.
517 * Copy that behaviour here.
518 */
519 if (is_cardbus) {
520 buses &= ~0xff000000;
521 buses |= CARDBUS_LATENCY_TIMER << 24;
522 }
523
524 /*
525 * We need to blast all three values with a single write.
526 */
527 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
528
529 if (!is_cardbus) {
Ivan Kokshaysky10f43382005-07-29 12:16:22 -0700530 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700531 /*
532 * Adjust subordinate busnr in parent buses.
533 * We do this before scanning for children because
534 * some devices may not be detected if the bios
535 * was lazy.
536 */
537 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 /* Now we can scan all subordinate buses... */
539 max = pci_scan_child_bus(child);
Kristen Accardie3ac86d2006-01-17 16:57:01 -0800540 /*
541 * now fix it up again since we have found
542 * the real value of max.
543 */
544 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545 } else {
546 /*
547 * For CardBus bridges, we leave 4 bus numbers
548 * as cards with a PCI-to-PCI bridge can be
549 * inserted later.
550 */
Dominik Brodowski49887942005-12-08 16:53:12 +0100551 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
552 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700553 if (pci_find_bus(pci_domain_nr(bus),
554 max+i+1))
555 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100556 while (parent->parent) {
557 if ((!pcibios_assign_all_busses()) &&
558 (parent->subordinate > max) &&
559 (parent->subordinate <= max+i)) {
560 j = 1;
561 }
562 parent = parent->parent;
563 }
564 if (j) {
565 /*
566 * Often, there are two cardbus bridges
567 * -- try to leave one valid bus number
568 * for each one.
569 */
570 i /= 2;
571 break;
572 }
573 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700574 max += i;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700575 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576 }
577 /*
578 * Set the subordinate bus number to its real value.
579 */
580 child->subordinate = max;
581 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
582 }
583
584 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
585
586 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
587
Dominik Brodowski49887942005-12-08 16:53:12 +0100588 while (bus->parent) {
589 if ((child->subordinate > bus->subordinate) ||
590 (child->number > bus->subordinate) ||
591 (child->number < bus->number) ||
592 (child->subordinate < bus->number)) {
593 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) may be "
594 "hidden behind%s bridge #%02x (-#%02x)%s\n",
595 child->number, child->subordinate,
596 bus->self->transparent ? " transparent" : " ",
597 bus->number, bus->subordinate,
598 pcibios_assign_all_busses() ? " " :
599 " (try 'pci=assign-busses')");
600 }
601 bus = bus->parent;
602 }
603
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 return max;
605}
606
607/*
608 * Read interrupt line and base address registers.
609 * The architecture-dependent code can tweak these, of course.
610 */
611static void pci_read_irq(struct pci_dev *dev)
612{
613 unsigned char irq;
614
615 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -0800616 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617 if (irq)
618 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
619 dev->irq = irq;
620}
621
622/**
623 * pci_setup_device - fill in class and map information of a device
624 * @dev: the device structure to fill
625 *
626 * Initialize the device structure with information about the device's
627 * vendor,class,memory and IO-space addresses,IRQ lines etc.
628 * Called at initialisation of the PCI subsystem and by CardBus services.
629 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
630 * or CardBus).
631 */
632static int pci_setup_device(struct pci_dev * dev)
633{
634 u32 class;
635
636 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
637 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
638
639 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
640 class >>= 8; /* upper 3 bytes */
641 dev->class = class;
642 class >>= 8;
643
644 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
645 dev->vendor, dev->device, class, dev->hdr_type);
646
647 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700648 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649
650 /* Early fixups, before probing the BARs */
651 pci_fixup_device(pci_fixup_early, dev);
652 class = dev->class >> 8;
653
654 switch (dev->hdr_type) { /* header type */
655 case PCI_HEADER_TYPE_NORMAL: /* standard header */
656 if (class == PCI_CLASS_BRIDGE_PCI)
657 goto bad;
658 pci_read_irq(dev);
659 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
660 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
661 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
662 break;
663
664 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
665 if (class != PCI_CLASS_BRIDGE_PCI)
666 goto bad;
667 /* The PCI-to-PCI bridge spec requires that subtractive
668 decoding (i.e. transparent) bridge must have programming
669 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -0800670 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 dev->transparent = ((dev->class & 0xff) == 1);
672 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
673 break;
674
675 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
676 if (class != PCI_CLASS_BRIDGE_CARDBUS)
677 goto bad;
678 pci_read_irq(dev);
679 pci_read_bases(dev, 1, 0);
680 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
681 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
682 break;
683
684 default: /* unknown header */
685 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
686 pci_name(dev), dev->hdr_type);
687 return -1;
688
689 bad:
690 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
691 pci_name(dev), class, dev->hdr_type);
692 dev->class = PCI_CLASS_NOT_DEFINED;
693 }
694
695 /* We found a fine healthy device, go go go... */
696 return 0;
697}
698
699/**
700 * pci_release_dev - free a pci device structure when all users of it are finished.
701 * @dev: device that's been disconnected
702 *
703 * Will be called only by the device core when all users of this pci device are
704 * done.
705 */
706static void pci_release_dev(struct device *dev)
707{
708 struct pci_dev *pci_dev;
709
710 pci_dev = to_pci_dev(dev);
711 kfree(pci_dev);
712}
713
714/**
715 * pci_cfg_space_size - get the configuration space size of the PCI device.
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700716 * @dev: PCI device
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 *
718 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
719 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
720 * access it. Maybe we don't have a way to generate extended config space
721 * accesses, or the device is behind a reverse Express bridge. So we try
722 * reading the dword at 0x100 which must either be 0 or a valid extended
723 * capability header.
724 */
Benjamin Herrenschmidtac7dc652005-12-13 18:09:16 +1100725int pci_cfg_space_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726{
727 int pos;
728 u32 status;
729
730 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
731 if (!pos) {
732 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
733 if (!pos)
734 goto fail;
735
736 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
737 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
738 goto fail;
739 }
740
741 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
742 goto fail;
743 if (status == 0xffffffff)
744 goto fail;
745
746 return PCI_CFG_SPACE_EXP_SIZE;
747
748 fail:
749 return PCI_CFG_SPACE_SIZE;
750}
751
752static void pci_release_bus_bridge_dev(struct device *dev)
753{
754 kfree(dev);
755}
756
757/*
758 * Read the config data for a PCI device, sanity-check it
759 * and fill in the dev structure...
760 */
761static struct pci_dev * __devinit
762pci_scan_device(struct pci_bus *bus, int devfn)
763{
764 struct pci_dev *dev;
765 u32 l;
766 u8 hdr_type;
767 int delay = 1;
768
769 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
770 return NULL;
771
772 /* some broken boards return 0 or ~0 if a slot is empty: */
773 if (l == 0xffffffff || l == 0x00000000 ||
774 l == 0x0000ffff || l == 0xffff0000)
775 return NULL;
776
777 /* Configuration request Retry Status */
778 while (l == 0xffff0001) {
779 msleep(delay);
780 delay *= 2;
781 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
782 return NULL;
783 /* Card hasn't responded in 60 seconds? Must be stuck. */
784 if (delay > 60 * 1000) {
785 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
786 "responding\n", pci_domain_nr(bus),
787 bus->number, PCI_SLOT(devfn),
788 PCI_FUNC(devfn));
789 return NULL;
790 }
791 }
792
793 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
794 return NULL;
795
796 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
797 if (!dev)
798 return NULL;
799
800 memset(dev, 0, sizeof(struct pci_dev));
801 dev->bus = bus;
802 dev->sysdata = bus->sysdata;
803 dev->dev.parent = bus->bridge;
804 dev->dev.bus = &pci_bus_type;
805 dev->devfn = devfn;
806 dev->hdr_type = hdr_type & 0x7f;
807 dev->multifunction = !!(hdr_type & 0x80);
808 dev->vendor = l & 0xffff;
809 dev->device = (l >> 16) & 0xffff;
810 dev->cfg_size = pci_cfg_space_size(dev);
811
812 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
813 set this higher, assuming the system even supports it. */
814 dev->dma_mask = 0xffffffff;
815 if (pci_setup_device(dev) < 0) {
816 kfree(dev);
817 return NULL;
818 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +1000819
820 return dev;
821}
822
823void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
824{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 device_initialize(&dev->dev);
826 dev->dev.release = pci_release_dev;
827 pci_dev_get(dev);
828
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 dev->dev.dma_mask = &dev->dma_mask;
830 dev->dev.coherent_dma_mask = 0xffffffffull;
831
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 /* Fix up broken headers */
833 pci_fixup_device(pci_fixup_header, dev);
834
835 /*
836 * Add the device to our list of discovered devices
837 * and the bus list for fixup functions, etc.
838 */
839 INIT_LIST_HEAD(&dev->global_list);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700840 spin_lock(&pci_bus_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 list_add_tail(&dev->bus_list, &bus->devices);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700842 spin_unlock(&pci_bus_lock);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +1000843}
844
845struct pci_dev * __devinit
846pci_scan_single_device(struct pci_bus *bus, int devfn)
847{
848 struct pci_dev *dev;
849
850 dev = pci_scan_device(bus, devfn);
851 if (!dev)
852 return NULL;
853
854 pci_device_add(dev, bus);
855 pci_scan_msi_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856
857 return dev;
858}
859
860/**
861 * pci_scan_slot - scan a PCI slot on a bus for devices.
862 * @bus: PCI bus to scan
863 * @devfn: slot number to scan (must have zero function.)
864 *
865 * Scan a PCI slot on the specified PCI bus for devices, adding
866 * discovered devices to the @bus->devices list. New devices
867 * will have an empty dev->global_list head.
868 */
869int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
870{
871 int func, nr = 0;
872 int scan_all_fns;
873
874 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
875
876 for (func = 0; func < 8; func++, devfn++) {
877 struct pci_dev *dev;
878
879 dev = pci_scan_single_device(bus, devfn);
880 if (dev) {
881 nr++;
882
883 /*
884 * If this is a single function device,
885 * don't scan past the first function.
886 */
887 if (!dev->multifunction) {
888 if (func > 0) {
889 dev->multifunction = 1;
890 } else {
891 break;
892 }
893 }
894 } else {
895 if (func == 0 && !scan_all_fns)
896 break;
897 }
898 }
899 return nr;
900}
901
902unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
903{
904 unsigned int devfn, pass, max = bus->secondary;
905 struct pci_dev *dev;
906
907 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
908
909 /* Go find them, Rover! */
910 for (devfn = 0; devfn < 0x100; devfn += 8)
911 pci_scan_slot(bus, devfn);
912
913 /*
914 * After performing arch-dependent fixup of the bus, look behind
915 * all PCI-to-PCI bridges on this bus.
916 */
917 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
918 pcibios_fixup_bus(bus);
919 for (pass=0; pass < 2; pass++)
920 list_for_each_entry(dev, &bus->devices, bus_list) {
921 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
922 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
923 max = pci_scan_bridge(bus, dev, max, pass);
924 }
925
926 /*
927 * We've scanned the bus and so we know all about what's on
928 * the other side of any bridges that may be on this bus plus
929 * any devices.
930 *
931 * Return how far we've got finding sub-buses.
932 */
933 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
934 pci_domain_nr(bus), bus->number, max);
935 return max;
936}
937
938unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
939{
940 unsigned int max;
941
942 max = pci_scan_child_bus(bus);
943
944 /*
945 * Make the discovered devices available.
946 */
947 pci_bus_add_devices(bus);
948
949 return max;
950}
951
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +1000952struct pci_bus * __devinit pci_create_bus(struct device *parent,
953 int bus, struct pci_ops *ops, void *sysdata)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954{
955 int error;
956 struct pci_bus *b;
957 struct device *dev;
958
959 b = pci_alloc_bus();
960 if (!b)
961 return NULL;
962
963 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
964 if (!dev){
965 kfree(b);
966 return NULL;
967 }
968
969 b->sysdata = sysdata;
970 b->ops = ops;
971
972 if (pci_find_bus(pci_domain_nr(b), bus)) {
973 /* If we already got to this bus through a different bridge, ignore it */
974 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
975 goto err_out;
976 }
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700977 spin_lock(&pci_bus_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978 list_add_tail(&b->node, &pci_root_buses);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700979 spin_unlock(&pci_bus_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980
981 memset(dev, 0, sizeof(*dev));
982 dev->parent = parent;
983 dev->release = pci_release_bus_bridge_dev;
984 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
985 error = device_register(dev);
986 if (error)
987 goto dev_reg_err;
988 b->bridge = get_device(dev);
989
990 b->class_dev.class = &pcibus_class;
991 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
992 error = class_device_register(&b->class_dev);
993 if (error)
994 goto class_dev_reg_err;
995 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
996 if (error)
997 goto class_dev_create_file_err;
998
999 /* Create legacy_io and legacy_mem files for this bus */
1000 pci_create_legacy_files(b);
1001
1002 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1003 if (error)
1004 goto sys_create_link_err;
1005
1006 b->number = b->secondary = bus;
1007 b->resource[0] = &ioport_resource;
1008 b->resource[1] = &iomem_resource;
1009
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 return b;
1011
1012sys_create_link_err:
1013 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1014class_dev_create_file_err:
1015 class_device_unregister(&b->class_dev);
1016class_dev_reg_err:
1017 device_unregister(dev);
1018dev_reg_err:
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -07001019 spin_lock(&pci_bus_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 list_del(&b->node);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -07001021 spin_unlock(&pci_bus_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022err_out:
1023 kfree(dev);
1024 kfree(b);
1025 return NULL;
1026}
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001027EXPORT_SYMBOL_GPL(pci_create_bus);
1028
1029struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1030 int bus, struct pci_ops *ops, void *sysdata)
1031{
1032 struct pci_bus *b;
1033
1034 b = pci_create_bus(parent, bus, ops, sysdata);
1035 if (b)
1036 b->subordinate = pci_scan_child_bus(b);
1037 return b;
1038}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039EXPORT_SYMBOL(pci_scan_bus_parented);
1040
1041#ifdef CONFIG_HOTPLUG
1042EXPORT_SYMBOL(pci_add_new_bus);
1043EXPORT_SYMBOL(pci_do_scan_bus);
1044EXPORT_SYMBOL(pci_scan_slot);
1045EXPORT_SYMBOL(pci_scan_bridge);
1046EXPORT_SYMBOL(pci_scan_single_device);
1047EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1048#endif