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Catalin Marinasc0da0852005-06-20 18:51:06 +01001/*
2 * linux/arch/arm/mach-versatile/pci.c
3 *
4 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
5 * You can redistribute and/or modify this software under the terms of version 2
6 * of the GNU General Public License as published by the Free Software Foundation.
7 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
8 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9 * General Public License for more details.
10 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
11 *
12 * ARM Versatile PCI driver.
13 *
14 * 14/04/2005 Initial version, colin.king@philips.com
15 *
16 */
Catalin Marinasc0da0852005-06-20 18:51:06 +010017#include <linux/kernel.h>
18#include <linux/pci.h>
Catalin Marinasc0da0852005-06-20 18:51:06 +010019#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +010023#include <linux/io.h>
Catalin Marinasc0da0852005-06-20 18:51:06 +010024
Russell Kinga09e64f2008-08-05 16:14:15 +010025#include <mach/hardware.h>
Linus Walleije3e92a72013-01-28 21:58:22 +010026#include <mach/irqs.h>
Catalin Marinasc0da0852005-06-20 18:51:06 +010027#include <asm/irq.h>
Catalin Marinasc0da0852005-06-20 18:51:06 +010028#include <asm/mach/pci.h>
Catalin Marinasc0da0852005-06-20 18:51:06 +010029
30/*
31 * these spaces are mapped using the following base registers:
32 *
33 * Usage Local Bus Memory Base/Map registers used
34 *
35 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
36 * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
37 * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
38 * Cfg 42000000 - 42FFFFFF PCI config
39 *
40 */
Al Viro399ad772006-10-11 17:22:34 +010041#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
42#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
43#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
44#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
45#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
46#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
47#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
48#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
49#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
Catalin Marinasc0da0852005-06-20 18:51:06 +010050
51#define DEVICE_ID_OFFSET 0x00
52#define CSR_OFFSET 0x04
53#define CLASS_ID_OFFSET 0x08
54
55#define VP_PCI_DEVICE_ID 0x030010ee
56#define VP_PCI_CLASS_ID 0x0b400000
57
58static unsigned long pci_slot_ignore = 0;
59
60static int __init versatile_pci_slot_ignore(char *str)
61{
62 int retval;
63 int slot;
64
65 while ((retval = get_option(&str,&slot))) {
66 if ((slot < 0) || (slot > 31)) {
67 printk("Illegal slot value: %d\n",slot);
68 } else {
69 pci_slot_ignore |= (1 << slot);
70 }
71 }
72 return 1;
73}
74
75__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
76
77
Al Viro399ad772006-10-11 17:22:34 +010078static void __iomem *__pci_addr(struct pci_bus *bus,
Catalin Marinasc0da0852005-06-20 18:51:06 +010079 unsigned int devfn, int offset)
80{
81 unsigned int busnr = bus->number;
82
83 /*
84 * Trap out illegal values
85 */
86 if (offset > 255)
87 BUG();
88 if (busnr > 255)
89 BUG();
90 if (devfn > 255)
91 BUG();
92
Al Viro399ad772006-10-11 17:22:34 +010093 return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
Catalin Marinasc0da0852005-06-20 18:51:06 +010094 (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
95}
96
97static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
98 int size, u32 *val)
99{
Al Viro399ad772006-10-11 17:22:34 +0100100 void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
Catalin Marinasc0da0852005-06-20 18:51:06 +0100101 u32 v;
102 int slot = PCI_SLOT(devfn);
103
104 if (pci_slot_ignore & (1 << slot)) {
105 /* Ignore this slot */
106 switch (size) {
107 case 1:
108 v = 0xff;
109 break;
110 case 2:
111 v = 0xffff;
112 break;
113 default:
114 v = 0xffffffff;
115 }
116 } else {
117 switch (size) {
118 case 1:
Andrzej Zaborowski756813c2007-06-26 14:31:23 +0100119 v = __raw_readl(addr);
120 if (where & 2) v >>= 16;
121 if (where & 1) v >>= 8;
122 v &= 0xff;
Catalin Marinasc0da0852005-06-20 18:51:06 +0100123 break;
124
125 case 2:
Al Viro399ad772006-10-11 17:22:34 +0100126 v = __raw_readl(addr);
127 if (where & 2) v >>= 16;
Catalin Marinasc0da0852005-06-20 18:51:06 +0100128 v &= 0xffff;
129 break;
130
131 default:
Catalin Marinasc0da0852005-06-20 18:51:06 +0100132 v = __raw_readl(addr);
133 break;
134 }
135 }
136
137 *val = v;
138 return PCIBIOS_SUCCESSFUL;
139}
140
141static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
142 int size, u32 val)
143{
Al Viro399ad772006-10-11 17:22:34 +0100144 void __iomem *addr = __pci_addr(bus, devfn, where);
Catalin Marinasc0da0852005-06-20 18:51:06 +0100145 int slot = PCI_SLOT(devfn);
146
147 if (pci_slot_ignore & (1 << slot)) {
148 return PCIBIOS_SUCCESSFUL;
149 }
150
151 switch (size) {
152 case 1:
153 __raw_writeb((u8)val, addr);
154 break;
155
156 case 2:
157 __raw_writew((u16)val, addr);
158 break;
159
160 case 4:
161 __raw_writel(val, addr);
162 break;
163 }
164
165 return PCIBIOS_SUCCESSFUL;
166}
167
168static struct pci_ops pci_versatile_ops = {
169 .read = versatile_read_config,
170 .write = versatile_write_config,
171};
172
173static struct resource io_mem = {
174 .name = "PCI I/O space",
175 .start = VERSATILE_PCI_MEM_BASE0,
176 .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
Arnd Bergmann9b0f7e32012-06-11 09:03:58 -0500177 .flags = IORESOURCE_MEM,
Catalin Marinasc0da0852005-06-20 18:51:06 +0100178};
179
180static struct resource non_mem = {
181 .name = "PCI non-prefetchable",
182 .start = VERSATILE_PCI_MEM_BASE1,
183 .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
184 .flags = IORESOURCE_MEM,
185};
186
187static struct resource pre_mem = {
188 .name = "PCI prefetchable",
189 .start = VERSATILE_PCI_MEM_BASE2,
190 .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
191 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
192};
193
Paul Gortmakeree5324e2012-04-02 19:48:25 -0400194static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
Catalin Marinasc0da0852005-06-20 18:51:06 +0100195{
196 int ret = 0;
197
198 ret = request_resource(&iomem_resource, &io_mem);
199 if (ret) {
200 printk(KERN_ERR "PCI: unable to allocate I/O "
201 "memory region (%d)\n", ret);
202 goto out;
203 }
204 ret = request_resource(&iomem_resource, &non_mem);
205 if (ret) {
206 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
207 "memory region (%d)\n", ret);
208 goto release_io_mem;
209 }
210 ret = request_resource(&iomem_resource, &pre_mem);
211 if (ret) {
212 printk(KERN_ERR "PCI: unable to allocate prefetchable "
213 "memory region (%d)\n", ret);
214 goto release_non_mem;
215 }
216
217 /*
Bjorn Helgaas37d15902011-10-28 16:26:16 -0600218 * the mem resource for this bus
219 * the prefetch mem resource for this bus
Catalin Marinasc0da0852005-06-20 18:51:06 +0100220 */
Paul Gortmakeree5324e2012-04-02 19:48:25 -0400221 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
222 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
Catalin Marinasc0da0852005-06-20 18:51:06 +0100223
224 goto out;
225
226 release_non_mem:
227 release_resource(&non_mem);
228 release_io_mem:
229 release_resource(&io_mem);
230 out:
231 return ret;
232}
233
234int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
235{
236 int ret = 0;
237 int i;
238 int myslot = -1;
239 unsigned long val;
Catalin Marinasc27a2162006-02-22 19:51:38 +0000240 void __iomem *local_pci_cfg_base;
241
242 val = __raw_readl(SYS_PCICTL);
243 if (!(val & 1)) {
244 printk("Not plugged into PCI backplane!\n");
245 ret = -EIO;
246 goto out;
247 }
Catalin Marinasc0da0852005-06-20 18:51:06 +0100248
Rob Herringfe505172012-07-08 22:13:54 -0500249 ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0);
250 if (ret)
251 goto out;
252
Catalin Marinasc0da0852005-06-20 18:51:06 +0100253 if (nr == 0) {
Paul Gortmakeree5324e2012-04-02 19:48:25 -0400254 ret = pci_versatile_setup_resources(sys);
Catalin Marinasc0da0852005-06-20 18:51:06 +0100255 if (ret < 0) {
256 printk("pci_versatile_setup: resources... oops?\n");
257 goto out;
258 }
259 } else {
260 printk("pci_versatile_setup: resources... nr == 0??\n");
261 goto out;
262 }
263
Catalin Marinasc0da0852005-06-20 18:51:06 +0100264 /*
265 * We need to discover the PCI core first to configure itself
266 * before the main PCI probing is performed
267 */
Catalin Marinasc27a2162006-02-22 19:51:38 +0000268 for (i=0; i<32; i++)
Catalin Marinasc0da0852005-06-20 18:51:06 +0100269 if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
270 (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
271 myslot = i;
Catalin Marinasc0da0852005-06-20 18:51:06 +0100272 break;
273 }
Catalin Marinasc0da0852005-06-20 18:51:06 +0100274
275 if (myslot == -1) {
276 printk("Cannot find PCI core!\n");
277 ret = -EIO;
Catalin Marinasc27a2162006-02-22 19:51:38 +0000278 goto out;
Catalin Marinasc0da0852005-06-20 18:51:06 +0100279 }
280
Catalin Marinasc27a2162006-02-22 19:51:38 +0000281 printk("PCI core found (slot %d)\n",myslot);
282
283 __raw_writel(myslot, PCI_SELFID);
Al Viro399ad772006-10-11 17:22:34 +0100284 local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
Catalin Marinasc27a2162006-02-22 19:51:38 +0000285
286 val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
287 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
288 __raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
289
290 /*
291 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
292 */
293 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
294 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
295 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
296
297 /*
298 * Do not to map Versatile FPGA PCI device into memory space
299 */
300 pci_slot_ignore |= (1 << myslot);
301 ret = 1;
302
Catalin Marinasc0da0852005-06-20 18:51:06 +0100303 out:
304 return ret;
305}
306
307
Catalin Marinasc0da0852005-06-20 18:51:06 +0100308void __init pci_versatile_preinit(void)
309{
Rob Herringc9d95fb2011-06-28 21:16:13 -0500310 pcibios_min_mem = 0x50000000;
311
Catalin Marinasc27a2162006-02-22 19:51:38 +0000312 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
313 __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
314 __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
Catalin Marinasc0da0852005-06-20 18:51:06 +0100315
Catalin Marinasc27a2162006-02-22 19:51:38 +0000316 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
317 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
318 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
Catalin Marinasc0da0852005-06-20 18:51:06 +0100319
Catalin Marinasc27a2162006-02-22 19:51:38 +0000320 __raw_writel(1, SYS_PCICTL);
321}
Catalin Marinasc0da0852005-06-20 18:51:06 +0100322
323/*
324 * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
325 */
Ralf Baechled5341942011-06-10 15:30:21 +0100326static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
Catalin Marinasc0da0852005-06-20 18:51:06 +0100327{
328 int irq;
Catalin Marinasc0da0852005-06-20 18:51:06 +0100329
Catalin Marinasc27a2162006-02-22 19:51:38 +0000330 /* slot, pin, irq
Linus Walleije3e92a72013-01-28 21:58:22 +0100331 * 24 1 IRQ_SIC_PCI0
332 * 25 1 IRQ_SIC_PCI1
333 * 26 1 IRQ_SIC_PCI2
334 * 27 1 IRQ_SIC_PCI3
Catalin Marinasc27a2162006-02-22 19:51:38 +0000335 */
Linus Walleije3e92a72013-01-28 21:58:22 +0100336 irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3);
Catalin Marinasc0da0852005-06-20 18:51:06 +0100337
338 return irq;
339}
340
341static struct hw_pci versatile_pci __initdata = {
Catalin Marinasc0da0852005-06-20 18:51:06 +0100342 .map_irq = versatile_map_irq,
343 .nr_controllers = 1,
Russell Kingc23bfc32012-03-10 12:49:16 +0000344 .ops = &pci_versatile_ops,
Catalin Marinasc0da0852005-06-20 18:51:06 +0100345 .setup = pci_versatile_setup,
Catalin Marinasc0da0852005-06-20 18:51:06 +0100346 .preinit = pci_versatile_preinit,
Catalin Marinasc0da0852005-06-20 18:51:06 +0100347};
348
349static int __init versatile_pci_init(void)
350{
351 pci_common_init(&versatile_pci);
352 return 0;
353}
354
355subsys_initcall(versatile_pci_init);