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Raja Mallik8b88b232019-04-04 14:32:27 +05301/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
Raja Mallikc7e256f2018-12-06 17:36:28 +05302 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _CAM_CPAS_API_H_
14#define _CAM_CPAS_API_H_
15
16#include <linux/device.h>
17#include <linux/platform_device.h>
18
19#include <media/cam_cpas.h>
20#include "cam_soc_util.h"
21
22#define CAM_HW_IDENTIFIER_LENGTH 128
23
24/* Default AXI Bandwidth vote */
25#define CAM_CPAS_DEFAULT_AXI_BW 1024
26
27/**
28 * enum cam_cpas_reg_base - Enum for register base identifier. These
29 * are the identifiers used in generic register
30 * write/read APIs provided by cpas driver.
31 */
32enum cam_cpas_reg_base {
33 CAM_CPAS_REG_CPASTOP,
34 CAM_CPAS_REG_CAMNOC,
35 CAM_CPAS_REG_CSR_TCSR,
36 CAM_CPAS_REG_CAMSS,
37 CAM_CPAS_REG_MAX
38};
39
40/**
41 * enum cam_cpas_hw_version - Enum for Titan CPAS HW Versions
42 */
43enum cam_cpas_hw_version {
44 CAM_CPAS_TITAN_NONE = 0,
45 CAM_CPAS_TITAN_150_V100 = 0x150100,
Raja Mallike3ed1a32019-08-22 17:12:32 +053046 CAM_CPAS_TITAN_150_V110 = 0x150110,
Raja Mallikc7e256f2018-12-06 17:36:28 +053047 CAM_CPAS_TITAN_170_V100 = 0x170100,
48 CAM_CPAS_TITAN_170_V110 = 0x170110,
49 CAM_CPAS_TITAN_170_V120 = 0x170120,
50 CAM_CPAS_TITAN_175_V100 = 0x175100,
51 CAM_CPAS_TITAN_175_V101 = 0x175101,
52 CAM_CPAS_TITAN_175_V120 = 0x175120,
53 CAM_CPAS_TITAN_MAX
54};
55
56
57/**
58 * enum cam_camnoc_irq_type - Enum for camnoc irq types
59 *
60 * @CAM_CAMNOC_IRQ_SLAVE_ERROR: Each slave port in CAMNOC (3 QSB ports and
61 * 1 QHB port) has an error logger. The error
62 * observed at any slave port is logged into
63 * the error logger register and an IRQ is
64 * triggered
65 * @CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR : Triggered if any error detected
66 * in the IFE0 UBWC encoder instance
67 * @CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR : Triggered if any error detected
68 * in the IFE1 or IFE3 UBWC encoder
69 * instance
70 * @CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR : Triggered if any error detected
71 * in the IFE0 UBWC encoder instance
72 * @CAM_CAMNOC_IRQ_IFE1_WR_UBWC_ENCODE_ERROR : Triggered if any error detected
73 * in the IFE1 UBWC encoder
74 * instance
75 * @CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR: Triggered if any error detected
76 * in the IPE/BPS UBWC decoder
77 * instance
78 * @CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: Triggered if any error detected
79 * in the IPE/BPS UBWC encoder
80 * instance
81 * @CAM_CAMNOC_IRQ_AHB_TIMEOUT : Triggered when the QHS_ICP slave
82 * times out after 4000 AHB cycles
83 */
84enum cam_camnoc_irq_type {
85 CAM_CAMNOC_IRQ_SLAVE_ERROR,
86 CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR,
87 CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR,
88 CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR,
89 CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,
90 CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
91 CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
92 CAM_CAMNOC_IRQ_AHB_TIMEOUT,
93};
94
95/**
96 * struct cam_camnoc_irq_slave_err_data : Data for Slave error.
97 *
98 * @mainctrl : Err logger mainctrl info
99 * @errvld : Err logger errvld info
100 * @errlog0_low : Err logger errlog0_low info
101 * @errlog0_high : Err logger errlog0_high info
102 * @errlog1_low : Err logger errlog1_low info
103 * @errlog1_high : Err logger errlog1_high info
104 * @errlog2_low : Err logger errlog2_low info
105 * @errlog2_high : Err logger errlog2_high info
106 * @errlog3_low : Err logger errlog3_low info
107 * @errlog3_high : Err logger errlog3_high info
108 *
109 */
110struct cam_camnoc_irq_slave_err_data {
111 union {
112 struct {
113 uint32_t stall_en : 1; /* bit 0 */
114 uint32_t fault_en : 1; /* bit 1 */
115 uint32_t rsv : 30; /* bits 2-31 */
116 };
117 uint32_t value;
118 } mainctrl;
119 union {
120 struct {
121 uint32_t err_vld : 1; /* bit 0 */
122 uint32_t rsv : 31; /* bits 1-31 */
123 };
124 uint32_t value;
125 } errvld;
126 union {
127 struct {
128 uint32_t loginfo_vld : 1; /* bit 0 */
129 uint32_t word_error : 1; /* bit 1 */
130 uint32_t non_secure : 1; /* bit 2 */
131 uint32_t device : 1; /* bit 3 */
132 uint32_t opc : 3; /* bits 4 - 6 */
133 uint32_t rsv0 : 1; /* bit 7 */
134 uint32_t err_code : 3; /* bits 8 - 10 */
135 uint32_t sizef : 3; /* bits 11 - 13 */
136 uint32_t rsv1 : 2; /* bits 14 - 15 */
137 uint32_t addr_space : 6; /* bits 16 - 21 */
138 uint32_t rsv2 : 10; /* bits 22 - 31 */
139 };
140 uint32_t value;
141 } errlog0_low;
142 union {
143 struct {
144 uint32_t len1 : 10; /* bits 0 - 9 */
145 uint32_t rsv : 22; /* bits 10 - 31 */
146 };
147 uint32_t value;
148 } errlog0_high;
149 union {
150 struct {
151 uint32_t path : 16; /* bits 0 - 15 */
152 uint32_t rsv : 16; /* bits 16 - 31 */
153 };
154 uint32_t value;
155 } errlog1_low;
156 union {
157 struct {
158 uint32_t extid : 18; /* bits 0 - 17 */
159 uint32_t rsv : 14; /* bits 18 - 31 */
160 };
161 uint32_t value;
162 } errlog1_high;
163 union {
164 struct {
165 uint32_t errlog2_lsb : 32; /* bits 0 - 31 */
166 };
167 uint32_t value;
168 } errlog2_low;
169 union {
170 struct {
171 uint32_t errlog2_msb : 16; /* bits 0 - 16 */
172 uint32_t rsv : 16; /* bits 16 - 31 */
173 };
174 uint32_t value;
175 } errlog2_high;
176 union {
177 struct {
178 uint32_t errlog3_lsb : 32; /* bits 0 - 31 */
179 };
180 uint32_t value;
181 } errlog3_low;
182 union {
183 struct {
184 uint32_t errlog3_msb : 32; /* bits 0 - 31 */
185 };
186 uint32_t value;
187 } errlog3_high;
188};
189
190/**
191 * struct cam_camnoc_irq_ubwc_enc_data : Data for UBWC Encode error.
192 *
193 * @encerr_status : Encode error status
194 *
195 */
196struct cam_camnoc_irq_ubwc_enc_data {
197 union {
198 struct {
199 uint32_t encerrstatus : 3; /* bits 0 - 2 */
200 uint32_t rsv : 29; /* bits 3 - 31 */
201 };
202 uint32_t value;
203 } encerr_status;
204};
205
206/**
207 * struct cam_camnoc_irq_ubwc_dec_data : Data for UBWC Decode error.
208 *
209 * @decerr_status : Decoder error status
210 * @thr_err : Set to 1 if
211 * At least one of the bflc_len fields in the bit steam exceeds
212 * its threshold value. This error is possible only for
213 * RGBA1010102, TP10, and RGB565 formats
214 * @fcl_err : Set to 1 if
215 * Fast clear with a legal non-RGB format
216 * @len_md_err : Set to 1 if
217 * The calculated burst length does not match burst length
218 * specified by the metadata value
219 * @format_err : Set to 1 if
220 * Illegal format
221 * 1. bad format :2,3,6
222 * 2. For 32B MAL, metadata=6
223 * 3. For 32B MAL RGB565, Metadata != 0,1,7
224 * 4. For 64B MAL RGB565, metadata[3:1] == 1,2
225 *
226 */
227struct cam_camnoc_irq_ubwc_dec_data {
228 union {
229 struct {
230 uint32_t thr_err : 1; /* bit 0 */
231 uint32_t fcl_err : 1; /* bit 1 */
232 uint32_t len_md_err : 1; /* bit 2 */
233 uint32_t format_err : 1; /* bit 3 */
234 uint32_t rsv : 28; /* bits 4 - 31 */
235 };
236 uint32_t value;
237 } decerr_status;
238};
239
240struct cam_camnoc_irq_ahb_timeout_data {
241 uint32_t data;
242};
243
244/**
245 * struct cam_cpas_irq_data : CAMNOC IRQ data
246 *
247 * @irq_type : To identify the type of IRQ
248 * @u : Union of irq err data information
249 * @slave_err : Data for Slave error.
250 * Valid if type is CAM_CAMNOC_IRQ_SLAVE_ERROR
251 * @enc_err : Data for UBWC Encode error.
252 * Valid if type is one of below:
253 * CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR
254 * CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR
255 * CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR
256 * @dec_err : Data for UBWC Decode error.
257 * Valid if type is CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR
258 * @ahb_err : Data for Slave error.
259 * Valid if type is CAM_CAMNOC_IRQ_AHB_TIMEOUT
260 *
261 */
262struct cam_cpas_irq_data {
263 enum cam_camnoc_irq_type irq_type;
264 union {
265 struct cam_camnoc_irq_slave_err_data slave_err;
266 struct cam_camnoc_irq_ubwc_enc_data enc_err;
267 struct cam_camnoc_irq_ubwc_dec_data dec_err;
268 struct cam_camnoc_irq_ahb_timeout_data ahb_err;
269 } u;
270};
271
272/**
273 * struct cam_cpas_register_params : Register params for cpas client
274 *
275 * @identifier : Input identifier string which is the device label
276 * from dt like vfe, ife, jpeg etc
277 * @cell_index : Input integer identifier pointing to the cell index
278 * from dt of the device. This can be used to form a
279 * unique string with @identifier like vfe0, ife1,
280 * jpeg0, etc
281 * @dev : device handle
282 * @userdata : Input private data which will be passed as
283 * an argument while callback.
284 * @cam_cpas_callback : Input callback pointer for triggering the
285 * callbacks from CPAS driver.
286 * @client_handle : CPAS client handle
287 * @userdata : User data given at the time of register
288 * @event_type : event type
289 * @event_data : event data
290 * @client_handle : Output Unique handle generated for this register
291 *
292 */
293struct cam_cpas_register_params {
294 char identifier[CAM_HW_IDENTIFIER_LENGTH];
295 uint32_t cell_index;
296 struct device *dev;
297 void *userdata;
298 bool (*cam_cpas_client_cb)(
299 uint32_t client_handle,
300 void *userdata,
301 struct cam_cpas_irq_data *irq_data);
302 uint32_t client_handle;
303};
304
305/**
306 * enum cam_vote_type - Enum for voting type
307 *
308 * @CAM_VOTE_ABSOLUTE : Absolute vote
309 * @CAM_VOTE_DYNAMIC : Dynamic vote
310 */
311enum cam_vote_type {
312 CAM_VOTE_ABSOLUTE,
313 CAM_VOTE_DYNAMIC,
314};
315
316/**
317 * struct cam_ahb_vote : AHB vote
318 *
319 * @type : AHB voting type.
320 * CAM_VOTE_ABSOLUTE : vote based on the value 'level' is set
321 * CAM_VOTE_DYNAMIC : vote calculated dynamically using 'freq'
322 * and 'dev' handle is set
323 * @level : AHB vote level
324 * @freq : AHB vote dynamic frequency
325 *
326 */
327struct cam_ahb_vote {
328 enum cam_vote_type type;
329 union {
330 enum cam_vote_level level;
331 unsigned long freq;
332 } vote;
333};
334
335/**
336 * struct cam_axi_vote : AXI vote
337 *
338 * @uncompressed_bw : Bus bandwidth required in Bytes for uncompressed data
339 * This is the required bandwidth for uncompressed
340 * data traffic between hw core and camnoc.
341 * @compressed_bw : Bus bandwidth required in Bytes for compressed data.
342 * This is the required bandwidth for compressed
343 * data traffic between camnoc and mmnoc.
344 *
345 * If one of the above is not applicable to a hw client, it has to
346 * fill the same values in both.
347 *
348 */
349struct cam_axi_vote {
350 uint64_t uncompressed_bw;
351 uint64_t compressed_bw;
Raja Mallik8b88b232019-04-04 14:32:27 +0530352 uint64_t compressed_bw_ab;
Raja Mallikc7e256f2018-12-06 17:36:28 +0530353};
354
355/**
356 * cam_cpas_register_client()
357 *
358 * @brief: API to register cpas client
359 *
360 * @register_params: Input params to register as a client to CPAS
361 *
362 * @return 0 on success.
363 *
364 */
365int cam_cpas_register_client(
366 struct cam_cpas_register_params *register_params);
367
368/**
369 * cam_cpas_unregister_client()
370 *
371 * @brief: API to unregister cpas client
372 *
373 * @client_handle: Client handle to be unregistered
374 *
375 * @return 0 on success.
376 *
377 */
378int cam_cpas_unregister_client(uint32_t client_handle);
379
380/**
381 * cam_cpas_start()
382 *
383 * @brief: API to start cpas client hw. Clients have to vote for minimal
384 * bandwidth requirements for AHB, AXI. Use cam_cpas_update_ahb_vote
385 * to scale bandwidth after start.
386 *
387 * @client_handle: client cpas handle
388 * @ahb_vote : Pointer to ahb vote info
389 * @axi_vote : Pointer to axi bandwidth vote info
390 *
391 * If AXI vote is not applicable to a particular client, use the value exposed
392 * by CAM_CPAS_DEFAULT_AXI_BW as the default vote request.
393 *
394 * @return 0 on success.
395 *
396 */
397int cam_cpas_start(
398 uint32_t client_handle,
399 struct cam_ahb_vote *ahb_vote,
400 struct cam_axi_vote *axi_vote);
401
402/**
403 * cam_cpas_stop()
404 *
405 * @brief: API to stop cpas client hw. Bandwidth for AHB, AXI votes
406 * would be removed for this client on this call. Clients should not
407 * use cam_cpas_update_ahb_vote or cam_cpas_update_axi_vote
408 * to remove their bandwidth vote.
409 *
410 * @client_handle: client cpas handle
411 *
412 * @return 0 on success.
413 *
414 */
415int cam_cpas_stop(uint32_t client_handle);
416
417/**
418 * cam_cpas_update_ahb_vote()
419 *
420 * @brief: API to update AHB vote requirement. Use this function only
421 * between cam_cpas_start and cam_cpas_stop in case clients wants
422 * to scale to different vote level. Do not use this function to de-vote,
423 * removing client's vote is implicit on cam_cpas_stop
424 *
425 * @client_handle : Client cpas handle
426 * @ahb_vote : Pointer to ahb vote info
427 *
428 * @return 0 on success.
429 *
430 */
431int cam_cpas_update_ahb_vote(
432 uint32_t client_handle,
433 struct cam_ahb_vote *ahb_vote);
434
435/**
436 * cam_cpas_update_axi_vote()
437 *
438 * @brief: API to update AXI vote requirement. Use this function only
439 * between cam_cpas_start and cam_cpas_stop in case clients wants
440 * to scale to different vote level. Do not use this function to de-vote,
441 * removing client's vote is implicit on cam_cpas_stop
442 *
443 * @client_handle : Client cpas handle
444 * @axi_vote : Pointer to axi bandwidth vote info
445 *
446 * @return 0 on success.
447 *
448 */
449int cam_cpas_update_axi_vote(
450 uint32_t client_handle,
451 struct cam_axi_vote *axi_vote);
452
453/**
454 * cam_cpas_reg_write()
455 *
456 * @brief: API to write a register value in CPAS register space
457 *
458 * @client_handle : Client cpas handle
459 * @reg_base : Register base identifier
460 * @offset : Offset from the register base address
461 * @mb : Whether to do reg write with memory barrier
462 * @value : Value to be written in register
463 *
464 * @return 0 on success.
465 *
466 */
467int cam_cpas_reg_write(
468 uint32_t client_handle,
469 enum cam_cpas_reg_base reg_base,
470 uint32_t offset,
471 bool mb,
472 uint32_t value);
473
474/**
475 * cam_cpas_reg_read()
476 *
477 * @brief: API to read a register value from CPAS register space
478 *
479 * @client_handle : Client cpas handle
480 * @reg_base : Register base identifier
481 * @offset : Offset from the register base address
482 * @mb : Whether to do reg read with memory barrier
483 * @value : Value to be red from register
484 *
485 * @return 0 on success.
486 *
487 */
488int cam_cpas_reg_read(
489 uint32_t client_handle,
490 enum cam_cpas_reg_base reg_base,
491 uint32_t offset,
492 bool mb,
493 uint32_t *value);
494
495/**
496 * cam_cpas_get_hw_info()
497 *
498 * @brief: API to get camera hw information
499 *
500 * @camera_family : Camera family type. One of
501 * CAM_FAMILY_CAMERA_SS
502 * CAM_FAMILY_CPAS_SS
503 * @camera_version : Camera platform version
504 * @cpas_version : Camera cpas version
505 * @cam_caps : Camera capability
506 *
507 * @return 0 on success.
508 *
509 */
510int cam_cpas_get_hw_info(
511 uint32_t *camera_family,
512 struct cam_hw_version *camera_version,
513 struct cam_hw_version *cpas_version,
514 uint32_t *cam_caps);
515
516/**
517 * cam_cpas_get_cpas_hw_version()
518 *
519 * @brief: API to get camera cpas hw version
520 *
521 * @hw_version : Camera cpas hw version
522 *
523 * @return 0 on success.
524 *
525 */
526int cam_cpas_get_cpas_hw_version(
527 uint32_t *hw_version);
528
529#endif /* _CAM_CPAS_API_H_ */