Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /****************************************************************************/ |
| 2 | |
| 3 | /* |
| 4 | * m5249sim.h -- ColdFire 5249 System Integration Module support. |
| 5 | * |
| 6 | * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) |
| 7 | */ |
| 8 | |
| 9 | /****************************************************************************/ |
| 10 | #ifndef m5249sim_h |
| 11 | #define m5249sim_h |
| 12 | /****************************************************************************/ |
| 13 | |
| 14 | /* |
| 15 | * Define the 5249 SIM register set addresses. |
| 16 | */ |
| 17 | #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ |
| 18 | #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ |
| 19 | #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ |
| 20 | #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ |
| 21 | #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ |
| 22 | #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ |
| 23 | #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ |
| 24 | #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ |
| 25 | #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ |
| 26 | #define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ |
| 27 | #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ |
| 28 | #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ |
| 29 | #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ |
| 30 | #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ |
| 31 | #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ |
| 32 | #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ |
| 33 | #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ |
| 34 | #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ |
| 35 | #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ |
| 36 | #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ |
| 37 | #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ |
| 38 | #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ |
| 39 | |
| 40 | #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ |
| 41 | #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ |
| 42 | #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ |
| 43 | #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ |
| 44 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ |
| 45 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ |
Joe Perches | ab690d9 | 2008-02-03 17:38:04 +0200 | [diff] [blame] | 46 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ |
| 48 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ |
Joe Perches | ab690d9 | 2008-02-03 17:38:04 +0200 | [diff] [blame] | 49 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ |
| 51 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ |
| 52 | |
| 53 | #define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ |
| 54 | #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ |
| 55 | #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ |
| 56 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ |
| 57 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ |
| 58 | |
| 59 | |
| 60 | /* |
| 61 | * Some symbol defines for the above... |
| 62 | */ |
| 63 | #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ |
| 64 | #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ |
| 65 | #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ |
| 66 | #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ |
| 67 | #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ |
| 68 | #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ |
| 69 | #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ |
| 70 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ |
| 71 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ |
| 72 | |
| 73 | /* |
Greg Ungerer | 04b75b1 | 2009-05-19 14:52:40 +1000 | [diff] [blame] | 74 | * Define system peripheral IRQ usage. |
| 75 | */ |
| 76 | #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ |
| 77 | #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ |
| 78 | |
| 79 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | * General purpose IO registers (in MBAR2). |
| 81 | */ |
sfking@fdwdc.com | 9e8ded1 | 2009-06-19 18:11:05 -0700 | [diff] [blame] | 82 | #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ |
| 83 | #define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */ |
| 84 | #define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */ |
| 85 | #define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */ |
| 86 | #define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */ |
| 87 | #define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */ |
| 88 | #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ |
| 89 | #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | |
| 91 | #define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ |
| 92 | #define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ |
| 93 | #define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */ |
| 94 | |
| 95 | #define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */ |
| 96 | #define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */ |
| 97 | #define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */ |
| 98 | #define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */ |
| 99 | #define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */ |
| 100 | #define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */ |
| 101 | #define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */ |
| 102 | #define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */ |
| 103 | |
| 104 | #define MCFSIM2_DMAROUTE 0x188 /* DMA routing */ |
| 105 | |
| 106 | #define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ |
| 107 | #define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ |
| 108 | |
sfking@fdwdc.com | 9e8ded1 | 2009-06-19 18:11:05 -0700 | [diff] [blame] | 109 | /* |
Greg Ungerer | da3601a | 2009-05-22 14:16:39 +1000 | [diff] [blame] | 110 | * Define the base interrupt for the second interrupt controller. |
| 111 | * We set it to 128, out of the way of the base interrupts, and plenty |
| 112 | * of room for its 64 interrupts. |
| 113 | */ |
| 114 | #define MCFINTC2_VECBASE 128 |
| 115 | |
| 116 | #define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32) |
| 117 | #define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33) |
| 118 | #define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34) |
| 119 | #define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35) |
| 120 | #define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36) |
| 121 | #define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37) |
| 122 | #define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38) |
| 123 | #define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39) |
| 124 | |
| 125 | /* |
sfking@fdwdc.com | 9e8ded1 | 2009-06-19 18:11:05 -0700 | [diff] [blame] | 126 | * Generic GPIO support |
| 127 | */ |
| 128 | #define MCFGPIO_PIN_MAX 64 |
| 129 | #define MCFGPIO_IRQ_MAX -1 |
| 130 | #define MCFGPIO_IRQ_VECBASE -1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | |
| 132 | /****************************************************************************/ |
| 133 | |
| 134 | #ifdef __ASSEMBLER__ |
| 135 | |
| 136 | /* |
| 137 | * The M5249C3 board needs a little help getting all its SIM devices |
| 138 | * initialized at kernel start time. dBUG doesn't set much up, so |
| 139 | * we need to do it manually. |
| 140 | */ |
| 141 | .macro m5249c3_setup |
| 142 | /* |
| 143 | * Set MBAR1 and MBAR2, just incase they are not set. |
| 144 | */ |
| 145 | movel #0x10000001,%a0 |
| 146 | movec %a0,%MBAR /* map MBAR region */ |
| 147 | subql #1,%a0 /* get MBAR address in a0 */ |
| 148 | |
| 149 | movel #0x80000001,%a1 |
| 150 | movec %a1,#3086 /* map MBAR2 region */ |
| 151 | subql #1,%a1 /* get MBAR2 address in a1 */ |
| 152 | |
| 153 | /* |
Greg Ungerer | da3601a | 2009-05-22 14:16:39 +1000 | [diff] [blame] | 154 | * Move secondary interrupts to their base (128). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | */ |
Greg Ungerer | da3601a | 2009-05-22 14:16:39 +1000 | [diff] [blame] | 156 | moveb #MCFINTC2_VECBASE,%d0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | moveb %d0,0x16b(%a1) /* interrupt base register */ |
| 158 | |
| 159 | /* |
| 160 | * Work around broken CSMR0/DRAM vector problem. |
| 161 | */ |
| 162 | movel #0x001F0021,%d0 /* disable C/I bit */ |
| 163 | movel %d0,0x84(%a0) /* set CSMR0 */ |
| 164 | |
| 165 | /* |
| 166 | * Disable the PLL firstly. (Who knows what state it is |
| 167 | * in here!). |
| 168 | */ |
| 169 | movel 0x180(%a1),%d0 /* get current PLL value */ |
| 170 | andl #0xfffffffe,%d0 /* PLL bypass first */ |
| 171 | movel %d0,0x180(%a1) /* set PLL register */ |
| 172 | nop |
| 173 | |
Greg Ungerer | afd1b83 | 2006-06-26 11:43:35 +1000 | [diff] [blame] | 174 | #if CONFIG_CLOCK_FREQ == 140000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | /* |
| 176 | * Set initial clock frequency. This assumes M5249C3 board |
| 177 | * is fitted with 11.2896MHz crystal. It will program the |
| 178 | * PLL for 140MHz. Lets go fast :-) |
| 179 | */ |
| 180 | movel #0x125a40f0,%d0 /* set for 140MHz */ |
| 181 | movel %d0,0x180(%a1) /* set PLL register */ |
| 182 | orl #0x1,%d0 |
| 183 | movel %d0,0x180(%a1) /* set PLL register */ |
| 184 | #endif |
| 185 | |
| 186 | /* |
| 187 | * Setup CS1 for ethernet controller. |
| 188 | * (Setup as per M5249C3 doco). |
| 189 | */ |
| 190 | movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */ |
| 191 | movel %d0,0x8c(%a0) |
| 192 | movel #0x001f0021,%d0 /* CS1 size of 1Mb */ |
| 193 | movel %d0,0x90(%a0) |
| 194 | movew #0x0080,%d0 /* CS1 = 16bit port, AA */ |
| 195 | movew %d0,0x96(%a0) |
| 196 | |
| 197 | /* |
| 198 | * Setup CS2 for IDE interface. |
| 199 | */ |
| 200 | movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */ |
| 201 | movel %d0,0x98(%a0) |
| 202 | movel #0x001f0001,%d0 /* CS2 size of 1MB */ |
| 203 | movel %d0,0x9c(%a0) |
| 204 | movew #0x0080,%d0 /* CS2 = 16bit, TA */ |
| 205 | movew %d0,0xa2(%a0) |
| 206 | |
| 207 | movel #0x00107000,%d0 /* IDEconfig1 */ |
| 208 | movel %d0,0x18c(%a1) |
| 209 | movel #0x000c0400,%d0 /* IDEconfig2 */ |
| 210 | movel %d0,0x190(%a1) |
| 211 | |
| 212 | movel #0x00080000,%d0 /* GPIO19, IDE reset bit */ |
| 213 | orl %d0,0xc(%a1) /* function GPIO19 */ |
| 214 | orl %d0,0x8(%a1) /* enable GPIO19 as output */ |
| 215 | orl %d0,0x4(%a1) /* de-assert IDE reset */ |
| 216 | .endm |
| 217 | |
| 218 | #define PLATFORM_SETUP m5249c3_setup |
| 219 | |
| 220 | #endif /* __ASSEMBLER__ */ |
| 221 | |
| 222 | /****************************************************************************/ |
| 223 | #endif /* m5249sim_h */ |