Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * core.c - ChipIdea USB IP core family device controller |
| 3 | * |
| 4 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. |
| 5 | * |
| 6 | * Author: David Lopo |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Description: ChipIdea USB IP core family device controller |
| 15 | * |
| 16 | * This driver is composed of several blocks: |
| 17 | * - HW: hardware interface |
| 18 | * - DBG: debug facilities (optional) |
| 19 | * - UTIL: utilities |
| 20 | * - ISR: interrupts handling |
| 21 | * - ENDPT: endpoint operations (Gadget API) |
| 22 | * - GADGET: gadget operations (Gadget API) |
| 23 | * - BUS: bus glue code, bus abstraction layer |
| 24 | * |
| 25 | * Compile Options |
| 26 | * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities |
| 27 | * - STALL_IN: non-empty bulk-in pipes cannot be halted |
| 28 | * if defined mass storage compliance succeeds but with warnings |
| 29 | * => case 4: Hi > Dn |
| 30 | * => case 5: Hi > Di |
| 31 | * => case 8: Hi <> Do |
| 32 | * if undefined usbtest 13 fails |
| 33 | * - TRACE: enable function tracing (depends on DEBUG) |
| 34 | * |
| 35 | * Main Features |
| 36 | * - Chapter 9 & Mass Storage Compliance with Gadget File Storage |
| 37 | * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) |
| 38 | * - Normal & LPM support |
| 39 | * |
| 40 | * USBTEST Report |
| 41 | * - OK: 0-12, 13 (STALL_IN defined) & 14 |
| 42 | * - Not Supported: 15 & 16 (ISO) |
| 43 | * |
| 44 | * TODO List |
| 45 | * - OTG |
| 46 | * - Isochronous & Interrupt Traffic |
| 47 | * - Handle requests which spawns into several TDs |
| 48 | * - GET_STATUS(device) - always reports 0 |
| 49 | * - Gadget API (majority of optional features) |
| 50 | * - Suspend & Remote Wakeup |
| 51 | */ |
| 52 | #include <linux/delay.h> |
| 53 | #include <linux/device.h> |
| 54 | #include <linux/dmapool.h> |
| 55 | #include <linux/dma-mapping.h> |
| 56 | #include <linux/init.h> |
| 57 | #include <linux/platform_device.h> |
| 58 | #include <linux/module.h> |
| 59 | #include <linux/interrupt.h> |
| 60 | #include <linux/io.h> |
| 61 | #include <linux/irq.h> |
| 62 | #include <linux/kernel.h> |
| 63 | #include <linux/slab.h> |
| 64 | #include <linux/pm_runtime.h> |
| 65 | #include <linux/usb/ch9.h> |
| 66 | #include <linux/usb/gadget.h> |
| 67 | #include <linux/usb/otg.h> |
| 68 | #include <linux/usb/chipidea.h> |
| 69 | |
| 70 | #include "ci.h" |
| 71 | #include "udc.h" |
| 72 | #include "bits.h" |
| 73 | #include "debug.h" |
| 74 | |
| 75 | /* MSM specific */ |
| 76 | #define ABS_AHBBURST (0x0090UL) |
| 77 | #define ABS_AHBMODE (0x0098UL) |
| 78 | /* UDC register map */ |
| 79 | static uintptr_t ci_regs_nolpm[] = { |
| 80 | [CAP_CAPLENGTH] = 0x000UL, |
| 81 | [CAP_HCCPARAMS] = 0x008UL, |
| 82 | [CAP_DCCPARAMS] = 0x024UL, |
| 83 | [CAP_TESTMODE] = 0x038UL, |
| 84 | [OP_USBCMD] = 0x000UL, |
| 85 | [OP_USBSTS] = 0x004UL, |
| 86 | [OP_USBINTR] = 0x008UL, |
| 87 | [OP_DEVICEADDR] = 0x014UL, |
| 88 | [OP_ENDPTLISTADDR] = 0x018UL, |
| 89 | [OP_PORTSC] = 0x044UL, |
| 90 | [OP_DEVLC] = 0x084UL, |
| 91 | [OP_USBMODE] = 0x068UL, |
| 92 | [OP_ENDPTSETUPSTAT] = 0x06CUL, |
| 93 | [OP_ENDPTPRIME] = 0x070UL, |
| 94 | [OP_ENDPTFLUSH] = 0x074UL, |
| 95 | [OP_ENDPTSTAT] = 0x078UL, |
| 96 | [OP_ENDPTCOMPLETE] = 0x07CUL, |
| 97 | [OP_ENDPTCTRL] = 0x080UL, |
| 98 | }; |
| 99 | |
| 100 | static uintptr_t ci_regs_lpm[] = { |
| 101 | [CAP_CAPLENGTH] = 0x000UL, |
| 102 | [CAP_HCCPARAMS] = 0x008UL, |
| 103 | [CAP_DCCPARAMS] = 0x024UL, |
| 104 | [CAP_TESTMODE] = 0x0FCUL, |
| 105 | [OP_USBCMD] = 0x000UL, |
| 106 | [OP_USBSTS] = 0x004UL, |
| 107 | [OP_USBINTR] = 0x008UL, |
| 108 | [OP_DEVICEADDR] = 0x014UL, |
| 109 | [OP_ENDPTLISTADDR] = 0x018UL, |
| 110 | [OP_PORTSC] = 0x044UL, |
| 111 | [OP_DEVLC] = 0x084UL, |
| 112 | [OP_USBMODE] = 0x0C8UL, |
| 113 | [OP_ENDPTSETUPSTAT] = 0x0D8UL, |
| 114 | [OP_ENDPTPRIME] = 0x0DCUL, |
| 115 | [OP_ENDPTFLUSH] = 0x0E0UL, |
| 116 | [OP_ENDPTSTAT] = 0x0E4UL, |
| 117 | [OP_ENDPTCOMPLETE] = 0x0E8UL, |
| 118 | [OP_ENDPTCTRL] = 0x0ECUL, |
| 119 | }; |
| 120 | |
| 121 | static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm) |
| 122 | { |
| 123 | int i; |
| 124 | |
| 125 | kfree(udc->hw_bank.regmap); |
| 126 | |
| 127 | udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *), |
| 128 | GFP_KERNEL); |
| 129 | if (!udc->hw_bank.regmap) |
| 130 | return -ENOMEM; |
| 131 | |
| 132 | for (i = 0; i < OP_ENDPTCTRL; i++) |
| 133 | udc->hw_bank.regmap[i] = |
| 134 | (i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) + |
| 135 | (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); |
| 136 | |
| 137 | for (; i <= OP_LAST; i++) |
| 138 | udc->hw_bank.regmap[i] = udc->hw_bank.op + |
| 139 | 4 * (i - OP_ENDPTCTRL) + |
| 140 | (is_lpm |
| 141 | ? ci_regs_lpm[OP_ENDPTCTRL] |
| 142 | : ci_regs_nolpm[OP_ENDPTCTRL]); |
| 143 | |
| 144 | return 0; |
| 145 | } |
| 146 | |
| 147 | /** |
| 148 | * hw_port_test_set: writes port test mode (execute without interruption) |
| 149 | * @mode: new value |
| 150 | * |
| 151 | * This function returns an error code |
| 152 | */ |
| 153 | int hw_port_test_set(struct ci13xxx *ci, u8 mode) |
| 154 | { |
| 155 | const u8 TEST_MODE_MAX = 7; |
| 156 | |
| 157 | if (mode > TEST_MODE_MAX) |
| 158 | return -EINVAL; |
| 159 | |
| 160 | hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC)); |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | /** |
| 165 | * hw_port_test_get: reads port test mode value |
| 166 | * |
| 167 | * This function returns port test mode value |
| 168 | */ |
| 169 | u8 hw_port_test_get(struct ci13xxx *ci) |
| 170 | { |
| 171 | return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC); |
| 172 | } |
| 173 | |
| 174 | int hw_device_init(struct ci13xxx *udc, void __iomem *base, |
| 175 | uintptr_t cap_offset) |
| 176 | { |
| 177 | u32 reg; |
| 178 | |
| 179 | /* bank is a module variable */ |
| 180 | udc->hw_bank.abs = base; |
| 181 | |
| 182 | udc->hw_bank.cap = udc->hw_bank.abs; |
| 183 | udc->hw_bank.cap += cap_offset; |
| 184 | udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap); |
| 185 | |
| 186 | hw_alloc_regmap(udc, false); |
| 187 | reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >> |
| 188 | ffs_nr(HCCPARAMS_LEN); |
| 189 | udc->hw_bank.lpm = reg; |
| 190 | hw_alloc_regmap(udc, !!reg); |
| 191 | udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs; |
| 192 | udc->hw_bank.size += OP_LAST; |
| 193 | udc->hw_bank.size /= sizeof(u32); |
| 194 | |
| 195 | reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >> |
| 196 | ffs_nr(DCCPARAMS_DEN); |
| 197 | udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ |
| 198 | |
| 199 | if (udc->hw_ep_max == 0 || udc->hw_ep_max > ENDPT_MAX) |
| 200 | return -ENODEV; |
| 201 | |
| 202 | dev_dbg(udc->dev, "ChipIdea UDC found, lpm: %d; cap: %p op: %p\n", |
| 203 | udc->hw_bank.lpm, udc->hw_bank.cap, udc->hw_bank.op); |
| 204 | |
| 205 | /* setup lock mode ? */ |
| 206 | |
| 207 | /* ENDPTSETUPSTAT is '0' by default */ |
| 208 | |
| 209 | /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ |
| 210 | |
| 211 | return 0; |
| 212 | } |
| 213 | |
| 214 | /** |
| 215 | * hw_device_reset: resets chip (execute without interruption) |
| 216 | * @ci: the controller |
| 217 | * |
| 218 | * This function returns an error code |
| 219 | */ |
| 220 | int hw_device_reset(struct ci13xxx *ci) |
| 221 | { |
| 222 | /* should flush & stop before reset */ |
| 223 | hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); |
| 224 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); |
| 225 | |
| 226 | hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); |
| 227 | while (hw_read(ci, OP_USBCMD, USBCMD_RST)) |
| 228 | udelay(10); /* not RTOS friendly */ |
| 229 | |
| 230 | |
| 231 | if (ci->udc_driver->notify_event) |
| 232 | ci->udc_driver->notify_event(ci, |
| 233 | CI13XXX_CONTROLLER_RESET_EVENT); |
| 234 | |
| 235 | if (ci->udc_driver->flags & CI13XXX_DISABLE_STREAMING) |
| 236 | hw_write(ci, OP_USBMODE, USBMODE_SDIS, USBMODE_SDIS); |
| 237 | |
| 238 | /* USBMODE should be configured step by step */ |
| 239 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); |
| 240 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE); |
| 241 | /* HW >= 2.3 */ |
| 242 | hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); |
| 243 | |
| 244 | if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) { |
| 245 | pr_err("cannot enter in device mode"); |
| 246 | pr_err("lpm = %i", ci->hw_bank.lpm); |
| 247 | return -ENODEV; |
| 248 | } |
| 249 | |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | static int __devinit ci_udc_probe(struct platform_device *pdev) |
| 254 | { |
| 255 | struct device *dev = &pdev->dev; |
| 256 | struct ci13xxx_udc_driver *driver = dev->platform_data; |
| 257 | struct ci13xxx *udc; |
| 258 | struct resource *res; |
| 259 | void __iomem *base; |
| 260 | int ret; |
| 261 | |
| 262 | if (!driver) { |
| 263 | dev_err(dev, "platform data missing\n"); |
| 264 | return -ENODEV; |
| 265 | } |
| 266 | |
| 267 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 268 | if (!res) { |
| 269 | dev_err(dev, "missing resource\n"); |
| 270 | return -ENODEV; |
| 271 | } |
| 272 | |
| 273 | base = devm_request_and_ioremap(dev, res); |
| 274 | if (!res) { |
| 275 | dev_err(dev, "can't request and ioremap resource\n"); |
| 276 | return -ENOMEM; |
| 277 | } |
| 278 | |
| 279 | ret = udc_probe(driver, dev, base, &udc); |
| 280 | if (ret) |
| 281 | return ret; |
| 282 | |
| 283 | udc->irq = platform_get_irq(pdev, 0); |
| 284 | if (udc->irq < 0) { |
| 285 | dev_err(dev, "missing IRQ\n"); |
| 286 | ret = -ENODEV; |
| 287 | goto out; |
| 288 | } |
| 289 | |
| 290 | platform_set_drvdata(pdev, udc); |
| 291 | ret = request_irq(udc->irq, udc_irq, IRQF_SHARED, driver->name, udc); |
| 292 | |
| 293 | out: |
| 294 | if (ret) |
| 295 | udc_remove(udc); |
| 296 | |
| 297 | return ret; |
| 298 | } |
| 299 | |
| 300 | static int __devexit ci_udc_remove(struct platform_device *pdev) |
| 301 | { |
| 302 | struct ci13xxx *udc = platform_get_drvdata(pdev); |
| 303 | |
| 304 | free_irq(udc->irq, udc); |
| 305 | udc_remove(udc); |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | static struct platform_driver ci_udc_driver = { |
| 311 | .probe = ci_udc_probe, |
| 312 | .remove = __devexit_p(ci_udc_remove), |
| 313 | .driver = { |
| 314 | .name = "ci_udc", |
| 315 | }, |
| 316 | }; |
| 317 | |
| 318 | module_platform_driver(ci_udc_driver); |
| 319 | |
| 320 | MODULE_ALIAS("platform:ci_udc"); |
| 321 | MODULE_ALIAS("platform:ci13xxx"); |
| 322 | MODULE_LICENSE("GPL v2"); |
| 323 | MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); |
| 324 | MODULE_DESCRIPTION("ChipIdea UDC Driver"); |