blob: d1b646c099fa9a19a0c00c330d1fc14a33da7287 [file] [log] [blame]
Kevin Hilmane38d92f2009-04-29 17:44:58 -07001/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000011#include <linux/dma-mapping.h>
Kevin Hilmane38d92f2009-04-29 17:44:58 -070012#include <linux/init.h>
13#include <linux/clk.h>
Mark A. Greer65e866a2009-03-18 12:36:08 -050014#include <linux/serial_8250.h>
Kevin Hilmane38d92f2009-04-29 17:44:58 -070015#include <linux/platform_device.h>
Matt Porter3ad7a422013-03-06 11:15:31 -050016#include <linux/platform_data/edma.h>
Philip Avinash9cc15152013-08-18 10:49:00 +053017#include <linux/platform_data/gpio-davinci.h>
Kevin Hilmane38d92f2009-04-29 17:44:58 -070018
Mark A. Greer79c3c0b2009-04-15 12:38:58 -070019#include <asm/mach/map.h>
20
Kevin Hilmane38d92f2009-04-29 17:44:58 -070021#include <mach/cputype.h>
Kevin Hilmane38d92f2009-04-29 17:44:58 -070022#include <mach/irqs.h>
23#include <mach/psc.h>
24#include <mach/mux.h>
Mark A. Greerf64691b2009-04-15 12:40:11 -070025#include <mach/time.h>
Mark A. Greer65e866a2009-03-18 12:36:08 -050026#include <mach/serial.h>
Mark A. Greer79c3c0b2009-04-15 12:38:58 -070027#include <mach/common.h>
Kevin Hilmane38d92f2009-04-29 17:44:58 -070028
Manjunath Hadli39c6d2d2011-12-21 19:13:35 +053029#include "davinci.h"
Kevin Hilmane38d92f2009-04-29 17:44:58 -070030#include "clock.h"
31#include "mux.h"
Hebbar, Gururaja896f66b2012-08-27 18:56:41 +053032#include "asp.h"
Kevin Hilmane38d92f2009-04-29 17:44:58 -070033
Muralidharan Karicheri85609c12009-09-16 13:15:30 -040034#define DAVINCI_VPIF_BASE (0x01C12000)
Muralidharan Karicheri85609c12009-09-16 13:15:30 -040035
36#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
37 BIT_MASK(0))
38#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
39 BIT_MASK(8))
40
Kevin Hilmane38d92f2009-04-29 17:44:58 -070041/*
42 * Device specific clocks
43 */
Sekhar Nori56e580d2011-06-14 15:33:20 +000044#define DM646X_REF_FREQ 27000000
Kevin Hilmane38d92f2009-04-29 17:44:58 -070045#define DM646X_AUX_FREQ 24000000
46
Manjunath Hadli3d091402011-12-15 17:41:51 +053047#define DM646X_EMAC_BASE 0x01c80000
48#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
49#define DM646X_EMAC_CNTRL_OFFSET 0x0000
50#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
51#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
52#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
53
Kevin Hilmane38d92f2009-04-29 17:44:58 -070054static struct pll_data pll1_data = {
55 .num = 1,
56 .phys_base = DAVINCI_PLL1_BASE,
57};
58
59static struct pll_data pll2_data = {
60 .num = 2,
61 .phys_base = DAVINCI_PLL2_BASE,
62};
63
64static struct clk ref_clk = {
65 .name = "ref_clk",
Sekhar Nori56e580d2011-06-14 15:33:20 +000066 .rate = DM646X_REF_FREQ,
67 .set_rate = davinci_simple_set_rate,
Kevin Hilmane38d92f2009-04-29 17:44:58 -070068};
69
70static struct clk aux_clkin = {
71 .name = "aux_clkin",
72 .rate = DM646X_AUX_FREQ,
73};
74
75static struct clk pll1_clk = {
76 .name = "pll1",
77 .parent = &ref_clk,
78 .pll_data = &pll1_data,
79 .flags = CLK_PLL,
80};
81
82static struct clk pll1_sysclk1 = {
83 .name = "pll1_sysclk1",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV1,
87};
88
89static struct clk pll1_sysclk2 = {
90 .name = "pll1_sysclk2",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV2,
94};
95
96static struct clk pll1_sysclk3 = {
97 .name = "pll1_sysclk3",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV3,
101};
102
103static struct clk pll1_sysclk4 = {
104 .name = "pll1_sysclk4",
105 .parent = &pll1_clk,
106 .flags = CLK_PLL,
107 .div_reg = PLLDIV4,
108};
109
110static struct clk pll1_sysclk5 = {
111 .name = "pll1_sysclk5",
112 .parent = &pll1_clk,
113 .flags = CLK_PLL,
114 .div_reg = PLLDIV5,
115};
116
117static struct clk pll1_sysclk6 = {
118 .name = "pll1_sysclk6",
119 .parent = &pll1_clk,
120 .flags = CLK_PLL,
121 .div_reg = PLLDIV6,
122};
123
124static struct clk pll1_sysclk8 = {
125 .name = "pll1_sysclk8",
126 .parent = &pll1_clk,
127 .flags = CLK_PLL,
128 .div_reg = PLLDIV8,
129};
130
131static struct clk pll1_sysclk9 = {
132 .name = "pll1_sysclk9",
133 .parent = &pll1_clk,
134 .flags = CLK_PLL,
135 .div_reg = PLLDIV9,
136};
137
138static struct clk pll1_sysclkbp = {
139 .name = "pll1_sysclkbp",
140 .parent = &pll1_clk,
141 .flags = CLK_PLL | PRE_PLL,
142 .div_reg = BPDIV,
143};
144
145static struct clk pll1_aux_clk = {
146 .name = "pll1_aux_clk",
147 .parent = &pll1_clk,
148 .flags = CLK_PLL | PRE_PLL,
149};
150
151static struct clk pll2_clk = {
152 .name = "pll2_clk",
153 .parent = &ref_clk,
154 .pll_data = &pll2_data,
155 .flags = CLK_PLL,
156};
157
158static struct clk pll2_sysclk1 = {
159 .name = "pll2_sysclk1",
160 .parent = &pll2_clk,
161 .flags = CLK_PLL,
162 .div_reg = PLLDIV1,
163};
164
165static struct clk dsp_clk = {
166 .name = "dsp",
167 .parent = &pll1_sysclk1,
168 .lpsc = DM646X_LPSC_C64X_CPU,
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700169 .usecount = 1, /* REVISIT how to disable? */
170};
171
172static struct clk arm_clk = {
173 .name = "arm",
174 .parent = &pll1_sysclk2,
175 .lpsc = DM646X_LPSC_ARM,
176 .flags = ALWAYS_ENABLED,
177};
178
Sudhakar Rajashekhara2bcb6132009-06-02 03:38:26 -0400179static struct clk edma_cc_clk = {
180 .name = "edma_cc",
181 .parent = &pll1_sysclk2,
182 .lpsc = DM646X_LPSC_TPCC,
183 .flags = ALWAYS_ENABLED,
184};
185
186static struct clk edma_tc0_clk = {
187 .name = "edma_tc0",
188 .parent = &pll1_sysclk2,
189 .lpsc = DM646X_LPSC_TPTC0,
190 .flags = ALWAYS_ENABLED,
191};
192
193static struct clk edma_tc1_clk = {
194 .name = "edma_tc1",
195 .parent = &pll1_sysclk2,
196 .lpsc = DM646X_LPSC_TPTC1,
197 .flags = ALWAYS_ENABLED,
198};
199
200static struct clk edma_tc2_clk = {
201 .name = "edma_tc2",
202 .parent = &pll1_sysclk2,
203 .lpsc = DM646X_LPSC_TPTC2,
204 .flags = ALWAYS_ENABLED,
205};
206
207static struct clk edma_tc3_clk = {
208 .name = "edma_tc3",
209 .parent = &pll1_sysclk2,
210 .lpsc = DM646X_LPSC_TPTC3,
211 .flags = ALWAYS_ENABLED,
212};
213
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700214static struct clk uart0_clk = {
215 .name = "uart0",
216 .parent = &aux_clkin,
217 .lpsc = DM646X_LPSC_UART0,
218};
219
220static struct clk uart1_clk = {
221 .name = "uart1",
222 .parent = &aux_clkin,
223 .lpsc = DM646X_LPSC_UART1,
224};
225
226static struct clk uart2_clk = {
227 .name = "uart2",
228 .parent = &aux_clkin,
229 .lpsc = DM646X_LPSC_UART2,
230};
231
232static struct clk i2c_clk = {
233 .name = "I2CCLK",
234 .parent = &pll1_sysclk3,
235 .lpsc = DM646X_LPSC_I2C,
236};
237
238static struct clk gpio_clk = {
239 .name = "gpio",
240 .parent = &pll1_sysclk3,
241 .lpsc = DM646X_LPSC_GPIO,
242};
243
Chaithrika U S75d0fa72009-05-28 05:09:21 -0400244static struct clk mcasp0_clk = {
245 .name = "mcasp0",
246 .parent = &pll1_sysclk3,
247 .lpsc = DM646X_LPSC_McASP0,
248};
249
250static struct clk mcasp1_clk = {
251 .name = "mcasp1",
252 .parent = &pll1_sysclk3,
253 .lpsc = DM646X_LPSC_McASP1,
254};
255
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700256static struct clk aemif_clk = {
257 .name = "aemif",
258 .parent = &pll1_sysclk3,
259 .lpsc = DM646X_LPSC_AEMIF,
260 .flags = ALWAYS_ENABLED,
261};
262
263static struct clk emac_clk = {
264 .name = "emac",
265 .parent = &pll1_sysclk3,
266 .lpsc = DM646X_LPSC_EMAC,
267};
268
269static struct clk pwm0_clk = {
270 .name = "pwm0",
271 .parent = &pll1_sysclk3,
272 .lpsc = DM646X_LPSC_PWM0,
273 .usecount = 1, /* REVIST: disabling hangs system */
274};
275
276static struct clk pwm1_clk = {
277 .name = "pwm1",
278 .parent = &pll1_sysclk3,
279 .lpsc = DM646X_LPSC_PWM1,
280 .usecount = 1, /* REVIST: disabling hangs system */
281};
282
283static struct clk timer0_clk = {
284 .name = "timer0",
285 .parent = &pll1_sysclk3,
286 .lpsc = DM646X_LPSC_TIMER0,
287};
288
289static struct clk timer1_clk = {
290 .name = "timer1",
291 .parent = &pll1_sysclk3,
292 .lpsc = DM646X_LPSC_TIMER1,
293};
294
295static struct clk timer2_clk = {
296 .name = "timer2",
297 .parent = &pll1_sysclk3,
298 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
299};
300
Hemant Pedanekar3e25d5f2009-07-07 19:49:41 +0530301
302static struct clk ide_clk = {
303 .name = "ide",
304 .parent = &pll1_sysclk4,
305 .lpsc = DAVINCI_LPSC_ATA,
306};
307
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700308static struct clk vpif0_clk = {
309 .name = "vpif0",
310 .parent = &ref_clk,
311 .lpsc = DM646X_LPSC_VPSSMSTR,
312 .flags = ALWAYS_ENABLED,
313};
314
315static struct clk vpif1_clk = {
316 .name = "vpif1",
317 .parent = &ref_clk,
318 .lpsc = DM646X_LPSC_VPSSSLV,
319 .flags = ALWAYS_ENABLED,
320};
321
Kevin Hilman28552c22010-02-25 15:36:38 -0800322static struct clk_lookup dm646x_clks[] = {
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700323 CLK(NULL, "ref", &ref_clk),
324 CLK(NULL, "aux", &aux_clkin),
325 CLK(NULL, "pll1", &pll1_clk),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
329 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
330 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
331 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
332 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
333 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
334 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
335 CLK(NULL, "pll1_aux", &pll1_aux_clk),
336 CLK(NULL, "pll2", &pll2_clk),
337 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
338 CLK(NULL, "dsp", &dsp_clk),
339 CLK(NULL, "arm", &arm_clk),
Sudhakar Rajashekhara2bcb6132009-06-02 03:38:26 -0400340 CLK(NULL, "edma_cc", &edma_cc_clk),
341 CLK(NULL, "edma_tc0", &edma_tc0_clk),
342 CLK(NULL, "edma_tc1", &edma_tc1_clk),
343 CLK(NULL, "edma_tc2", &edma_tc2_clk),
344 CLK(NULL, "edma_tc3", &edma_tc3_clk),
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530345 CLK("serial8250.0", NULL, &uart0_clk),
346 CLK("serial8250.1", NULL, &uart1_clk),
347 CLK("serial8250.2", NULL, &uart2_clk),
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700348 CLK("i2c_davinci.1", NULL, &i2c_clk),
349 CLK(NULL, "gpio", &gpio_clk),
Kevin Hilman61aa0732009-07-15 08:47:48 -0700350 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
351 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700352 CLK(NULL, "aemif", &aemif_clk),
353 CLK("davinci_emac.1", NULL, &emac_clk),
Lad, Prabhakar46c18332013-08-15 11:31:33 +0530354 CLK("davinci_mdio.0", "fck", &emac_clk),
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700355 CLK(NULL, "pwm0", &pwm0_clk),
356 CLK(NULL, "pwm1", &pwm1_clk),
357 CLK(NULL, "timer0", &timer0_clk),
358 CLK(NULL, "timer1", &timer1_clk),
359 CLK("watchdog", NULL, &timer2_clk),
Hemant Pedanekar3e25d5f2009-07-07 19:49:41 +0530360 CLK("palm_bk3710", NULL, &ide_clk),
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700361 CLK(NULL, "vpif0", &vpif0_clk),
362 CLK(NULL, "vpif1", &vpif1_clk),
363 CLK(NULL, NULL, NULL),
364};
365
Mark A. Greer972412b2009-04-15 12:40:56 -0700366static struct emac_platform_data dm646x_emac_pdata = {
367 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
368 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
369 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
Mark A. Greer972412b2009-04-15 12:40:56 -0700370 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
371 .version = EMAC_VERSION_2,
372};
373
Kevin Hilmanac7b75b2009-05-07 06:19:40 -0700374static struct resource dm646x_emac_resources[] = {
375 {
376 .start = DM646X_EMAC_BASE,
Cyril Chemparathyd22960c2010-09-15 10:11:22 -0400377 .end = DM646X_EMAC_BASE + SZ_16K - 1,
Kevin Hilmanac7b75b2009-05-07 06:19:40 -0700378 .flags = IORESOURCE_MEM,
379 },
380 {
381 .start = IRQ_DM646X_EMACRXTHINT,
382 .end = IRQ_DM646X_EMACRXTHINT,
383 .flags = IORESOURCE_IRQ,
384 },
385 {
386 .start = IRQ_DM646X_EMACRXINT,
387 .end = IRQ_DM646X_EMACRXINT,
388 .flags = IORESOURCE_IRQ,
389 },
390 {
391 .start = IRQ_DM646X_EMACTXINT,
392 .end = IRQ_DM646X_EMACTXINT,
393 .flags = IORESOURCE_IRQ,
394 },
395 {
396 .start = IRQ_DM646X_EMACMISCINT,
397 .end = IRQ_DM646X_EMACMISCINT,
398 .flags = IORESOURCE_IRQ,
399 },
400};
401
402static struct platform_device dm646x_emac_device = {
403 .name = "davinci_emac",
404 .id = 1,
Mark A. Greer972412b2009-04-15 12:40:56 -0700405 .dev = {
406 .platform_data = &dm646x_emac_pdata,
407 },
Kevin Hilmanac7b75b2009-05-07 06:19:40 -0700408 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
409 .resource = dm646x_emac_resources,
410};
411
Cyril Chemparathyd22960c2010-09-15 10:11:22 -0400412static struct resource dm646x_mdio_resources[] = {
413 {
414 .start = DM646X_EMAC_MDIO_BASE,
415 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
416 .flags = IORESOURCE_MEM,
417 },
418};
419
420static struct platform_device dm646x_mdio_device = {
421 .name = "davinci_mdio",
422 .id = 0,
423 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
424 .resource = dm646x_mdio_resources,
425};
426
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700427/*
428 * Device specific mux setup
429 *
430 * soc description mux mode mode mux dbg
431 * reg offset mask mode
432 */
433static const struct mux_config dm646x_pins[] = {
Mark A. Greer0e585952009-04-15 12:39:48 -0700434#ifdef CONFIG_DAVINCI_MUX
Hemant Pedanekar3e25d5f2009-07-07 19:49:41 +0530435MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700436
437MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
438
439MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
440
441MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
442
443MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
444
445MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
446
447MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
448
449MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
450
451MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
452
453MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
454
455MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
456
457MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
458
459MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
460
461MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
Mark A. Greer0e585952009-04-15 12:39:48 -0700462#endif
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700463};
464
Mark A. Greer673dd362009-04-15 12:40:00 -0700465static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
466 [IRQ_DM646X_VP_VERTINT0] = 7,
467 [IRQ_DM646X_VP_VERTINT1] = 7,
468 [IRQ_DM646X_VP_VERTINT2] = 7,
469 [IRQ_DM646X_VP_VERTINT3] = 7,
470 [IRQ_DM646X_VP_ERRINT] = 7,
471 [IRQ_DM646X_RESERVED_1] = 7,
472 [IRQ_DM646X_RESERVED_2] = 7,
473 [IRQ_DM646X_WDINT] = 7,
474 [IRQ_DM646X_CRGENINT0] = 7,
475 [IRQ_DM646X_CRGENINT1] = 7,
476 [IRQ_DM646X_TSIFINT0] = 7,
477 [IRQ_DM646X_TSIFINT1] = 7,
478 [IRQ_DM646X_VDCEINT] = 7,
479 [IRQ_DM646X_USBINT] = 7,
480 [IRQ_DM646X_USBDMAINT] = 7,
481 [IRQ_DM646X_PCIINT] = 7,
482 [IRQ_CCINT0] = 7, /* dma */
483 [IRQ_CCERRINT] = 7, /* dma */
484 [IRQ_TCERRINT0] = 7, /* dma */
485 [IRQ_TCERRINT] = 7, /* dma */
486 [IRQ_DM646X_TCERRINT2] = 7,
487 [IRQ_DM646X_TCERRINT3] = 7,
488 [IRQ_DM646X_IDE] = 7,
489 [IRQ_DM646X_HPIINT] = 7,
490 [IRQ_DM646X_EMACRXTHINT] = 7,
491 [IRQ_DM646X_EMACRXINT] = 7,
492 [IRQ_DM646X_EMACTXINT] = 7,
493 [IRQ_DM646X_EMACMISCINT] = 7,
494 [IRQ_DM646X_MCASP0TXINT] = 7,
495 [IRQ_DM646X_MCASP0RXINT] = 7,
496 [IRQ_AEMIFINT] = 7,
497 [IRQ_DM646X_RESERVED_3] = 7,
498 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
499 [IRQ_TINT0_TINT34] = 7, /* clocksource */
500 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
501 [IRQ_TINT1_TINT34] = 7, /* system tick */
502 [IRQ_PWMINT0] = 7,
503 [IRQ_PWMINT1] = 7,
504 [IRQ_DM646X_VLQINT] = 7,
505 [IRQ_I2C] = 7,
506 [IRQ_UARTINT0] = 7,
507 [IRQ_UARTINT1] = 7,
508 [IRQ_DM646X_UARTINT2] = 7,
509 [IRQ_DM646X_SPINT0] = 7,
510 [IRQ_DM646X_SPINT1] = 7,
511 [IRQ_DM646X_DSP2ARMINT] = 7,
512 [IRQ_DM646X_RESERVED_4] = 7,
513 [IRQ_DM646X_PSCINT] = 7,
514 [IRQ_DM646X_GPIO0] = 7,
515 [IRQ_DM646X_GPIO1] = 7,
516 [IRQ_DM646X_GPIO2] = 7,
517 [IRQ_DM646X_GPIO3] = 7,
518 [IRQ_DM646X_GPIO4] = 7,
519 [IRQ_DM646X_GPIO5] = 7,
520 [IRQ_DM646X_GPIO6] = 7,
521 [IRQ_DM646X_GPIO7] = 7,
522 [IRQ_DM646X_GPIOBNK0] = 7,
523 [IRQ_DM646X_GPIOBNK1] = 7,
524 [IRQ_DM646X_GPIOBNK2] = 7,
525 [IRQ_DM646X_DDRINT] = 7,
526 [IRQ_DM646X_AEMIFINT] = 7,
527 [IRQ_COMMTX] = 7,
528 [IRQ_COMMRX] = 7,
529 [IRQ_EMUINT] = 7,
530};
531
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700532/*----------------------------------------------------------------------*/
533
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400534/* Four Transfer Controllers on DM646x */
Matt Porter6cba4352013-06-20 16:06:38 -0500535static s8
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400536dm646x_queue_tc_mapping[][2] = {
537 /* {event queue no, TC no} */
538 {0, 0},
539 {1, 1},
540 {2, 2},
541 {3, 3},
542 {-1, -1},
543};
544
Matt Porter6cba4352013-06-20 16:06:38 -0500545static s8
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400546dm646x_queue_priority_mapping[][2] = {
547 /* {event queue no, Priority} */
548 {0, 4},
549 {1, 0},
550 {2, 5},
551 {3, 1},
552 {-1, -1},
553};
554
Sekhar Noribc3ac9f2010-06-29 11:35:12 +0530555static struct edma_soc_info edma_cc0_info = {
556 .n_channel = 64,
557 .n_region = 6, /* 0-1, 4-7 */
558 .n_slot = 512,
559 .n_tc = 4,
560 .n_cc = 1,
561 .queue_tc_mapping = dm646x_queue_tc_mapping,
562 .queue_priority_mapping = dm646x_queue_priority_mapping,
Ido Yarivf23fe852011-07-10 16:14:35 +0300563 .default_queue = EVENTQ_1,
Sekhar Noribc3ac9f2010-06-29 11:35:12 +0530564};
565
566static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
567 &edma_cc0_info,
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700568};
569
570static struct resource edma_resources[] = {
571 {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400572 .name = "edma_cc0",
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700573 .start = 0x01c00000,
574 .end = 0x01c00000 + SZ_64K - 1,
575 .flags = IORESOURCE_MEM,
576 },
577 {
578 .name = "edma_tc0",
579 .start = 0x01c10000,
580 .end = 0x01c10000 + SZ_1K - 1,
581 .flags = IORESOURCE_MEM,
582 },
583 {
584 .name = "edma_tc1",
585 .start = 0x01c10400,
586 .end = 0x01c10400 + SZ_1K - 1,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .name = "edma_tc2",
591 .start = 0x01c10800,
592 .end = 0x01c10800 + SZ_1K - 1,
593 .flags = IORESOURCE_MEM,
594 },
595 {
596 .name = "edma_tc3",
597 .start = 0x01c10c00,
598 .end = 0x01c10c00 + SZ_1K - 1,
599 .flags = IORESOURCE_MEM,
600 },
601 {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400602 .name = "edma0",
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700603 .start = IRQ_CCINT0,
604 .flags = IORESOURCE_IRQ,
605 },
606 {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400607 .name = "edma0_err",
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700608 .start = IRQ_CCERRINT,
609 .flags = IORESOURCE_IRQ,
610 },
611 /* not using TC*_ERR */
612};
613
614static struct platform_device dm646x_edma_device = {
615 .name = "edma",
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400616 .id = 0,
617 .dev.platform_data = dm646x_edma_info,
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700618 .num_resources = ARRAY_SIZE(edma_resources),
619 .resource = edma_resources,
620};
621
Chaithrika U S25acf552009-06-05 06:28:08 -0400622static struct resource dm646x_mcasp0_resources[] = {
623 {
624 .name = "mcasp0",
625 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
626 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
627 .flags = IORESOURCE_MEM,
628 },
629 /* first TX, then RX */
630 {
631 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
632 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
633 .flags = IORESOURCE_DMA,
634 },
635 {
636 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
637 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
638 .flags = IORESOURCE_DMA,
639 },
640};
641
642static struct resource dm646x_mcasp1_resources[] = {
643 {
644 .name = "mcasp1",
645 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
646 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 /* DIT mode, only TX event */
650 {
651 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
652 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
653 .flags = IORESOURCE_DMA,
654 },
655 /* DIT mode, dummy entry */
656 {
657 .start = -1,
658 .end = -1,
659 .flags = IORESOURCE_DMA,
660 },
661};
662
663static struct platform_device dm646x_mcasp0_device = {
664 .name = "davinci-mcasp",
665 .id = 0,
666 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
667 .resource = dm646x_mcasp0_resources,
668};
669
670static struct platform_device dm646x_mcasp1_device = {
671 .name = "davinci-mcasp",
672 .id = 1,
673 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
674 .resource = dm646x_mcasp1_resources,
675};
676
677static struct platform_device dm646x_dit_device = {
678 .name = "spdif-dit",
679 .id = -1,
680};
681
Muralidharan Karicheri85609c12009-09-16 13:15:30 -0400682static u64 vpif_dma_mask = DMA_BIT_MASK(32);
683
684static struct resource vpif_resource[] = {
685 {
686 .start = DAVINCI_VPIF_BASE,
687 .end = DAVINCI_VPIF_BASE + 0x03ff,
688 .flags = IORESOURCE_MEM,
689 }
690};
691
692static struct platform_device vpif_dev = {
693 .name = "vpif",
694 .id = -1,
695 .dev = {
696 .dma_mask = &vpif_dma_mask,
697 .coherent_dma_mask = DMA_BIT_MASK(32),
698 },
699 .resource = vpif_resource,
700 .num_resources = ARRAY_SIZE(vpif_resource),
701};
702
703static struct resource vpif_display_resource[] = {
704 {
705 .start = IRQ_DM646X_VP_VERTINT2,
706 .end = IRQ_DM646X_VP_VERTINT2,
707 .flags = IORESOURCE_IRQ,
708 },
709 {
710 .start = IRQ_DM646X_VP_VERTINT3,
711 .end = IRQ_DM646X_VP_VERTINT3,
712 .flags = IORESOURCE_IRQ,
713 },
714};
715
716static struct platform_device vpif_display_dev = {
717 .name = "vpif_display",
718 .id = -1,
719 .dev = {
720 .dma_mask = &vpif_dma_mask,
721 .coherent_dma_mask = DMA_BIT_MASK(32),
722 },
723 .resource = vpif_display_resource,
724 .num_resources = ARRAY_SIZE(vpif_display_resource),
725};
726
727static struct resource vpif_capture_resource[] = {
728 {
729 .start = IRQ_DM646X_VP_VERTINT0,
730 .end = IRQ_DM646X_VP_VERTINT0,
731 .flags = IORESOURCE_IRQ,
732 },
733 {
734 .start = IRQ_DM646X_VP_VERTINT1,
735 .end = IRQ_DM646X_VP_VERTINT1,
736 .flags = IORESOURCE_IRQ,
737 },
738};
739
740static struct platform_device vpif_capture_dev = {
741 .name = "vpif_capture",
742 .id = -1,
743 .dev = {
744 .dma_mask = &vpif_dma_mask,
745 .coherent_dma_mask = DMA_BIT_MASK(32),
746 },
747 .resource = vpif_capture_resource,
748 .num_resources = ARRAY_SIZE(vpif_capture_resource),
749};
750
Philip Avinash9cc15152013-08-18 10:49:00 +0530751static struct resource dm646x_gpio_resources[] = {
752 { /* registers */
753 .start = DAVINCI_GPIO_BASE,
754 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
755 .flags = IORESOURCE_MEM,
756 },
757 { /* interrupt */
758 .start = IRQ_DM646X_GPIOBNK0,
759 .end = IRQ_DM646X_GPIOBNK2,
760 .flags = IORESOURCE_IRQ,
761 },
762};
763
764static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
765 .ngpio = 43,
766 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
767};
768
769int __init dm646x_gpio_register(void)
770{
771 return davinci_gpio_register(dm646x_gpio_resources,
Lad, Prabhakare462f1f2013-11-08 12:15:56 +0530772 ARRAY_SIZE(dm646x_gpio_resources),
Philip Avinash9cc15152013-08-18 10:49:00 +0530773 &dm646x_gpio_platform_data);
774}
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700775/*----------------------------------------------------------------------*/
776
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700777static struct map_desc dm646x_io_desc[] = {
778 {
779 .virtual = IO_VIRT,
780 .pfn = __phys_to_pfn(IO_PHYS),
781 .length = IO_SIZE,
782 .type = MT_DEVICE
783 },
784};
785
Mark A. Greerb9ab1272009-04-15 12:39:09 -0700786/* Contents of JTAG ID register used to identify exact cpu type */
787static struct davinci_id dm646x_ids[] = {
788 {
789 .variant = 0x0,
790 .part_no = 0xb770,
791 .manufacturer = 0x017,
792 .cpu_id = DAVINCI_CPU_ID_DM6467,
Hemant Pedanekarf63dd122009-09-02 16:49:35 +0530793 .name = "dm6467_rev1.x",
794 },
795 {
796 .variant = 0x1,
797 .part_no = 0xb770,
798 .manufacturer = 0x017,
799 .cpu_id = DAVINCI_CPU_ID_DM6467,
800 .name = "dm6467_rev3.x",
Mark A. Greerb9ab1272009-04-15 12:39:09 -0700801 },
802};
803
Cyril Chemparathye4c822c2010-05-07 17:06:36 -0400804static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
Mark A. Greerd81d1882009-04-15 12:39:33 -0700805
Mark A. Greerf64691b2009-04-15 12:40:11 -0700806/*
807 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
808 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
809 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
810 * T1_TOP: Timer 1, top : <unused>
811 */
Kevin Hilman28552c22010-02-25 15:36:38 -0800812static struct davinci_timer_info dm646x_timer_info = {
Mark A. Greerf64691b2009-04-15 12:40:11 -0700813 .timers = davinci_timer_instance,
814 .clockevent_id = T0_BOT,
815 .clocksource_id = T0_TOP,
816};
817
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530818static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
Mark A. Greer65e866a2009-03-18 12:36:08 -0500819 {
820 .mapbase = DAVINCI_UART0_BASE,
821 .irq = IRQ_UARTINT0,
822 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
823 UPF_IOREMAP,
824 .iotype = UPIO_MEM32,
825 .regshift = 2,
826 },
827 {
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530828 .flags = 0,
829 }
830};
831static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
832 {
Mark A. Greer65e866a2009-03-18 12:36:08 -0500833 .mapbase = DAVINCI_UART1_BASE,
834 .irq = IRQ_UARTINT1,
835 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
836 UPF_IOREMAP,
837 .iotype = UPIO_MEM32,
838 .regshift = 2,
839 },
840 {
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530841 .flags = 0,
842 }
843};
844static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
845 {
Mark A. Greer65e866a2009-03-18 12:36:08 -0500846 .mapbase = DAVINCI_UART2_BASE,
847 .irq = IRQ_DM646X_UARTINT2,
848 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
849 UPF_IOREMAP,
850 .iotype = UPIO_MEM32,
851 .regshift = 2,
852 },
853 {
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530854 .flags = 0,
855 }
Mark A. Greer65e866a2009-03-18 12:36:08 -0500856};
857
Manjunathappa, Prakashfcf71572013-06-19 14:45:42 +0530858struct platform_device dm646x_serial_device[] = {
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530859 {
860 .name = "serial8250",
861 .id = PLAT8250_DEV_PLATFORM,
862 .dev = {
863 .platform_data = dm646x_serial0_platform_data,
864 }
Mark A. Greer65e866a2009-03-18 12:36:08 -0500865 },
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530866 {
867 .name = "serial8250",
868 .id = PLAT8250_DEV_PLATFORM1,
869 .dev = {
870 .platform_data = dm646x_serial1_platform_data,
871 }
872 },
873 {
874 .name = "serial8250",
875 .id = PLAT8250_DEV_PLATFORM2,
876 .dev = {
877 .platform_data = dm646x_serial2_platform_data,
878 }
879 },
880 {
881 }
Mark A. Greer65e866a2009-03-18 12:36:08 -0500882};
883
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700884static struct davinci_soc_info davinci_soc_info_dm646x = {
885 .io_desc = dm646x_io_desc,
886 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
Cyril Chemparathy3347db82010-05-07 17:06:34 -0400887 .jtag_id_reg = 0x01c40028,
Mark A. Greerb9ab1272009-04-15 12:39:09 -0700888 .ids = dm646x_ids,
889 .ids_num = ARRAY_SIZE(dm646x_ids),
Mark A. Greer66e0c392009-04-15 12:39:23 -0700890 .cpu_clks = dm646x_clks,
Mark A. Greerd81d1882009-04-15 12:39:33 -0700891 .psc_bases = dm646x_psc_bases,
892 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
Cyril Chemparathy779b0d52010-05-07 17:06:38 -0400893 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
Mark A. Greer0e585952009-04-15 12:39:48 -0700894 .pinmux_pins = dm646x_pins,
895 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
Cyril Chemparathybd808942010-05-07 17:06:37 -0400896 .intc_base = DAVINCI_ARM_INTC_BASE,
Mark A. Greer673dd362009-04-15 12:40:00 -0700897 .intc_type = DAVINCI_INTC_TYPE_AINTC,
898 .intc_irq_prios = dm646x_default_priorities,
899 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
Mark A. Greerf64691b2009-04-15 12:40:11 -0700900 .timer_info = &dm646x_timer_info,
Mark A. Greer972412b2009-04-15 12:40:56 -0700901 .emac_pdata = &dm646x_emac_pdata,
David Brownell0d04eb42009-04-30 17:35:48 -0700902 .sram_dma = 0x10010000,
903 .sram_len = SZ_32K,
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700904};
905
Chaithrika U S25acf552009-06-05 06:28:08 -0400906void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
907{
908 dm646x_mcasp0_device.dev.platform_data = pdata;
909 platform_device_register(&dm646x_mcasp0_device);
910}
911
912void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
913{
914 dm646x_mcasp1_device.dev.platform_data = pdata;
915 platform_device_register(&dm646x_mcasp1_device);
916 platform_device_register(&dm646x_dit_device);
917}
918
Muralidharan Karicheri85609c12009-09-16 13:15:30 -0400919void dm646x_setup_vpif(struct vpif_display_config *display_config,
920 struct vpif_capture_config *capture_config)
921{
922 unsigned int value;
Muralidharan Karicheri85609c12009-09-16 13:15:30 -0400923
Manjunath Hadli5cfb19a2011-12-21 19:13:36 +0530924 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
Muralidharan Karicheri85609c12009-09-16 13:15:30 -0400925 value &= ~VSCLKDIS_MASK;
Manjunath Hadli5cfb19a2011-12-21 19:13:36 +0530926 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
Muralidharan Karicheri85609c12009-09-16 13:15:30 -0400927
Manjunath Hadli5cfb19a2011-12-21 19:13:36 +0530928 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
Muralidharan Karicheri85609c12009-09-16 13:15:30 -0400929 value &= ~VDD3P3V_VID_MASK;
Manjunath Hadli5cfb19a2011-12-21 19:13:36 +0530930 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
Muralidharan Karicheri85609c12009-09-16 13:15:30 -0400931
932 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
933 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
934 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
935 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
936
937 vpif_display_dev.dev.platform_data = display_config;
938 vpif_capture_dev.dev.platform_data = capture_config;
939 platform_device_register(&vpif_dev);
940 platform_device_register(&vpif_display_dev);
941 platform_device_register(&vpif_capture_dev);
942}
943
Rajashekhara, Sudhakarcce3ddd2010-06-29 11:35:15 +0530944int __init dm646x_init_edma(struct edma_rsv_info *rsv)
945{
946 edma_cc0_info.rsv = rsv;
947
948 return platform_device_register(&dm646x_edma_device);
949}
950
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700951void __init dm646x_init(void)
952{
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700953 davinci_common_init(&davinci_soc_info_dm646x);
Manjunath Hadli5cfb19a2011-12-21 19:13:36 +0530954 davinci_map_sysmod();
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700955}
956
957static int __init dm646x_init_devices(void)
958{
959 if (!cpu_is_davinci_dm646x())
960 return 0;
961
Cyril Chemparathyd22960c2010-09-15 10:11:22 -0400962 platform_device_register(&dm646x_mdio_device);
Mark A. Greer972412b2009-04-15 12:40:56 -0700963 platform_device_register(&dm646x_emac_device);
Cyril Chemparathyd22960c2010-09-15 10:11:22 -0400964
Kevin Hilmane38d92f2009-04-29 17:44:58 -0700965 return 0;
966}
967postcore_initcall(dm646x_init_devices);