Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf561/bf561.h |
| 3 | * Based on: |
| 4 | * Author: |
| 5 | * |
| 6 | * Created: |
| 7 | * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 |
| 8 | * |
| 9 | * Modified: |
| 10 | * Copyright 2004-2006 Analog Devices Inc. |
| 11 | * |
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, see the file COPYING, or write |
| 26 | * to the Free Software Foundation, Inc., |
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 28 | */ |
| 29 | |
| 30 | #ifndef __MACH_BF561_H__ |
| 31 | #define __MACH_BF561_H__ |
| 32 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 33 | #define OFFSET_(x) ((x) & 0x0000FFFF) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 34 | |
| 35 | /*some misc defines*/ |
| 36 | #define IMASK_IVG15 0x8000 |
| 37 | #define IMASK_IVG14 0x4000 |
| 38 | #define IMASK_IVG13 0x2000 |
| 39 | #define IMASK_IVG12 0x1000 |
| 40 | |
| 41 | #define IMASK_IVG11 0x0800 |
| 42 | #define IMASK_IVG10 0x0400 |
| 43 | #define IMASK_IVG9 0x0200 |
| 44 | #define IMASK_IVG8 0x0100 |
| 45 | |
| 46 | #define IMASK_IVG7 0x0080 |
| 47 | #define IMASK_IVGTMR 0x0040 |
| 48 | #define IMASK_IVGHW 0x0020 |
| 49 | |
| 50 | /*************************** |
| 51 | * Blackfin Cache setup |
| 52 | */ |
| 53 | |
| 54 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 55 | #define BFIN_ISUBBANKS 4 |
| 56 | #define BFIN_IWAYS 4 |
| 57 | #define BFIN_ILINES 32 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 58 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 59 | #define BFIN_DSUBBANKS 4 |
| 60 | #define BFIN_DWAYS 2 |
| 61 | #define BFIN_DLINES 64 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 62 | |
| 63 | #define WAY0_L 0x1 |
| 64 | #define WAY1_L 0x2 |
| 65 | #define WAY01_L 0x3 |
| 66 | #define WAY2_L 0x4 |
| 67 | #define WAY02_L 0x5 |
| 68 | #define WAY12_L 0x6 |
| 69 | #define WAY012_L 0x7 |
| 70 | |
| 71 | #define WAY3_L 0x8 |
| 72 | #define WAY03_L 0x9 |
| 73 | #define WAY13_L 0xA |
| 74 | #define WAY013_L 0xB |
| 75 | |
| 76 | #define WAY32_L 0xC |
| 77 | #define WAY320_L 0xD |
| 78 | #define WAY321_L 0xE |
| 79 | #define WAYALL_L 0xF |
| 80 | |
| 81 | #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ |
| 82 | |
| 83 | /* IAR0 BIT FIELDS */ |
| 84 | #define PLL_WAKEUP_BIT 0xFFFFFFFF |
| 85 | #define DMA1_ERROR_BIT 0xFFFFFF0F |
| 86 | #define DMA2_ERROR_BIT 0xFFFFF0FF |
| 87 | #define IMDMA_ERROR_BIT 0xFFFF0FFF |
| 88 | #define PPI1_ERROR_BIT 0xFFF0FFFF |
| 89 | #define PPI2_ERROR_BIT 0xFF0FFFFF |
| 90 | #define SPORT0_ERROR_BIT 0xF0FFFFFF |
| 91 | #define SPORT1_ERROR_BIT 0x0FFFFFFF |
| 92 | /* IAR1 BIT FIELDS */ |
| 93 | #define SPI_ERROR_BIT 0xFFFFFFFF |
| 94 | #define UART_ERROR_BIT 0xFFFFFF0F |
| 95 | #define RESERVED_ERROR_BIT 0xFFFFF0FF |
| 96 | #define DMA1_0_BIT 0xFFFF0FFF |
| 97 | #define DMA1_1_BIT 0xFFF0FFFF |
| 98 | #define DMA1_2_BIT 0xFF0FFFFF |
| 99 | #define DMA1_3_BIT 0xF0FFFFFF |
| 100 | #define DMA1_4_BIT 0x0FFFFFFF |
| 101 | /* IAR2 BIT FIELDS */ |
| 102 | #define DMA1_5_BIT 0xFFFFFFFF |
| 103 | #define DMA1_6_BIT 0xFFFFFF0F |
| 104 | #define DMA1_7_BIT 0xFFFFF0FF |
| 105 | #define DMA1_8_BIT 0xFFFF0FFF |
| 106 | #define DMA1_9_BIT 0xFFF0FFFF |
| 107 | #define DMA1_10_BIT 0xFF0FFFFF |
| 108 | #define DMA1_11_BIT 0xF0FFFFFF |
| 109 | #define DMA2_0_BIT 0x0FFFFFFF |
| 110 | /* IAR3 BIT FIELDS */ |
| 111 | #define DMA2_1_BIT 0xFFFFFFFF |
| 112 | #define DMA2_2_BIT 0xFFFFFF0F |
| 113 | #define DMA2_3_BIT 0xFFFFF0FF |
| 114 | #define DMA2_4_BIT 0xFFFF0FFF |
| 115 | #define DMA2_5_BIT 0xFFF0FFFF |
| 116 | #define DMA2_6_BIT 0xFF0FFFFF |
| 117 | #define DMA2_7_BIT 0xF0FFFFFF |
| 118 | #define DMA2_8_BIT 0x0FFFFFFF |
| 119 | /* IAR4 BIT FIELDS */ |
| 120 | #define DMA2_9_BIT 0xFFFFFFFF |
| 121 | #define DMA2_10_BIT 0xFFFFFF0F |
| 122 | #define DMA2_11_BIT 0xFFFFF0FF |
| 123 | #define TIMER0_BIT 0xFFFF0FFF |
| 124 | #define TIMER1_BIT 0xFFF0FFFF |
| 125 | #define TIMER2_BIT 0xFF0FFFFF |
| 126 | #define TIMER3_BIT 0xF0FFFFFF |
| 127 | #define TIMER4_BIT 0x0FFFFFFF |
| 128 | /* IAR5 BIT FIELDS */ |
| 129 | #define TIMER5_BIT 0xFFFFFFFF |
| 130 | #define TIMER6_BIT 0xFFFFFF0F |
| 131 | #define TIMER7_BIT 0xFFFFF0FF |
| 132 | #define TIMER8_BIT 0xFFFF0FFF |
| 133 | #define TIMER9_BIT 0xFFF0FFFF |
| 134 | #define TIMER10_BIT 0xFF0FFFFF |
| 135 | #define TIMER11_BIT 0xF0FFFFFF |
| 136 | #define PROG0_INTA_BIT 0x0FFFFFFF |
| 137 | /* IAR6 BIT FIELDS */ |
| 138 | #define PROG0_INTB_BIT 0xFFFFFFFF |
| 139 | #define PROG1_INTA_BIT 0xFFFFFF0F |
| 140 | #define PROG1_INTB_BIT 0xFFFFF0FF |
| 141 | #define PROG2_INTA_BIT 0xFFFF0FFF |
| 142 | #define PROG2_INTB_BIT 0xFFF0FFFF |
| 143 | #define DMA1_WRRD0_BIT 0xFF0FFFFF |
| 144 | #define DMA1_WRRD1_BIT 0xF0FFFFFF |
| 145 | #define DMA2_WRRD0_BIT 0x0FFFFFFF |
| 146 | /* IAR7 BIT FIELDS */ |
| 147 | #define DMA2_WRRD1_BIT 0xFFFFFFFF |
| 148 | #define IMDMA_WRRD0_BIT 0xFFFFFF0F |
| 149 | #define IMDMA_WRRD1_BIT 0xFFFFF0FF |
| 150 | #define WATCH_BIT 0xFFFF0FFF |
| 151 | #define RESERVED_1_BIT 0xFFF0FFFF |
| 152 | #define RESERVED_2_BIT 0xFF0FFFFF |
| 153 | #define SUPPLE_0_BIT 0xF0FFFFFF |
| 154 | #define SUPPLE_1_BIT 0x0FFFFFFF |
| 155 | |
| 156 | /* Miscellaneous Values */ |
| 157 | |
| 158 | /****************************** EBIU Settings ********************************/ |
| 159 | #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) |
| 160 | #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) |
| 161 | |
| 162 | #if defined(CONFIG_C_AMBEN_ALL) |
| 163 | #define V_AMBEN AMBEN_ALL |
| 164 | #elif defined(CONFIG_C_AMBEN) |
| 165 | #define V_AMBEN 0x0 |
| 166 | #elif defined(CONFIG_C_AMBEN_B0) |
| 167 | #define V_AMBEN AMBEN_B0 |
| 168 | #elif defined(CONFIG_C_AMBEN_B0_B1) |
| 169 | #define V_AMBEN AMBEN_B0_B1 |
| 170 | #elif defined(CONFIG_C_AMBEN_B0_B1_B2) |
| 171 | #define V_AMBEN AMBEN_B0_B1_B2 |
| 172 | #endif |
| 173 | |
| 174 | #ifdef CONFIG_C_AMCKEN |
| 175 | #define V_AMCKEN AMCKEN |
| 176 | #else |
| 177 | #define V_AMCKEN 0x0 |
| 178 | #endif |
| 179 | |
| 180 | #ifdef CONFIG_C_B0PEN |
| 181 | #define V_B0PEN 0x10 |
| 182 | #else |
| 183 | #define V_B0PEN 0x00 |
| 184 | #endif |
| 185 | |
| 186 | #ifdef CONFIG_C_B1PEN |
| 187 | #define V_B1PEN 0x20 |
| 188 | #else |
| 189 | #define V_B1PEN 0x00 |
| 190 | #endif |
| 191 | |
| 192 | #ifdef CONFIG_C_B2PEN |
| 193 | #define V_B2PEN 0x40 |
| 194 | #else |
| 195 | #define V_B2PEN 0x00 |
| 196 | #endif |
| 197 | |
| 198 | #ifdef CONFIG_C_B3PEN |
| 199 | #define V_B3PEN 0x80 |
| 200 | #else |
| 201 | #define V_B3PEN 0x00 |
| 202 | #endif |
| 203 | |
| 204 | #ifdef CONFIG_C_CDPRIO |
| 205 | #define V_CDPRIO 0x100 |
| 206 | #else |
| 207 | #define V_CDPRIO 0x0 |
| 208 | #endif |
| 209 | |
| 210 | #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002) |
| 211 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 212 | #ifdef CONFIG_BF561 |
| 213 | #define CPU "BF561" |
| 214 | #define CPUID 0x027bb000 |
| 215 | #endif |
| 216 | #ifndef CPU |
| 217 | #define CPU "UNKNOWN" |
| 218 | #define CPUID 0x0 |
| 219 | #endif |
| 220 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 221 | #endif /* __MACH_BF561_H__ */ |