Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation |
| 3 | * Provides Bus interface for MIIM regs |
| 4 | * |
| 5 | * Author: Andy Fleming <afleming@freescale.com> |
Sandeep Gopalpet | 1d2397d | 2009-11-02 07:03:22 +0000 | [diff] [blame] | 6 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 7 | * |
Sandeep Gopalpet | 1d2397d | 2009-11-02 07:03:22 +0000 | [diff] [blame] | 8 | * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc. |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 9 | * |
| 10 | * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify it |
| 13 | * under the terms of the GNU General Public License as published by the |
| 14 | * Free Software Foundation; either version 2 of the License, or (at your |
| 15 | * option) any later version. |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/string.h> |
| 21 | #include <linux/errno.h> |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 22 | #include <linux/slab.h> |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 23 | #include <linux/delay.h> |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 24 | #include <linux/module.h> |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 25 | #include <linux/mii.h> |
Grant Likely | 22ae782 | 2010-07-29 11:49:01 -0600 | [diff] [blame] | 26 | #include <linux/of_address.h> |
Grant Likely | 324931b | 2009-04-25 12:53:07 +0000 | [diff] [blame] | 27 | #include <linux/of_mdio.h> |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 28 | #include <linux/of_device.h> |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 29 | |
| 30 | #include <asm/io.h> |
Claudiu Manoil | 9a4cbd5 | 2014-10-07 10:44:28 +0300 | [diff] [blame] | 31 | #if IS_ENABLED(CONFIG_UCC_GETH) |
Timur Tabi | 1aa06d4 | 2012-08-29 08:07:58 +0000 | [diff] [blame] | 32 | #include <asm/ucc.h> /* for ucc_set_qe_mux_mii_mng() */ |
Claudiu Manoil | 9a4cbd5 | 2014-10-07 10:44:28 +0300 | [diff] [blame] | 33 | #endif |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 34 | |
| 35 | #include "gianfar.h" |
Timur Tabi | 19bcd6c | 2012-08-29 08:07:57 +0000 | [diff] [blame] | 36 | |
| 37 | #define MIIMIND_BUSY 0x00000001 |
| 38 | #define MIIMIND_NOTVALID 0x00000004 |
| 39 | #define MIIMCFG_INIT_VALUE 0x00000007 |
| 40 | #define MIIMCFG_RESET 0x80000000 |
| 41 | |
| 42 | #define MII_READ_COMMAND 0x00000001 |
| 43 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 44 | struct fsl_pq_mii { |
| 45 | u32 miimcfg; /* MII management configuration reg */ |
| 46 | u32 miimcom; /* MII management command reg */ |
| 47 | u32 miimadd; /* MII management address reg */ |
| 48 | u32 miimcon; /* MII management control reg */ |
| 49 | u32 miimstat; /* MII management status reg */ |
| 50 | u32 miimind; /* MII management indication reg */ |
| 51 | }; |
| 52 | |
Timur Tabi | 19bcd6c | 2012-08-29 08:07:57 +0000 | [diff] [blame] | 53 | struct fsl_pq_mdio { |
| 54 | u8 res1[16]; |
| 55 | u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/ |
| 56 | u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/ |
| 57 | u8 res2[4]; |
| 58 | u32 emapm; /* MDIO Event mapping register (for etsec2)*/ |
| 59 | u8 res3[1280]; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 60 | struct fsl_pq_mii mii; |
Timur Tabi | 19bcd6c | 2012-08-29 08:07:57 +0000 | [diff] [blame] | 61 | u8 res4[28]; |
| 62 | u32 utbipar; /* TBI phy address reg (only on UCC) */ |
| 63 | u8 res5[2728]; |
| 64 | } __packed; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 65 | |
Timur Tabi | 59399c5 | 2012-07-09 16:57:36 -0500 | [diff] [blame] | 66 | /* Number of microseconds to wait for an MII register to respond */ |
| 67 | #define MII_TIMEOUT 1000 |
| 68 | |
Anton Vorontsov | b3319b1 | 2009-12-30 08:23:34 +0000 | [diff] [blame] | 69 | struct fsl_pq_mdio_priv { |
| 70 | void __iomem *map; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 71 | struct fsl_pq_mii __iomem *regs; |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 72 | int irqs[PHY_MAX_ADDR]; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | /* |
| 76 | * Per-device-type data. Each type of device tree node that we support gets |
| 77 | * one of these. |
| 78 | * |
| 79 | * @mii_offset: the offset of the MII registers within the memory map of the |
| 80 | * node. Some nodes define only the MII registers, and some define the whole |
| 81 | * MAC (which includes the MII registers). |
| 82 | * |
| 83 | * @get_tbipa: determines the address of the TBIPA register |
| 84 | * |
| 85 | * @ucc_configure: a special function for extra QE configuration |
| 86 | */ |
| 87 | struct fsl_pq_mdio_data { |
| 88 | unsigned int mii_offset; /* offset of the MII registers */ |
| 89 | uint32_t __iomem * (*get_tbipa)(void __iomem *p); |
| 90 | void (*ucc_configure)(phys_addr_t start, phys_addr_t end); |
Anton Vorontsov | b3319b1 | 2009-12-30 08:23:34 +0000 | [diff] [blame] | 91 | }; |
| 92 | |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 93 | /* |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 94 | * Write value to the PHY at mii_id at register regnum, on the bus attached |
| 95 | * to the local interface, which may be different from the generic mdio bus |
| 96 | * (tied to a single interface), waiting until the write is done before |
| 97 | * returning. This is helpful in programming interfaces like the TBI which |
| 98 | * control interfaces like onchip SERDES and are always tied to the local |
| 99 | * mdio pins, which may not be the same as system mdio bus, used for |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 100 | * controlling the external PHYs, for example. |
| 101 | */ |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 102 | static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
| 103 | u16 value) |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 104 | { |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 105 | struct fsl_pq_mdio_priv *priv = bus->priv; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 106 | struct fsl_pq_mii __iomem *regs = priv->regs; |
Claudiu Manoil | e4b081f | 2014-10-07 10:44:30 +0300 | [diff] [blame^] | 107 | unsigned int timeout; |
Timur Tabi | 59399c5 | 2012-07-09 16:57:36 -0500 | [diff] [blame] | 108 | |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 109 | /* Set the PHY address and the register address we want to write */ |
Claudiu Manoil | f5bbd26 | 2014-10-07 10:44:29 +0300 | [diff] [blame] | 110 | iowrite32be((mii_id << 8) | regnum, ®s->miimadd); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 111 | |
| 112 | /* Write out the value we want */ |
Claudiu Manoil | f5bbd26 | 2014-10-07 10:44:29 +0300 | [diff] [blame] | 113 | iowrite32be(value, ®s->miimcon); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 114 | |
| 115 | /* Wait for the transaction to finish */ |
Claudiu Manoil | e4b081f | 2014-10-07 10:44:30 +0300 | [diff] [blame^] | 116 | timeout = MII_TIMEOUT; |
| 117 | while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) { |
| 118 | cpu_relax(); |
| 119 | timeout--; |
| 120 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 121 | |
Claudiu Manoil | e4b081f | 2014-10-07 10:44:30 +0300 | [diff] [blame^] | 122 | return timeout ? 0 : -ETIMEDOUT; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | /* |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 126 | * Read the bus for PHY at addr mii_id, register regnum, and return the value. |
| 127 | * Clears miimcom first. |
| 128 | * |
| 129 | * All PHY operation done on the bus attached to the local interface, which |
| 130 | * may be different from the generic mdio bus. This is helpful in programming |
| 131 | * interfaces like the TBI which, in turn, control interfaces like on-chip |
| 132 | * SERDES and are always tied to the local mdio pins, which may not be the |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 133 | * same as system mdio bus, used for controlling the external PHYs, for eg. |
| 134 | */ |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 135 | static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 136 | { |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 137 | struct fsl_pq_mdio_priv *priv = bus->priv; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 138 | struct fsl_pq_mii __iomem *regs = priv->regs; |
Claudiu Manoil | e4b081f | 2014-10-07 10:44:30 +0300 | [diff] [blame^] | 139 | unsigned int timeout; |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 140 | u16 value; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 141 | |
| 142 | /* Set the PHY address and the register address we want to read */ |
Claudiu Manoil | f5bbd26 | 2014-10-07 10:44:29 +0300 | [diff] [blame] | 143 | iowrite32be((mii_id << 8) | regnum, ®s->miimadd); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 144 | |
| 145 | /* Clear miimcom, and then initiate a read */ |
Claudiu Manoil | f5bbd26 | 2014-10-07 10:44:29 +0300 | [diff] [blame] | 146 | iowrite32be(0, ®s->miimcom); |
| 147 | iowrite32be(MII_READ_COMMAND, ®s->miimcom); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 148 | |
Timur Tabi | 59399c5 | 2012-07-09 16:57:36 -0500 | [diff] [blame] | 149 | /* Wait for the transaction to finish, normally less than 100us */ |
Claudiu Manoil | e4b081f | 2014-10-07 10:44:30 +0300 | [diff] [blame^] | 150 | timeout = MII_TIMEOUT; |
| 151 | while ((ioread32be(®s->miimind) & |
| 152 | (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) { |
| 153 | cpu_relax(); |
| 154 | timeout--; |
| 155 | } |
| 156 | |
| 157 | if (!timeout) |
Timur Tabi | 59399c5 | 2012-07-09 16:57:36 -0500 | [diff] [blame] | 158 | return -ETIMEDOUT; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 159 | |
| 160 | /* Grab the value of the register from miimstat */ |
Claudiu Manoil | f5bbd26 | 2014-10-07 10:44:29 +0300 | [diff] [blame] | 161 | value = ioread32be(®s->miimstat); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 162 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 163 | dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 164 | return value; |
| 165 | } |
| 166 | |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 167 | /* Reset the MIIM registers, and wait for the bus to free */ |
| 168 | static int fsl_pq_mdio_reset(struct mii_bus *bus) |
| 169 | { |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 170 | struct fsl_pq_mdio_priv *priv = bus->priv; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 171 | struct fsl_pq_mii __iomem *regs = priv->regs; |
Claudiu Manoil | e4b081f | 2014-10-07 10:44:30 +0300 | [diff] [blame^] | 172 | unsigned int timeout; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 173 | |
| 174 | mutex_lock(&bus->mdio_lock); |
| 175 | |
| 176 | /* Reset the management interface */ |
Claudiu Manoil | f5bbd26 | 2014-10-07 10:44:29 +0300 | [diff] [blame] | 177 | iowrite32be(MIIMCFG_RESET, ®s->miimcfg); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 178 | |
| 179 | /* Setup the MII Mgmt clock speed */ |
Claudiu Manoil | f5bbd26 | 2014-10-07 10:44:29 +0300 | [diff] [blame] | 180 | iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 181 | |
| 182 | /* Wait until the bus is free */ |
Claudiu Manoil | e4b081f | 2014-10-07 10:44:30 +0300 | [diff] [blame^] | 183 | timeout = MII_TIMEOUT; |
| 184 | while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) { |
| 185 | cpu_relax(); |
| 186 | timeout--; |
| 187 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 188 | |
| 189 | mutex_unlock(&bus->mdio_lock); |
| 190 | |
Claudiu Manoil | e4b081f | 2014-10-07 10:44:30 +0300 | [diff] [blame^] | 191 | if (!timeout) { |
Timur Tabi | 5078ac7 | 2012-08-29 08:08:00 +0000 | [diff] [blame] | 192 | dev_err(&bus->dev, "timeout waiting for MII bus\n"); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 193 | return -EBUSY; |
| 194 | } |
| 195 | |
| 196 | return 0; |
| 197 | } |
| 198 | |
Andy Fleming | 952c5ca | 2011-11-11 05:10:39 +0000 | [diff] [blame] | 199 | #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 200 | /* |
| 201 | * This is mildly evil, but so is our hardware for doing this. |
| 202 | * Also, we have to cast back to struct gfar because of |
| 203 | * definition weirdness done in gianfar.h. |
| 204 | */ |
| 205 | static uint32_t __iomem *get_gfar_tbipa(void __iomem *p) |
| 206 | { |
| 207 | struct gfar __iomem *enet_regs = p; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 208 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 209 | return &enet_regs->tbipa; |
Andy Fleming | 952c5ca | 2011-11-11 05:10:39 +0000 | [diff] [blame] | 210 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 211 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 212 | /* |
| 213 | * Return the TBIPAR address for an eTSEC2 node |
| 214 | */ |
| 215 | static uint32_t __iomem *get_etsec_tbipa(void __iomem *p) |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 216 | { |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 217 | return p; |
| 218 | } |
| 219 | #endif |
| 220 | |
Andy Fleming | 952c5ca | 2011-11-11 05:10:39 +0000 | [diff] [blame] | 221 | #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 222 | /* |
| 223 | * Return the TBIPAR address for a QE MDIO node |
| 224 | */ |
| 225 | static uint32_t __iomem *get_ucc_tbipa(void __iomem *p) |
| 226 | { |
| 227 | struct fsl_pq_mdio __iomem *mdio = p; |
| 228 | |
| 229 | return &mdio->utbipar; |
| 230 | } |
| 231 | |
| 232 | /* |
| 233 | * Find the UCC node that controls the given MDIO node |
| 234 | * |
| 235 | * For some reason, the QE MDIO nodes are not children of the UCC devices |
| 236 | * that control them. Therefore, we need to scan all UCC nodes looking for |
| 237 | * the one that encompases the given MDIO node. We do this by comparing |
| 238 | * physical addresses. The 'start' and 'end' addresses of the MDIO node are |
| 239 | * passed, and the correct UCC node will cover the entire address range. |
| 240 | * |
| 241 | * This assumes that there is only one QE MDIO node in the entire device tree. |
| 242 | */ |
| 243 | static void ucc_configure(phys_addr_t start, phys_addr_t end) |
| 244 | { |
| 245 | static bool found_mii_master; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 246 | struct device_node *np = NULL; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 247 | |
| 248 | if (found_mii_master) |
| 249 | return; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 250 | |
| 251 | for_each_compatible_node(np, NULL, "ucc_geth") { |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 252 | struct resource res; |
| 253 | const uint32_t *iprop; |
| 254 | uint32_t id; |
| 255 | int ret; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 256 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 257 | ret = of_address_to_resource(np, 0, &res); |
| 258 | if (ret < 0) { |
| 259 | pr_debug("fsl-pq-mdio: no address range in node %s\n", |
| 260 | np->full_name); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 261 | continue; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 262 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 263 | |
| 264 | /* if our mdio regs fall within this UCC regs range */ |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 265 | if ((start < res.start) || (end > res.end)) |
| 266 | continue; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 267 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 268 | iprop = of_get_property(np, "cell-index", NULL); |
| 269 | if (!iprop) { |
| 270 | iprop = of_get_property(np, "device-id", NULL); |
| 271 | if (!iprop) { |
| 272 | pr_debug("fsl-pq-mdio: no UCC ID in node %s\n", |
| 273 | np->full_name); |
| 274 | continue; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 275 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 276 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 277 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 278 | id = be32_to_cpup(iprop); |
| 279 | |
| 280 | /* |
| 281 | * cell-index and device-id for QE nodes are |
| 282 | * numbered from 1, not 0. |
| 283 | */ |
| 284 | if (ucc_set_qe_mux_mii_mng(id - 1) < 0) { |
| 285 | pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n", |
| 286 | np->full_name); |
| 287 | continue; |
| 288 | } |
| 289 | |
| 290 | pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id); |
| 291 | found_mii_master = true; |
| 292 | } |
Andy Fleming | 952c5ca | 2011-11-11 05:10:39 +0000 | [diff] [blame] | 293 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 294 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 295 | #endif |
| 296 | |
| 297 | static struct of_device_id fsl_pq_mdio_match[] = { |
| 298 | #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE) |
| 299 | { |
| 300 | .compatible = "fsl,gianfar-tbi", |
| 301 | .data = &(struct fsl_pq_mdio_data) { |
| 302 | .mii_offset = 0, |
| 303 | .get_tbipa = get_gfar_tbipa, |
| 304 | }, |
| 305 | }, |
| 306 | { |
| 307 | .compatible = "fsl,gianfar-mdio", |
| 308 | .data = &(struct fsl_pq_mdio_data) { |
| 309 | .mii_offset = 0, |
| 310 | .get_tbipa = get_gfar_tbipa, |
| 311 | }, |
| 312 | }, |
| 313 | { |
| 314 | .type = "mdio", |
| 315 | .compatible = "gianfar", |
| 316 | .data = &(struct fsl_pq_mdio_data) { |
| 317 | .mii_offset = offsetof(struct fsl_pq_mdio, mii), |
| 318 | .get_tbipa = get_gfar_tbipa, |
| 319 | }, |
| 320 | }, |
| 321 | { |
| 322 | .compatible = "fsl,etsec2-tbi", |
| 323 | .data = &(struct fsl_pq_mdio_data) { |
| 324 | .mii_offset = offsetof(struct fsl_pq_mdio, mii), |
| 325 | .get_tbipa = get_etsec_tbipa, |
| 326 | }, |
| 327 | }, |
| 328 | { |
| 329 | .compatible = "fsl,etsec2-mdio", |
| 330 | .data = &(struct fsl_pq_mdio_data) { |
| 331 | .mii_offset = offsetof(struct fsl_pq_mdio, mii), |
| 332 | .get_tbipa = get_etsec_tbipa, |
| 333 | }, |
| 334 | }, |
| 335 | #endif |
| 336 | #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE) |
| 337 | { |
| 338 | .compatible = "fsl,ucc-mdio", |
| 339 | .data = &(struct fsl_pq_mdio_data) { |
| 340 | .mii_offset = 0, |
| 341 | .get_tbipa = get_ucc_tbipa, |
| 342 | .ucc_configure = ucc_configure, |
| 343 | }, |
| 344 | }, |
| 345 | { |
| 346 | /* Legacy UCC MDIO node */ |
| 347 | .type = "mdio", |
| 348 | .compatible = "ucc_geth_phy", |
| 349 | .data = &(struct fsl_pq_mdio_data) { |
| 350 | .mii_offset = 0, |
| 351 | .get_tbipa = get_ucc_tbipa, |
| 352 | .ucc_configure = ucc_configure, |
| 353 | }, |
| 354 | }, |
| 355 | #endif |
Timur Tabi | 761743e | 2012-08-29 08:08:03 +0000 | [diff] [blame] | 356 | /* No Kconfig option for Fman support yet */ |
| 357 | { |
| 358 | .compatible = "fsl,fman-mdio", |
| 359 | .data = &(struct fsl_pq_mdio_data) { |
| 360 | .mii_offset = 0, |
| 361 | /* Fman TBI operations are handled elsewhere */ |
| 362 | }, |
| 363 | }, |
| 364 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 365 | {}, |
| 366 | }; |
| 367 | MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); |
| 368 | |
Timur Tabi | 5078ac7 | 2012-08-29 08:08:00 +0000 | [diff] [blame] | 369 | static int fsl_pq_mdio_probe(struct platform_device *pdev) |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 370 | { |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 371 | const struct of_device_id *id = |
| 372 | of_match_device(fsl_pq_mdio_match, &pdev->dev); |
| 373 | const struct fsl_pq_mdio_data *data = id->data; |
Timur Tabi | 5078ac7 | 2012-08-29 08:08:00 +0000 | [diff] [blame] | 374 | struct device_node *np = pdev->dev.of_node; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 375 | struct resource res; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 376 | struct device_node *tbi; |
Anton Vorontsov | b3319b1 | 2009-12-30 08:23:34 +0000 | [diff] [blame] | 377 | struct fsl_pq_mdio_priv *priv; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 378 | struct mii_bus *new_bus; |
Anton Vorontsov | 08d18f3 | 2010-05-14 04:27:30 +0000 | [diff] [blame] | 379 | int err; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 380 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 381 | dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible); |
| 382 | |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 383 | new_bus = mdiobus_alloc_size(sizeof(*priv)); |
| 384 | if (!new_bus) |
Anton Vorontsov | b3319b1 | 2009-12-30 08:23:34 +0000 | [diff] [blame] | 385 | return -ENOMEM; |
| 386 | |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 387 | priv = new_bus->priv; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 388 | new_bus->name = "Freescale PowerQUICC MII Bus", |
Timur Tabi | 5078ac7 | 2012-08-29 08:08:00 +0000 | [diff] [blame] | 389 | new_bus->read = &fsl_pq_mdio_read; |
| 390 | new_bus->write = &fsl_pq_mdio_write; |
| 391 | new_bus->reset = &fsl_pq_mdio_reset; |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 392 | new_bus->irq = priv->irqs; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 393 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 394 | err = of_address_to_resource(np, 0, &res); |
| 395 | if (err < 0) { |
| 396 | dev_err(&pdev->dev, "could not obtain address information\n"); |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 397 | goto error; |
Anton Vorontsov | 3b1fd3e | 2010-04-23 07:12:35 +0000 | [diff] [blame] | 398 | } |
| 399 | |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 400 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name, |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 401 | (unsigned long long)res.start); |
Timur Tabi | 69cfb41 | 2012-08-29 08:07:59 +0000 | [diff] [blame] | 402 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 403 | priv->map = of_iomap(np, 0); |
| 404 | if (!priv->map) { |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 405 | err = -ENOMEM; |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 406 | goto error; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 407 | } |
| 408 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 409 | /* |
| 410 | * Some device tree nodes represent only the MII registers, and |
| 411 | * others represent the MAC and MII registers. The 'mii_offset' field |
| 412 | * contains the offset of the MII registers inside the mapped register |
| 413 | * space. |
| 414 | */ |
| 415 | if (data->mii_offset > resource_size(&res)) { |
| 416 | dev_err(&pdev->dev, "invalid register map\n"); |
| 417 | err = -EINVAL; |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 418 | goto error; |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 419 | } |
| 420 | priv->regs = priv->map + data->mii_offset; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 421 | |
Timur Tabi | 5078ac7 | 2012-08-29 08:08:00 +0000 | [diff] [blame] | 422 | new_bus->parent = &pdev->dev; |
Libo Chen | a0e1860 | 2013-08-19 19:58:40 +0800 | [diff] [blame] | 423 | platform_set_drvdata(pdev, new_bus); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 424 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 425 | if (data->get_tbipa) { |
| 426 | for_each_child_of_node(np, tbi) { |
| 427 | if (strcmp(tbi->type, "tbi-phy") == 0) { |
| 428 | dev_dbg(&pdev->dev, "found TBI PHY node %s\n", |
| 429 | strrchr(tbi->full_name, '/') + 1); |
| 430 | break; |
| 431 | } |
Sandeep Gopalpet | 1d2397d | 2009-11-02 07:03:22 +0000 | [diff] [blame] | 432 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 433 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 434 | if (tbi) { |
| 435 | const u32 *prop = of_get_property(tbi, "reg", NULL); |
| 436 | uint32_t __iomem *tbipa; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 437 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 438 | if (!prop) { |
| 439 | dev_err(&pdev->dev, |
| 440 | "missing 'reg' property in node %s\n", |
| 441 | tbi->full_name); |
| 442 | err = -EBUSY; |
| 443 | goto error; |
| 444 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 445 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 446 | tbipa = data->get_tbipa(priv->map); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 447 | |
Claudiu Manoil | f5bbd26 | 2014-10-07 10:44:29 +0300 | [diff] [blame] | 448 | iowrite32be(be32_to_cpup(prop), tbipa); |
Kenth Eriksson | 464b57d | 2012-03-27 22:05:54 +0000 | [diff] [blame] | 449 | } |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 450 | } |
| 451 | |
Timur Tabi | afae5ad | 2012-08-29 08:08:01 +0000 | [diff] [blame] | 452 | if (data->ucc_configure) |
| 453 | data->ucc_configure(res.start, res.end); |
| 454 | |
Grant Likely | 324931b | 2009-04-25 12:53:07 +0000 | [diff] [blame] | 455 | err = of_mdiobus_register(new_bus, np); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 456 | if (err) { |
Timur Tabi | 5078ac7 | 2012-08-29 08:08:00 +0000 | [diff] [blame] | 457 | dev_err(&pdev->dev, "cannot register %s as MDIO bus\n", |
| 458 | new_bus->name); |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 459 | goto error; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 460 | } |
| 461 | |
| 462 | return 0; |
| 463 | |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 464 | error: |
| 465 | if (priv->map) |
| 466 | iounmap(priv->map); |
| 467 | |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 468 | kfree(new_bus); |
Timur Tabi | dd3b8a3 | 2012-08-29 08:08:02 +0000 | [diff] [blame] | 469 | |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 470 | return err; |
| 471 | } |
| 472 | |
| 473 | |
Timur Tabi | 5078ac7 | 2012-08-29 08:08:00 +0000 | [diff] [blame] | 474 | static int fsl_pq_mdio_remove(struct platform_device *pdev) |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 475 | { |
Timur Tabi | 5078ac7 | 2012-08-29 08:08:00 +0000 | [diff] [blame] | 476 | struct device *device = &pdev->dev; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 477 | struct mii_bus *bus = dev_get_drvdata(device); |
Anton Vorontsov | b3319b1 | 2009-12-30 08:23:34 +0000 | [diff] [blame] | 478 | struct fsl_pq_mdio_priv *priv = bus->priv; |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 479 | |
| 480 | mdiobus_unregister(bus); |
| 481 | |
Anton Vorontsov | b3319b1 | 2009-12-30 08:23:34 +0000 | [diff] [blame] | 482 | iounmap(priv->map); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 483 | mdiobus_free(bus); |
| 484 | |
| 485 | return 0; |
| 486 | } |
| 487 | |
Grant Likely | 7488876 | 2011-02-22 21:05:51 -0700 | [diff] [blame] | 488 | static struct platform_driver fsl_pq_mdio_driver = { |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 489 | .driver = { |
| 490 | .name = "fsl-pq_mdio", |
| 491 | .owner = THIS_MODULE, |
| 492 | .of_match_table = fsl_pq_mdio_match, |
| 493 | }, |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 494 | .probe = fsl_pq_mdio_probe, |
| 495 | .remove = fsl_pq_mdio_remove, |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 496 | }; |
| 497 | |
Axel Lin | db62f68 | 2011-11-27 16:44:17 +0000 | [diff] [blame] | 498 | module_platform_driver(fsl_pq_mdio_driver); |
Andy Fleming | 1577ece | 2009-02-04 16:42:12 -0800 | [diff] [blame] | 499 | |
Sebastian Siewior | 2606289 | 2009-11-06 08:50:28 +0000 | [diff] [blame] | 500 | MODULE_LICENSE("GPL"); |