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Mugunthan V Ndf828592012-03-18 20:17:54 +00001/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
Richard Cochran2e5b38a2012-10-29 08:45:20 +000027#include <linux/net_tstamp.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000028#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
Mugunthan V Nf150bd72012-07-17 08:09:50 +000031#include <linux/pm_runtime.h>
Mugunthan V N2eb32b02012-07-30 10:17:14 +000032#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
Mugunthan V N3b72c2f2013-02-05 08:26:48 +000035#include <linux/if_vlan.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000036
Mugunthan V N739683b2013-06-06 23:45:14 +053037#include <linux/pinctrl/consumer.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000038
Mugunthan V Ndbe34722013-08-19 17:47:40 +053039#include "cpsw.h"
Mugunthan V Ndf828592012-03-18 20:17:54 +000040#include "cpsw_ale.h"
Richard Cochran2e5b38a2012-10-29 08:45:20 +000041#include "cpts.h"
Mugunthan V Ndf828592012-03-18 20:17:54 +000042#include "davinci_cpdma.h"
43
44#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
45 NETIF_MSG_DRV | NETIF_MSG_LINK | \
46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
51 NETIF_MSG_RX_STATUS)
52
53#define cpsw_info(priv, type, format, ...) \
54do { \
55 if (netif_msg_##type(priv) && net_ratelimit()) \
56 dev_info(priv->dev, format, ## __VA_ARGS__); \
57} while (0)
58
59#define cpsw_err(priv, type, format, ...) \
60do { \
61 if (netif_msg_##type(priv) && net_ratelimit()) \
62 dev_err(priv->dev, format, ## __VA_ARGS__); \
63} while (0)
64
65#define cpsw_dbg(priv, type, format, ...) \
66do { \
67 if (netif_msg_##type(priv) && net_ratelimit()) \
68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
69} while (0)
70
71#define cpsw_notice(priv, type, format, ...) \
72do { \
73 if (netif_msg_##type(priv) && net_ratelimit()) \
74 dev_notice(priv->dev, format, ## __VA_ARGS__); \
75} while (0)
76
Mugunthan V N5c50a852012-10-29 08:45:11 +000077#define ALE_ALL_PORTS 0x7
78
Mugunthan V Ndf828592012-03-18 20:17:54 +000079#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
80#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
81#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
82
Richard Cochrane90cfac2012-10-29 08:45:14 +000083#define CPSW_VERSION_1 0x19010a
84#define CPSW_VERSION_2 0x19010c
Mugunthan V Nc193f362013-08-05 17:30:05 +053085#define CPSW_VERSION_3 0x19010f
Mugunthan V N926489b2013-08-12 17:11:15 +053086#define CPSW_VERSION_4 0x190112
Richard Cochran549985e2012-11-14 09:07:56 +000087
88#define HOST_PORT_NUM 0
89#define SLIVER_SIZE 0x40
90
91#define CPSW1_HOST_PORT_OFFSET 0x028
92#define CPSW1_SLAVE_OFFSET 0x050
93#define CPSW1_SLAVE_SIZE 0x040
94#define CPSW1_CPDMA_OFFSET 0x100
95#define CPSW1_STATERAM_OFFSET 0x200
Mugunthan V Nd9718542013-07-23 15:38:17 +053096#define CPSW1_HW_STATS 0x400
Richard Cochran549985e2012-11-14 09:07:56 +000097#define CPSW1_CPTS_OFFSET 0x500
98#define CPSW1_ALE_OFFSET 0x600
99#define CPSW1_SLIVER_OFFSET 0x700
100
101#define CPSW2_HOST_PORT_OFFSET 0x108
102#define CPSW2_SLAVE_OFFSET 0x200
103#define CPSW2_SLAVE_SIZE 0x100
104#define CPSW2_CPDMA_OFFSET 0x800
Mugunthan V Nd9718542013-07-23 15:38:17 +0530105#define CPSW2_HW_STATS 0x900
Richard Cochran549985e2012-11-14 09:07:56 +0000106#define CPSW2_STATERAM_OFFSET 0xa00
107#define CPSW2_CPTS_OFFSET 0xc00
108#define CPSW2_ALE_OFFSET 0xd00
109#define CPSW2_SLIVER_OFFSET 0xd80
110#define CPSW2_BD_OFFSET 0x2000
111
Mugunthan V Ndf828592012-03-18 20:17:54 +0000112#define CPDMA_RXTHRESH 0x0c0
113#define CPDMA_RXFREE 0x0e0
114#define CPDMA_TXHDP 0x00
115#define CPDMA_RXHDP 0x20
116#define CPDMA_TXCP 0x40
117#define CPDMA_RXCP 0x60
118
Mugunthan V Ndf828592012-03-18 20:17:54 +0000119#define CPSW_POLL_WEIGHT 64
120#define CPSW_MIN_PACKET_SIZE 60
121#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
122
123#define RX_PRIORITY_MAPPING 0x76543210
124#define TX_PRIORITY_MAPPING 0x33221100
125#define CPDMA_TX_PRIORITY_MAP 0x76543210
126
Mugunthan V N3b72c2f2013-02-05 08:26:48 +0000127#define CPSW_VLAN_AWARE BIT(1)
128#define CPSW_ALE_VLAN_AWARE 1
129
John Ogness35717d82014-11-14 15:42:52 +0100130#define CPSW_FIFO_NORMAL_MODE (0 << 16)
131#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
132#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000133
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000134#define CPSW_INTPACEEN (0x3f << 16)
135#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
136#define CPSW_CMINTMAX_CNT 63
137#define CPSW_CMINTMIN_CNT 2
138#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
139#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
140
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +0000141#define cpsw_slave_index(priv) \
142 ((priv->data.dual_emac) ? priv->emac_port : \
143 priv->data.active_slave)
144
Mugunthan V Ndf828592012-03-18 20:17:54 +0000145static int debug_level;
146module_param(debug_level, int, 0);
147MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
148
149static int ale_ageout = 10;
150module_param(ale_ageout, int, 0);
151MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
152
153static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
154module_param(rx_packet_max, int, 0);
155MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
156
Richard Cochran996a5c22012-10-29 08:45:12 +0000157struct cpsw_wr_regs {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000158 u32 id_ver;
159 u32 soft_reset;
160 u32 control;
161 u32 int_control;
162 u32 rx_thresh_en;
163 u32 rx_en;
164 u32 tx_en;
165 u32 misc_en;
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000166 u32 mem_allign1[8];
167 u32 rx_thresh_stat;
168 u32 rx_stat;
169 u32 tx_stat;
170 u32 misc_stat;
171 u32 mem_allign2[8];
172 u32 rx_imax;
173 u32 tx_imax;
174
Mugunthan V Ndf828592012-03-18 20:17:54 +0000175};
176
Richard Cochran996a5c22012-10-29 08:45:12 +0000177struct cpsw_ss_regs {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000178 u32 id_ver;
179 u32 control;
180 u32 soft_reset;
181 u32 stat_port_en;
182 u32 ptype;
Richard Cochranbd357af2012-10-29 08:45:13 +0000183 u32 soft_idle;
184 u32 thru_rate;
185 u32 gap_thresh;
186 u32 tx_start_wds;
187 u32 flow_control;
188 u32 vlan_ltype;
189 u32 ts_ltype;
190 u32 dlr_ltype;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000191};
192
Richard Cochran9750a3a2012-10-29 08:45:15 +0000193/* CPSW_PORT_V1 */
194#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
195#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
196#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
197#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
198#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
199#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
200#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
201#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
202
203/* CPSW_PORT_V2 */
204#define CPSW2_CONTROL 0x00 /* Control Register */
205#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
206#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
207#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
208#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
209#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
210#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
211
212/* CPSW_PORT_V1 and V2 */
213#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
214#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
215#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
216
217/* CPSW_PORT_V2 only */
218#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
219#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
220#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
221#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
222#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
223#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
224#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
225#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
226
227/* Bit definitions for the CPSW2_CONTROL register */
228#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
229#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
230#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
231#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
232#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
233#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
234#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
235#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
236#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
237#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
George Cherian09c55372014-05-02 12:02:02 +0530238#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
239#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
Richard Cochran9750a3a2012-10-29 08:45:15 +0000240#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
241#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
242#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
243#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
244#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
245
George Cherian09c55372014-05-02 12:02:02 +0530246#define CTRL_V2_TS_BITS \
247 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
248 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
Richard Cochran9750a3a2012-10-29 08:45:15 +0000249
George Cherian09c55372014-05-02 12:02:02 +0530250#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
251#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
252#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
253
254
255#define CTRL_V3_TS_BITS \
256 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
257 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
258 TS_LTYPE1_EN)
259
260#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
261#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
262#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
Richard Cochran9750a3a2012-10-29 08:45:15 +0000263
264/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
265#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
266#define TS_SEQ_ID_OFFSET_MASK (0x3f)
267#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
268#define TS_MSG_TYPE_EN_MASK (0xffff)
269
270/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
271#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
Mugunthan V Ndf828592012-03-18 20:17:54 +0000272
Richard Cochran2e5b38a2012-10-29 08:45:20 +0000273/* Bit definitions for the CPSW1_TS_CTL register */
274#define CPSW_V1_TS_RX_EN BIT(0)
275#define CPSW_V1_TS_TX_EN BIT(4)
276#define CPSW_V1_MSG_TYPE_OFS 16
277
278/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
279#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
280
Mugunthan V Ndf828592012-03-18 20:17:54 +0000281struct cpsw_host_regs {
282 u32 max_blks;
283 u32 blk_cnt;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000284 u32 tx_in_ctl;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000285 u32 port_vlan;
286 u32 tx_pri_map;
287 u32 cpdma_tx_pri_map;
288 u32 cpdma_rx_chan_map;
289};
290
291struct cpsw_sliver_regs {
292 u32 id_ver;
293 u32 mac_control;
294 u32 mac_status;
295 u32 soft_reset;
296 u32 rx_maxlen;
297 u32 __reserved_0;
298 u32 rx_pause;
299 u32 tx_pause;
300 u32 __reserved_1;
301 u32 rx_pri_map;
302};
303
Mugunthan V Nd9718542013-07-23 15:38:17 +0530304struct cpsw_hw_stats {
305 u32 rxgoodframes;
306 u32 rxbroadcastframes;
307 u32 rxmulticastframes;
308 u32 rxpauseframes;
309 u32 rxcrcerrors;
310 u32 rxaligncodeerrors;
311 u32 rxoversizedframes;
312 u32 rxjabberframes;
313 u32 rxundersizedframes;
314 u32 rxfragments;
315 u32 __pad_0[2];
316 u32 rxoctets;
317 u32 txgoodframes;
318 u32 txbroadcastframes;
319 u32 txmulticastframes;
320 u32 txpauseframes;
321 u32 txdeferredframes;
322 u32 txcollisionframes;
323 u32 txsinglecollframes;
324 u32 txmultcollframes;
325 u32 txexcessivecollisions;
326 u32 txlatecollisions;
327 u32 txunderrun;
328 u32 txcarriersenseerrors;
329 u32 txoctets;
330 u32 octetframes64;
331 u32 octetframes65t127;
332 u32 octetframes128t255;
333 u32 octetframes256t511;
334 u32 octetframes512t1023;
335 u32 octetframes1024tup;
336 u32 netoctets;
337 u32 rxsofoverruns;
338 u32 rxmofoverruns;
339 u32 rxdmaoverruns;
340};
341
Mugunthan V Ndf828592012-03-18 20:17:54 +0000342struct cpsw_slave {
Richard Cochran9750a3a2012-10-29 08:45:15 +0000343 void __iomem *regs;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000344 struct cpsw_sliver_regs __iomem *sliver;
345 int slave_num;
346 u32 mac_control;
347 struct cpsw_slave_data *data;
348 struct phy_device *phy;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000349 struct net_device *ndev;
350 u32 port_vlan;
351 u32 open_stat;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000352};
353
Richard Cochran9750a3a2012-10-29 08:45:15 +0000354static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
355{
356 return __raw_readl(slave->regs + offset);
357}
358
359static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
360{
361 __raw_writel(val, slave->regs + offset);
362}
363
Mugunthan V Ndf828592012-03-18 20:17:54 +0000364struct cpsw_priv {
365 spinlock_t lock;
366 struct platform_device *pdev;
367 struct net_device *ndev;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000368 struct napi_struct napi;
369 struct device *dev;
370 struct cpsw_platform_data data;
Richard Cochran996a5c22012-10-29 08:45:12 +0000371 struct cpsw_ss_regs __iomem *regs;
372 struct cpsw_wr_regs __iomem *wr_regs;
Mugunthan V Nd9718542013-07-23 15:38:17 +0530373 u8 __iomem *hw_stats;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000374 struct cpsw_host_regs __iomem *host_port_regs;
375 u32 msg_enable;
Richard Cochrane90cfac2012-10-29 08:45:14 +0000376 u32 version;
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000377 u32 coal_intvl;
378 u32 bus_freq_mhz;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000379 int rx_packet_max;
380 int host_port;
381 struct clk *clk;
382 u8 mac_addr[ETH_ALEN];
383 struct cpsw_slave *slaves;
384 struct cpdma_ctlr *dma;
385 struct cpdma_chan *txch, *rxch;
386 struct cpsw_ale *ale;
Mugunthan V N1923d6e2014-09-08 22:54:02 +0530387 bool rx_pause;
388 bool tx_pause;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000389 /* snapshot of IRQ numbers */
390 u32 irqs_table[4];
391 u32 num_irqs;
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000392 bool irq_enabled;
Mugunthan V N9232b162013-02-11 09:52:19 +0000393 struct cpts *cpts;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000394 u32 emac_port;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000395};
396
Mugunthan V Nd9718542013-07-23 15:38:17 +0530397struct cpsw_stats {
398 char stat_string[ETH_GSTRING_LEN];
399 int type;
400 int sizeof_stat;
401 int stat_offset;
402};
403
404enum {
405 CPSW_STATS,
406 CPDMA_RX_STATS,
407 CPDMA_TX_STATS,
408};
409
410#define CPSW_STAT(m) CPSW_STATS, \
411 sizeof(((struct cpsw_hw_stats *)0)->m), \
412 offsetof(struct cpsw_hw_stats, m)
413#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
414 sizeof(((struct cpdma_chan_stats *)0)->m), \
415 offsetof(struct cpdma_chan_stats, m)
416#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
417 sizeof(((struct cpdma_chan_stats *)0)->m), \
418 offsetof(struct cpdma_chan_stats, m)
419
420static const struct cpsw_stats cpsw_gstrings_stats[] = {
421 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
422 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
423 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
424 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
425 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
426 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
427 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
428 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
429 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
430 { "Rx Fragments", CPSW_STAT(rxfragments) },
431 { "Rx Octets", CPSW_STAT(rxoctets) },
432 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
433 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
434 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
435 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
436 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
437 { "Collisions", CPSW_STAT(txcollisionframes) },
438 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
439 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
440 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
441 { "Late Collisions", CPSW_STAT(txlatecollisions) },
442 { "Tx Underrun", CPSW_STAT(txunderrun) },
443 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
444 { "Tx Octets", CPSW_STAT(txoctets) },
445 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
446 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
447 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
448 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
449 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
450 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
451 { "Net Octets", CPSW_STAT(netoctets) },
452 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
453 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
454 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
455 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
456 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
457 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
458 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
459 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
460 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
461 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
462 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
463 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
464 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
465 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
466 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
467 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
468 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
469 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
470 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
471 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
472 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
473 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
474 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
475 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
476 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
477 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
478 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
479 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
480 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
481};
482
483#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
484
Mugunthan V Ndf828592012-03-18 20:17:54 +0000485#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000486#define for_each_slave(priv, func, arg...) \
487 do { \
Sebastian Siewior6e6ceae2013-04-24 08:48:24 +0000488 struct cpsw_slave *slave; \
489 int n; \
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000490 if (priv->data.dual_emac) \
491 (func)((priv)->slaves + priv->emac_port, ##arg);\
492 else \
Sebastian Siewior6e6ceae2013-04-24 08:48:24 +0000493 for (n = (priv)->data.slaves, \
494 slave = (priv)->slaves; \
495 n; n--) \
496 (func)(slave++, ##arg); \
Mugunthan V Ndf828592012-03-18 20:17:54 +0000497 } while (0)
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000498#define cpsw_get_slave_ndev(priv, __slave_no__) \
Mugunthan V N1973db02015-07-07 18:30:39 +0530499 ((__slave_no__ < priv->data.slaves) ? \
500 priv->slaves[__slave_no__].ndev : NULL)
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000501#define cpsw_get_slave_priv(priv, __slave_no__) \
Mugunthan V N1973db02015-07-07 18:30:39 +0530502 (((__slave_no__ < priv->data.slaves) && \
503 (priv->slaves[__slave_no__].ndev)) ? \
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000504 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
505
506#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
507 do { \
508 if (!priv->data.dual_emac) \
509 break; \
510 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
511 ndev = cpsw_get_slave_ndev(priv, 0); \
512 priv = netdev_priv(ndev); \
513 skb->dev = ndev; \
514 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
515 ndev = cpsw_get_slave_ndev(priv, 1); \
516 priv = netdev_priv(ndev); \
517 skb->dev = ndev; \
518 } \
519 } while (0)
520#define cpsw_add_mcast(priv, addr) \
521 do { \
522 if (priv->data.dual_emac) { \
523 struct cpsw_slave *slave = priv->slaves + \
524 priv->emac_port; \
525 int slave_port = cpsw_get_slave_port(priv, \
526 slave->slave_num); \
527 cpsw_ale_add_mcast(priv->ale, addr, \
528 1 << slave_port | 1 << priv->host_port, \
529 ALE_VLAN, slave->port_vlan, 0); \
530 } else { \
531 cpsw_ale_add_mcast(priv->ale, addr, \
532 ALE_ALL_PORTS << priv->host_port, \
533 0, 0, 0); \
534 } \
535 } while (0)
536
537static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
538{
539 if (priv->host_port == 0)
540 return slave_num + 1;
541 else
542 return slave_num;
543}
Mugunthan V Ndf828592012-03-18 20:17:54 +0000544
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530545static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
546{
547 struct cpsw_priv *priv = netdev_priv(ndev);
548 struct cpsw_ale *ale = priv->ale;
549 int i;
550
551 if (priv->data.dual_emac) {
552 bool flag = false;
553
554 /* Enabling promiscuous mode for one interface will be
555 * common for both the interface as the interface shares
556 * the same hardware resource.
557 */
Heiko Schocher0d961b32014-02-13 14:47:27 +0100558 for (i = 0; i < priv->data.slaves; i++)
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530559 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
560 flag = true;
561
562 if (!enable && flag) {
563 enable = true;
564 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
565 }
566
567 if (enable) {
568 /* Enable Bypass */
569 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
570
571 dev_dbg(&ndev->dev, "promiscuity enabled\n");
572 } else {
573 /* Disable Bypass */
574 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
575 dev_dbg(&ndev->dev, "promiscuity disabled\n");
576 }
577 } else {
578 if (enable) {
579 unsigned long timeout = jiffies + HZ;
580
Lennart Sorensen6f979eb2014-10-31 13:28:54 -0400581 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
582 for (i = 0; i <= priv->data.slaves; i++) {
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530583 cpsw_ale_control_set(ale, i,
584 ALE_PORT_NOLEARN, 1);
585 cpsw_ale_control_set(ale, i,
586 ALE_PORT_NO_SA_UPDATE, 1);
587 }
588
589 /* Clear All Untouched entries */
590 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
591 do {
592 cpu_relax();
593 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
594 break;
595 } while (time_after(timeout, jiffies));
596 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
597
598 /* Clear all mcast from ALE */
599 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
Mugunthan V N25906052015-01-13 17:35:49 +0530600 priv->host_port, -1);
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530601
602 /* Flood All Unicast Packets to Host port */
603 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
604 dev_dbg(&ndev->dev, "promiscuity enabled\n");
605 } else {
Lennart Sorensen6f979eb2014-10-31 13:28:54 -0400606 /* Don't Flood All Unicast Packets to Host port */
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530607 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
608
Lennart Sorensen6f979eb2014-10-31 13:28:54 -0400609 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
610 for (i = 0; i <= priv->data.slaves; i++) {
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530611 cpsw_ale_control_set(ale, i,
612 ALE_PORT_NOLEARN, 0);
613 cpsw_ale_control_set(ale, i,
614 ALE_PORT_NO_SA_UPDATE, 0);
615 }
616 dev_dbg(&ndev->dev, "promiscuity disabled\n");
617 }
618 }
619}
620
Mugunthan V N5c50a852012-10-29 08:45:11 +0000621static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
622{
623 struct cpsw_priv *priv = netdev_priv(ndev);
Mugunthan V N25906052015-01-13 17:35:49 +0530624 int vid;
625
626 if (priv->data.dual_emac)
627 vid = priv->slaves[priv->emac_port].port_vlan;
628 else
629 vid = priv->data.default_vlan;
Mugunthan V N5c50a852012-10-29 08:45:11 +0000630
631 if (ndev->flags & IFF_PROMISC) {
632 /* Enable promiscuous mode */
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530633 cpsw_set_promiscious(ndev, true);
Lennart Sorensen1e5c4bc2014-10-31 13:38:52 -0400634 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
Mugunthan V N5c50a852012-10-29 08:45:11 +0000635 return;
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530636 } else {
637 /* Disable promiscuous mode */
638 cpsw_set_promiscious(ndev, false);
Mugunthan V N5c50a852012-10-29 08:45:11 +0000639 }
640
Lennart Sorensen1e5c4bc2014-10-31 13:38:52 -0400641 /* Restore allmulti on vlans if necessary */
642 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
643
Mugunthan V N5c50a852012-10-29 08:45:11 +0000644 /* Clear all mcast from ALE */
Mugunthan V N25906052015-01-13 17:35:49 +0530645 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
646 vid);
Mugunthan V N5c50a852012-10-29 08:45:11 +0000647
648 if (!netdev_mc_empty(ndev)) {
649 struct netdev_hw_addr *ha;
650
651 /* program multicast address list into ALE register */
652 netdev_for_each_mc_addr(ha, ndev) {
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000653 cpsw_add_mcast(priv, (u8 *)ha->addr);
Mugunthan V N5c50a852012-10-29 08:45:11 +0000654 }
655 }
656}
657
Mugunthan V Ndf828592012-03-18 20:17:54 +0000658static void cpsw_intr_enable(struct cpsw_priv *priv)
659{
Richard Cochran996a5c22012-10-29 08:45:12 +0000660 __raw_writel(0xFF, &priv->wr_regs->tx_en);
661 __raw_writel(0xFF, &priv->wr_regs->rx_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000662
663 cpdma_ctlr_int_ctrl(priv->dma, true);
664 return;
665}
666
667static void cpsw_intr_disable(struct cpsw_priv *priv)
668{
Richard Cochran996a5c22012-10-29 08:45:12 +0000669 __raw_writel(0, &priv->wr_regs->tx_en);
670 __raw_writel(0, &priv->wr_regs->rx_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000671
672 cpdma_ctlr_int_ctrl(priv->dma, false);
673 return;
674}
675
Olof Johansson1a3b5052013-12-11 15:58:07 -0800676static void cpsw_tx_handler(void *token, int len, int status)
Mugunthan V Ndf828592012-03-18 20:17:54 +0000677{
678 struct sk_buff *skb = token;
679 struct net_device *ndev = skb->dev;
680 struct cpsw_priv *priv = netdev_priv(ndev);
681
Mugunthan V Nfae50822013-01-17 06:31:34 +0000682 /* Check whether the queue is stopped due to stalled tx dma, if the
683 * queue is stopped then start the queue as we have free desc for tx
684 */
Mugunthan V Ndf828592012-03-18 20:17:54 +0000685 if (unlikely(netif_queue_stopped(ndev)))
Mugunthan V Nb56d6b3f2013-03-27 04:41:59 +0000686 netif_wake_queue(ndev);
Mugunthan V N9232b162013-02-11 09:52:19 +0000687 cpts_tx_timestamp(priv->cpts, skb);
Tobias Klauser8dc43dd2014-03-10 13:12:23 +0100688 ndev->stats.tx_packets++;
689 ndev->stats.tx_bytes += len;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000690 dev_kfree_skb_any(skb);
691}
692
Olof Johansson1a3b5052013-12-11 15:58:07 -0800693static void cpsw_rx_handler(void *token, int len, int status)
Mugunthan V Ndf828592012-03-18 20:17:54 +0000694{
695 struct sk_buff *skb = token;
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000696 struct sk_buff *new_skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000697 struct net_device *ndev = skb->dev;
698 struct cpsw_priv *priv = netdev_priv(ndev);
699 int ret = 0;
700
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000701 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
702
Mugunthan V N16e5c572014-04-10 14:23:23 +0530703 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
Mugunthan V Na0e2c822014-09-10 16:38:09 +0530704 bool ndev_status = false;
705 struct cpsw_slave *slave = priv->slaves;
706 int n;
707
708 if (priv->data.dual_emac) {
709 /* In dual emac mode check for all interfaces */
710 for (n = priv->data.slaves; n; n--, slave++)
711 if (netif_running(slave->ndev))
712 ndev_status = true;
713 }
714
715 if (ndev_status && (status >= 0)) {
716 /* The packet received is for the interface which
717 * is already down and the other interface is up
Joe Perchesdbedd442015-03-06 20:49:12 -0800718 * and running, instead of freeing which results
Mugunthan V Na0e2c822014-09-10 16:38:09 +0530719 * in reducing of the number of rx descriptor in
720 * DMA engine, requeue skb back to cpdma.
721 */
722 new_skb = skb;
723 goto requeue;
724 }
725
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000726 /* the interface is going down, skbs are purged */
Mugunthan V Ndf828592012-03-18 20:17:54 +0000727 dev_kfree_skb_any(skb);
728 return;
729 }
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000730
731 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
732 if (new_skb) {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000733 skb_put(skb, len);
Mugunthan V N9232b162013-02-11 09:52:19 +0000734 cpts_rx_timestamp(priv->cpts, skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000735 skb->protocol = eth_type_trans(skb, ndev);
736 netif_receive_skb(skb);
Tobias Klauser8dc43dd2014-03-10 13:12:23 +0100737 ndev->stats.rx_bytes += len;
738 ndev->stats.rx_packets++;
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000739 } else {
Tobias Klauser8dc43dd2014-03-10 13:12:23 +0100740 ndev->stats.rx_dropped++;
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000741 new_skb = skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000742 }
743
Mugunthan V Na0e2c822014-09-10 16:38:09 +0530744requeue:
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000745 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
746 skb_tailroom(new_skb), 0);
747 if (WARN_ON(ret < 0))
748 dev_kfree_skb_any(new_skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000749}
750
Felipe Balbic03abd82015-01-16 10:11:12 -0600751static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
Mugunthan V Ndf828592012-03-18 20:17:54 +0000752{
753 struct cpsw_priv *priv = dev_id;
Felipe Balbi7ce67a32015-01-02 16:15:59 -0600754
Felipe Balbic03abd82015-01-16 10:11:12 -0600755 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
756 cpdma_chan_process(priv->txch, 128);
757
758 priv = cpsw_get_slave_priv(priv, 1);
759 if (priv)
760 cpdma_chan_process(priv->txch, 128);
761
762 return IRQ_HANDLED;
763}
764
765static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
766{
767 struct cpsw_priv *priv = dev_id;
768
769 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000770
771 cpsw_intr_disable(priv);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000772 if (priv->irq_enabled == true) {
Mugunthan V N5a0266a2015-07-08 14:35:22 +0530773 disable_irq_nosync(priv->irqs_table[0]);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000774 priv->irq_enabled = false;
775 }
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000776
777 if (netif_running(priv->ndev)) {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000778 napi_schedule(&priv->napi);
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000779 return IRQ_HANDLED;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000780 }
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000781
782 priv = cpsw_get_slave_priv(priv, 1);
783 if (!priv)
784 return IRQ_NONE;
785
786 if (netif_running(priv->ndev)) {
787 napi_schedule(&priv->napi);
788 return IRQ_HANDLED;
789 }
790 return IRQ_NONE;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000791}
792
Mugunthan V Ndf828592012-03-18 20:17:54 +0000793static int cpsw_poll(struct napi_struct *napi, int budget)
794{
795 struct cpsw_priv *priv = napi_to_priv(napi);
796 int num_tx, num_rx;
797
798 num_tx = cpdma_chan_process(priv->txch, 128);
Mugunthan V N510a1e722013-02-17 22:19:20 +0000799
Mugunthan V Ndf828592012-03-18 20:17:54 +0000800 num_rx = cpdma_chan_process(priv->rxch, budget);
Mugunthan V N510a1e722013-02-17 22:19:20 +0000801 if (num_rx < budget) {
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000802 struct cpsw_priv *prim_cpsw;
803
Mugunthan V N510a1e722013-02-17 22:19:20 +0000804 napi_complete(napi);
805 cpsw_intr_enable(priv);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000806 prim_cpsw = cpsw_get_slave_priv(priv, 0);
807 if (prim_cpsw->irq_enabled == false) {
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000808 prim_cpsw->irq_enabled = true;
Mugunthan V N5a0266a2015-07-08 14:35:22 +0530809 enable_irq(priv->irqs_table[0]);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000810 }
Mugunthan V N510a1e722013-02-17 22:19:20 +0000811 }
Mugunthan V Ndf828592012-03-18 20:17:54 +0000812
813 if (num_rx || num_tx)
814 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
815 num_rx, num_tx);
816
Mugunthan V Ndf828592012-03-18 20:17:54 +0000817 return num_rx;
818}
819
820static inline void soft_reset(const char *module, void __iomem *reg)
821{
822 unsigned long timeout = jiffies + HZ;
823
824 __raw_writel(1, reg);
825 do {
826 cpu_relax();
827 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
828
829 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
830}
831
832#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
833 ((mac)[2] << 16) | ((mac)[3] << 24))
834#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
835
836static void cpsw_set_slave_mac(struct cpsw_slave *slave,
837 struct cpsw_priv *priv)
838{
Richard Cochran9750a3a2012-10-29 08:45:15 +0000839 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
840 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000841}
842
843static void _cpsw_adjust_link(struct cpsw_slave *slave,
844 struct cpsw_priv *priv, bool *link)
845{
846 struct phy_device *phy = slave->phy;
847 u32 mac_control = 0;
848 u32 slave_port;
849
850 if (!phy)
851 return;
852
853 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
854
855 if (phy->link) {
856 mac_control = priv->data.mac_control;
857
858 /* enable forwarding */
859 cpsw_ale_control_set(priv->ale, slave_port,
860 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
861
862 if (phy->speed == 1000)
863 mac_control |= BIT(7); /* GIGABITEN */
864 if (phy->duplex)
865 mac_control |= BIT(0); /* FULLDUPLEXEN */
Daniel Mack342b7b72012-09-27 09:19:34 +0000866
867 /* set speed_in input in case RMII mode is used in 100Mbps */
868 if (phy->speed == 100)
869 mac_control |= BIT(15);
Mugunthan V Na81d8762013-12-13 18:42:55 +0530870 else if (phy->speed == 10)
871 mac_control |= BIT(18); /* In Band mode */
Daniel Mack342b7b72012-09-27 09:19:34 +0000872
Mugunthan V N1923d6e2014-09-08 22:54:02 +0530873 if (priv->rx_pause)
874 mac_control |= BIT(3);
875
876 if (priv->tx_pause)
877 mac_control |= BIT(4);
878
Mugunthan V Ndf828592012-03-18 20:17:54 +0000879 *link = true;
880 } else {
881 mac_control = 0;
882 /* disable forwarding */
883 cpsw_ale_control_set(priv->ale, slave_port,
884 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
885 }
886
887 if (mac_control != slave->mac_control) {
888 phy_print_status(phy);
889 __raw_writel(mac_control, &slave->sliver->mac_control);
890 }
891
892 slave->mac_control = mac_control;
893}
894
895static void cpsw_adjust_link(struct net_device *ndev)
896{
897 struct cpsw_priv *priv = netdev_priv(ndev);
898 bool link = false;
899
900 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
901
902 if (link) {
903 netif_carrier_on(ndev);
904 if (netif_running(ndev))
905 netif_wake_queue(ndev);
906 } else {
907 netif_carrier_off(ndev);
908 netif_stop_queue(ndev);
909 }
910}
911
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000912static int cpsw_get_coalesce(struct net_device *ndev,
913 struct ethtool_coalesce *coal)
914{
915 struct cpsw_priv *priv = netdev_priv(ndev);
916
917 coal->rx_coalesce_usecs = priv->coal_intvl;
918 return 0;
919}
920
921static int cpsw_set_coalesce(struct net_device *ndev,
922 struct ethtool_coalesce *coal)
923{
924 struct cpsw_priv *priv = netdev_priv(ndev);
925 u32 int_ctrl;
926 u32 num_interrupts = 0;
927 u32 prescale = 0;
928 u32 addnl_dvdr = 1;
929 u32 coal_intvl = 0;
930
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000931 coal_intvl = coal->rx_coalesce_usecs;
932
933 int_ctrl = readl(&priv->wr_regs->int_control);
934 prescale = priv->bus_freq_mhz * 4;
935
Mugunthan V Na84bc2a2014-07-15 20:26:53 +0530936 if (!coal->rx_coalesce_usecs) {
937 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
938 goto update_return;
939 }
940
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000941 if (coal_intvl < CPSW_CMINTMIN_INTVL)
942 coal_intvl = CPSW_CMINTMIN_INTVL;
943
944 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
945 /* Interrupt pacer works with 4us Pulse, we can
946 * throttle further by dilating the 4us pulse.
947 */
948 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
949
950 if (addnl_dvdr > 1) {
951 prescale *= addnl_dvdr;
952 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
953 coal_intvl = (CPSW_CMINTMAX_INTVL
954 * addnl_dvdr);
955 } else {
956 addnl_dvdr = 1;
957 coal_intvl = CPSW_CMINTMAX_INTVL;
958 }
959 }
960
961 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
962 writel(num_interrupts, &priv->wr_regs->rx_imax);
963 writel(num_interrupts, &priv->wr_regs->tx_imax);
964
965 int_ctrl |= CPSW_INTPACEEN;
966 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
967 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
Mugunthan V Na84bc2a2014-07-15 20:26:53 +0530968
969update_return:
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000970 writel(int_ctrl, &priv->wr_regs->int_control);
971
972 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
973 if (priv->data.dual_emac) {
974 int i;
975
976 for (i = 0; i < priv->data.slaves; i++) {
977 priv = netdev_priv(priv->slaves[i].ndev);
978 priv->coal_intvl = coal_intvl;
979 }
980 } else {
981 priv->coal_intvl = coal_intvl;
982 }
983
984 return 0;
985}
986
Mugunthan V Nd9718542013-07-23 15:38:17 +0530987static int cpsw_get_sset_count(struct net_device *ndev, int sset)
988{
989 switch (sset) {
990 case ETH_SS_STATS:
991 return CPSW_STATS_LEN;
992 default:
993 return -EOPNOTSUPP;
994 }
995}
996
997static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
998{
999 u8 *p = data;
1000 int i;
1001
1002 switch (stringset) {
1003 case ETH_SS_STATS:
1004 for (i = 0; i < CPSW_STATS_LEN; i++) {
1005 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1006 ETH_GSTRING_LEN);
1007 p += ETH_GSTRING_LEN;
1008 }
1009 break;
1010 }
1011}
1012
1013static void cpsw_get_ethtool_stats(struct net_device *ndev,
1014 struct ethtool_stats *stats, u64 *data)
1015{
1016 struct cpsw_priv *priv = netdev_priv(ndev);
1017 struct cpdma_chan_stats rx_stats;
1018 struct cpdma_chan_stats tx_stats;
1019 u32 val;
1020 u8 *p;
1021 int i;
1022
1023 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1024 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1025 cpdma_chan_get_stats(priv->txch, &tx_stats);
1026
1027 for (i = 0; i < CPSW_STATS_LEN; i++) {
1028 switch (cpsw_gstrings_stats[i].type) {
1029 case CPSW_STATS:
1030 val = readl(priv->hw_stats +
1031 cpsw_gstrings_stats[i].stat_offset);
1032 data[i] = val;
1033 break;
1034
1035 case CPDMA_RX_STATS:
1036 p = (u8 *)&rx_stats +
1037 cpsw_gstrings_stats[i].stat_offset;
1038 data[i] = *(u32 *)p;
1039 break;
1040
1041 case CPDMA_TX_STATS:
1042 p = (u8 *)&tx_stats +
1043 cpsw_gstrings_stats[i].stat_offset;
1044 data[i] = *(u32 *)p;
1045 break;
1046 }
1047 }
1048}
1049
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001050static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1051{
1052 u32 i;
1053 u32 usage_count = 0;
1054
1055 if (!priv->data.dual_emac)
1056 return 0;
1057
1058 for (i = 0; i < priv->data.slaves; i++)
1059 if (priv->slaves[i].open_stat)
1060 usage_count++;
1061
1062 return usage_count;
1063}
1064
1065static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1066 struct cpsw_priv *priv, struct sk_buff *skb)
1067{
1068 if (!priv->data.dual_emac)
1069 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001070 skb->len, 0);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001071
1072 if (ndev == cpsw_get_slave_ndev(priv, 0))
1073 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001074 skb->len, 1);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001075 else
1076 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001077 skb->len, 2);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001078}
1079
1080static inline void cpsw_add_dual_emac_def_ale_entries(
1081 struct cpsw_priv *priv, struct cpsw_slave *slave,
1082 u32 slave_port)
1083{
1084 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1085
1086 if (priv->version == CPSW_VERSION_1)
1087 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1088 else
1089 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1090 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1091 port_mask, port_mask, 0);
1092 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1093 port_mask, ALE_VLAN, slave->port_vlan, 0);
1094 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
George McCollister568871492015-02-26 15:19:30 -06001095 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001096}
1097
Daniel Mack1e7a2e22013-11-15 08:29:16 +01001098static void soft_reset_slave(struct cpsw_slave *slave)
Mugunthan V Ndf828592012-03-18 20:17:54 +00001099{
1100 char name[32];
Daniel Mack1e7a2e22013-11-15 08:29:16 +01001101
1102 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1103 soft_reset(name, &slave->sliver->soft_reset);
1104}
1105
1106static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1107{
Mugunthan V Ndf828592012-03-18 20:17:54 +00001108 u32 slave_port;
1109
Daniel Mack1e7a2e22013-11-15 08:29:16 +01001110 soft_reset_slave(slave);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001111
1112 /* setup priority mapping */
1113 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
Richard Cochran9750a3a2012-10-29 08:45:15 +00001114
1115 switch (priv->version) {
1116 case CPSW_VERSION_1:
1117 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1118 break;
1119 case CPSW_VERSION_2:
Mugunthan V Nc193f362013-08-05 17:30:05 +05301120 case CPSW_VERSION_3:
Mugunthan V N926489b2013-08-12 17:11:15 +05301121 case CPSW_VERSION_4:
Richard Cochran9750a3a2012-10-29 08:45:15 +00001122 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1123 break;
1124 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001125
1126 /* setup max packet size, and mac address */
1127 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1128 cpsw_set_slave_mac(slave, priv);
1129
1130 slave->mac_control = 0; /* no link yet */
1131
1132 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1133
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001134 if (priv->data.dual_emac)
1135 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1136 else
1137 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1138 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001139
1140 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
Florian Fainellif9a8f832013-01-14 00:52:52 +00001141 &cpsw_adjust_link, slave->data->phy_if);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001142 if (IS_ERR(slave->phy)) {
1143 dev_err(priv->dev, "phy %s not found on slave %d\n",
1144 slave->data->phy_id, slave->slave_num);
1145 slave->phy = NULL;
1146 } else {
1147 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1148 slave->phy->phy_id);
1149 phy_start(slave->phy);
Mugunthan V N388367a2013-09-21 00:50:40 +05301150
1151 /* Configure GMII_SEL register */
1152 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1153 slave->slave_num);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001154 }
1155}
1156
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001157static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1158{
1159 const int vlan = priv->data.default_vlan;
1160 const int port = priv->host_port;
1161 u32 reg;
1162 int i;
Lennart Sorensen1e5c4bc2014-10-31 13:38:52 -04001163 int unreg_mcast_mask;
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001164
1165 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1166 CPSW2_PORT_VLAN;
1167
1168 writel(vlan, &priv->host_port_regs->port_vlan);
1169
Daniel Mack0237c112013-02-26 04:06:20 +00001170 for (i = 0; i < priv->data.slaves; i++)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001171 slave_write(priv->slaves + i, vlan, reg);
1172
Lennart Sorensen1e5c4bc2014-10-31 13:38:52 -04001173 if (priv->ndev->flags & IFF_ALLMULTI)
1174 unreg_mcast_mask = ALE_ALL_PORTS;
1175 else
1176 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1177
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001178 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1179 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
Lennart Sorensen1e5c4bc2014-10-31 13:38:52 -04001180 unreg_mcast_mask << port);
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001181}
1182
Mugunthan V Ndf828592012-03-18 20:17:54 +00001183static void cpsw_init_host_port(struct cpsw_priv *priv)
1184{
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001185 u32 control_reg;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001186 u32 fifo_mode;
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001187
Mugunthan V Ndf828592012-03-18 20:17:54 +00001188 /* soft reset the controller and initialize ale */
1189 soft_reset("cpsw", &priv->regs->soft_reset);
1190 cpsw_ale_start(priv->ale);
1191
1192 /* switch to vlan unaware mode */
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001193 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1194 CPSW_ALE_VLAN_AWARE);
1195 control_reg = readl(&priv->regs->control);
1196 control_reg |= CPSW_VLAN_AWARE;
1197 writel(control_reg, &priv->regs->control);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001198 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1199 CPSW_FIFO_NORMAL_MODE;
1200 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001201
1202 /* setup host port priority mapping */
1203 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1204 &priv->host_port_regs->cpdma_tx_pri_map);
1205 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1206
1207 cpsw_ale_control_set(priv->ale, priv->host_port,
1208 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1209
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001210 if (!priv->data.dual_emac) {
1211 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1212 0, 0);
1213 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1214 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1215 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001216}
1217
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001218static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1219{
Schuyler Patton3995d262014-03-03 16:19:06 +05301220 u32 slave_port;
1221
1222 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1223
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001224 if (!slave->phy)
1225 return;
1226 phy_stop(slave->phy);
1227 phy_disconnect(slave->phy);
1228 slave->phy = NULL;
Schuyler Patton3995d262014-03-03 16:19:06 +05301229 cpsw_ale_control_set(priv->ale, slave_port,
1230 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001231}
1232
Mugunthan V Ndf828592012-03-18 20:17:54 +00001233static int cpsw_ndo_open(struct net_device *ndev)
1234{
1235 struct cpsw_priv *priv = netdev_priv(ndev);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +00001236 struct cpsw_priv *prim_cpsw;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001237 int i, ret;
1238 u32 reg;
1239
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001240 if (!cpsw_common_res_usage_state(priv))
1241 cpsw_intr_disable(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001242 netif_carrier_off(ndev);
1243
Mugunthan V Nf150bd72012-07-17 08:09:50 +00001244 pm_runtime_get_sync(&priv->pdev->dev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001245
Richard Cochran549985e2012-11-14 09:07:56 +00001246 reg = priv->version;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001247
1248 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1249 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1250 CPSW_RTL_VERSION(reg));
1251
1252 /* initialize host and slave ports */
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001253 if (!cpsw_common_res_usage_state(priv))
1254 cpsw_init_host_port(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001255 for_each_slave(priv, cpsw_slave_open, priv);
1256
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001257 /* Add default VLAN */
Mugunthan V Ne6afea02014-06-18 17:21:48 +05301258 if (!priv->data.dual_emac)
1259 cpsw_add_default_vlan(priv);
1260 else
1261 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1262 ALE_ALL_PORTS << priv->host_port,
1263 ALE_ALL_PORTS << priv->host_port, 0, 0);
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001264
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001265 if (!cpsw_common_res_usage_state(priv)) {
1266 /* setup tx dma to fixed prio and zero offset */
1267 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1268 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001269
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001270 /* disable priority elevation */
1271 __raw_writel(0, &priv->regs->ptype);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001272
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001273 /* enable statistics collection only on all ports */
1274 __raw_writel(0x7, &priv->regs->stat_port_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001275
Mugunthan V N1923d6e2014-09-08 22:54:02 +05301276 /* Enable internal fifo flow control */
1277 writel(0x7, &priv->regs->flow_control);
1278
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001279 if (WARN_ON(!priv->data.rx_descs))
1280 priv->data.rx_descs = 128;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001281
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001282 for (i = 0; i < priv->data.rx_descs; i++) {
1283 struct sk_buff *skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001284
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001285 ret = -ENOMEM;
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001286 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1287 priv->rx_packet_max, GFP_KERNEL);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001288 if (!skb)
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001289 goto err_cleanup;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001290 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001291 skb_tailroom(skb), 0);
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001292 if (ret < 0) {
1293 kfree_skb(skb);
1294 goto err_cleanup;
1295 }
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001296 }
1297 /* continue even if we didn't manage to submit all
1298 * receive descs
1299 */
1300 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
Mugunthan V Nf280e892013-12-11 22:09:05 -06001301
1302 if (cpts_register(&priv->pdev->dev, priv->cpts,
1303 priv->data.cpts_clock_mult,
1304 priv->data.cpts_clock_shift))
1305 dev_err(priv->dev, "error registering cpts device\n");
1306
Mugunthan V Ndf828592012-03-18 20:17:54 +00001307 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001308
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001309 /* Enable Interrupt pacing if configured */
1310 if (priv->coal_intvl != 0) {
1311 struct ethtool_coalesce coal;
1312
1313 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1314 cpsw_set_coalesce(ndev, &coal);
1315 }
1316
Mugunthan V Nf63a9752014-04-10 14:23:24 +05301317 napi_enable(&priv->napi);
1318 cpdma_ctlr_start(priv->dma);
1319 cpsw_intr_enable(priv);
Mugunthan V Nf63a9752014-04-10 14:23:24 +05301320
Sebastian Siewiora11fbba2013-04-24 08:48:25 +00001321 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1322 if (prim_cpsw->irq_enabled == false) {
1323 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1324 prim_cpsw->irq_enabled = true;
Mugunthan V N5a0266a2015-07-08 14:35:22 +05301325 enable_irq(prim_cpsw->irqs_table[0]);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +00001326 }
1327 }
1328
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001329 if (priv->data.dual_emac)
1330 priv->slaves[priv->emac_port].open_stat = true;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001331 return 0;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001332
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001333err_cleanup:
1334 cpdma_ctlr_stop(priv->dma);
1335 for_each_slave(priv, cpsw_slave_stop, priv);
1336 pm_runtime_put_sync(&priv->pdev->dev);
1337 netif_carrier_off(priv->ndev);
1338 return ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001339}
1340
1341static int cpsw_ndo_stop(struct net_device *ndev)
1342{
1343 struct cpsw_priv *priv = netdev_priv(ndev);
1344
1345 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
Mugunthan V Ndf828592012-03-18 20:17:54 +00001346 netif_stop_queue(priv->ndev);
1347 napi_disable(&priv->napi);
1348 netif_carrier_off(priv->ndev);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001349
1350 if (cpsw_common_res_usage_state(priv) <= 1) {
Mugunthan V Nf280e892013-12-11 22:09:05 -06001351 cpts_unregister(priv->cpts);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001352 cpsw_intr_disable(priv);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001353 cpdma_ctlr_stop(priv->dma);
1354 cpsw_ale_stop(priv->ale);
1355 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001356 for_each_slave(priv, cpsw_slave_stop, priv);
Mugunthan V Nf150bd72012-07-17 08:09:50 +00001357 pm_runtime_put_sync(&priv->pdev->dev);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001358 if (priv->data.dual_emac)
1359 priv->slaves[priv->emac_port].open_stat = false;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001360 return 0;
1361}
1362
1363static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1364 struct net_device *ndev)
1365{
1366 struct cpsw_priv *priv = netdev_priv(ndev);
1367 int ret;
1368
1369 ndev->trans_start = jiffies;
1370
1371 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1372 cpsw_err(priv, tx_err, "packet pad failed\n");
Tobias Klauser8dc43dd2014-03-10 13:12:23 +01001373 ndev->stats.tx_dropped++;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001374 return NETDEV_TX_OK;
1375 }
1376
Mugunthan V N9232b162013-02-11 09:52:19 +00001377 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1378 priv->cpts->tx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001379 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1380
1381 skb_tx_timestamp(skb);
1382
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001383 ret = cpsw_tx_packet_submit(ndev, priv, skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001384 if (unlikely(ret != 0)) {
1385 cpsw_err(priv, tx_err, "desc submit failed\n");
1386 goto fail;
1387 }
1388
Mugunthan V Nfae50822013-01-17 06:31:34 +00001389 /* If there is no more tx desc left free then we need to
1390 * tell the kernel to stop sending us tx frames.
1391 */
Daniel Mackd35162f2013-03-12 06:31:19 +00001392 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
Mugunthan V Nfae50822013-01-17 06:31:34 +00001393 netif_stop_queue(ndev);
1394
Mugunthan V Ndf828592012-03-18 20:17:54 +00001395 return NETDEV_TX_OK;
1396fail:
Tobias Klauser8dc43dd2014-03-10 13:12:23 +01001397 ndev->stats.tx_dropped++;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001398 netif_stop_queue(ndev);
1399 return NETDEV_TX_BUSY;
1400}
1401
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001402#ifdef CONFIG_TI_CPTS
1403
1404static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1405{
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001406 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001407 u32 ts_en, seq_id;
1408
Mugunthan V N9232b162013-02-11 09:52:19 +00001409 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001410 slave_write(slave, 0, CPSW1_TS_CTL);
1411 return;
1412 }
1413
1414 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1415 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1416
Mugunthan V N9232b162013-02-11 09:52:19 +00001417 if (priv->cpts->tx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001418 ts_en |= CPSW_V1_TS_TX_EN;
1419
Mugunthan V N9232b162013-02-11 09:52:19 +00001420 if (priv->cpts->rx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001421 ts_en |= CPSW_V1_TS_RX_EN;
1422
1423 slave_write(slave, ts_en, CPSW1_TS_CTL);
1424 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1425}
1426
1427static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1428{
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001429 struct cpsw_slave *slave;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001430 u32 ctrl, mtype;
1431
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001432 if (priv->data.dual_emac)
1433 slave = &priv->slaves[priv->emac_port];
1434 else
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001435 slave = &priv->slaves[priv->data.active_slave];
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001436
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001437 ctrl = slave_read(slave, CPSW2_CONTROL);
George Cherian09c55372014-05-02 12:02:02 +05301438 switch (priv->version) {
1439 case CPSW_VERSION_2:
1440 ctrl &= ~CTRL_V2_ALL_TS_MASK;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001441
George Cherian09c55372014-05-02 12:02:02 +05301442 if (priv->cpts->tx_enable)
1443 ctrl |= CTRL_V2_TX_TS_BITS;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001444
George Cherian09c55372014-05-02 12:02:02 +05301445 if (priv->cpts->rx_enable)
1446 ctrl |= CTRL_V2_RX_TS_BITS;
Richard Cochran26fe7eb2015-05-25 11:02:13 +02001447 break;
George Cherian09c55372014-05-02 12:02:02 +05301448 case CPSW_VERSION_3:
1449 default:
1450 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1451
1452 if (priv->cpts->tx_enable)
1453 ctrl |= CTRL_V3_TX_TS_BITS;
1454
1455 if (priv->cpts->rx_enable)
1456 ctrl |= CTRL_V3_RX_TS_BITS;
Richard Cochran26fe7eb2015-05-25 11:02:13 +02001457 break;
George Cherian09c55372014-05-02 12:02:02 +05301458 }
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001459
1460 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1461
1462 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1463 slave_write(slave, ctrl, CPSW2_CONTROL);
1464 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1465}
1466
Ben Hutchingsa5b41452013-11-18 23:23:40 +00001467static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001468{
Mugunthan V N3177bf62012-11-27 07:53:40 +00001469 struct cpsw_priv *priv = netdev_priv(dev);
Mugunthan V N9232b162013-02-11 09:52:19 +00001470 struct cpts *cpts = priv->cpts;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001471 struct hwtstamp_config cfg;
1472
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001473 if (priv->version != CPSW_VERSION_1 &&
George Cherianf7d403c2014-05-02 12:02:01 +05301474 priv->version != CPSW_VERSION_2 &&
1475 priv->version != CPSW_VERSION_3)
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001476 return -EOPNOTSUPP;
1477
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001478 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1479 return -EFAULT;
1480
1481 /* reserved for future extensions */
1482 if (cfg.flags)
1483 return -EINVAL;
1484
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001485 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001486 return -ERANGE;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001487
1488 switch (cfg.rx_filter) {
1489 case HWTSTAMP_FILTER_NONE:
1490 cpts->rx_enable = 0;
1491 break;
1492 case HWTSTAMP_FILTER_ALL:
1493 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1494 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1495 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1496 return -ERANGE;
1497 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1498 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1499 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1500 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1501 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1502 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1503 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1504 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1505 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1506 cpts->rx_enable = 1;
1507 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1508 break;
1509 default:
1510 return -ERANGE;
1511 }
1512
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001513 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1514
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001515 switch (priv->version) {
1516 case CPSW_VERSION_1:
1517 cpsw_hwtstamp_v1(priv);
1518 break;
1519 case CPSW_VERSION_2:
George Cherianf7d403c2014-05-02 12:02:01 +05301520 case CPSW_VERSION_3:
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001521 cpsw_hwtstamp_v2(priv);
1522 break;
1523 default:
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001524 WARN_ON(1);
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001525 }
1526
1527 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1528}
1529
Ben Hutchingsa5b41452013-11-18 23:23:40 +00001530static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1531{
1532 struct cpsw_priv *priv = netdev_priv(dev);
1533 struct cpts *cpts = priv->cpts;
1534 struct hwtstamp_config cfg;
1535
1536 if (priv->version != CPSW_VERSION_1 &&
George Cherianf7d403c2014-05-02 12:02:01 +05301537 priv->version != CPSW_VERSION_2 &&
1538 priv->version != CPSW_VERSION_3)
Ben Hutchingsa5b41452013-11-18 23:23:40 +00001539 return -EOPNOTSUPP;
1540
1541 cfg.flags = 0;
1542 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1543 cfg.rx_filter = (cpts->rx_enable ?
1544 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1545
1546 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1547}
1548
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001549#endif /*CONFIG_TI_CPTS*/
1550
1551static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1552{
Mugunthan V N11f2c982013-03-11 23:16:38 +00001553 struct cpsw_priv *priv = netdev_priv(dev);
Mugunthan V N11f2c982013-03-11 23:16:38 +00001554 int slave_no = cpsw_slave_index(priv);
1555
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001556 if (!netif_running(dev))
1557 return -EINVAL;
1558
Mugunthan V N11f2c982013-03-11 23:16:38 +00001559 switch (cmd) {
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001560#ifdef CONFIG_TI_CPTS
Mugunthan V N11f2c982013-03-11 23:16:38 +00001561 case SIOCSHWTSTAMP:
Ben Hutchingsa5b41452013-11-18 23:23:40 +00001562 return cpsw_hwtstamp_set(dev, req);
1563 case SIOCGHWTSTAMP:
1564 return cpsw_hwtstamp_get(dev, req);
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001565#endif
Mugunthan V N11f2c982013-03-11 23:16:38 +00001566 }
1567
Stefan Sørensenc1b59942014-02-16 14:54:25 +01001568 if (!priv->slaves[slave_no].phy)
1569 return -EOPNOTSUPP;
1570 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001571}
1572
Mugunthan V Ndf828592012-03-18 20:17:54 +00001573static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1574{
1575 struct cpsw_priv *priv = netdev_priv(ndev);
1576
1577 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
Tobias Klauser8dc43dd2014-03-10 13:12:23 +01001578 ndev->stats.tx_errors++;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001579 cpsw_intr_disable(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001580 cpdma_chan_stop(priv->txch);
1581 cpdma_chan_start(priv->txch);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001582 cpsw_intr_enable(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001583}
1584
Mugunthan V Ndcfd8d52013-07-25 23:44:01 +05301585static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1586{
1587 struct cpsw_priv *priv = netdev_priv(ndev);
1588 struct sockaddr *addr = (struct sockaddr *)p;
1589 int flags = 0;
1590 u16 vid = 0;
1591
1592 if (!is_valid_ether_addr(addr->sa_data))
1593 return -EADDRNOTAVAIL;
1594
1595 if (priv->data.dual_emac) {
1596 vid = priv->slaves[priv->emac_port].port_vlan;
1597 flags = ALE_VLAN;
1598 }
1599
1600 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1601 flags, vid);
1602 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1603 flags, vid);
1604
1605 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1606 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1607 for_each_slave(priv, cpsw_set_slave_mac, priv);
1608
1609 return 0;
1610}
1611
Mugunthan V Ndf828592012-03-18 20:17:54 +00001612#ifdef CONFIG_NET_POLL_CONTROLLER
1613static void cpsw_ndo_poll_controller(struct net_device *ndev)
1614{
1615 struct cpsw_priv *priv = netdev_priv(ndev);
1616
1617 cpsw_intr_disable(priv);
Felipe Balbi92cb13f2015-01-19 11:52:36 -06001618 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1619 cpsw_tx_interrupt(priv->irqs_table[1], priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001620 cpsw_intr_enable(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001621}
1622#endif
1623
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001624static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1625 unsigned short vid)
1626{
1627 int ret;
Mugunthan V N9f6bd8f2015-01-15 14:59:28 +05301628 int unreg_mcast_mask = 0;
1629 u32 port_mask;
Lennart Sorensen1e5c4bc2014-10-31 13:38:52 -04001630
Mugunthan V N9f6bd8f2015-01-15 14:59:28 +05301631 if (priv->data.dual_emac) {
1632 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001633
Mugunthan V N9f6bd8f2015-01-15 14:59:28 +05301634 if (priv->ndev->flags & IFF_ALLMULTI)
1635 unreg_mcast_mask = port_mask;
1636 } else {
1637 port_mask = ALE_ALL_PORTS;
1638
1639 if (priv->ndev->flags & IFF_ALLMULTI)
1640 unreg_mcast_mask = ALE_ALL_PORTS;
1641 else
1642 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1643 }
1644
1645 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
Lennart Sorensen1e5c4bc2014-10-31 13:38:52 -04001646 unreg_mcast_mask << priv->host_port);
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001647 if (ret != 0)
1648 return ret;
1649
1650 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1651 priv->host_port, ALE_VLAN, vid);
1652 if (ret != 0)
1653 goto clean_vid;
1654
1655 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
Mugunthan V N9f6bd8f2015-01-15 14:59:28 +05301656 port_mask, ALE_VLAN, vid, 0);
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001657 if (ret != 0)
1658 goto clean_vlan_ucast;
1659 return 0;
1660
1661clean_vlan_ucast:
1662 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1663 priv->host_port, ALE_VLAN, vid);
1664clean_vid:
1665 cpsw_ale_del_vlan(priv->ale, vid, 0);
1666 return ret;
1667}
1668
1669static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
Patrick McHardy80d5c362013-04-19 02:04:28 +00001670 __be16 proto, u16 vid)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001671{
1672 struct cpsw_priv *priv = netdev_priv(ndev);
1673
1674 if (vid == priv->data.default_vlan)
1675 return 0;
1676
Mugunthan V N02a54162015-01-22 15:19:22 +05301677 if (priv->data.dual_emac) {
1678 /* In dual EMAC, reserved VLAN id should not be used for
1679 * creating VLAN interfaces as this can break the dual
1680 * EMAC port separation
1681 */
1682 int i;
1683
1684 for (i = 0; i < priv->data.slaves; i++) {
1685 if (vid == priv->slaves[i].port_vlan)
1686 return -EINVAL;
1687 }
1688 }
1689
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001690 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1691 return cpsw_add_vlan_ale_entry(priv, vid);
1692}
1693
1694static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
Patrick McHardy80d5c362013-04-19 02:04:28 +00001695 __be16 proto, u16 vid)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001696{
1697 struct cpsw_priv *priv = netdev_priv(ndev);
1698 int ret;
1699
1700 if (vid == priv->data.default_vlan)
1701 return 0;
1702
Mugunthan V N02a54162015-01-22 15:19:22 +05301703 if (priv->data.dual_emac) {
1704 int i;
1705
1706 for (i = 0; i < priv->data.slaves; i++) {
1707 if (vid == priv->slaves[i].port_vlan)
1708 return -EINVAL;
1709 }
1710 }
1711
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001712 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1713 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1714 if (ret != 0)
1715 return ret;
1716
1717 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1718 priv->host_port, ALE_VLAN, vid);
1719 if (ret != 0)
1720 return ret;
1721
1722 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1723 0, ALE_VLAN, vid);
1724}
1725
Mugunthan V Ndf828592012-03-18 20:17:54 +00001726static const struct net_device_ops cpsw_netdev_ops = {
1727 .ndo_open = cpsw_ndo_open,
1728 .ndo_stop = cpsw_ndo_stop,
1729 .ndo_start_xmit = cpsw_ndo_start_xmit,
Mugunthan V Ndcfd8d52013-07-25 23:44:01 +05301730 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001731 .ndo_do_ioctl = cpsw_ndo_ioctl,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001732 .ndo_validate_addr = eth_validate_addr,
David S. Miller5c473ed2012-03-20 00:33:59 -04001733 .ndo_change_mtu = eth_change_mtu,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001734 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
Mugunthan V N5c50a852012-10-29 08:45:11 +00001735 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001736#ifdef CONFIG_NET_POLL_CONTROLLER
1737 .ndo_poll_controller = cpsw_ndo_poll_controller,
1738#endif
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001739 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1740 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001741};
1742
Mugunthan V N52c4f0e2014-07-22 23:25:07 +05301743static int cpsw_get_regs_len(struct net_device *ndev)
1744{
1745 struct cpsw_priv *priv = netdev_priv(ndev);
1746
1747 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1748}
1749
1750static void cpsw_get_regs(struct net_device *ndev,
1751 struct ethtool_regs *regs, void *p)
1752{
1753 struct cpsw_priv *priv = netdev_priv(ndev);
1754 u32 *reg = p;
1755
1756 /* update CPSW IP version */
1757 regs->version = priv->version;
1758
1759 cpsw_ale_dump(priv->ale, reg);
1760}
1761
Mugunthan V Ndf828592012-03-18 20:17:54 +00001762static void cpsw_get_drvinfo(struct net_device *ndev,
1763 struct ethtool_drvinfo *info)
1764{
1765 struct cpsw_priv *priv = netdev_priv(ndev);
Jiri Pirko7826d432013-01-06 00:44:26 +00001766
Mugunthan V N52c4f0e2014-07-22 23:25:07 +05301767 strlcpy(info->driver, "cpsw", sizeof(info->driver));
Jiri Pirko7826d432013-01-06 00:44:26 +00001768 strlcpy(info->version, "1.0", sizeof(info->version));
1769 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
Mugunthan V N52c4f0e2014-07-22 23:25:07 +05301770 info->regdump_len = cpsw_get_regs_len(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001771}
1772
1773static u32 cpsw_get_msglevel(struct net_device *ndev)
1774{
1775 struct cpsw_priv *priv = netdev_priv(ndev);
1776 return priv->msg_enable;
1777}
1778
1779static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1780{
1781 struct cpsw_priv *priv = netdev_priv(ndev);
1782 priv->msg_enable = value;
1783}
1784
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001785static int cpsw_get_ts_info(struct net_device *ndev,
1786 struct ethtool_ts_info *info)
1787{
1788#ifdef CONFIG_TI_CPTS
1789 struct cpsw_priv *priv = netdev_priv(ndev);
1790
1791 info->so_timestamping =
1792 SOF_TIMESTAMPING_TX_HARDWARE |
1793 SOF_TIMESTAMPING_TX_SOFTWARE |
1794 SOF_TIMESTAMPING_RX_HARDWARE |
1795 SOF_TIMESTAMPING_RX_SOFTWARE |
1796 SOF_TIMESTAMPING_SOFTWARE |
1797 SOF_TIMESTAMPING_RAW_HARDWARE;
Mugunthan V N9232b162013-02-11 09:52:19 +00001798 info->phc_index = priv->cpts->phc_index;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001799 info->tx_types =
1800 (1 << HWTSTAMP_TX_OFF) |
1801 (1 << HWTSTAMP_TX_ON);
1802 info->rx_filters =
1803 (1 << HWTSTAMP_FILTER_NONE) |
1804 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1805#else
1806 info->so_timestamping =
1807 SOF_TIMESTAMPING_TX_SOFTWARE |
1808 SOF_TIMESTAMPING_RX_SOFTWARE |
1809 SOF_TIMESTAMPING_SOFTWARE;
1810 info->phc_index = -1;
1811 info->tx_types = 0;
1812 info->rx_filters = 0;
1813#endif
1814 return 0;
1815}
1816
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +00001817static int cpsw_get_settings(struct net_device *ndev,
1818 struct ethtool_cmd *ecmd)
1819{
1820 struct cpsw_priv *priv = netdev_priv(ndev);
1821 int slave_no = cpsw_slave_index(priv);
1822
1823 if (priv->slaves[slave_no].phy)
1824 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1825 else
1826 return -EOPNOTSUPP;
1827}
1828
1829static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1830{
1831 struct cpsw_priv *priv = netdev_priv(ndev);
1832 int slave_no = cpsw_slave_index(priv);
1833
1834 if (priv->slaves[slave_no].phy)
1835 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1836 else
1837 return -EOPNOTSUPP;
1838}
1839
Matus Ujhelyid8a64422013-08-20 07:59:38 +02001840static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1841{
1842 struct cpsw_priv *priv = netdev_priv(ndev);
1843 int slave_no = cpsw_slave_index(priv);
1844
1845 wol->supported = 0;
1846 wol->wolopts = 0;
1847
1848 if (priv->slaves[slave_no].phy)
1849 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1850}
1851
1852static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1853{
1854 struct cpsw_priv *priv = netdev_priv(ndev);
1855 int slave_no = cpsw_slave_index(priv);
1856
1857 if (priv->slaves[slave_no].phy)
1858 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1859 else
1860 return -EOPNOTSUPP;
1861}
1862
Mugunthan V N1923d6e2014-09-08 22:54:02 +05301863static void cpsw_get_pauseparam(struct net_device *ndev,
1864 struct ethtool_pauseparam *pause)
1865{
1866 struct cpsw_priv *priv = netdev_priv(ndev);
1867
1868 pause->autoneg = AUTONEG_DISABLE;
1869 pause->rx_pause = priv->rx_pause ? true : false;
1870 pause->tx_pause = priv->tx_pause ? true : false;
1871}
1872
1873static int cpsw_set_pauseparam(struct net_device *ndev,
1874 struct ethtool_pauseparam *pause)
1875{
1876 struct cpsw_priv *priv = netdev_priv(ndev);
1877 bool link;
1878
1879 priv->rx_pause = pause->rx_pause ? true : false;
1880 priv->tx_pause = pause->tx_pause ? true : false;
1881
1882 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1883
1884 return 0;
1885}
1886
Mugunthan V Ndf828592012-03-18 20:17:54 +00001887static const struct ethtool_ops cpsw_ethtool_ops = {
1888 .get_drvinfo = cpsw_get_drvinfo,
1889 .get_msglevel = cpsw_get_msglevel,
1890 .set_msglevel = cpsw_set_msglevel,
1891 .get_link = ethtool_op_get_link,
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001892 .get_ts_info = cpsw_get_ts_info,
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +00001893 .get_settings = cpsw_get_settings,
1894 .set_settings = cpsw_set_settings,
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001895 .get_coalesce = cpsw_get_coalesce,
1896 .set_coalesce = cpsw_set_coalesce,
Mugunthan V Nd9718542013-07-23 15:38:17 +05301897 .get_sset_count = cpsw_get_sset_count,
1898 .get_strings = cpsw_get_strings,
1899 .get_ethtool_stats = cpsw_get_ethtool_stats,
Mugunthan V N1923d6e2014-09-08 22:54:02 +05301900 .get_pauseparam = cpsw_get_pauseparam,
1901 .set_pauseparam = cpsw_set_pauseparam,
Matus Ujhelyid8a64422013-08-20 07:59:38 +02001902 .get_wol = cpsw_get_wol,
1903 .set_wol = cpsw_set_wol,
Mugunthan V N52c4f0e2014-07-22 23:25:07 +05301904 .get_regs_len = cpsw_get_regs_len,
1905 .get_regs = cpsw_get_regs,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001906};
1907
Richard Cochran549985e2012-11-14 09:07:56 +00001908static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1909 u32 slave_reg_ofs, u32 sliver_reg_ofs)
Mugunthan V Ndf828592012-03-18 20:17:54 +00001910{
1911 void __iomem *regs = priv->regs;
1912 int slave_num = slave->slave_num;
1913 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1914
1915 slave->data = data;
Richard Cochran549985e2012-11-14 09:07:56 +00001916 slave->regs = regs + slave_reg_ofs;
1917 slave->sliver = regs + sliver_reg_ofs;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001918 slave->port_vlan = data->dual_emac_res_vlan;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001919}
1920
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001921static int cpsw_probe_dt(struct cpsw_platform_data *data,
1922 struct platform_device *pdev)
1923{
1924 struct device_node *node = pdev->dev.of_node;
1925 struct device_node *slave_node;
1926 int i = 0, ret;
1927 u32 prop;
1928
1929 if (!node)
1930 return -EINVAL;
1931
1932 if (of_property_read_u32(node, "slaves", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301933 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001934 return -EINVAL;
1935 }
1936 data->slaves = prop;
1937
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001938 if (of_property_read_u32(node, "active_slave", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301939 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301940 return -EINVAL;
Richard Cochran78ca0b22012-10-29 08:45:18 +00001941 }
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001942 data->active_slave = prop;
Richard Cochran78ca0b22012-10-29 08:45:18 +00001943
Richard Cochran00ab94e2012-10-29 08:45:19 +00001944 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301945 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301946 return -EINVAL;
Richard Cochran00ab94e2012-10-29 08:45:19 +00001947 }
1948 data->cpts_clock_mult = prop;
1949
1950 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301951 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301952 return -EINVAL;
Richard Cochran00ab94e2012-10-29 08:45:19 +00001953 }
1954 data->cpts_clock_shift = prop;
1955
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301956 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1957 * sizeof(struct cpsw_slave_data),
1958 GFP_KERNEL);
Joe Perchesb2adaca2013-02-03 17:43:58 +00001959 if (!data->slave_data)
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301960 return -ENOMEM;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001961
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001962 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301963 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301964 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001965 }
1966 data->channels = prop;
1967
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001968 if (of_property_read_u32(node, "ale_entries", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301969 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301970 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001971 }
1972 data->ale_entries = prop;
1973
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001974 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301975 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301976 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001977 }
1978 data->bd_ram_size = prop;
1979
1980 if (of_property_read_u32(node, "rx_descs", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301981 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301982 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001983 }
1984 data->rx_descs = prop;
1985
1986 if (of_property_read_u32(node, "mac_control", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301987 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301988 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001989 }
1990 data->mac_control = prop;
1991
Markus Pargmann281abd92013-10-04 14:44:40 +02001992 if (of_property_read_bool(node, "dual_emac"))
1993 data->dual_emac = 1;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001994
Vaibhav Hiremath1fb19aa2012-11-14 09:07:55 +00001995 /*
1996 * Populate all the child nodes here...
1997 */
1998 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1999 /* We do not want to force this, as in some cases may not have child */
2000 if (ret)
George Cherian88c99ff2014-05-12 10:21:19 +05302001 dev_warn(&pdev->dev, "Doesn't have any child node\n");
Vaibhav Hiremath1fb19aa2012-11-14 09:07:55 +00002002
Markus Pargmannf468b102013-10-04 14:44:39 +02002003 for_each_child_of_node(node, slave_node) {
Richard Cochran549985e2012-11-14 09:07:56 +00002004 struct cpsw_slave_data *slave_data = data->slave_data + i;
2005 const void *mac_addr = NULL;
2006 u32 phyid;
2007 int lenp;
2008 const __be32 *parp;
2009 struct device_node *mdio_node;
2010 struct platform_device *mdio;
2011
Markus Pargmannf468b102013-10-04 14:44:39 +02002012 /* This is no slave child node, continue */
2013 if (strcmp(slave_node->name, "slave"))
2014 continue;
2015
Richard Cochran549985e2012-11-14 09:07:56 +00002016 parp = of_get_property(slave_node, "phy_id", &lenp);
Lothar Waßmannce162942013-03-21 02:20:11 +00002017 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
George Cherian88c99ff2014-05-12 10:21:19 +05302018 dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
Mugunthan V N47276fc2014-10-24 18:51:33 +05302019 goto no_phy_slave;
Richard Cochran549985e2012-11-14 09:07:56 +00002020 }
2021 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2022 phyid = be32_to_cpup(parp+1);
2023 mdio = of_find_device_by_node(mdio_node);
Johan Hovold60e71ab2014-05-08 10:09:24 +02002024 of_node_put(mdio_node);
Johan Hovold6954cc12014-05-08 10:09:23 +02002025 if (!mdio) {
Markus Pargmann56fdb2e2014-09-29 08:53:16 +02002026 dev_err(&pdev->dev, "Missing mdio platform device\n");
Johan Hovold6954cc12014-05-08 10:09:23 +02002027 return -EINVAL;
Stefan Roesef8d56d82014-01-29 11:32:37 +01002028 }
Johan Hovold59993f482014-05-08 10:09:22 +02002029 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2030 PHY_ID_FMT, mdio->name, phyid);
Richard Cochran549985e2012-11-14 09:07:56 +00002031
Mugunthan V N47276fc2014-10-24 18:51:33 +05302032 slave_data->phy_if = of_get_phy_mode(slave_node);
2033 if (slave_data->phy_if < 0) {
2034 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2035 i);
2036 return slave_data->phy_if;
2037 }
2038
2039no_phy_slave:
Richard Cochran549985e2012-11-14 09:07:56 +00002040 mac_addr = of_get_mac_address(slave_node);
Markus Pargmann0ba517b2014-09-29 08:53:17 +02002041 if (mac_addr) {
Richard Cochran549985e2012-11-14 09:07:56 +00002042 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
Markus Pargmann0ba517b2014-09-29 08:53:17 +02002043 } else {
2044 if (of_machine_is_compatible("ti,am33xx")) {
Tony Lindgrene5a49c12015-01-28 11:33:04 -08002045 ret = cpsw_am33xx_cm_get_macid(&pdev->dev,
2046 0x630, i,
Markus Pargmann0ba517b2014-09-29 08:53:17 +02002047 slave_data->mac_addr);
2048 if (ret)
2049 return ret;
2050 }
2051 }
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002052 if (data->dual_emac) {
Mugunthan V N91c41662013-04-15 07:31:28 +00002053 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002054 &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05302055 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002056 slave_data->dual_emac_res_vlan = i+1;
George Cherian88c99ff2014-05-12 10:21:19 +05302057 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2058 slave_data->dual_emac_res_vlan, i);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002059 } else {
2060 slave_data->dual_emac_res_vlan = prop;
2061 }
2062 }
2063
Richard Cochran549985e2012-11-14 09:07:56 +00002064 i++;
Mugunthan V N3a27bfa2013-12-02 12:53:39 +05302065 if (i == data->slaves)
2066 break;
Richard Cochran549985e2012-11-14 09:07:56 +00002067 }
2068
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002069 return 0;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002070}
2071
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002072static int cpsw_probe_dual_emac(struct platform_device *pdev,
2073 struct cpsw_priv *priv)
2074{
2075 struct cpsw_platform_data *data = &priv->data;
2076 struct net_device *ndev;
2077 struct cpsw_priv *priv_sl2;
2078 int ret = 0, i;
2079
2080 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2081 if (!ndev) {
George Cherian88c99ff2014-05-12 10:21:19 +05302082 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002083 return -ENOMEM;
2084 }
2085
2086 priv_sl2 = netdev_priv(ndev);
2087 spin_lock_init(&priv_sl2->lock);
2088 priv_sl2->data = *data;
2089 priv_sl2->pdev = pdev;
2090 priv_sl2->ndev = ndev;
2091 priv_sl2->dev = &ndev->dev;
2092 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2093 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2094
2095 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2096 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2097 ETH_ALEN);
George Cherian88c99ff2014-05-12 10:21:19 +05302098 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002099 } else {
2100 random_ether_addr(priv_sl2->mac_addr);
George Cherian88c99ff2014-05-12 10:21:19 +05302101 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002102 }
2103 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2104
2105 priv_sl2->slaves = priv->slaves;
2106 priv_sl2->clk = priv->clk;
2107
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00002108 priv_sl2->coal_intvl = 0;
2109 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2110
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002111 priv_sl2->regs = priv->regs;
2112 priv_sl2->host_port = priv->host_port;
2113 priv_sl2->host_port_regs = priv->host_port_regs;
2114 priv_sl2->wr_regs = priv->wr_regs;
Mugunthan V Nd9718542013-07-23 15:38:17 +05302115 priv_sl2->hw_stats = priv->hw_stats;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002116 priv_sl2->dma = priv->dma;
2117 priv_sl2->txch = priv->txch;
2118 priv_sl2->rxch = priv->rxch;
2119 priv_sl2->ale = priv->ale;
2120 priv_sl2->emac_port = 1;
2121 priv->slaves[1].ndev = ndev;
2122 priv_sl2->cpts = priv->cpts;
2123 priv_sl2->version = priv->version;
2124
2125 for (i = 0; i < priv->num_irqs; i++) {
2126 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2127 priv_sl2->num_irqs = priv->num_irqs;
2128 }
Patrick McHardyf6469682013-04-19 02:04:27 +00002129 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002130
2131 ndev->netdev_ops = &cpsw_netdev_ops;
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00002132 ndev->ethtool_ops = &cpsw_ethtool_ops;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002133 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2134
2135 /* register the network device */
2136 SET_NETDEV_DEV(ndev, &pdev->dev);
2137 ret = register_netdev(ndev);
2138 if (ret) {
George Cherian88c99ff2014-05-12 10:21:19 +05302139 dev_err(&pdev->dev, "cpsw: error registering net device\n");
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002140 free_netdev(ndev);
2141 ret = -ENODEV;
2142 }
2143
2144 return ret;
2145}
2146
Bill Pemberton663e12e2012-12-03 09:23:45 -05002147static int cpsw_probe(struct platform_device *pdev)
Mugunthan V Ndf828592012-03-18 20:17:54 +00002148{
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002149 struct cpsw_platform_data *data;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002150 struct net_device *ndev;
2151 struct cpsw_priv *priv;
2152 struct cpdma_params dma_params;
2153 struct cpsw_ale_params ale_params;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302154 void __iomem *ss_regs;
2155 struct resource *res, *ss_res;
Richard Cochran549985e2012-11-14 09:07:56 +00002156 u32 slave_offset, sliver_offset, slave_size;
Felipe Balbi5087b912015-01-16 10:11:11 -06002157 int ret = 0, i;
2158 int irq;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002159
Mugunthan V Ndf828592012-03-18 20:17:54 +00002160 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2161 if (!ndev) {
George Cherian88c99ff2014-05-12 10:21:19 +05302162 dev_err(&pdev->dev, "error allocating net_device\n");
Mugunthan V Ndf828592012-03-18 20:17:54 +00002163 return -ENOMEM;
2164 }
2165
2166 platform_set_drvdata(pdev, ndev);
2167 priv = netdev_priv(ndev);
2168 spin_lock_init(&priv->lock);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002169 priv->pdev = pdev;
2170 priv->ndev = ndev;
2171 priv->dev = &ndev->dev;
2172 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2173 priv->rx_packet_max = max(rx_packet_max, 128);
Mugunthan V N9232b162013-02-11 09:52:19 +00002174 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
Mugunthan V N7dcf3132013-04-29 23:27:28 +00002175 priv->irq_enabled = true;
Sebastian Siewiorab8e99d2013-06-17 19:31:52 +02002176 if (!priv->cpts) {
George Cherian88c99ff2014-05-12 10:21:19 +05302177 dev_err(&pdev->dev, "error allocating cpts\n");
Markus Pargmann4d507df2014-09-29 08:53:14 +02002178 ret = -ENOMEM;
Mugunthan V N9232b162013-02-11 09:52:19 +00002179 goto clean_ndev_ret;
2180 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00002181
Vaibhav Hiremath1fb19aa2012-11-14 09:07:55 +00002182 /*
2183 * This may be required here for child devices.
2184 */
2185 pm_runtime_enable(&pdev->dev);
2186
Mugunthan V N739683b2013-06-06 23:45:14 +05302187 /* Select default pin state */
2188 pinctrl_pm_select_default_state(&pdev->dev);
2189
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002190 if (cpsw_probe_dt(&priv->data, pdev)) {
George Cherian88c99ff2014-05-12 10:21:19 +05302191 dev_err(&pdev->dev, "cpsw: platform data missing\n");
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002192 ret = -ENODEV;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302193 goto clean_runtime_disable_ret;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002194 }
2195 data = &priv->data;
2196
Mugunthan V Ndf828592012-03-18 20:17:54 +00002197 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2198 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
George Cherian88c99ff2014-05-12 10:21:19 +05302199 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002200 } else {
Joe Perches7efd26d2012-07-12 19:33:06 +00002201 eth_random_addr(priv->mac_addr);
George Cherian88c99ff2014-05-12 10:21:19 +05302202 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002203 }
2204
2205 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2206
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302207 priv->slaves = devm_kzalloc(&pdev->dev,
2208 sizeof(struct cpsw_slave) * data->slaves,
2209 GFP_KERNEL);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002210 if (!priv->slaves) {
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302211 ret = -ENOMEM;
2212 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002213 }
2214 for (i = 0; i < data->slaves; i++)
2215 priv->slaves[i].slave_num = i;
2216
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002217 priv->slaves[0].ndev = ndev;
2218 priv->emac_port = 0;
2219
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302220 priv->clk = devm_clk_get(&pdev->dev, "fck");
Mugunthan V Ndf828592012-03-18 20:17:54 +00002221 if (IS_ERR(priv->clk)) {
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302222 dev_err(priv->dev, "fck is not found\n");
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002223 ret = -ENODEV;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302224 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002225 }
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00002226 priv->coal_intvl = 0;
2227 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002228
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302229 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2230 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2231 if (IS_ERR(ss_regs)) {
2232 ret = PTR_ERR(ss_regs);
2233 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002234 }
Richard Cochran549985e2012-11-14 09:07:56 +00002235 priv->regs = ss_regs;
Richard Cochran549985e2012-11-14 09:07:56 +00002236 priv->host_port = HOST_PORT_NUM;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002237
Mugunthan V Nf280e892013-12-11 22:09:05 -06002238 /* Need to enable clocks with runtime PM api to access module
2239 * registers
2240 */
2241 pm_runtime_get_sync(&pdev->dev);
2242 priv->version = readl(&priv->regs->id_ver);
2243 pm_runtime_put_sync(&pdev->dev);
2244
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302245 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2246 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2247 if (IS_ERR(priv->wr_regs)) {
2248 ret = PTR_ERR(priv->wr_regs);
2249 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002250 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00002251
2252 memset(&dma_params, 0, sizeof(dma_params));
Richard Cochran549985e2012-11-14 09:07:56 +00002253 memset(&ale_params, 0, sizeof(ale_params));
2254
2255 switch (priv->version) {
2256 case CPSW_VERSION_1:
2257 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
Mugunthan V Nd9718542013-07-23 15:38:17 +05302258 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2259 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
Richard Cochran549985e2012-11-14 09:07:56 +00002260 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2261 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2262 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2263 slave_offset = CPSW1_SLAVE_OFFSET;
2264 slave_size = CPSW1_SLAVE_SIZE;
2265 sliver_offset = CPSW1_SLIVER_OFFSET;
2266 dma_params.desc_mem_phys = 0;
2267 break;
2268 case CPSW_VERSION_2:
Mugunthan V Nc193f362013-08-05 17:30:05 +05302269 case CPSW_VERSION_3:
Mugunthan V N926489b2013-08-12 17:11:15 +05302270 case CPSW_VERSION_4:
Richard Cochran549985e2012-11-14 09:07:56 +00002271 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
Mugunthan V Nd9718542013-07-23 15:38:17 +05302272 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2273 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
Richard Cochran549985e2012-11-14 09:07:56 +00002274 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2275 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2276 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2277 slave_offset = CPSW2_SLAVE_OFFSET;
2278 slave_size = CPSW2_SLAVE_SIZE;
2279 sliver_offset = CPSW2_SLIVER_OFFSET;
2280 dma_params.desc_mem_phys =
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302281 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
Richard Cochran549985e2012-11-14 09:07:56 +00002282 break;
2283 default:
2284 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2285 ret = -ENODEV;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302286 goto clean_runtime_disable_ret;
Richard Cochran549985e2012-11-14 09:07:56 +00002287 }
2288 for (i = 0; i < priv->data.slaves; i++) {
2289 struct cpsw_slave *slave = &priv->slaves[i];
2290 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2291 slave_offset += slave_size;
2292 sliver_offset += SLIVER_SIZE;
2293 }
2294
Mugunthan V Ndf828592012-03-18 20:17:54 +00002295 dma_params.dev = &pdev->dev;
Richard Cochran549985e2012-11-14 09:07:56 +00002296 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2297 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2298 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2299 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2300 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002301
2302 dma_params.num_chan = data->channels;
2303 dma_params.has_soft_reset = true;
2304 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2305 dma_params.desc_mem_size = data->bd_ram_size;
2306 dma_params.desc_align = 16;
2307 dma_params.has_ext_regs = true;
Richard Cochran549985e2012-11-14 09:07:56 +00002308 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002309
2310 priv->dma = cpdma_ctlr_create(&dma_params);
2311 if (!priv->dma) {
2312 dev_err(priv->dev, "error initializing dma\n");
2313 ret = -ENOMEM;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302314 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002315 }
2316
2317 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2318 cpsw_tx_handler);
2319 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2320 cpsw_rx_handler);
2321
2322 if (WARN_ON(!priv->txch || !priv->rxch)) {
2323 dev_err(priv->dev, "error initializing dma channels\n");
2324 ret = -ENOMEM;
2325 goto clean_dma_ret;
2326 }
2327
Mugunthan V Ndf828592012-03-18 20:17:54 +00002328 ale_params.dev = &ndev->dev;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002329 ale_params.ale_ageout = ale_ageout;
2330 ale_params.ale_entries = data->ale_entries;
2331 ale_params.ale_ports = data->slaves;
2332
2333 priv->ale = cpsw_ale_create(&ale_params);
2334 if (!priv->ale) {
2335 dev_err(priv->dev, "error initializing ale engine\n");
2336 ret = -ENODEV;
2337 goto clean_dma_ret;
2338 }
2339
Felipe Balbic03abd82015-01-16 10:11:12 -06002340 ndev->irq = platform_get_irq(pdev, 1);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002341 if (ndev->irq < 0) {
2342 dev_err(priv->dev, "error getting irq resource\n");
2343 ret = -ENOENT;
2344 goto clean_ale_ret;
2345 }
2346
Felipe Balbic03abd82015-01-16 10:11:12 -06002347 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2348 * MISC IRQs which are always kept disabled with this driver so
2349 * we will not request them.
2350 *
2351 * If anyone wants to implement support for those, make sure to
2352 * first request and append them to irqs_table array.
2353 */
Daniel Mackc2b32e52014-09-04 09:00:23 +02002354
Felipe Balbic03abd82015-01-16 10:11:12 -06002355 /* RX IRQ */
Felipe Balbi5087b912015-01-16 10:11:11 -06002356 irq = platform_get_irq(pdev, 1);
2357 if (irq < 0)
2358 goto clean_ale_ret;
2359
Felipe Balbic03abd82015-01-16 10:11:12 -06002360 priv->irqs_table[0] = irq;
2361 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
Felipe Balbi5087b912015-01-16 10:11:11 -06002362 0, dev_name(&pdev->dev), priv);
2363 if (ret < 0) {
2364 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2365 goto clean_ale_ret;
2366 }
2367
Felipe Balbic03abd82015-01-16 10:11:12 -06002368 /* TX IRQ */
Felipe Balbi5087b912015-01-16 10:11:11 -06002369 irq = platform_get_irq(pdev, 2);
2370 if (irq < 0)
2371 goto clean_ale_ret;
2372
Felipe Balbic03abd82015-01-16 10:11:12 -06002373 priv->irqs_table[1] = irq;
2374 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
Felipe Balbi5087b912015-01-16 10:11:11 -06002375 0, dev_name(&pdev->dev), priv);
2376 if (ret < 0) {
2377 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2378 goto clean_ale_ret;
2379 }
Felipe Balbic03abd82015-01-16 10:11:12 -06002380 priv->num_irqs = 2;
Daniel Mackc2b32e52014-09-04 09:00:23 +02002381
Patrick McHardyf6469682013-04-19 02:04:27 +00002382 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002383
2384 ndev->netdev_ops = &cpsw_netdev_ops;
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00002385 ndev->ethtool_ops = &cpsw_ethtool_ops;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002386 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2387
2388 /* register the network device */
2389 SET_NETDEV_DEV(ndev, &pdev->dev);
2390 ret = register_netdev(ndev);
2391 if (ret) {
2392 dev_err(priv->dev, "error registering net device\n");
2393 ret = -ENODEV;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302394 goto clean_ale_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002395 }
2396
Olof Johansson1a3b5052013-12-11 15:58:07 -08002397 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2398 &ss_res->start, ndev->irq);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002399
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002400 if (priv->data.dual_emac) {
2401 ret = cpsw_probe_dual_emac(pdev, priv);
2402 if (ret) {
2403 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302404 goto clean_ale_ret;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002405 }
2406 }
2407
Mugunthan V Ndf828592012-03-18 20:17:54 +00002408 return 0;
2409
Mugunthan V Ndf828592012-03-18 20:17:54 +00002410clean_ale_ret:
2411 cpsw_ale_destroy(priv->ale);
2412clean_dma_ret:
2413 cpdma_chan_destroy(priv->txch);
2414 cpdma_chan_destroy(priv->rxch);
2415 cpdma_ctlr_destroy(priv->dma);
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302416clean_runtime_disable_ret:
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002417 pm_runtime_disable(&pdev->dev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002418clean_ndev_ret:
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002419 free_netdev(priv->ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002420 return ret;
2421}
2422
Mugunthan V N030b16a2014-10-13 22:21:07 +05302423static int cpsw_remove_child_device(struct device *dev, void *c)
2424{
2425 struct platform_device *pdev = to_platform_device(dev);
2426
2427 of_device_unregister(pdev);
2428
2429 return 0;
2430}
2431
Bill Pemberton663e12e2012-12-03 09:23:45 -05002432static int cpsw_remove(struct platform_device *pdev)
Mugunthan V Ndf828592012-03-18 20:17:54 +00002433{
2434 struct net_device *ndev = platform_get_drvdata(pdev);
2435 struct cpsw_priv *priv = netdev_priv(ndev);
2436
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002437 if (priv->data.dual_emac)
2438 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2439 unregister_netdev(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002440
Mugunthan V Ndf828592012-03-18 20:17:54 +00002441 cpsw_ale_destroy(priv->ale);
2442 cpdma_chan_destroy(priv->txch);
2443 cpdma_chan_destroy(priv->rxch);
2444 cpdma_ctlr_destroy(priv->dma);
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002445 pm_runtime_disable(&pdev->dev);
Mugunthan V N030b16a2014-10-13 22:21:07 +05302446 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002447 if (priv->data.dual_emac)
2448 free_netdev(cpsw_get_slave_ndev(priv, 1));
Mugunthan V Ndf828592012-03-18 20:17:54 +00002449 free_netdev(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002450 return 0;
2451}
2452
Grygorii Strashko8963a502015-02-27 13:19:45 +02002453#ifdef CONFIG_PM_SLEEP
Mugunthan V Ndf828592012-03-18 20:17:54 +00002454static int cpsw_suspend(struct device *dev)
2455{
2456 struct platform_device *pdev = to_platform_device(dev);
2457 struct net_device *ndev = platform_get_drvdata(pdev);
Mugunthan V Nb90fc272013-06-21 19:15:09 +05302458 struct cpsw_priv *priv = netdev_priv(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002459
Mugunthan V N618073e2014-09-11 22:52:38 +05302460 if (priv->data.dual_emac) {
2461 int i;
Daniel Mack1e7a2e22013-11-15 08:29:16 +01002462
Mugunthan V N618073e2014-09-11 22:52:38 +05302463 for (i = 0; i < priv->data.slaves; i++) {
2464 if (netif_running(priv->slaves[i].ndev))
2465 cpsw_ndo_stop(priv->slaves[i].ndev);
2466 soft_reset_slave(priv->slaves + i);
2467 }
2468 } else {
2469 if (netif_running(ndev))
2470 cpsw_ndo_stop(ndev);
2471 for_each_slave(priv, soft_reset_slave);
2472 }
Daniel Mack1e7a2e22013-11-15 08:29:16 +01002473
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002474 pm_runtime_put_sync(&pdev->dev);
2475
Mugunthan V N739683b2013-06-06 23:45:14 +05302476 /* Select sleep pin state */
2477 pinctrl_pm_select_sleep_state(&pdev->dev);
2478
Mugunthan V Ndf828592012-03-18 20:17:54 +00002479 return 0;
2480}
2481
2482static int cpsw_resume(struct device *dev)
2483{
2484 struct platform_device *pdev = to_platform_device(dev);
2485 struct net_device *ndev = platform_get_drvdata(pdev);
Mugunthan V N618073e2014-09-11 22:52:38 +05302486 struct cpsw_priv *priv = netdev_priv(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002487
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002488 pm_runtime_get_sync(&pdev->dev);
Mugunthan V N739683b2013-06-06 23:45:14 +05302489
2490 /* Select default pin state */
2491 pinctrl_pm_select_default_state(&pdev->dev);
2492
Mugunthan V N618073e2014-09-11 22:52:38 +05302493 if (priv->data.dual_emac) {
2494 int i;
2495
2496 for (i = 0; i < priv->data.slaves; i++) {
2497 if (netif_running(priv->slaves[i].ndev))
2498 cpsw_ndo_open(priv->slaves[i].ndev);
2499 }
2500 } else {
2501 if (netif_running(ndev))
2502 cpsw_ndo_open(ndev);
2503 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00002504 return 0;
2505}
Grygorii Strashko8963a502015-02-27 13:19:45 +02002506#endif
Mugunthan V Ndf828592012-03-18 20:17:54 +00002507
Grygorii Strashko8963a502015-02-27 13:19:45 +02002508static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002509
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002510static const struct of_device_id cpsw_of_mtable[] = {
2511 { .compatible = "ti,cpsw", },
2512 { /* sentinel */ },
2513};
Sebastian Siewior4bc21d42013-04-24 08:48:22 +00002514MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002515
Mugunthan V Ndf828592012-03-18 20:17:54 +00002516static struct platform_driver cpsw_driver = {
2517 .driver = {
2518 .name = "cpsw",
Mugunthan V Ndf828592012-03-18 20:17:54 +00002519 .pm = &cpsw_pm_ops,
Sachin Kamat1e5c76d2013-09-30 09:55:12 +05302520 .of_match_table = cpsw_of_mtable,
Mugunthan V Ndf828592012-03-18 20:17:54 +00002521 },
2522 .probe = cpsw_probe,
Bill Pemberton663e12e2012-12-03 09:23:45 -05002523 .remove = cpsw_remove,
Mugunthan V Ndf828592012-03-18 20:17:54 +00002524};
2525
2526static int __init cpsw_init(void)
2527{
2528 return platform_driver_register(&cpsw_driver);
2529}
2530late_initcall(cpsw_init);
2531
2532static void __exit cpsw_exit(void)
2533{
2534 platform_driver_unregister(&cpsw_driver);
2535}
2536module_exit(cpsw_exit);
2537
2538MODULE_LICENSE("GPL");
2539MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2540MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2541MODULE_DESCRIPTION("TI CPSW Ethernet driver");