blob: 88e8a8d89b56dc6d86fd6957c3edf97e33bcd0a4 [file] [log] [blame]
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
Javier Martin9e15db72012-03-02 09:28:47 +01008 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
Sascha Hauer1f1846c2010-10-06 10:25:55 +02009 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
17#include <linux/init.h>
18#include <linux/types.h>
19#include <linux/mm.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
Javier Martin6bd08122012-03-22 14:54:01 +010026#include <linux/clk.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020027#include <linux/dmaengine.h>
Paul Gortmaker5c45ad72011-07-31 16:14:17 -040028#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020029
30#include <asm/irq.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020031#include <linux/platform_data/dma-imx.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020032#include <mach/hardware.h>
33
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000034#include "dmaengine.h"
Javier Martin9e15db72012-03-02 09:28:47 +010035#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
Javier Martin6bd08122012-03-22 14:54:01 +010036#define IMX_DMA_CHANNELS 16
37
Javier Martinf606ab82012-03-22 14:54:14 +010038#define IMX_DMA_2D_SLOTS 2
39#define IMX_DMA_2D_SLOT_A 0
40#define IMX_DMA_2D_SLOT_B 1
41
Javier Martin6bd08122012-03-22 14:54:01 +010042#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
43#define IMX_DMA_MEMSIZE_32 (0 << 4)
44#define IMX_DMA_MEMSIZE_8 (1 << 4)
45#define IMX_DMA_MEMSIZE_16 (2 << 4)
46#define IMX_DMA_TYPE_LINEAR (0 << 10)
47#define IMX_DMA_TYPE_2D (1 << 10)
48#define IMX_DMA_TYPE_FIFO (2 << 10)
49
50#define IMX_DMA_ERR_BURST (1 << 0)
51#define IMX_DMA_ERR_REQUEST (1 << 1)
52#define IMX_DMA_ERR_TRANSFER (1 << 2)
53#define IMX_DMA_ERR_BUFFER (1 << 3)
54#define IMX_DMA_ERR_TIMEOUT (1 << 4)
55
56#define DMA_DCR 0x00 /* Control Register */
57#define DMA_DISR 0x04 /* Interrupt status Register */
58#define DMA_DIMR 0x08 /* Interrupt mask Register */
59#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
60#define DMA_DRTOSR 0x10 /* Request timeout Register */
61#define DMA_DSESR 0x14 /* Transfer Error Status Register */
62#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
63#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
64#define DMA_WSRA 0x40 /* W-Size Register A */
65#define DMA_XSRA 0x44 /* X-Size Register A */
66#define DMA_YSRA 0x48 /* Y-Size Register A */
67#define DMA_WSRB 0x4c /* W-Size Register B */
68#define DMA_XSRB 0x50 /* X-Size Register B */
69#define DMA_YSRB 0x54 /* Y-Size Register B */
70#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
71#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
72#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
73#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
74#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
75#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
76#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
77#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
78#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
79
80#define DCR_DRST (1<<1)
81#define DCR_DEN (1<<0)
82#define DBTOCR_EN (1<<15)
83#define DBTOCR_CNT(x) ((x) & 0x7fff)
84#define CNTR_CNT(x) ((x) & 0xffffff)
85#define CCR_ACRPT (1<<14)
86#define CCR_DMOD_LINEAR (0x0 << 12)
87#define CCR_DMOD_2D (0x1 << 12)
88#define CCR_DMOD_FIFO (0x2 << 12)
89#define CCR_DMOD_EOBFIFO (0x3 << 12)
90#define CCR_SMOD_LINEAR (0x0 << 10)
91#define CCR_SMOD_2D (0x1 << 10)
92#define CCR_SMOD_FIFO (0x2 << 10)
93#define CCR_SMOD_EOBFIFO (0x3 << 10)
94#define CCR_MDIR_DEC (1<<9)
95#define CCR_MSEL_B (1<<8)
96#define CCR_DSIZ_32 (0x0 << 6)
97#define CCR_DSIZ_8 (0x1 << 6)
98#define CCR_DSIZ_16 (0x2 << 6)
99#define CCR_SSIZ_32 (0x0 << 4)
100#define CCR_SSIZ_8 (0x1 << 4)
101#define CCR_SSIZ_16 (0x2 << 4)
102#define CCR_REN (1<<3)
103#define CCR_RPT (1<<2)
104#define CCR_FRC (1<<1)
105#define CCR_CEN (1<<0)
106#define RTOR_EN (1<<15)
107#define RTOR_CLK (1<<14)
108#define RTOR_PSC (1<<13)
Javier Martin9e15db72012-03-02 09:28:47 +0100109
110enum imxdma_prep_type {
111 IMXDMA_DESC_MEMCPY,
112 IMXDMA_DESC_INTERLEAVED,
113 IMXDMA_DESC_SLAVE_SG,
114 IMXDMA_DESC_CYCLIC,
115};
116
Javier Martinf606ab82012-03-22 14:54:14 +0100117struct imx_dma_2d_config {
118 u16 xsr;
119 u16 ysr;
120 u16 wsr;
121 int count;
122};
123
Javier Martin9e15db72012-03-02 09:28:47 +0100124struct imxdma_desc {
125 struct list_head node;
126 struct dma_async_tx_descriptor desc;
127 enum dma_status status;
128 dma_addr_t src;
129 dma_addr_t dest;
130 size_t len;
Javier Martin2efc3442012-03-22 14:54:03 +0100131 enum dma_transfer_direction direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100132 enum imxdma_prep_type type;
133 /* For memcpy and interleaved */
134 unsigned int config_port;
135 unsigned int config_mem;
136 /* For interleaved transfers */
137 unsigned int x;
138 unsigned int y;
139 unsigned int w;
140 /* For slave sg and cyclic */
141 struct scatterlist *sg;
142 unsigned int sgcount;
143};
144
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200145struct imxdma_channel {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100146 int hw_chaining;
147 struct timer_list watchdog;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200148 struct imxdma_engine *imxdma;
149 unsigned int channel;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200150
Javier Martin9e15db72012-03-02 09:28:47 +0100151 struct tasklet_struct dma_tasklet;
152 struct list_head ld_free;
153 struct list_head ld_queue;
154 struct list_head ld_active;
155 int descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200156 enum dma_slave_buswidth word_size;
157 dma_addr_t per_address;
158 u32 watermark_level;
159 struct dma_chan chan;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200160 struct dma_async_tx_descriptor desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200161 enum dma_status status;
162 int dma_request;
163 struct scatterlist *sg_list;
Javier Martin359291a2012-03-22 14:54:06 +0100164 u32 ccr_from_device;
165 u32 ccr_to_device;
Javier Martinf606ab82012-03-22 14:54:14 +0100166 bool enabled_2d;
167 int slot_2d;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200168};
169
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200170struct imxdma_engine {
171 struct device *dev;
Sascha Hauer1e070a62011-01-12 13:14:37 +0100172 struct device_dma_parameters dma_parms;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200173 struct dma_device dma_device;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100174 void __iomem *base;
Fabio Estevama2367db2012-07-03 15:33:29 -0300175 struct clk *dma_ahb;
176 struct clk *dma_ipg;
Javier Martinf606ab82012-03-22 14:54:14 +0100177 spinlock_t lock;
178 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
Javier Martin6bd08122012-03-22 14:54:01 +0100179 struct imxdma_channel channel[IMX_DMA_CHANNELS];
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200180};
181
182static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
183{
184 return container_of(chan, struct imxdma_channel, chan);
185}
186
Javier Martin9e15db72012-03-02 09:28:47 +0100187static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200188{
Javier Martin9e15db72012-03-02 09:28:47 +0100189 struct imxdma_desc *desc;
190
191 if (!list_empty(&imxdmac->ld_active)) {
192 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
193 node);
194 if (desc->type == IMXDMA_DESC_CYCLIC)
195 return true;
196 }
197 return false;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200198}
199
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200200
Javier Martincd5cf9d2012-03-22 14:54:12 +0100201
202static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
203 unsigned offset)
Javier Martin6bd08122012-03-22 14:54:01 +0100204{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100205 __raw_writel(val, imxdma->base + offset);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200206}
207
Javier Martincd5cf9d2012-03-22 14:54:12 +0100208static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200209{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100210 return __raw_readl(imxdma->base + offset);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200211}
212
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100213static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200214{
Javier Martin6bd08122012-03-22 14:54:01 +0100215 if (cpu_is_mx27())
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100216 return imxdmac->hw_chaining;
Javier Martin6bd08122012-03-22 14:54:01 +0100217 else
218 return 0;
219}
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200220
Javier Martin6bd08122012-03-22 14:54:01 +0100221/*
222 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
223 */
Javier Martina6cbb2d2012-03-22 14:54:11 +0100224static inline int imxdma_sg_next(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100225{
Javier Martin2efc3442012-03-22 14:54:03 +0100226 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100227 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100228 struct scatterlist *sg = d->sg;
Javier Martin6bd08122012-03-22 14:54:01 +0100229 unsigned long now;
230
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200231 now = min(d->len, sg_dma_len(sg));
Javier Martin6b0e2f52012-03-22 14:54:09 +0100232 if (d->len != IMX_DMA_LENGTH_LOOP)
233 d->len -= now;
Javier Martin6bd08122012-03-22 14:54:01 +0100234
Javier Martin2efc3442012-03-22 14:54:03 +0100235 if (d->direction == DMA_DEV_TO_MEM)
Javier Martincd5cf9d2012-03-22 14:54:12 +0100236 imx_dmav1_writel(imxdma, sg->dma_address,
237 DMA_DAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100238 else
Javier Martincd5cf9d2012-03-22 14:54:12 +0100239 imx_dmav1_writel(imxdma, sg->dma_address,
240 DMA_SAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100241
Javier Martincd5cf9d2012-03-22 14:54:12 +0100242 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100243
Javier Martinf9b283a2012-03-22 14:54:13 +0100244 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
245 "size 0x%08x\n", __func__, imxdmac->channel,
Javier Martincd5cf9d2012-03-22 14:54:12 +0100246 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
247 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
248 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
Javier Martin6bd08122012-03-22 14:54:01 +0100249
250 return now;
251}
252
Javier Martin2efc3442012-03-22 14:54:03 +0100253static void imxdma_enable_hw(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100254{
Javier Martin2efc3442012-03-22 14:54:03 +0100255 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100256 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100257 int channel = imxdmac->channel;
258 unsigned long flags;
259
Javier Martinf9b283a2012-03-22 14:54:13 +0100260 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100261
Javier Martin6bd08122012-03-22 14:54:01 +0100262 local_irq_save(flags);
263
Javier Martincd5cf9d2012-03-22 14:54:12 +0100264 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
265 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
266 ~(1 << channel), DMA_DIMR);
267 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
268 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100269
270 if ((cpu_is_mx21() || cpu_is_mx27()) &&
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100271 d->sg && imxdma_hw_chain(imxdmac)) {
Javier Martin833bc032012-03-22 14:54:07 +0100272 d->sg = sg_next(d->sg);
273 if (d->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100274 u32 tmp;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100275 imxdma_sg_next(d);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100276 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
277 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
278 DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100279 }
280 }
Javier Martin6bd08122012-03-22 14:54:01 +0100281
282 local_irq_restore(flags);
283}
284
285static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
286{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100287 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100288 int channel = imxdmac->channel;
289 unsigned long flags;
290
Javier Martinf9b283a2012-03-22 14:54:13 +0100291 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100292
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100293 if (imxdma_hw_chain(imxdmac))
294 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100295
296 local_irq_save(flags);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100297 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
298 (1 << channel), DMA_DIMR);
299 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
300 ~CCR_CEN, DMA_CCR(channel));
301 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100302 local_irq_restore(flags);
303}
304
Javier Martin6bd08122012-03-22 14:54:01 +0100305static void imxdma_watchdog(unsigned long data)
306{
307 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100308 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100309 int channel = imxdmac->channel;
310
Javier Martincd5cf9d2012-03-22 14:54:12 +0100311 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100312
313 /* Tasklet watchdog error handler */
314 tasklet_schedule(&imxdmac->dma_tasklet);
Javier Martinf9b283a2012-03-22 14:54:13 +0100315 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
316 imxdmac->channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100317}
318
319static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
320{
321 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100322 unsigned int err_mask;
323 int i, disr;
324 int errcode;
325
Javier Martincd5cf9d2012-03-22 14:54:12 +0100326 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100327
Javier Martincd5cf9d2012-03-22 14:54:12 +0100328 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
329 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
330 imx_dmav1_readl(imxdma, DMA_DSESR) |
331 imx_dmav1_readl(imxdma, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100332
333 if (!err_mask)
334 return IRQ_HANDLED;
335
Javier Martincd5cf9d2012-03-22 14:54:12 +0100336 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100337
338 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
339 if (!(err_mask & (1 << i)))
340 continue;
Javier Martin6bd08122012-03-22 14:54:01 +0100341 errcode = 0;
342
Javier Martincd5cf9d2012-03-22 14:54:12 +0100343 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
344 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100345 errcode |= IMX_DMA_ERR_BURST;
346 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100347 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
348 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100349 errcode |= IMX_DMA_ERR_REQUEST;
350 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100351 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
352 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
Javier Martin6bd08122012-03-22 14:54:01 +0100353 errcode |= IMX_DMA_ERR_TRANSFER;
354 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100355 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
356 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100357 errcode |= IMX_DMA_ERR_BUFFER;
358 }
359 /* Tasklet error handler */
360 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
361
362 printk(KERN_WARNING
363 "DMA timeout on channel %d -%s%s%s%s\n", i,
364 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
365 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
366 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
367 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
368 }
369 return IRQ_HANDLED;
370}
371
372static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
373{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100374 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100375 int chno = imxdmac->channel;
Javier Martin2efc3442012-03-22 14:54:03 +0100376 struct imxdma_desc *desc;
Javier Martin6bd08122012-03-22 14:54:01 +0100377
Javier Martinf606ab82012-03-22 14:54:14 +0100378 spin_lock(&imxdma->lock);
Javier Martin833bc032012-03-22 14:54:07 +0100379 if (list_empty(&imxdmac->ld_active)) {
Javier Martinf606ab82012-03-22 14:54:14 +0100380 spin_unlock(&imxdma->lock);
Javier Martin833bc032012-03-22 14:54:07 +0100381 goto out;
382 }
383
384 desc = list_first_entry(&imxdmac->ld_active,
385 struct imxdma_desc,
386 node);
Javier Martinf606ab82012-03-22 14:54:14 +0100387 spin_unlock(&imxdma->lock);
Javier Martin833bc032012-03-22 14:54:07 +0100388
389 if (desc->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100390 u32 tmp;
Javier Martin833bc032012-03-22 14:54:07 +0100391 desc->sg = sg_next(desc->sg);
Javier Martin6bd08122012-03-22 14:54:01 +0100392
Javier Martin833bc032012-03-22 14:54:07 +0100393 if (desc->sg) {
Javier Martina6cbb2d2012-03-22 14:54:11 +0100394 imxdma_sg_next(desc);
Javier Martin6bd08122012-03-22 14:54:01 +0100395
Javier Martincd5cf9d2012-03-22 14:54:12 +0100396 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100397
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100398 if (imxdma_hw_chain(imxdmac)) {
Javier Martin6bd08122012-03-22 14:54:01 +0100399 /* FIXME: The timeout should probably be
400 * configurable
401 */
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100402 mod_timer(&imxdmac->watchdog,
Javier Martin6bd08122012-03-22 14:54:01 +0100403 jiffies + msecs_to_jiffies(500));
404
405 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100406 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100407 } else {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100408 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
409 DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100410 tmp |= CCR_CEN;
411 }
412
Javier Martincd5cf9d2012-03-22 14:54:12 +0100413 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100414
415 if (imxdma_chan_is_doing_cyclic(imxdmac))
416 /* Tasklet progression */
417 tasklet_schedule(&imxdmac->dma_tasklet);
418
419 return;
420 }
421
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100422 if (imxdma_hw_chain(imxdmac)) {
423 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100424 return;
425 }
426 }
427
Javier Martin2efc3442012-03-22 14:54:03 +0100428out:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100429 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100430 /* Tasklet irq */
Javier Martin9e15db72012-03-02 09:28:47 +0100431 tasklet_schedule(&imxdmac->dma_tasklet);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200432}
433
Javier Martin6bd08122012-03-22 14:54:01 +0100434static irqreturn_t dma_irq_handler(int irq, void *dev_id)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200435{
Javier Martin6bd08122012-03-22 14:54:01 +0100436 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100437 int i, disr;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200438
Javier Martin6bd08122012-03-22 14:54:01 +0100439 if (cpu_is_mx21() || cpu_is_mx27())
440 imxdma_err_handler(irq, dev_id);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200441
Javier Martincd5cf9d2012-03-22 14:54:12 +0100442 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200443
Javier Martinf9b283a2012-03-22 14:54:13 +0100444 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
Javier Martin6bd08122012-03-22 14:54:01 +0100445
Javier Martincd5cf9d2012-03-22 14:54:12 +0100446 imx_dmav1_writel(imxdma, disr, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100447 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100448 if (disr & (1 << i))
Javier Martin6bd08122012-03-22 14:54:01 +0100449 dma_irq_handle_channel(&imxdma->channel[i]);
Javier Martin6bd08122012-03-22 14:54:01 +0100450 }
451
452 return IRQ_HANDLED;
Javier Martin9e15db72012-03-02 09:28:47 +0100453}
454
455static int imxdma_xfer_desc(struct imxdma_desc *d)
456{
457 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martin3b4b6df2012-03-22 14:54:04 +0100458 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martinf606ab82012-03-22 14:54:14 +0100459 unsigned long flags;
460 int slot = -1;
461 int i;
Javier Martin9e15db72012-03-02 09:28:47 +0100462
463 /* Configure and enable */
464 switch (d->type) {
Javier Martinf606ab82012-03-22 14:54:14 +0100465 case IMXDMA_DESC_INTERLEAVED:
466 /* Try to get a free 2D slot */
467 spin_lock_irqsave(&imxdma->lock, flags);
468 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
469 if ((imxdma->slots_2d[i].count > 0) &&
470 ((imxdma->slots_2d[i].xsr != d->x) ||
471 (imxdma->slots_2d[i].ysr != d->y) ||
472 (imxdma->slots_2d[i].wsr != d->w)))
473 continue;
474 slot = i;
475 break;
476 }
477 if (slot < 0)
478 return -EBUSY;
479
480 imxdma->slots_2d[slot].xsr = d->x;
481 imxdma->slots_2d[slot].ysr = d->y;
482 imxdma->slots_2d[slot].wsr = d->w;
483 imxdma->slots_2d[slot].count++;
484
485 imxdmac->slot_2d = slot;
486 imxdmac->enabled_2d = true;
487 spin_unlock_irqrestore(&imxdma->lock, flags);
488
489 if (slot == IMX_DMA_2D_SLOT_A) {
490 d->config_mem &= ~CCR_MSEL_B;
491 d->config_port &= ~CCR_MSEL_B;
492 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
493 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
494 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
495 } else {
496 d->config_mem |= CCR_MSEL_B;
497 d->config_port |= CCR_MSEL_B;
498 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
499 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
500 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
501 }
502 /*
503 * We fall-through here intentionally, since a 2D transfer is
504 * similar to MEMCPY just adding the 2D slot configuration.
505 */
Javier Martin9e15db72012-03-02 09:28:47 +0100506 case IMXDMA_DESC_MEMCPY:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100507 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
508 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
509 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
Javier Martin3b4b6df2012-03-22 14:54:04 +0100510 DMA_CCR(imxdmac->channel));
511
Javier Martincd5cf9d2012-03-22 14:54:12 +0100512 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
Javier Martin3b4b6df2012-03-22 14:54:04 +0100513
514 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
515 "dma_length=%d\n", __func__, imxdmac->channel,
516 d->dest, d->src, d->len);
517
518 break;
Javier Martin6bd08122012-03-22 14:54:01 +0100519 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
Javier Martin9e15db72012-03-02 09:28:47 +0100520 case IMXDMA_DESC_CYCLIC:
Javier Martin9e15db72012-03-02 09:28:47 +0100521 case IMXDMA_DESC_SLAVE_SG:
Javier Martin359291a2012-03-22 14:54:06 +0100522 if (d->direction == DMA_DEV_TO_MEM) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100523 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100524 DMA_SAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100525 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
Javier Martin359291a2012-03-22 14:54:06 +0100526 DMA_CCR(imxdmac->channel));
527
528 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
529 "total length=%d dev_addr=0x%08x (dev2mem)\n",
530 __func__, imxdmac->channel, d->sg, d->sgcount,
531 d->len, imxdmac->per_address);
532 } else if (d->direction == DMA_MEM_TO_DEV) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100533 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100534 DMA_DAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100535 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
Javier Martin359291a2012-03-22 14:54:06 +0100536 DMA_CCR(imxdmac->channel));
537
538 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
539 "total length=%d dev_addr=0x%08x (mem2dev)\n",
540 __func__, imxdmac->channel, d->sg, d->sgcount,
541 d->len, imxdmac->per_address);
542 } else {
543 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
544 __func__, imxdmac->channel);
545 return -EINVAL;
546 }
547
Javier Martina6cbb2d2012-03-22 14:54:11 +0100548 imxdma_sg_next(d);
Javier Martin359291a2012-03-22 14:54:06 +0100549
Javier Martin9e15db72012-03-02 09:28:47 +0100550 break;
551 default:
552 return -EINVAL;
553 }
Javier Martin2efc3442012-03-22 14:54:03 +0100554 imxdma_enable_hw(d);
Javier Martin9e15db72012-03-02 09:28:47 +0100555 return 0;
556}
557
558static void imxdma_tasklet(unsigned long data)
559{
560 struct imxdma_channel *imxdmac = (void *)data;
561 struct imxdma_engine *imxdma = imxdmac->imxdma;
562 struct imxdma_desc *desc;
563
Javier Martinf606ab82012-03-22 14:54:14 +0100564 spin_lock(&imxdma->lock);
Javier Martin9e15db72012-03-02 09:28:47 +0100565
566 if (list_empty(&imxdmac->ld_active)) {
567 /* Someone might have called terminate all */
568 goto out;
569 }
570 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
571
572 if (desc->desc.callback)
573 desc->desc.callback(desc->desc.callback_param);
574
Masanari Iidad73111c2012-08-04 23:37:53 +0900575 /* If we are dealing with a cyclic descriptor, keep it on ld_active
576 * and dont mark the descriptor as complete.
Vinod Koul60f29512012-04-20 15:28:07 +0530577 * Only in non-cyclic cases it would be marked as complete
578 */
Javier Martin9e15db72012-03-02 09:28:47 +0100579 if (imxdma_chan_is_doing_cyclic(imxdmac))
580 goto out;
Vinod Koul60f29512012-04-20 15:28:07 +0530581 else
582 dma_cookie_complete(&desc->desc);
Javier Martin9e15db72012-03-02 09:28:47 +0100583
Javier Martinf606ab82012-03-22 14:54:14 +0100584 /* Free 2D slot if it was an interleaved transfer */
585 if (imxdmac->enabled_2d) {
586 imxdma->slots_2d[imxdmac->slot_2d].count--;
587 imxdmac->enabled_2d = false;
588 }
589
Javier Martin9e15db72012-03-02 09:28:47 +0100590 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
591
592 if (!list_empty(&imxdmac->ld_queue)) {
593 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
594 node);
595 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
596 if (imxdma_xfer_desc(desc) < 0)
597 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
598 __func__, imxdmac->channel);
599 }
600out:
Javier Martinf606ab82012-03-22 14:54:14 +0100601 spin_unlock(&imxdma->lock);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200602}
603
604static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
605 unsigned long arg)
606{
607 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
608 struct dma_slave_config *dmaengine_cfg = (void *)arg;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100609 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100610 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200611 unsigned int mode = 0;
612
613 switch (cmd) {
614 case DMA_TERMINATE_ALL:
Javier Martin6bd08122012-03-22 14:54:01 +0100615 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100616
Javier Martinf606ab82012-03-22 14:54:14 +0100617 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100618 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
619 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
Javier Martinf606ab82012-03-22 14:54:14 +0100620 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200621 return 0;
622 case DMA_SLAVE_CONFIG:
Vinod Kouldb8196d2011-10-13 22:34:23 +0530623 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200624 imxdmac->per_address = dmaengine_cfg->src_addr;
625 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
626 imxdmac->word_size = dmaengine_cfg->src_addr_width;
627 } else {
628 imxdmac->per_address = dmaengine_cfg->dst_addr;
629 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
630 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
631 }
632
633 switch (imxdmac->word_size) {
634 case DMA_SLAVE_BUSWIDTH_1_BYTE:
635 mode = IMX_DMA_MEMSIZE_8;
636 break;
637 case DMA_SLAVE_BUSWIDTH_2_BYTES:
638 mode = IMX_DMA_MEMSIZE_16;
639 break;
640 default:
641 case DMA_SLAVE_BUSWIDTH_4_BYTES:
642 mode = IMX_DMA_MEMSIZE_32;
643 break;
644 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200645
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100646 imxdmac->hw_chaining = 1;
647 if (!imxdma_hw_chain(imxdmac))
Javier Martinbdc0c752012-03-22 14:54:05 +0100648 return -EINVAL;
Javier Martin359291a2012-03-22 14:54:06 +0100649 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
Javier Martinbdc0c752012-03-22 14:54:05 +0100650 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
651 CCR_REN;
Javier Martin359291a2012-03-22 14:54:06 +0100652 imxdmac->ccr_to_device =
Javier Martinbdc0c752012-03-22 14:54:05 +0100653 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
654 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100655 imx_dmav1_writel(imxdma, imxdmac->dma_request,
Javier Martinbdc0c752012-03-22 14:54:05 +0100656 DMA_RSSR(imxdmac->channel));
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200657
Javier Martin6bd08122012-03-22 14:54:01 +0100658 /* Set burst length */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100659 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
660 imxdmac->word_size, DMA_BLR(imxdmac->channel));
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200661
662 return 0;
663 default:
664 return -ENOSYS;
665 }
666
667 return -EINVAL;
668}
669
670static enum dma_status imxdma_tx_status(struct dma_chan *chan,
671 dma_cookie_t cookie,
672 struct dma_tx_state *txstate)
673{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000674 return dma_cookie_status(chan, cookie, txstate);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200675}
676
677static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
678{
679 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
Javier Martinf606ab82012-03-22 14:54:14 +0100680 struct imxdma_engine *imxdma = imxdmac->imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200681 dma_cookie_t cookie;
Javier Martin9e15db72012-03-02 09:28:47 +0100682 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200683
Javier Martinf606ab82012-03-22 14:54:14 +0100684 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin660cd0d2012-03-22 14:54:15 +0100685 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000686 cookie = dma_cookie_assign(tx);
Javier Martinf606ab82012-03-22 14:54:14 +0100687 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200688
689 return cookie;
690}
691
692static int imxdma_alloc_chan_resources(struct dma_chan *chan)
693{
694 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
695 struct imx_dma_data *data = chan->private;
696
Javier Martin6c05f092012-02-28 17:08:17 +0100697 if (data != NULL)
698 imxdmac->dma_request = data->dma_request;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200699
Javier Martin9e15db72012-03-02 09:28:47 +0100700 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
701 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200702
Javier Martin9e15db72012-03-02 09:28:47 +0100703 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
704 if (!desc)
705 break;
706 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
707 dma_async_tx_descriptor_init(&desc->desc, chan);
708 desc->desc.tx_submit = imxdma_tx_submit;
709 /* txd.flags will be overwritten in prep funcs */
710 desc->desc.flags = DMA_CTRL_ACK;
711 desc->status = DMA_SUCCESS;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200712
Javier Martin9e15db72012-03-02 09:28:47 +0100713 list_add_tail(&desc->node, &imxdmac->ld_free);
714 imxdmac->descs_allocated++;
715 }
716
717 if (!imxdmac->descs_allocated)
718 return -ENOMEM;
719
720 return imxdmac->descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200721}
722
723static void imxdma_free_chan_resources(struct dma_chan *chan)
724{
725 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martinf606ab82012-03-22 14:54:14 +0100726 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100727 struct imxdma_desc *desc, *_desc;
728 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200729
Javier Martinf606ab82012-03-22 14:54:14 +0100730 spin_lock_irqsave(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200731
Javier Martin6bd08122012-03-22 14:54:01 +0100732 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100733 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
734 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
735
Javier Martinf606ab82012-03-22 14:54:14 +0100736 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100737
738 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
739 kfree(desc);
740 imxdmac->descs_allocated--;
741 }
742 INIT_LIST_HEAD(&imxdmac->ld_free);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200743
744 if (imxdmac->sg_list) {
745 kfree(imxdmac->sg_list);
746 imxdmac->sg_list = NULL;
747 }
748}
749
750static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
751 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530752 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500753 unsigned long flags, void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200754{
755 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
756 struct scatterlist *sg;
Javier Martin9e15db72012-03-02 09:28:47 +0100757 int i, dma_length = 0;
758 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200759
Javier Martin9e15db72012-03-02 09:28:47 +0100760 if (list_empty(&imxdmac->ld_free) ||
761 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200762 return NULL;
763
Javier Martin9e15db72012-03-02 09:28:47 +0100764 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200765
766 for_each_sg(sgl, sg, sg_len, i) {
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200767 dma_length += sg_dma_len(sg);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200768 }
769
Sascha Hauerd07102a2011-01-12 14:13:23 +0100770 switch (imxdmac->word_size) {
771 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200772 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
Sascha Hauerd07102a2011-01-12 14:13:23 +0100773 return NULL;
774 break;
775 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200776 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
Sascha Hauerd07102a2011-01-12 14:13:23 +0100777 return NULL;
778 break;
779 case DMA_SLAVE_BUSWIDTH_1_BYTE:
780 break;
781 default:
782 return NULL;
783 }
784
Javier Martin9e15db72012-03-02 09:28:47 +0100785 desc->type = IMXDMA_DESC_SLAVE_SG;
786 desc->sg = sgl;
787 desc->sgcount = sg_len;
788 desc->len = dma_length;
Javier Martin2efc3442012-03-22 14:54:03 +0100789 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100790 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100791 desc->src = imxdmac->per_address;
792 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100793 desc->dest = imxdmac->per_address;
794 }
795 desc->desc.callback = NULL;
796 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200797
Javier Martin9e15db72012-03-02 09:28:47 +0100798 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200799}
800
801static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
802 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500803 size_t period_len, enum dma_transfer_direction direction,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +0300804 unsigned long flags, void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200805{
806 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
807 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100808 struct imxdma_desc *desc;
809 int i;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200810 unsigned int periods = buf_len / period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200811
812 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
813 __func__, imxdmac->channel, buf_len, period_len);
814
Javier Martin9e15db72012-03-02 09:28:47 +0100815 if (list_empty(&imxdmac->ld_free) ||
816 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200817 return NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200818
Javier Martin9e15db72012-03-02 09:28:47 +0100819 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200820
821 if (imxdmac->sg_list)
822 kfree(imxdmac->sg_list);
823
824 imxdmac->sg_list = kcalloc(periods + 1,
825 sizeof(struct scatterlist), GFP_KERNEL);
826 if (!imxdmac->sg_list)
827 return NULL;
828
829 sg_init_table(imxdmac->sg_list, periods);
830
831 for (i = 0; i < periods; i++) {
832 imxdmac->sg_list[i].page_link = 0;
833 imxdmac->sg_list[i].offset = 0;
834 imxdmac->sg_list[i].dma_address = dma_addr;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200835 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200836 dma_addr += period_len;
837 }
838
839 /* close the loop */
840 imxdmac->sg_list[periods].offset = 0;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200841 sg_dma_len(&imxdmac->sg_list[periods]) = 0;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200842 imxdmac->sg_list[periods].page_link =
843 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
844
Javier Martin9e15db72012-03-02 09:28:47 +0100845 desc->type = IMXDMA_DESC_CYCLIC;
846 desc->sg = imxdmac->sg_list;
847 desc->sgcount = periods;
848 desc->len = IMX_DMA_LENGTH_LOOP;
Javier Martin2efc3442012-03-22 14:54:03 +0100849 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100850 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100851 desc->src = imxdmac->per_address;
852 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100853 desc->dest = imxdmac->per_address;
854 }
855 desc->desc.callback = NULL;
856 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200857
Javier Martin9e15db72012-03-02 09:28:47 +0100858 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200859}
860
Javier Martin6c05f092012-02-28 17:08:17 +0100861static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
862 struct dma_chan *chan, dma_addr_t dest,
863 dma_addr_t src, size_t len, unsigned long flags)
864{
865 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
866 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100867 struct imxdma_desc *desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100868
869 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
870 __func__, imxdmac->channel, src, dest, len);
871
Javier Martin9e15db72012-03-02 09:28:47 +0100872 if (list_empty(&imxdmac->ld_free) ||
873 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200874 return NULL;
875
Javier Martin9e15db72012-03-02 09:28:47 +0100876 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Javier Martin6c05f092012-02-28 17:08:17 +0100877
Javier Martin9e15db72012-03-02 09:28:47 +0100878 desc->type = IMXDMA_DESC_MEMCPY;
879 desc->src = src;
880 desc->dest = dest;
881 desc->len = len;
Javier Martin2efc3442012-03-22 14:54:03 +0100882 desc->direction = DMA_MEM_TO_MEM;
Javier Martin9e15db72012-03-02 09:28:47 +0100883 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
884 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
885 desc->desc.callback = NULL;
886 desc->desc.callback_param = NULL;
887
888 return &desc->desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100889}
890
Javier Martinf606ab82012-03-22 14:54:14 +0100891static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
892 struct dma_chan *chan, struct dma_interleaved_template *xt,
893 unsigned long flags)
894{
895 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
896 struct imxdma_engine *imxdma = imxdmac->imxdma;
897 struct imxdma_desc *desc;
898
899 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
900 " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
901 imxdmac->channel, xt->src_start, xt->dst_start,
902 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
903 xt->numf, xt->frame_size);
904
905 if (list_empty(&imxdmac->ld_free) ||
906 imxdma_chan_is_doing_cyclic(imxdmac))
907 return NULL;
908
909 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
910 return NULL;
911
912 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
913
914 desc->type = IMXDMA_DESC_INTERLEAVED;
915 desc->src = xt->src_start;
916 desc->dest = xt->dst_start;
917 desc->x = xt->sgl[0].size;
918 desc->y = xt->numf;
919 desc->w = xt->sgl[0].icg + desc->x;
920 desc->len = desc->x * desc->y;
921 desc->direction = DMA_MEM_TO_MEM;
922 desc->config_port = IMX_DMA_MEMSIZE_32;
923 desc->config_mem = IMX_DMA_MEMSIZE_32;
924 if (xt->src_sgl)
925 desc->config_mem |= IMX_DMA_TYPE_2D;
926 if (xt->dst_sgl)
927 desc->config_port |= IMX_DMA_TYPE_2D;
928 desc->desc.callback = NULL;
929 desc->desc.callback_param = NULL;
930
931 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200932}
933
934static void imxdma_issue_pending(struct dma_chan *chan)
935{
Sascha Hauer5b316872012-01-09 10:32:49 +0100936 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martin9e15db72012-03-02 09:28:47 +0100937 struct imxdma_engine *imxdma = imxdmac->imxdma;
938 struct imxdma_desc *desc;
939 unsigned long flags;
Sascha Hauer5b316872012-01-09 10:32:49 +0100940
Javier Martinf606ab82012-03-22 14:54:14 +0100941 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100942 if (list_empty(&imxdmac->ld_active) &&
943 !list_empty(&imxdmac->ld_queue)) {
944 desc = list_first_entry(&imxdmac->ld_queue,
945 struct imxdma_desc, node);
946
947 if (imxdma_xfer_desc(desc) < 0) {
948 dev_warn(imxdma->dev,
949 "%s: channel: %d couldn't issue DMA xfer\n",
950 __func__, imxdmac->channel);
951 } else {
952 list_move_tail(imxdmac->ld_queue.next,
953 &imxdmac->ld_active);
954 }
955 }
Javier Martinf606ab82012-03-22 14:54:14 +0100956 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200957}
958
959static int __init imxdma_probe(struct platform_device *pdev)
Javier Martin6bd08122012-03-22 14:54:01 +0100960 {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200961 struct imxdma_engine *imxdma;
Shawn Guo73930eb2012-09-15 15:57:00 +0800962 struct resource *res;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200963 int ret, i;
Shawn Guo73930eb2012-09-15 15:57:00 +0800964 int irq, irq_err;
Javier Martin6bd08122012-03-22 14:54:01 +0100965
Shawn Guo04bbd8e2012-09-15 15:16:47 +0800966 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200967 if (!imxdma)
968 return -ENOMEM;
969
Shawn Guo73930eb2012-09-15 15:57:00 +0800970 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
971 imxdma->base = devm_request_and_ioremap(&pdev->dev, res);
972 if (!imxdma->base)
973 return -EADDRNOTAVAIL;
974
975 irq = platform_get_irq(pdev, 0);
976 if (irq < 0)
977 return irq;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100978
Fabio Estevama2367db2012-07-03 15:33:29 -0300979 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
Shawn Guo04bbd8e2012-09-15 15:16:47 +0800980 if (IS_ERR(imxdma->dma_ipg))
981 return PTR_ERR(imxdma->dma_ipg);
Fabio Estevama2367db2012-07-03 15:33:29 -0300982
983 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
Shawn Guo04bbd8e2012-09-15 15:16:47 +0800984 if (IS_ERR(imxdma->dma_ahb))
985 return PTR_ERR(imxdma->dma_ahb);
Fabio Estevama2367db2012-07-03 15:33:29 -0300986
987 clk_prepare_enable(imxdma->dma_ipg);
988 clk_prepare_enable(imxdma->dma_ahb);
Javier Martin6bd08122012-03-22 14:54:01 +0100989
990 /* reset DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100991 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +0100992
993 if (cpu_is_mx1()) {
Shawn Guo73930eb2012-09-15 15:57:00 +0800994 ret = devm_request_irq(&pdev->dev, irq,
Shawn Guo04bbd8e2012-09-15 15:16:47 +0800995 dma_irq_handler, 0, "DMA", imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +0100996 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +0100997 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +0800998 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +0100999 }
1000
Shawn Guo73930eb2012-09-15 15:57:00 +08001001 irq_err = platform_get_irq(pdev, 1);
1002 if (irq_err < 0) {
1003 ret = irq_err;
1004 goto err;
1005 }
1006
1007 ret = devm_request_irq(&pdev->dev, irq_err,
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001008 imxdma_err_handler, 0, "DMA", imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +01001009 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001010 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001011 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +01001012 }
1013 }
1014
1015 /* enable DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001016 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +01001017
1018 /* clear all interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001019 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +01001020
1021 /* disable interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001022 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001023
1024 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1025
Sascha Hauerf8a356f2011-01-31 11:35:59 +01001026 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1027 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
Javier Martin6c05f092012-02-28 17:08:17 +01001028 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
Javier Martinf606ab82012-03-22 14:54:14 +01001029 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1030
1031 /* Initialize 2D global parameters */
1032 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1033 imxdma->slots_2d[i].count = 0;
1034
1035 spin_lock_init(&imxdma->lock);
Sascha Hauerf8a356f2011-01-31 11:35:59 +01001036
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001037 /* Initialize channel parameters */
Javier Martin6bd08122012-03-22 14:54:01 +01001038 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001039 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1040
Javier Martin6bd08122012-03-22 14:54:01 +01001041 if (cpu_is_mx21() || cpu_is_mx27()) {
Shawn Guo73930eb2012-09-15 15:57:00 +08001042 ret = devm_request_irq(&pdev->dev, irq + i,
Javier Martin6bd08122012-03-22 14:54:01 +01001043 dma_irq_handler, 0, "DMA", imxdma);
1044 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001045 dev_warn(imxdma->dev, "Can't register IRQ %d "
1046 "for DMA channel %d\n",
Shawn Guo73930eb2012-09-15 15:57:00 +08001047 irq + i, i);
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001048 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +01001049 }
Javier Martin2d9c2fc2012-03-22 14:54:10 +01001050 init_timer(&imxdmac->watchdog);
1051 imxdmac->watchdog.function = &imxdma_watchdog;
1052 imxdmac->watchdog.data = (unsigned long)imxdmac;
Sascha Hauer8267f162010-10-20 08:37:19 +02001053 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001054
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001055 imxdmac->imxdma = imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001056
Javier Martin9e15db72012-03-02 09:28:47 +01001057 INIT_LIST_HEAD(&imxdmac->ld_queue);
1058 INIT_LIST_HEAD(&imxdmac->ld_free);
1059 INIT_LIST_HEAD(&imxdmac->ld_active);
1060
1061 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1062 (unsigned long)imxdmac);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001063 imxdmac->chan.device = &imxdma->dma_device;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001064 dma_cookie_init(&imxdmac->chan);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001065 imxdmac->channel = i;
1066
1067 /* Add the channel to the DMAC list */
Javier Martin9e15db72012-03-02 09:28:47 +01001068 list_add_tail(&imxdmac->chan.device_node,
1069 &imxdma->dma_device.channels);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001070 }
1071
1072 imxdma->dev = &pdev->dev;
1073 imxdma->dma_device.dev = &pdev->dev;
1074
1075 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1076 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1077 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1078 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1079 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
Javier Martin6c05f092012-02-28 17:08:17 +01001080 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
Javier Martinf606ab82012-03-22 14:54:14 +01001081 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001082 imxdma->dma_device.device_control = imxdma_control;
1083 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1084
1085 platform_set_drvdata(pdev, imxdma);
1086
Javier Martin6c05f092012-02-28 17:08:17 +01001087 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
Sascha Hauer1e070a62011-01-12 13:14:37 +01001088 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1089 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1090
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001091 ret = dma_async_device_register(&imxdma->dma_device);
1092 if (ret) {
1093 dev_err(&pdev->dev, "unable to register\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001094 goto err;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001095 }
1096
1097 return 0;
1098
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001099err:
Fabio Estevama2367db2012-07-03 15:33:29 -03001100 clk_disable_unprepare(imxdma->dma_ipg);
1101 clk_disable_unprepare(imxdma->dma_ahb);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001102 return ret;
1103}
1104
1105static int __exit imxdma_remove(struct platform_device *pdev)
1106{
1107 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001108
1109 dma_async_device_unregister(&imxdma->dma_device);
1110
Fabio Estevama2367db2012-07-03 15:33:29 -03001111 clk_disable_unprepare(imxdma->dma_ipg);
1112 clk_disable_unprepare(imxdma->dma_ahb);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001113
1114 return 0;
1115}
1116
1117static struct platform_driver imxdma_driver = {
1118 .driver = {
1119 .name = "imx-dma",
1120 },
1121 .remove = __exit_p(imxdma_remove),
1122};
1123
1124static int __init imxdma_module_init(void)
1125{
1126 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1127}
1128subsys_initcall(imxdma_module_init);
1129
1130MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1131MODULE_DESCRIPTION("i.MX dma driver");
1132MODULE_LICENSE("GPL");