Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * AMD K7 AGPGART routines. |
| 3 | */ |
| 4 | |
| 5 | #include <linux/module.h> |
| 6 | #include <linux/pci.h> |
| 7 | #include <linux/init.h> |
| 8 | #include <linux/agp_backend.h> |
| 9 | #include <linux/gfp.h> |
| 10 | #include <linux/page-flags.h> |
| 11 | #include <linux/mm.h> |
| 12 | #include "agp.h" |
| 13 | |
| 14 | #define AMD_MMBASE 0x14 |
| 15 | #define AMD_APSIZE 0xac |
| 16 | #define AMD_MODECNTL 0xb0 |
| 17 | #define AMD_MODECNTL2 0xb2 |
| 18 | #define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */ |
| 19 | #define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */ |
| 20 | #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */ |
| 21 | #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */ |
| 22 | |
| 23 | static struct pci_device_id agp_amdk7_pci_table[]; |
| 24 | |
| 25 | struct amd_page_map { |
| 26 | unsigned long *real; |
| 27 | unsigned long __iomem *remapped; |
| 28 | }; |
| 29 | |
| 30 | static struct _amd_irongate_private { |
| 31 | volatile u8 __iomem *registers; |
| 32 | struct amd_page_map **gatt_pages; |
| 33 | int num_tables; |
| 34 | } amd_irongate_private; |
| 35 | |
| 36 | static int amd_create_page_map(struct amd_page_map *page_map) |
| 37 | { |
| 38 | int i; |
| 39 | |
| 40 | page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL); |
| 41 | if (page_map->real == NULL) |
| 42 | return -ENOMEM; |
| 43 | |
| 44 | SetPageReserved(virt_to_page(page_map->real)); |
| 45 | global_cache_flush(); |
Keir Fraser | 07eee78 | 2005-03-30 13:17:04 -0800 | [diff] [blame] | 46 | page_map->remapped = ioremap_nocache(virt_to_gart(page_map->real), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | PAGE_SIZE); |
| 48 | if (page_map->remapped == NULL) { |
| 49 | ClearPageReserved(virt_to_page(page_map->real)); |
| 50 | free_page((unsigned long) page_map->real); |
| 51 | page_map->real = NULL; |
| 52 | return -ENOMEM; |
| 53 | } |
| 54 | global_cache_flush(); |
| 55 | |
| 56 | for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) { |
| 57 | writel(agp_bridge->scratch_page, page_map->remapped+i); |
| 58 | readl(page_map->remapped+i); /* PCI Posting. */ |
| 59 | } |
| 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | static void amd_free_page_map(struct amd_page_map *page_map) |
| 65 | { |
| 66 | iounmap(page_map->remapped); |
| 67 | ClearPageReserved(virt_to_page(page_map->real)); |
| 68 | free_page((unsigned long) page_map->real); |
| 69 | } |
| 70 | |
| 71 | static void amd_free_gatt_pages(void) |
| 72 | { |
| 73 | int i; |
| 74 | struct amd_page_map **tables; |
| 75 | struct amd_page_map *entry; |
| 76 | |
| 77 | tables = amd_irongate_private.gatt_pages; |
| 78 | for (i = 0; i < amd_irongate_private.num_tables; i++) { |
| 79 | entry = tables[i]; |
| 80 | if (entry != NULL) { |
| 81 | if (entry->real != NULL) |
| 82 | amd_free_page_map(entry); |
| 83 | kfree(entry); |
| 84 | } |
| 85 | } |
| 86 | kfree(tables); |
| 87 | amd_irongate_private.gatt_pages = NULL; |
| 88 | } |
| 89 | |
| 90 | static int amd_create_gatt_pages(int nr_tables) |
| 91 | { |
| 92 | struct amd_page_map **tables; |
| 93 | struct amd_page_map *entry; |
| 94 | int retval = 0; |
| 95 | int i; |
| 96 | |
Dave Jones | 0ea27d9 | 2005-10-20 15:12:16 -0700 | [diff] [blame] | 97 | tables = kzalloc((nr_tables + 1) * sizeof(struct amd_page_map *),GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | if (tables == NULL) |
| 99 | return -ENOMEM; |
| 100 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | for (i = 0; i < nr_tables; i++) { |
Dave Jones | 0ea27d9 | 2005-10-20 15:12:16 -0700 | [diff] [blame] | 102 | entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | if (entry == NULL) { |
Dave Jones | c30efba | 2007-01-28 17:39:19 -0500 | [diff] [blame] | 104 | while (i > 0) { |
| 105 | kfree(tables[i-1]); |
| 106 | i--; |
| 107 | } |
| 108 | kfree(tables); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | retval = -ENOMEM; |
| 110 | break; |
| 111 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | tables[i] = entry; |
| 113 | retval = amd_create_page_map(entry); |
| 114 | if (retval != 0) |
| 115 | break; |
| 116 | } |
| 117 | amd_irongate_private.num_tables = nr_tables; |
| 118 | amd_irongate_private.gatt_pages = tables; |
| 119 | |
| 120 | if (retval != 0) |
| 121 | amd_free_gatt_pages(); |
| 122 | |
| 123 | return retval; |
| 124 | } |
| 125 | |
Andreas Mohr | d6e05ed | 2006-06-26 18:35:02 +0200 | [diff] [blame] | 126 | /* Since we don't need contiguous memory we just try |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | * to get the gatt table once |
| 128 | */ |
| 129 | |
| 130 | #define GET_PAGE_DIR_OFF(addr) (addr >> 22) |
| 131 | #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ |
| 132 | GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) |
| 133 | #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) |
| 134 | #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\ |
| 135 | GET_PAGE_DIR_IDX(addr)]->remapped) |
| 136 | |
| 137 | static int amd_create_gatt_table(struct agp_bridge_data *bridge) |
| 138 | { |
| 139 | struct aper_size_info_lvl2 *value; |
| 140 | struct amd_page_map page_dir; |
| 141 | unsigned long addr; |
| 142 | int retval; |
| 143 | u32 temp; |
| 144 | int i; |
| 145 | |
| 146 | value = A_SIZE_LVL2(agp_bridge->current_size); |
| 147 | retval = amd_create_page_map(&page_dir); |
| 148 | if (retval != 0) |
| 149 | return retval; |
| 150 | |
| 151 | retval = amd_create_gatt_pages(value->num_entries / 1024); |
| 152 | if (retval != 0) { |
| 153 | amd_free_page_map(&page_dir); |
| 154 | return retval; |
| 155 | } |
| 156 | |
| 157 | agp_bridge->gatt_table_real = (u32 *)page_dir.real; |
| 158 | agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped; |
Keir Fraser | 07eee78 | 2005-03-30 13:17:04 -0800 | [diff] [blame] | 159 | agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | |
| 161 | /* Get the address for the gart region. |
| 162 | * This is a bus address even on the alpha, b/c its |
| 163 | * used to program the agp master not the cpu |
| 164 | */ |
| 165 | |
| 166 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); |
| 167 | addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
| 168 | agp_bridge->gart_bus_addr = addr; |
| 169 | |
| 170 | /* Calculate the agp offset */ |
| 171 | for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) { |
Keir Fraser | 07eee78 | 2005-03-30 13:17:04 -0800 | [diff] [blame] | 172 | writel(virt_to_gart(amd_irongate_private.gatt_pages[i]->real) | 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | page_dir.remapped+GET_PAGE_DIR_OFF(addr)); |
| 174 | readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */ |
| 175 | } |
| 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | static int amd_free_gatt_table(struct agp_bridge_data *bridge) |
| 181 | { |
| 182 | struct amd_page_map page_dir; |
| 183 | |
| 184 | page_dir.real = (unsigned long *)agp_bridge->gatt_table_real; |
| 185 | page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table; |
| 186 | |
| 187 | amd_free_gatt_pages(); |
| 188 | amd_free_page_map(&page_dir); |
| 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | static int amd_irongate_fetch_size(void) |
| 193 | { |
| 194 | int i; |
| 195 | u32 temp; |
| 196 | struct aper_size_info_lvl2 *values; |
| 197 | |
| 198 | pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); |
| 199 | temp = (temp & 0x0000000e); |
| 200 | values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); |
| 201 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { |
| 202 | if (temp == values[i].size_value) { |
| 203 | agp_bridge->previous_size = |
| 204 | agp_bridge->current_size = (void *) (values + i); |
| 205 | |
| 206 | agp_bridge->aperture_size_idx = i; |
| 207 | return values[i].size; |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | return 0; |
| 212 | } |
| 213 | |
| 214 | static int amd_irongate_configure(void) |
| 215 | { |
| 216 | struct aper_size_info_lvl2 *current_size; |
| 217 | u32 temp; |
| 218 | u16 enable_reg; |
| 219 | |
| 220 | current_size = A_SIZE_LVL2(agp_bridge->current_size); |
| 221 | |
| 222 | /* Get the memory mapped registers */ |
| 223 | pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp); |
| 224 | temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
| 225 | amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); |
| 226 | |
| 227 | /* Write out the address of the gatt table */ |
| 228 | writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE); |
| 229 | readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ |
| 230 | |
| 231 | /* Write the Sync register */ |
| 232 | pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80); |
| 233 | |
| 234 | /* Set indexing mode */ |
| 235 | pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00); |
| 236 | |
| 237 | /* Write the enable register */ |
| 238 | enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); |
| 239 | enable_reg = (enable_reg | 0x0004); |
| 240 | writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); |
| 241 | readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ |
| 242 | |
| 243 | /* Write out the size register */ |
| 244 | pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); |
| 245 | temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1); |
| 246 | pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp); |
| 247 | |
| 248 | /* Flush the tlb */ |
| 249 | writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); |
| 250 | readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/ |
| 251 | return 0; |
| 252 | } |
| 253 | |
| 254 | static void amd_irongate_cleanup(void) |
| 255 | { |
| 256 | struct aper_size_info_lvl2 *previous_size; |
| 257 | u32 temp; |
| 258 | u16 enable_reg; |
| 259 | |
| 260 | previous_size = A_SIZE_LVL2(agp_bridge->previous_size); |
| 261 | |
| 262 | enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); |
| 263 | enable_reg = (enable_reg & ~(0x0004)); |
| 264 | writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); |
| 265 | readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ |
| 266 | |
| 267 | /* Write back the previous size and disable gart translation */ |
| 268 | pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); |
| 269 | temp = ((temp & ~(0x0000000f)) | previous_size->size_value); |
| 270 | pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp); |
| 271 | iounmap((void __iomem *) amd_irongate_private.registers); |
| 272 | } |
| 273 | |
| 274 | /* |
| 275 | * This routine could be implemented by taking the addresses |
| 276 | * written to the GATT, and flushing them individually. However |
| 277 | * currently it just flushes the whole table. Which is probably |
| 278 | * more efficent, since agp_memory blocks can be a large number of |
| 279 | * entries. |
| 280 | */ |
| 281 | |
| 282 | static void amd_irongate_tlbflush(struct agp_memory *temp) |
| 283 | { |
| 284 | writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); |
| 285 | readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */ |
| 286 | } |
| 287 | |
| 288 | static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type) |
| 289 | { |
| 290 | int i, j, num_entries; |
| 291 | unsigned long __iomem *cur_gatt; |
| 292 | unsigned long addr; |
| 293 | |
| 294 | num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; |
| 295 | |
| 296 | if (type != 0 || mem->type != 0) |
| 297 | return -EINVAL; |
| 298 | |
| 299 | if ((pg_start + mem->page_count) > num_entries) |
| 300 | return -EINVAL; |
| 301 | |
| 302 | j = pg_start; |
| 303 | while (j < (pg_start + mem->page_count)) { |
| 304 | addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; |
| 305 | cur_gatt = GET_GATT(addr); |
| 306 | if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr)))) |
| 307 | return -EBUSY; |
| 308 | j++; |
| 309 | } |
| 310 | |
| 311 | if (mem->is_flushed == FALSE) { |
| 312 | global_cache_flush(); |
| 313 | mem->is_flushed = TRUE; |
| 314 | } |
| 315 | |
| 316 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
| 317 | addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; |
| 318 | cur_gatt = GET_GATT(addr); |
| 319 | writel(agp_generic_mask_memory(agp_bridge, |
| 320 | mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr)); |
| 321 | readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ |
| 322 | } |
| 323 | amd_irongate_tlbflush(mem); |
| 324 | return 0; |
| 325 | } |
| 326 | |
| 327 | static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type) |
| 328 | { |
| 329 | int i; |
| 330 | unsigned long __iomem *cur_gatt; |
| 331 | unsigned long addr; |
| 332 | |
| 333 | if (type != 0 || mem->type != 0) |
| 334 | return -EINVAL; |
| 335 | |
| 336 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
| 337 | addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; |
| 338 | cur_gatt = GET_GATT(addr); |
| 339 | writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr)); |
| 340 | readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ |
| 341 | } |
| 342 | |
| 343 | amd_irongate_tlbflush(mem); |
| 344 | return 0; |
| 345 | } |
| 346 | |
Dave Jones | e5524f3 | 2007-02-22 18:41:28 -0500 | [diff] [blame^] | 347 | static const struct aper_size_info_lvl2 amd_irongate_sizes[7] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | { |
| 349 | {2048, 524288, 0x0000000c}, |
| 350 | {1024, 262144, 0x0000000a}, |
| 351 | {512, 131072, 0x00000008}, |
| 352 | {256, 65536, 0x00000006}, |
| 353 | {128, 32768, 0x00000004}, |
| 354 | {64, 16384, 0x00000002}, |
| 355 | {32, 8192, 0x00000000} |
| 356 | }; |
| 357 | |
Dave Jones | e5524f3 | 2007-02-22 18:41:28 -0500 | [diff] [blame^] | 358 | static const struct gatt_mask amd_irongate_masks[] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | { |
| 360 | {.mask = 1, .type = 0} |
| 361 | }; |
| 362 | |
Dave Jones | e5524f3 | 2007-02-22 18:41:28 -0500 | [diff] [blame^] | 363 | static const struct agp_bridge_driver amd_irongate_driver = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 364 | .owner = THIS_MODULE, |
| 365 | .aperture_sizes = amd_irongate_sizes, |
| 366 | .size_type = LVL2_APER_SIZE, |
| 367 | .num_aperture_sizes = 7, |
| 368 | .configure = amd_irongate_configure, |
| 369 | .fetch_size = amd_irongate_fetch_size, |
| 370 | .cleanup = amd_irongate_cleanup, |
| 371 | .tlb_flush = amd_irongate_tlbflush, |
| 372 | .mask_memory = agp_generic_mask_memory, |
| 373 | .masks = amd_irongate_masks, |
| 374 | .agp_enable = agp_generic_enable, |
| 375 | .cache_flush = global_cache_flush, |
| 376 | .create_gatt_table = amd_create_gatt_table, |
| 377 | .free_gatt_table = amd_free_gatt_table, |
| 378 | .insert_memory = amd_insert_memory, |
| 379 | .remove_memory = amd_remove_memory, |
| 380 | .alloc_by_type = agp_generic_alloc_by_type, |
| 381 | .free_by_type = agp_generic_free_by_type, |
| 382 | .agp_alloc_page = agp_generic_alloc_page, |
| 383 | .agp_destroy_page = agp_generic_destroy_page, |
Thomas Hellstrom | a030ce4 | 2007-01-23 10:33:43 +0100 | [diff] [blame] | 384 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 385 | }; |
| 386 | |
| 387 | static struct agp_device_ids amd_agp_device_ids[] __devinitdata = |
| 388 | { |
| 389 | { |
| 390 | .device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006, |
| 391 | .chipset_name = "Irongate", |
| 392 | }, |
| 393 | { |
| 394 | .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E, |
| 395 | .chipset_name = "761", |
| 396 | }, |
| 397 | { |
| 398 | .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C, |
| 399 | .chipset_name = "760MP", |
| 400 | }, |
| 401 | { }, /* dummy final entry, always present */ |
| 402 | }; |
| 403 | |
| 404 | static int __devinit agp_amdk7_probe(struct pci_dev *pdev, |
| 405 | const struct pci_device_id *ent) |
| 406 | { |
| 407 | struct agp_bridge_data *bridge; |
| 408 | u8 cap_ptr; |
| 409 | int j; |
| 410 | |
| 411 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); |
| 412 | if (!cap_ptr) |
| 413 | return -ENODEV; |
| 414 | |
| 415 | j = ent - agp_amdk7_pci_table; |
| 416 | printk(KERN_INFO PFX "Detected AMD %s chipset\n", |
| 417 | amd_agp_device_ids[j].chipset_name); |
| 418 | |
| 419 | bridge = agp_alloc_bridge(); |
| 420 | if (!bridge) |
| 421 | return -ENOMEM; |
| 422 | |
| 423 | bridge->driver = &amd_irongate_driver; |
| 424 | bridge->dev_private_data = &amd_irongate_private, |
| 425 | bridge->dev = pdev; |
| 426 | bridge->capndx = cap_ptr; |
| 427 | |
| 428 | /* 751 Errata (22564_B-1.PDF) |
| 429 | erratum 20: strobe glitch with Nvidia NV10 GeForce cards. |
| 430 | system controller may experience noise due to strong drive strengths |
| 431 | */ |
| 432 | if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) { |
| 433 | u8 cap_ptr=0; |
| 434 | struct pci_dev *gfxcard=NULL; |
| 435 | while (!cap_ptr) { |
| 436 | gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard); |
| 437 | if (!gfxcard) { |
| 438 | printk (KERN_INFO PFX "Couldn't find an AGP VGA controller.\n"); |
| 439 | return -ENODEV; |
| 440 | } |
| 441 | cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP); |
| 442 | if (!cap_ptr) { |
| 443 | pci_dev_put(gfxcard); |
| 444 | continue; |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | /* With so many variants of NVidia cards, it's simpler just |
| 449 | to blacklist them all, and then whitelist them as needed |
| 450 | (if necessary at all). */ |
| 451 | if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) { |
| 452 | agp_bridge->flags |= AGP_ERRATA_1X; |
| 453 | printk (KERN_INFO PFX "AMD 751 chipset with NVidia GeForce detected. Forcing to 1X due to errata.\n"); |
| 454 | } |
| 455 | pci_dev_put(gfxcard); |
| 456 | } |
| 457 | |
| 458 | /* 761 Errata (23613_F.pdf) |
| 459 | * Revisions B0/B1 were a disaster. |
| 460 | * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X |
| 461 | * erratum 45: Timing problem prevents fast writes -- Disable fast write. |
| 462 | * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing. |
| 463 | * With this lot disabled, we should prevent lockups. */ |
| 464 | if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) { |
| 465 | u8 revision=0; |
| 466 | pci_read_config_byte(pdev, PCI_REVISION_ID, &revision); |
| 467 | if (revision == 0x10 || revision == 0x11) { |
| 468 | agp_bridge->flags = AGP_ERRATA_FASTWRITES; |
| 469 | agp_bridge->flags |= AGP_ERRATA_SBA; |
| 470 | agp_bridge->flags |= AGP_ERRATA_1X; |
| 471 | printk (KERN_INFO PFX "AMD 761 chipset with errata detected - disabling AGP fast writes & SBA and forcing to 1X.\n"); |
| 472 | } |
| 473 | } |
| 474 | |
| 475 | /* Fill in the mode register */ |
| 476 | pci_read_config_dword(pdev, |
| 477 | bridge->capndx+PCI_AGP_STATUS, |
| 478 | &bridge->mode); |
| 479 | |
| 480 | pci_set_drvdata(pdev, bridge); |
| 481 | return agp_add_bridge(bridge); |
| 482 | } |
| 483 | |
| 484 | static void __devexit agp_amdk7_remove(struct pci_dev *pdev) |
| 485 | { |
| 486 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); |
| 487 | |
| 488 | agp_remove_bridge(bridge); |
| 489 | agp_put_bridge(bridge); |
| 490 | } |
| 491 | |
| 492 | /* must be the same order as name table above */ |
| 493 | static struct pci_device_id agp_amdk7_pci_table[] = { |
| 494 | { |
| 495 | .class = (PCI_CLASS_BRIDGE_HOST << 8), |
| 496 | .class_mask = ~0, |
| 497 | .vendor = PCI_VENDOR_ID_AMD, |
| 498 | .device = PCI_DEVICE_ID_AMD_FE_GATE_7006, |
| 499 | .subvendor = PCI_ANY_ID, |
| 500 | .subdevice = PCI_ANY_ID, |
| 501 | }, |
| 502 | { |
| 503 | .class = (PCI_CLASS_BRIDGE_HOST << 8), |
| 504 | .class_mask = ~0, |
| 505 | .vendor = PCI_VENDOR_ID_AMD, |
| 506 | .device = PCI_DEVICE_ID_AMD_FE_GATE_700E, |
| 507 | .subvendor = PCI_ANY_ID, |
| 508 | .subdevice = PCI_ANY_ID, |
| 509 | }, |
| 510 | { |
| 511 | .class = (PCI_CLASS_BRIDGE_HOST << 8), |
| 512 | .class_mask = ~0, |
| 513 | .vendor = PCI_VENDOR_ID_AMD, |
| 514 | .device = PCI_DEVICE_ID_AMD_FE_GATE_700C, |
| 515 | .subvendor = PCI_ANY_ID, |
| 516 | .subdevice = PCI_ANY_ID, |
| 517 | }, |
| 518 | { } |
| 519 | }; |
| 520 | |
| 521 | MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table); |
| 522 | |
| 523 | static struct pci_driver agp_amdk7_pci_driver = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 524 | .name = "agpgart-amdk7", |
| 525 | .id_table = agp_amdk7_pci_table, |
| 526 | .probe = agp_amdk7_probe, |
| 527 | .remove = agp_amdk7_remove, |
| 528 | }; |
| 529 | |
| 530 | static int __init agp_amdk7_init(void) |
| 531 | { |
| 532 | if (agp_off) |
| 533 | return -EINVAL; |
| 534 | return pci_register_driver(&agp_amdk7_pci_driver); |
| 535 | } |
| 536 | |
| 537 | static void __exit agp_amdk7_cleanup(void) |
| 538 | { |
| 539 | pci_unregister_driver(&agp_amdk7_pci_driver); |
| 540 | } |
| 541 | |
| 542 | module_init(agp_amdk7_init); |
| 543 | module_exit(agp_amdk7_cleanup); |
| 544 | |
| 545 | MODULE_LICENSE("GPL and additional rights"); |