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Alan Cox806c35f2006-01-18 17:44:08 -08001/*
2 * AMD 76x Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
10 *
11 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
12 *
13 */
14
Alan Cox806c35f2006-01-18 17:44:08 -080015#include <linux/module.h>
16#include <linux/init.h>
Alan Cox806c35f2006-01-18 17:44:08 -080017#include <linux/pci.h>
18#include <linux/pci_ids.h>
Alan Cox806c35f2006-01-18 17:44:08 -080019#include <linux/slab.h>
Alan Cox806c35f2006-01-18 17:44:08 -080020#include "edac_mc.h"
21
Doug Thompson929a40e2006-07-01 04:35:45 -070022#define AMD76X_REVISION " Ver: 2.0.1 " __DATE__
23#define EDAC_MOD_STR "amd76x_edac"
Doug Thompson37f04582006-06-30 01:56:07 -070024
Dave Peterson537fba22006-03-26 01:38:40 -080025#define amd76x_printk(level, fmt, arg...) \
Dave Petersone7ecd892006-03-26 01:38:52 -080026 edac_printk(level, "amd76x", fmt, ##arg)
Dave Peterson537fba22006-03-26 01:38:40 -080027
28#define amd76x_mc_printk(mci, level, fmt, arg...) \
Dave Petersone7ecd892006-03-26 01:38:52 -080029 edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
Dave Peterson537fba22006-03-26 01:38:40 -080030
Alan Cox806c35f2006-01-18 17:44:08 -080031#define AMD76X_NR_CSROWS 8
32#define AMD76X_NR_CHANS 1
33#define AMD76X_NR_DIMMS 4
34
Alan Cox806c35f2006-01-18 17:44:08 -080035/* AMD 76x register addresses - device 0 function 0 - PCI bridge */
Dave Petersone7ecd892006-03-26 01:38:52 -080036
Alan Cox806c35f2006-01-18 17:44:08 -080037#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
38 *
39 * 31:16 reserved
40 * 15:14 SERR enabled: x1=ue 1x=ce
41 * 13 reserved
42 * 12 diag: disabled, enabled
43 * 11:10 mode: dis, EC, ECC, ECC+scrub
44 * 9:8 status: x1=ue 1x=ce
45 * 7:4 UE cs row
46 * 3:0 CE cs row
47 */
Dave Petersone7ecd892006-03-26 01:38:52 -080048
Alan Cox806c35f2006-01-18 17:44:08 -080049#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
50 *
51 * 31:26 clock disable 5 - 0
52 * 25 SDRAM init
53 * 24 reserved
54 * 23 mode register service
55 * 22:21 suspend to RAM
56 * 20 burst refresh enable
57 * 19 refresh disable
58 * 18 reserved
59 * 17:16 cycles-per-refresh
60 * 15:8 reserved
61 * 7:0 x4 mode enable 7 - 0
62 */
Dave Petersone7ecd892006-03-26 01:38:52 -080063
Alan Cox806c35f2006-01-18 17:44:08 -080064#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
65 *
66 * 31:23 chip-select base
67 * 22:16 reserved
68 * 15:7 chip-select mask
69 * 6:3 reserved
70 * 2:1 address mode
71 * 0 chip-select enable
72 */
73
Alan Cox806c35f2006-01-18 17:44:08 -080074struct amd76x_error_info {
75 u32 ecc_mode_status;
76};
77
Alan Cox806c35f2006-01-18 17:44:08 -080078enum amd76x_chips {
79 AMD761 = 0,
80 AMD762
81};
82
Alan Cox806c35f2006-01-18 17:44:08 -080083struct amd76x_dev_info {
84 const char *ctl_name;
85};
86
Alan Cox806c35f2006-01-18 17:44:08 -080087static const struct amd76x_dev_info amd76x_devs[] = {
Dave Petersone7ecd892006-03-26 01:38:52 -080088 [AMD761] = {
89 .ctl_name = "AMD761"
90 },
91 [AMD762] = {
92 .ctl_name = "AMD762"
93 },
Alan Cox806c35f2006-01-18 17:44:08 -080094};
95
Alan Cox806c35f2006-01-18 17:44:08 -080096/**
97 * amd76x_get_error_info - fetch error information
98 * @mci: Memory controller
99 * @info: Info to fill in
100 *
101 * Fetch and store the AMD76x ECC status. Clear pending status
102 * on the chip so that further errors will be reported
103 */
Dave Petersone7ecd892006-03-26 01:38:52 -0800104static void amd76x_get_error_info(struct mem_ctl_info *mci,
105 struct amd76x_error_info *info)
Alan Cox806c35f2006-01-18 17:44:08 -0800106{
Doug Thompson37f04582006-06-30 01:56:07 -0700107 struct pci_dev *pdev;
108
109 pdev = to_pci_dev(mci->dev);
110 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
Alan Cox806c35f2006-01-18 17:44:08 -0800111 &info->ecc_mode_status);
112
113 if (info->ecc_mode_status & BIT(8))
Doug Thompson37f04582006-06-30 01:56:07 -0700114 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
Dave Petersone7ecd892006-03-26 01:38:52 -0800115 (u32) BIT(8), (u32) BIT(8));
Alan Cox806c35f2006-01-18 17:44:08 -0800116
117 if (info->ecc_mode_status & BIT(9))
Doug Thompson37f04582006-06-30 01:56:07 -0700118 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
Dave Petersone7ecd892006-03-26 01:38:52 -0800119 (u32) BIT(9), (u32) BIT(9));
Alan Cox806c35f2006-01-18 17:44:08 -0800120}
121
Alan Cox806c35f2006-01-18 17:44:08 -0800122/**
123 * amd76x_process_error_info - Error check
124 * @mci: Memory controller
125 * @info: Previously fetched information from chip
126 * @handle_errors: 1 if we should do recovery
127 *
128 * Process the chip state and decide if an error has occurred.
129 * A return of 1 indicates an error. Also if handle_errors is true
130 * then attempt to handle and clean up after the error
131 */
Dave Petersone7ecd892006-03-26 01:38:52 -0800132static int amd76x_process_error_info(struct mem_ctl_info *mci,
Alan Cox806c35f2006-01-18 17:44:08 -0800133 struct amd76x_error_info *info, int handle_errors)
134{
135 int error_found;
136 u32 row;
137
138 error_found = 0;
139
140 /*
141 * Check for an uncorrectable error
142 */
143 if (info->ecc_mode_status & BIT(8)) {
144 error_found = 1;
145
146 if (handle_errors) {
147 row = (info->ecc_mode_status >> 4) & 0xf;
Dave Petersone7ecd892006-03-26 01:38:52 -0800148 edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
149 row, mci->ctl_name);
Alan Cox806c35f2006-01-18 17:44:08 -0800150 }
151 }
152
153 /*
154 * Check for a correctable error
155 */
156 if (info->ecc_mode_status & BIT(9)) {
157 error_found = 1;
158
159 if (handle_errors) {
160 row = info->ecc_mode_status & 0xf;
Dave Petersone7ecd892006-03-26 01:38:52 -0800161 edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
162 0, row, 0, mci->ctl_name);
Alan Cox806c35f2006-01-18 17:44:08 -0800163 }
164 }
Dave Petersone7ecd892006-03-26 01:38:52 -0800165
Alan Cox806c35f2006-01-18 17:44:08 -0800166 return error_found;
167}
168
169/**
170 * amd76x_check - Poll the controller
171 * @mci: Memory controller
172 *
173 * Called by the poll handlers this function reads the status
174 * from the controller and checks for errors.
175 */
Alan Cox806c35f2006-01-18 17:44:08 -0800176static void amd76x_check(struct mem_ctl_info *mci)
177{
178 struct amd76x_error_info info;
Dave Peterson537fba22006-03-26 01:38:40 -0800179 debugf3("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800180 amd76x_get_error_info(mci, &info);
181 amd76x_process_error_info(mci, &info, 1);
182}
183
Doug Thompson13189522006-06-30 01:56:08 -0700184static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
185 enum edac_type edac_mode)
Alan Cox806c35f2006-01-18 17:44:08 -0800186{
Doug Thompson13189522006-06-30 01:56:08 -0700187 struct csrow_info *csrow;
188 u32 mba, mba_base, mba_mask, dms;
Alan Cox806c35f2006-01-18 17:44:08 -0800189 int index;
Alan Cox806c35f2006-01-18 17:44:08 -0800190
191 for (index = 0; index < mci->nr_csrows; index++) {
Doug Thompson13189522006-06-30 01:56:08 -0700192 csrow = &mci->csrows[index];
Alan Cox806c35f2006-01-18 17:44:08 -0800193
194 /* find the DRAM Chip Select Base address and mask */
Doug Thompson37f04582006-06-30 01:56:07 -0700195 pci_read_config_dword(pdev,
Doug Thompson13189522006-06-30 01:56:08 -0700196 AMD76X_MEM_BASE_ADDR + (index * 4),
197 &mba);
Alan Cox806c35f2006-01-18 17:44:08 -0800198
199 if (!(mba & BIT(0)))
200 continue;
201
202 mba_base = mba & 0xff800000UL;
203 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
Doug Thompson37f04582006-06-30 01:56:07 -0700204 pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
Alan Cox806c35f2006-01-18 17:44:08 -0800205 csrow->first_page = mba_base >> PAGE_SHIFT;
206 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
207 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
208 csrow->page_mask = mba_mask >> PAGE_SHIFT;
209 csrow->grain = csrow->nr_pages << PAGE_SHIFT;
210 csrow->mtype = MEM_RDDR;
211 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
Doug Thompson13189522006-06-30 01:56:08 -0700212 csrow->edac_mode = edac_mode;
213 }
214}
215
216/**
217 * amd76x_probe1 - Perform set up for detected device
218 * @pdev; PCI device detected
219 * @dev_idx: Device type index
220 *
221 * We have found an AMD76x and now need to set up the memory
222 * controller status reporting. We configure and set up the
223 * memory controller reporting and claim the device.
224 */
225static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
226{
227 static const enum edac_type ems_modes[] = {
228 EDAC_NONE,
229 EDAC_EC,
230 EDAC_SECDED,
231 EDAC_SECDED
232 };
233 struct mem_ctl_info *mci = NULL;
234 u32 ems;
235 u32 ems_mode;
236 struct amd76x_error_info discard;
237
238 debugf0("%s()\n", __func__);
239 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
240 ems_mode = (ems >> 10) & 0x3;
241 mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
242
243 if (mci == NULL) {
244 return -ENOMEM;
Alan Cox806c35f2006-01-18 17:44:08 -0800245 }
246
Doug Thompson13189522006-06-30 01:56:08 -0700247 debugf0("%s(): mci = %p\n", __func__, mci);
248 mci->dev = &pdev->dev;
249 mci->mtype_cap = MEM_FLAG_RDDR;
250 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
251 mci->edac_cap = ems_mode ?
252 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
253 mci->mod_name = EDAC_MOD_STR;
254 mci->mod_ver = AMD76X_REVISION;
255 mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
256 mci->edac_check = amd76x_check;
257 mci->ctl_page_to_phys = NULL;
258
259 amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
Dave Peterson749ede52006-03-26 01:38:45 -0800260 amd76x_get_error_info(mci, &discard); /* clear counters */
Alan Cox806c35f2006-01-18 17:44:08 -0800261
Doug Thompson2d7bbb92006-06-30 01:56:08 -0700262 /* Here we assume that we will never see multiple instances of this
263 * type of memory controller. The ID is therefore hardcoded to 0.
264 */
265 if (edac_mc_add_mc(mci,0)) {
Dave Peterson537fba22006-03-26 01:38:40 -0800266 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800267 goto fail;
268 }
269
270 /* get this far and it's successful */
Dave Peterson537fba22006-03-26 01:38:40 -0800271 debugf3("%s(): success\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800272 return 0;
273
274fail:
Doug Thompson13189522006-06-30 01:56:08 -0700275 edac_mc_free(mci);
276 return -ENODEV;
Alan Cox806c35f2006-01-18 17:44:08 -0800277}
278
279/* returns count (>= 0), or negative on error */
280static int __devinit amd76x_init_one(struct pci_dev *pdev,
Dave Petersone7ecd892006-03-26 01:38:52 -0800281 const struct pci_device_id *ent)
Alan Cox806c35f2006-01-18 17:44:08 -0800282{
Dave Peterson537fba22006-03-26 01:38:40 -0800283 debugf0("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800284
285 /* don't need to call pci_device_enable() */
286 return amd76x_probe1(pdev, ent->driver_data);
287}
288
Alan Cox806c35f2006-01-18 17:44:08 -0800289/**
290 * amd76x_remove_one - driver shutdown
291 * @pdev: PCI device being handed back
292 *
293 * Called when the driver is unloaded. Find the matching mci
294 * structure for the device then delete the mci and free the
295 * resources.
296 */
Alan Cox806c35f2006-01-18 17:44:08 -0800297static void __devexit amd76x_remove_one(struct pci_dev *pdev)
298{
299 struct mem_ctl_info *mci;
300
Dave Peterson537fba22006-03-26 01:38:40 -0800301 debugf0("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800302
Doug Thompson37f04582006-06-30 01:56:07 -0700303 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
Alan Cox806c35f2006-01-18 17:44:08 -0800304 return;
Dave Peterson18dbc332006-03-26 01:38:50 -0800305
Alan Cox806c35f2006-01-18 17:44:08 -0800306 edac_mc_free(mci);
307}
308
Alan Cox806c35f2006-01-18 17:44:08 -0800309static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
Dave Petersone7ecd892006-03-26 01:38:52 -0800310 {
311 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
312 AMD762
313 },
314 {
315 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
316 AMD761
317 },
318 {
319 0,
320 } /* 0 terminated list. */
Alan Cox806c35f2006-01-18 17:44:08 -0800321};
322
323MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
324
Alan Cox806c35f2006-01-18 17:44:08 -0800325static struct pci_driver amd76x_driver = {
Dave Peterson680cbbb2006-03-26 01:38:41 -0800326 .name = EDAC_MOD_STR,
Alan Cox806c35f2006-01-18 17:44:08 -0800327 .probe = amd76x_init_one,
328 .remove = __devexit_p(amd76x_remove_one),
329 .id_table = amd76x_pci_tbl,
330};
331
Alan Coxda9bb1d2006-01-18 17:44:13 -0800332static int __init amd76x_init(void)
Alan Cox806c35f2006-01-18 17:44:08 -0800333{
334 return pci_register_driver(&amd76x_driver);
335}
336
337static void __exit amd76x_exit(void)
338{
339 pci_unregister_driver(&amd76x_driver);
340}
341
342module_init(amd76x_init);
343module_exit(amd76x_exit);
344
345MODULE_LICENSE("GPL");
346MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
347MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");