blob: afc8151f4ca5caeeb98c7633441a39b960762cdb [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 */
13
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/types.h>
15#include <linux/kernel.h>
Paul Gortmaker363c75d2011-05-27 09:37:25 -040016#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040020#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070021#include <linux/kallsyms.h>
Andreas Petlund75e07fc2008-11-20 20:42:25 -080022#include <linux/dmi.h>
Alexander Duyck649426e2009-03-05 13:57:28 -050023#include <linux/pci-aspm.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090024#include <linux/ioport.h>
Arjan van de Ven32098742012-01-30 20:52:07 -080025#include <linux/sched.h>
26#include <linux/ktime.h>
Douglas Lehr9fe373f2014-08-21 09:26:52 +100027#include <linux/mm.h>
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010028#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090029#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Yuji Shimada32a9a6822009-03-16 17:13:39 +090031/*
Jacob Pan253d2e52010-07-16 10:19:22 -070032 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050037static void quirk_mmio_always_on(struct pci_dev *dev)
Jacob Pan253d2e52010-07-16 10:19:22 -070038{
Yinghai Lu52d21b52012-02-23 23:46:53 -080039 dev->mmio_always_on = 1;
Jacob Pan253d2e52010-07-16 10:19:22 -070040}
Yinghai Lu52d21b52012-02-23 23:46:53 -080041DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
Jacob Pan253d2e52010-07-16 10:19:22 -070043
Doug Thompsonbd8481e2006-05-08 17:06:09 -070044/* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
47 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050048static void quirk_mellanox_tavor(struct pci_dev *dev)
Doug Thompsonbd8481e2006-05-08 17:06:09 -070049{
50 dev->broken_parity_status = 1; /* This device gives false positives */
51}
Ryan Desfosses3c78bc62014-04-18 20:13:49 -040052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
Doug Thompsonbd8481e2006-05-08 17:06:09 -070054
Bjorn Helgaasf7625982013-11-14 11:28:18 -070055/* Deal with broken BIOSes that neglect to enable passive release,
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -080057static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070058{
59 struct pci_dev *d = NULL;
60 unsigned char dlc;
61
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
66 if (!(dlc & 1<<1)) {
Adam Jackson999da9f2008-12-01 14:30:29 -080067 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 dlc |= 1<<1;
69 pci_write_config_byte(d, 0x82, dlc);
70 }
71 }
72}
Andrew Morton652c5382007-11-21 15:07:13 -080073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
Bjorn Helgaasf7625982013-11-14 11:28:18 -070078 ask them for me please -- Alan
79
80 This appears to be BIOS not version dependent. So presumably there is a
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 chipset level fix */
Bjorn Helgaasf7625982013-11-14 11:28:18 -070082
Bill Pemberton15856ad2012-11-21 15:35:00 -050083static void quirk_isa_dma_hangs(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070084{
85 if (!isa_dma_bridge_buggy) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -040086 isa_dma_bridge_buggy = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -070087 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 }
89}
90 /*
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
93 */
Andrew Morton652c5382007-11-21 15:07:13 -080094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
Bjorn Helgaasf7625982013-11-14 11:28:18 -070097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
Andrew Morton652c5382007-11-21 15:07:13 -080098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102/*
Len Brown4731fdc2010-09-24 21:02:27 -0400103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
105 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500106static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
Len Brown4731fdc2010-09-24 21:02:27 -0400107{
108 u32 pmbase;
109 u16 pm1a;
110
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
113 pm1a = inw(pmbase);
114
115 if (pm1a & 0x10) {
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
117 outw(0x10, pmbase);
118 }
119}
120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
121
122/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123 * Chipsets where PCI->PCI transfers vanish or hang
124 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500125static void quirk_nopcipci(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 pci_pci_problems |= PCIPCI_FAIL;
130 }
131}
Andrew Morton652c5382007-11-21 15:07:13 -0800132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700134
Bill Pemberton15856ad2012-11-21 15:35:00 -0500135static void quirk_nopciamd(struct pci_dev *dev)
Alan Cox236561e2006-09-30 23:27:03 -0700136{
137 u8 rev;
138 pci_read_config_byte(dev, 0x08, &rev);
139 if (rev == 0x13) {
140 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700142 pci_pci_problems |= PCIAGP_FAIL;
143 }
144}
Andrew Morton652c5382007-11-21 15:07:13 -0800145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147/*
148 * Triton requires workarounds to be used by the drivers
149 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500150static void quirk_triton(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 pci_pci_problems |= PCIPCI_TRITON;
155 }
156}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161
162/*
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
Justin P. Mattock631dd1a2010-10-18 11:03:14 +0200166 * and http://www.georgebreese.com/net/software/#PCI
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
168 * the info on which Mr Breese based his work.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169 *
170 * Updated based on further information from the site and also on
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700171 * information provided by VIA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 */
Alan Cox1597cac2006-12-04 15:14:45 -0800173static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174{
175 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 u8 busarb;
177 /* Ok we have a potential problem chipset here. Now see if we have
178 a buggy southbridge */
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700179
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400181 if (p != NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
183 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700184 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 goto exit;
186 } else {
187 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400188 if (p == NULL) /* No problem parts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700191 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 goto exit;
193 }
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700194
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 /*
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700196 * Ok we have the problem. Now set the PCI master grant to
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197 * occur every master grant. The apparent bug is that under high
198 * PCI load (quite common in Linux of course) you can get data
199 * loss when the CPU is held off the bus for 3 bus master requests
200 * This happens to include the IDE controllers....
201 *
202 * VIA only apply this fix when an SB Live! is present but under
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300203 * both Linux and Windows this isn't enough, and we have seen
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 * corruption without SB Live! but with things like 3 UDMA IDE
205 * controllers. So we ignore that bit of the VIA recommendation..
206 */
207
208 pci_read_config_byte(dev, 0x76, &busarb);
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700209 /* Set bit 4 and bi 5 of byte 76 to 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 "Master priority rotation on every PCI master grant */
211 busarb &= ~(1<<5);
212 busarb |= (1<<4);
213 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700214 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215exit:
216 pci_dev_put(p);
217}
Andrew Morton652c5382007-11-21 15:07:13 -0800218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800221/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
224DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225
226/*
227 * VIA Apollo VP3 needs ETBF on BT848/878
228 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500229static void quirk_viaetbf(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400231 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700232 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 pci_pci_problems |= PCIPCI_VIAETBF;
234 }
235}
Andrew Morton652c5382007-11-21 15:07:13 -0800236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237
Bill Pemberton15856ad2012-11-21 15:35:00 -0500238static void quirk_vsfx(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400240 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 pci_pci_problems |= PCIPCI_VSFX;
243 }
244}
Andrew Morton652c5382007-11-21 15:07:13 -0800245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246
247/*
248 * Ali Magik requires workarounds to be used by the drivers
249 * that DMA to AGP space. Latency must be set to 0xA and triton
250 * workaround applied too
251 * [Info kindly provided by ALi]
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700252 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500253static void quirk_alimagik(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400255 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
258 }
259}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262
263/*
264 * Natoma has some interesting boundary conditions with Zoran stuff
265 * at least
266 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500267static void quirk_natoma(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400269 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 pci_pci_problems |= PCIPCI_NATOMA;
272 }
273}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280
281/*
282 * This chip can cause PCI parity errors if config register 0xA0 is read
283 * while DMAs are occurring.
284 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500285static void quirk_citrine(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286{
287 dev->cfg_size = 0xA0;
288}
Andrew Morton652c5382007-11-21 15:07:13 -0800289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290
Douglas Lehr9fe373f2014-08-21 09:26:52 +1000291/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
292static void quirk_extend_bar_to_page(struct pci_dev *dev)
293{
294 int i;
295
296 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
297 struct resource *r = &dev->resource[i];
298
299 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
300 r->end = PAGE_SIZE - 1;
301 r->start = 0;
302 r->flags |= IORESOURCE_UNSET;
303 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
304 i, r);
305 }
306 }
307}
308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
309
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310/*
311 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
312 * If it's needed, re-allocate the region.
313 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500314static void quirk_s3_64M(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315{
316 struct resource *r = &dev->resource[0];
317
318 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
Bjorn Helgaasbd064f02014-02-26 11:25:58 -0700319 r->flags |= IORESOURCE_UNSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 r->start = 0;
321 r->end = 0x3ffffff;
322 }
323}
Andrew Morton652c5382007-11-21 15:07:13 -0800324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326
Myron Stowe06cf35f2015-02-03 16:01:24 -0700327static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
328 const char *name)
329{
330 u32 region;
331 struct pci_bus_region bus_region;
332 struct resource *res = dev->resource + pos;
333
334 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
335
336 if (!region)
337 return;
338
339 res->name = pci_name(dev);
340 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
341 res->flags |=
342 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
343 region &= ~(size - 1);
344
345 /* Convert from PCI bus to resource space */
346 bus_region.start = region;
347 bus_region.end = region + size - 1;
348 pcibios_bus_to_resource(dev->bus, res, &bus_region);
349
350 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
351 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
352}
353
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500354/*
355 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
356 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
357 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
358 * (which conflicts w/ BAR1's memory range).
Myron Stowe06cf35f2015-02-03 16:01:24 -0700359 *
360 * CS553x's ISA PCI BARs may also be read-only (ref:
361 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500362 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500363static void quirk_cs5536_vsa(struct pci_dev *dev)
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500364{
Myron Stowe06cf35f2015-02-03 16:01:24 -0700365 static char *name = "CS5536 ISA bridge";
366
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500367 if (pci_resource_len(dev, 0) != 8) {
Myron Stowe06cf35f2015-02-03 16:01:24 -0700368 quirk_io(dev, 0, 8, name); /* SMB */
369 quirk_io(dev, 1, 256, name); /* GPIO */
370 quirk_io(dev, 2, 64, name); /* MFGPT */
371 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
372 name);
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500373 }
374}
375DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
376
Yinghai Lu65195c72013-04-12 12:44:15 +0000377static void quirk_io_region(struct pci_dev *dev, int port,
378 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379{
Yinghai Lu65195c72013-04-12 12:44:15 +0000380 u16 region;
381 struct pci_bus_region bus_region;
382 struct resource *res = dev->resource + nr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383
Yinghai Lu65195c72013-04-12 12:44:15 +0000384 pci_read_config_word(dev, port, &region);
385 region &= ~(size - 1);
David S. Miller085ae412005-08-08 13:19:08 -0700386
Yinghai Lu65195c72013-04-12 12:44:15 +0000387 if (!region)
388 return;
David S. Miller085ae412005-08-08 13:19:08 -0700389
Yinghai Lu65195c72013-04-12 12:44:15 +0000390 res->name = pci_name(dev);
391 res->flags = IORESOURCE_IO;
392
393 /* Convert from PCI bus to resource space */
394 bus_region.start = region;
395 bus_region.end = region + size - 1;
Yinghai Lufc279852013-12-09 22:54:40 -0800396 pcibios_bus_to_resource(dev->bus, res, &bus_region);
Yinghai Lu65195c72013-04-12 12:44:15 +0000397
398 if (!pci_claim_resource(dev, nr))
399 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
400}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401
402/*
403 * ATI Northbridge setups MCE the processor if you even
404 * read somewhere between 0x3b0->0x3bb or read 0x3d3
405 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500406static void quirk_ati_exploding_mce(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700408 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
410 request_region(0x3b0, 0x0C, "RadeonIGP");
411 request_region(0x3d3, 0x01, "RadeonIGP");
412}
Andrew Morton652c5382007-11-21 15:07:13 -0800413DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414
415/*
Huang Ruibe6646b2014-10-31 11:11:16 +0800416 * In the AMD NL platform, this device ([1022:7912]) has a class code of
417 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
418 * claim it.
419 * But the dwc3 driver is a more specific driver for this device, and we'd
420 * prefer to use it instead of xhci. To prevent xhci from claiming the
421 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
422 * defines as "USB device (not host controller)". The dwc3 driver can then
423 * claim it based on its Vendor and Device ID.
424 */
425static void quirk_amd_nl_class(struct pci_dev *pdev)
426{
Bjorn Helgaascd76d102015-06-19 15:28:31 -0500427 u32 class = pdev->class;
428
429 /* Use "USB Device (not host controller)" class */
430 pdev->class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe;
431 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
432 class, pdev->class);
Huang Ruibe6646b2014-10-31 11:11:16 +0800433}
434DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
435 quirk_amd_nl_class);
436
437/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 * Let's make the southbridge information explicit instead
439 * of having to worry about people probing the ACPI areas,
440 * for example.. (Yes, it happens, and if you read the wrong
441 * ACPI register it will put the machine to sleep with no
442 * way of waking it up again. Bummer).
443 *
444 * ALI M7101: Two IO regions pointed to by words at
445 * 0xE0 (64 bytes of ACPI registers)
446 * 0xE2 (32 bytes of SMB registers)
447 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500448static void quirk_ali7101_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449{
Yinghai Lu65195c72013-04-12 12:44:15 +0000450 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
451 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452}
Andrew Morton652c5382007-11-21 15:07:13 -0800453DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454
Linus Torvalds6693e742005-10-25 20:40:09 -0700455static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
456{
457 u32 devres;
458 u32 mask, size, base;
459
460 pci_read_config_dword(dev, port, &devres);
461 if ((devres & enable) != enable)
462 return;
463 mask = (devres >> 16) & 15;
464 base = devres & 0xffff;
465 size = 16;
466 for (;;) {
467 unsigned bit = size >> 1;
468 if ((bit & mask) == bit)
469 break;
470 size = bit;
471 }
472 /*
473 * For now we only print it out. Eventually we'll want to
474 * reserve it (at least if it's in the 0x1000+ range), but
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700475 * let's get enough confirmation reports first.
Linus Torvalds6693e742005-10-25 20:40:09 -0700476 */
477 base &= -size;
Ryan Desfosses227f0642014-04-18 20:13:50 -0400478 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
479 base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700480}
481
482static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
483{
484 u32 devres;
485 u32 mask, size, base;
486
487 pci_read_config_dword(dev, port, &devres);
488 if ((devres & enable) != enable)
489 return;
490 base = devres & 0xffff0000;
491 mask = (devres & 0x3f) << 16;
492 size = 128 << 16;
493 for (;;) {
494 unsigned bit = size >> 1;
495 if ((bit & mask) == bit)
496 break;
497 size = bit;
498 }
499 /*
500 * For now we only print it out. Eventually we'll want to
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700501 * reserve it, but let's get enough confirmation reports first.
Linus Torvalds6693e742005-10-25 20:40:09 -0700502 */
503 base &= -size;
Ryan Desfosses227f0642014-04-18 20:13:50 -0400504 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
505 base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700506}
507
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508/*
509 * PIIX4 ACPI: Two IO regions pointed to by longwords at
510 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800511 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700512 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500514static void quirk_piix4_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515{
Yinghai Lu65195c72013-04-12 12:44:15 +0000516 u32 res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517
Yinghai Lu65195c72013-04-12 12:44:15 +0000518 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
519 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700520
521 /* Device resource A has enables for some of the other ones */
522 pci_read_config_dword(dev, 0x5c, &res_a);
523
524 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
525 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
526
527 /* Device resource D is just bitfields for static resources */
528
529 /* Device 12 enabled? */
530 if (res_a & (1 << 29)) {
531 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
532 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
533 }
534 /* Device 13 enabled? */
535 if (res_a & (1 << 30)) {
536 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
537 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
538 }
539 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
540 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541}
Andrew Morton652c5382007-11-21 15:07:13 -0800542DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
543DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544
Jiri Slabycdb97552011-02-28 10:45:09 +0100545#define ICH_PMBASE 0x40
546#define ICH_ACPI_CNTL 0x44
547#define ICH4_ACPI_EN 0x10
548#define ICH6_ACPI_EN 0x80
549#define ICH4_GPIOBASE 0x58
550#define ICH4_GPIO_CNTL 0x5c
551#define ICH4_GPIO_EN 0x10
552#define ICH6_GPIOBASE 0x48
553#define ICH6_GPIO_CNTL 0x4c
554#define ICH6_GPIO_EN 0x10
555
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556/*
557 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
558 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
559 * 0x58 (64 bytes of GPIO I/O space)
560 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500561static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562{
Jiri Slabycdb97552011-02-28 10:45:09 +0100563 u8 enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100565 /*
566 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
567 * with low legacy (and fixed) ports. We don't know the decoding
568 * priority and can't tell whether the legacy device or the one created
569 * here is really at that address. This happens on boards with broken
570 * BIOSes.
571 */
572
Jiri Slabycdb97552011-02-28 10:45:09 +0100573 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000574 if (enable & ICH4_ACPI_EN)
575 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
576 "ICH4 ACPI/GPIO/TCO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577
Jiri Slabycdb97552011-02-28 10:45:09 +0100578 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000579 if (enable & ICH4_GPIO_EN)
580 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
581 "ICH4 GPIO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582}
Andrew Morton652c5382007-11-21 15:07:13 -0800583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
585DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593
Bill Pemberton15856ad2012-11-21 15:35:00 -0500594static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000595{
Jiri Slabycdb97552011-02-28 10:45:09 +0100596 u8 enable;
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000597
Jiri Slabycdb97552011-02-28 10:45:09 +0100598 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000599 if (enable & ICH6_ACPI_EN)
600 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
601 "ICH6 ACPI/GPIO/TCO");
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000602
Jiri Slabycdb97552011-02-28 10:45:09 +0100603 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000604 if (enable & ICH6_GPIO_EN)
605 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
606 "ICH6 GPIO");
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000607}
Linus Torvalds894886e2008-12-06 10:10:10 -0800608
Bill Pemberton15856ad2012-11-21 15:35:00 -0500609static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
Linus Torvalds894886e2008-12-06 10:10:10 -0800610{
611 u32 val;
612 u32 size, base;
613
614 pci_read_config_dword(dev, reg, &val);
615
616 /* Enabled? */
617 if (!(val & 1))
618 return;
619 base = val & 0xfffc;
620 if (dynsize) {
621 /*
622 * This is not correct. It is 16, 32 or 64 bytes depending on
623 * register D31:F0:ADh bits 5:4.
624 *
625 * But this gets us at least _part_ of it.
626 */
627 size = 16;
628 } else {
629 size = 128;
630 }
631 base &= ~(size-1);
632
633 /* Just print it out for now. We should reserve it after more debugging */
634 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
635}
636
Bill Pemberton15856ad2012-11-21 15:35:00 -0500637static void quirk_ich6_lpc(struct pci_dev *dev)
Linus Torvalds894886e2008-12-06 10:10:10 -0800638{
639 /* Shared ACPI/GPIO decode with all ICH6+ */
640 ich6_lpc_acpi_gpio(dev);
641
642 /* ICH6-specific generic IO decode */
643 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
644 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
645}
646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
647DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
648
Bill Pemberton15856ad2012-11-21 15:35:00 -0500649static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
Linus Torvalds894886e2008-12-06 10:10:10 -0800650{
651 u32 val;
652 u32 mask, base;
653
654 pci_read_config_dword(dev, reg, &val);
655
656 /* Enabled? */
657 if (!(val & 1))
658 return;
659
660 /*
661 * IO base in bits 15:2, mask in bits 23:18, both
662 * are dword-based
663 */
664 base = val & 0xfffc;
665 mask = (val >> 16) & 0xfc;
666 mask |= 3;
667
668 /* Just print it out for now. We should reserve it after more debugging */
669 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
670}
671
672/* ICH7-10 has the same common LPC generic IO decode registers */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500673static void quirk_ich7_lpc(struct pci_dev *dev)
Linus Torvalds894886e2008-12-06 10:10:10 -0800674{
Jean Delvare5d9c0a72011-04-15 10:03:53 +0200675 /* We share the common ACPI/GPIO decode with ICH6 */
Linus Torvalds894886e2008-12-06 10:10:10 -0800676 ich6_lpc_acpi_gpio(dev);
677
678 /* And have 4 ICH7+ generic decodes */
679 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
680 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
681 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
682 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
683}
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
685DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
686DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
687DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
688DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
689DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
690DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
691DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
692DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
693DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
694DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000697
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698/*
699 * VIA ACPI: One IO region pointed to by longword at
700 * 0x48 or 0x20 (256 bytes of ACPI registers)
701 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500702static void quirk_vt82c586_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703{
Yinghai Lu65195c72013-04-12 12:44:15 +0000704 if (dev->revision & 0x10)
705 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
706 "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707}
Andrew Morton652c5382007-11-21 15:07:13 -0800708DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709
710/*
711 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
712 * 0x48 (256 bytes of ACPI registers)
713 * 0x70 (128 bytes of hardware monitoring register)
714 * 0x90 (16 bytes of SMB registers)
715 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500716static void quirk_vt82c686_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 quirk_vt82c586_acpi(dev);
719
Yinghai Lu65195c72013-04-12 12:44:15 +0000720 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
721 "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722
Yinghai Lu65195c72013-04-12 12:44:15 +0000723 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724}
Andrew Morton652c5382007-11-21 15:07:13 -0800725DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400727/*
728 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
729 * 0x88 (128 bytes of power management registers)
730 * 0xd0 (16 bytes of SMB registers)
731 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500732static void quirk_vt8235_acpi(struct pci_dev *dev)
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400733{
Yinghai Lu65195c72013-04-12 12:44:15 +0000734 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
735 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400736}
737DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
738
Gabe Black1f56f4a2009-10-06 09:19:45 -0500739/*
740 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
741 * Disable fast back-to-back on the secondary bus segment
742 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500743static void quirk_xio2000a(struct pci_dev *dev)
Gabe Black1f56f4a2009-10-06 09:19:45 -0500744{
745 struct pci_dev *pdev;
746 u16 command;
747
Ryan Desfosses227f0642014-04-18 20:13:50 -0400748 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
Gabe Black1f56f4a2009-10-06 09:19:45 -0500749 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
750 pci_read_config_word(pdev, PCI_COMMAND, &command);
751 if (command & PCI_COMMAND_FAST_BACK)
752 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
753 }
754}
755DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
756 quirk_xio2000a);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700758#ifdef CONFIG_X86_IO_APIC
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759
760#include <asm/io_apic.h>
761
762/*
763 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
764 * devices to the external APIC.
765 *
766 * TODO: When we have device-specific interrupt routers,
767 * this code will go away from quirks.
768 */
Alan Cox1597cac2006-12-04 15:14:45 -0800769static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770{
771 u8 tmp;
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700772
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773 if (nr_ioapics < 1)
774 tmp = 0; /* nothing routed to external APIC */
775 else
776 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700777
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700778 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779 tmp == 0 ? "Disa" : "Ena");
780
781 /* Offset 0x58: External APIC IRQ output control */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400782 pci_write_config_byte(dev, 0x58, tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783}
Andrew Morton652c5382007-11-21 15:07:13 -0800784DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200785DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786
787/*
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700788 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
Karsten Wiesea1740912005-09-03 15:56:33 -0700789 * This leads to doubled level interrupt rates.
790 * Set this bit to get rid of cycle wastage.
791 * Otherwise uncritical.
792 */
Alan Cox1597cac2006-12-04 15:14:45 -0800793static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700794{
795 u8 misc_control2;
796#define BYPASS_APIC_DEASSERT 8
797
798 pci_read_config_byte(dev, 0x5B, &misc_control2);
799 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700800 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700801 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
802 }
803}
804DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200805DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700806
807/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808 * The AMD io apic can hang the box when an apic irq is masked.
809 * We check all revs >= B0 (yet not in the pre production!) as the bug
810 * is currently marked NoFix
811 *
812 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700813 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 * of course. However the advice is demonstrably good even if so..
815 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500816static void quirk_amd_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817{
Auke Kok44c10132007-06-08 15:46:36 -0700818 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700819 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
820 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821 }
822}
Andrew Morton652c5382007-11-21 15:07:13 -0800823DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824#endif /* CONFIG_X86_IO_APIC */
825
Peter Orubad556ad42007-05-15 13:59:13 +0200826/*
827 * Some settings of MMRBC can lead to data corruption so block changes.
828 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
829 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500830static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
Peter Orubad556ad42007-05-15 13:59:13 +0200831{
Auke Kokaa288d42007-08-27 16:17:47 -0700832 if (dev->subordinate && dev->revision <= 0x12) {
Ryan Desfosses227f0642014-04-18 20:13:50 -0400833 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
834 dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200835 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
836 }
837}
838DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839
840/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 * FIXME: it is questionable that quirk_via_acpi
842 * is needed. It shows up as an ISA bridge, and does not
843 * support the PCI_INTERRUPT_LINE register at all. Therefore
844 * it seems like setting the pci_dev's 'irq' to the
845 * value of the ACPI SCI interrupt is only done for convenience.
846 * -jgarzik
847 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500848static void quirk_via_acpi(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849{
850 /*
851 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
852 */
853 u8 irq;
854 pci_read_config_byte(d, 0x42, &irq);
855 irq &= 0xf;
856 if (irq && (irq != 2))
857 d->irq = irq;
858}
Andrew Morton652c5382007-11-21 15:07:13 -0800859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861
Daniel Drake09d60292006-09-25 16:52:19 -0700862
863/*
Alan Cox1597cac2006-12-04 15:14:45 -0800864 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700865 */
Alan Cox1597cac2006-12-04 15:14:45 -0800866
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800867static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
868
869static void quirk_via_bridge(struct pci_dev *dev)
870{
871 /* See what bridge we have and find the device ranges */
872 switch (dev->device) {
873 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800874 /* The VT82C686 is special, it attaches to PCI and can have
875 any device number. All its subdevices are functions of
876 that single device. */
877 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
878 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800879 break;
880 case PCI_DEVICE_ID_VIA_8237:
881 case PCI_DEVICE_ID_VIA_8237A:
882 via_vlink_dev_lo = 15;
883 break;
884 case PCI_DEVICE_ID_VIA_8235:
885 via_vlink_dev_lo = 16;
886 break;
887 case PCI_DEVICE_ID_VIA_8231:
888 case PCI_DEVICE_ID_VIA_8233_0:
889 case PCI_DEVICE_ID_VIA_8233A:
890 case PCI_DEVICE_ID_VIA_8233C_0:
891 via_vlink_dev_lo = 17;
892 break;
893 }
894}
895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700903
Alan Cox1597cac2006-12-04 15:14:45 -0800904/**
905 * quirk_via_vlink - VIA VLink IRQ number update
906 * @dev: PCI device
907 *
908 * If the device we are dealing with is on a PIC IRQ we need to
909 * ensure that the IRQ line register which usually is not relevant
910 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800911 * to the right place.
912 * We only do this on systems where a VIA south bridge was detected,
913 * and only for VIA devices on the motherboard (see quirk_via_bridge
914 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800915 */
916
917static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400918{
919 u8 irq, new_irq;
920
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800921 /* Check if we have VLink at all */
922 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700923 return;
924
925 new_irq = dev->irq;
926
927 /* Don't quirk interrupts outside the legacy IRQ range */
928 if (!new_irq || new_irq > 15)
929 return;
930
Alan Cox1597cac2006-12-04 15:14:45 -0800931 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800932 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
933 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800934 return;
935
936 /* This is an internal VLink device on a PIC interrupt. The BIOS
937 ought to have set this but may not have, so we redo it */
938
Len Brown25be5e62005-05-27 04:21:50 -0400939 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
940 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700941 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
942 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400943 udelay(15); /* unknown if delay really needed */
944 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
945 }
946}
Alan Cox1597cac2006-12-04 15:14:45 -0800947DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400948
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950 * VIA VT82C598 has its device ID settable and many BIOSes
951 * set it to the ID of VT82C597 for backward compatibility.
952 * We need to switch it off to be able to recognize the real
953 * type of the chip.
954 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500955static void quirk_vt82c598_id(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956{
957 pci_write_config_byte(dev, 0xfc, 0);
958 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
959}
Andrew Morton652c5382007-11-21 15:07:13 -0800960DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961
962/*
963 * CardBus controllers have a legacy base address that enables them
964 * to respond as i82365 pcmcia controllers. We don't want them to
965 * do this even if the Linux CardBus driver is not loaded, because
966 * the Linux i82365 driver does not (and should not) handle CardBus.
967 */
Alan Cox1597cac2006-12-04 15:14:45 -0800968static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700970 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
971}
Yinghai Luae9de562012-02-23 23:46:54 -0800972DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
973 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
974DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
975 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976
977/*
978 * Following the PCI ordering rules is optional on the AMD762. I'm not
979 * sure what the designers were smoking but let's not inhale...
980 *
981 * To be fair to AMD, it follows the spec by default, its BIOS people
982 * who turn it off!
983 */
Alan Cox1597cac2006-12-04 15:14:45 -0800984static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985{
986 u32 pcic;
987 pci_read_config_dword(dev, 0x4C, &pcic);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400988 if ((pcic & 6) != 6) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700990 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991 pci_write_config_dword(dev, 0x4C, pcic);
992 pci_read_config_dword(dev, 0x84, &pcic);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400993 pcic |= (1 << 23); /* Required in this mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994 pci_write_config_dword(dev, 0x84, pcic);
995 }
996}
Andrew Morton652c5382007-11-21 15:07:13 -0800997DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200998DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999
1000/*
1001 * DreamWorks provided workaround for Dunord I-3000 problem
1002 *
1003 * This card decodes and responds to addresses not apparently
1004 * assigned to it. We force a larger allocation to ensure that
1005 * nothing gets put too close to it.
1006 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001007static void quirk_dunord(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001009 struct resource *r = &dev->resource[1];
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001010
1011 r->flags |= IORESOURCE_UNSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012 r->start = 0;
1013 r->end = 0xffffff;
1014}
Andrew Morton652c5382007-11-21 15:07:13 -08001015DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016
1017/*
1018 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1019 * is subtractive decoding (transparent), and does indicate this
1020 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1021 * instead of 0x01.
1022 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001023static void quirk_transparent_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024{
1025 dev->transparent = 1;
1026}
Andrew Morton652c5382007-11-21 15:07:13 -08001027DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1028DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029
1030/*
1031 * Common misconfiguration of the MediaGX/Geode PCI master that will
1032 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
Justin P. Mattock631dd1a2010-10-18 11:03:14 +02001033 * datasheets found at http://www.national.com/analog for info on what
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034 * these bits do. <christer@weinigel.se>
1035 */
Alan Cox1597cac2006-12-04 15:14:45 -08001036static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037{
1038 u8 reg;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001039
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040 pci_read_config_byte(dev, 0x41, &reg);
1041 if (reg & 2) {
1042 reg &= ~2;
Ryan Desfosses227f0642014-04-18 20:13:50 -04001043 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1044 reg);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001045 pci_write_config_byte(dev, 0x41, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 }
1047}
Andrew Morton652c5382007-11-21 15:07:13 -08001048DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1049DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050
1051/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 * Ensure C0 rev restreaming is off. This is normally done by
1053 * the BIOS but in the odd case it is not the results are corruption
1054 * hence the presence of a Linux check
1055 */
Alan Cox1597cac2006-12-04 15:14:45 -08001056static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057{
1058 u16 config;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001059
Auke Kok44c10132007-06-08 15:46:36 -07001060 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 return;
1062 pci_read_config_word(pdev, 0x40, &config);
1063 if (config & (1<<6)) {
1064 config &= ~(1<<6);
1065 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001066 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067 }
1068}
Andrew Morton652c5382007-11-21 15:07:13 -08001069DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001070DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001071
Myron Stowe25e742b2012-07-09 15:36:14 -06001072static void quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -08001073{
Shane Huang5deab532009-10-13 11:14:00 +08001074 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
Crane Cai05a7d222008-02-02 13:56:56 +08001075 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -08001076
Crane Cai05a7d222008-02-02 13:56:56 +08001077 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1078 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -08001079 pci_read_config_byte(pdev, 0x40, &tmp);
1080 pci_write_config_byte(pdev, 0x40, tmp|1);
1081 pci_write_config_byte(pdev, 0x9, 1);
1082 pci_write_config_byte(pdev, 0xa, 6);
1083 pci_write_config_byte(pdev, 0x40, tmp);
1084
Conke Huc9f89472007-01-09 05:32:51 -05001085 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +08001086 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -08001087 }
1088}
Crane Cai05a7d222008-02-02 13:56:56 +08001089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001090DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +08001091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001092DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Shane Huang5deab532009-10-13 11:14:00 +08001093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1094DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
Shane Huangfafe5c3d82013-06-03 18:24:10 +08001095DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1096DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -08001097
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098/*
1099 * Serverworks CSB5 IDE does not fully support native mode
1100 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001101static void quirk_svwks_csb5ide(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102{
1103 u8 prog;
1104 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1105 if (prog & 5) {
1106 prog &= ~5;
1107 pdev->class &= ~5;
1108 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +01001109 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110 }
1111}
Andrew Morton652c5382007-11-21 15:07:13 -08001112DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113
1114/*
1115 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1116 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001117static void quirk_ide_samemode(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118{
1119 u8 prog;
1120
1121 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1122
1123 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001124 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125 prog &= ~5;
1126 pdev->class &= ~5;
1127 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128 }
1129}
Alan Cox368c73d2006-10-04 00:41:26 +01001130DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001131
Alan Cox979b1792008-07-24 17:18:38 +01001132/*
1133 * Some ATA devices break if put into D3
1134 */
1135
Bill Pemberton15856ad2012-11-21 15:35:00 -05001136static void quirk_no_ata_d3(struct pci_dev *pdev)
Alan Cox979b1792008-07-24 17:18:38 +01001137{
Yinghai Lufaa738b2012-02-23 23:46:55 -08001138 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
Alan Cox979b1792008-07-24 17:18:38 +01001139}
Yinghai Lufaa738b2012-02-23 23:46:55 -08001140/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1141DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1142 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1143DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1144 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001145/* ALi loses some register settings that we cannot then restore */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001146DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1147 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001148/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1149 occur when mode detecting */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001150DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1151 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox979b1792008-07-24 17:18:38 +01001152
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153/* This was originally an Alpha specific thing, but it really fits here.
1154 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1155 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001156static void quirk_eisa_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157{
1158 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1159}
Andrew Morton652c5382007-11-21 15:07:13 -08001160DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161
Johannes Goecke7daa0c42006-04-20 02:43:17 -07001162
1163/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1165 * is not activated. The myth is that Asus said that they do not want the
1166 * users to be irritated by just another PCI Device in the Win98 device
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001167 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168 * package 2.7.0 for details)
1169 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001170 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1171 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001172 * becomes necessary to do this tweak in two steps -- the chosen trigger
1173 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +01001174 *
1175 * Note that we used to unhide the SMBus that way on Toshiba laptops
1176 * (Satellite A40 and Tecra M2) but then found that the thermal management
1177 * was done by SMM code, which could cause unsynchronized concurrent
1178 * accesses to the SMBus registers, with potentially bad effects. Thus you
1179 * should be very careful when adding new entries: if SMM is accessing the
1180 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -07001181 *
1182 * Likewise, many recent laptops use ACPI for thermal management. If the
1183 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1184 * natively, and keeping the SMBus hidden is the right thing to do. If you
1185 * are about to add an entry in the table below, please first disassemble
1186 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187 */
Vivek Goyal9d24a812007-01-11 01:52:44 +01001188static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001189
Bill Pemberton15856ad2012-11-21 15:35:00 -05001190static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191{
1192 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1193 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001194 switch (dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +02001195 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196 case 0x8070: /* P4B */
1197 case 0x8088: /* P4B533 */
1198 case 0x1626: /* L3C notebook */
1199 asus_hides_smbus = 1;
1200 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001201 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001202 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203 case 0x80b1: /* P4GE-V */
1204 case 0x80b2: /* P4PE */
1205 case 0x8093: /* P4B533-V */
1206 asus_hides_smbus = 1;
1207 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001208 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001209 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 case 0x8030: /* P4T533 */
1211 asus_hides_smbus = 1;
1212 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001213 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214 switch (dev->subsystem_device) {
1215 case 0x8070: /* P4G8X Deluxe */
1216 asus_hides_smbus = 1;
1217 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001218 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +02001219 switch (dev->subsystem_device) {
1220 case 0x80c9: /* PU-DLS */
1221 asus_hides_smbus = 1;
1222 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001223 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224 switch (dev->subsystem_device) {
1225 case 0x1751: /* M2N notebook */
1226 case 0x1821: /* M5N notebook */
Mats Erik Andersson4096ed02009-05-12 12:05:23 +02001227 case 0x1897: /* A6L notebook */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228 asus_hides_smbus = 1;
1229 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001230 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231 switch (dev->subsystem_device) {
1232 case 0x184b: /* W1N notebook */
1233 case 0x186a: /* M6Ne notebook */
1234 asus_hides_smbus = 1;
1235 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001236 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001237 switch (dev->subsystem_device) {
1238 case 0x80f2: /* P4P800-X */
1239 asus_hides_smbus = 1;
1240 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001241 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001242 switch (dev->subsystem_device) {
1243 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001244 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001245 asus_hides_smbus = 1;
1246 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1248 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001249 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250 case 0x088C: /* HP Compaq nc8000 */
1251 case 0x0890: /* HP Compaq nc6000 */
1252 asus_hides_smbus = 1;
1253 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001254 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255 switch (dev->subsystem_device) {
1256 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001257 case 0x12bd: /* HP D530 */
Michal Miroslaw74c57422009-05-12 13:49:25 -07001258 case 0x006a: /* HP Compaq nx9500 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001259 asus_hides_smbus = 1;
1260 }
Jean Delvare677cc642007-11-21 18:29:06 +01001261 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1262 switch (dev->subsystem_device) {
1263 case 0x12bf: /* HP xw4100 */
1264 asus_hides_smbus = 1;
1265 }
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001266 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1267 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1268 switch (dev->subsystem_device) {
1269 case 0xC00C: /* Samsung P35 notebook */
1270 asus_hides_smbus = 1;
1271 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001272 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1273 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001274 switch (dev->subsystem_device) {
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001275 case 0x0058: /* Compaq Evo N620c */
1276 asus_hides_smbus = 1;
1277 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001278 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001279 switch (dev->subsystem_device) {
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001280 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1281 /* Motherboard doesn't have Host bridge
1282 * subvendor/subdevice IDs, therefore checking
1283 * its on-board VGA controller */
1284 asus_hides_smbus = 1;
1285 }
David O'Shea8293b0f2009-03-02 09:51:13 +01001286 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001287 switch (dev->subsystem_device) {
Jean Delvare10260d92008-06-04 13:53:31 +02001288 case 0x00b8: /* Compaq Evo D510 CMT */
1289 case 0x00b9: /* Compaq Evo D510 SFF */
Jean Delvare6b5096e2009-07-28 11:49:19 +02001290 case 0x00ba: /* Compaq Evo D510 USDT */
David O'Shea8293b0f2009-03-02 09:51:13 +01001291 /* Motherboard doesn't have Host bridge
1292 * subvendor/subdevice IDs and on-board VGA
1293 * controller is disabled if an AGP card is
1294 * inserted, therefore checking USB UHCI
1295 * Controller #1 */
Jean Delvare10260d92008-06-04 13:53:31 +02001296 asus_hides_smbus = 1;
1297 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001298 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1299 switch (dev->subsystem_device) {
1300 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1301 /* Motherboard doesn't have host bridge
1302 * subvendor/subdevice IDs, therefore checking
1303 * its on-board VGA controller */
1304 asus_hides_smbus = 1;
1305 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306 }
1307}
Andrew Morton652c5382007-11-21 15:07:13 -08001308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1316DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1317DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001318
Andrew Morton652c5382007-11-21 15:07:13 -08001319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
David O'Shea8293b0f2009-03-02 09:51:13 +01001320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001322
Alan Cox1597cac2006-12-04 15:14:45 -08001323static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324{
1325 u16 val;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001326
Linus Torvalds1da177e2005-04-16 15:20:36 -07001327 if (likely(!asus_hides_smbus))
1328 return;
1329
1330 pci_read_config_word(dev, 0xF2, &val);
1331 if (val & 0x8) {
1332 pci_write_config_word(dev, 0xF2, val & (~0x8));
1333 pci_read_config_word(dev, 0xF2, &val);
1334 if (val & 0x8)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001335 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1336 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001338 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339 }
1340}
Andrew Morton652c5382007-11-21 15:07:13 -08001341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001348DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1349DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1350DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1351DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1352DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1353DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1354DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001356/* It appears we just have one such device. If not, we have a warning */
1357static void __iomem *asus_rcba_base;
1358static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001359{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001360 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001361
1362 if (likely(!asus_hides_smbus))
1363 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001364 WARN_ON(asus_rcba_base);
1365
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001366 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001367 /* use bits 31:14, 16 kB aligned */
1368 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1369 if (asus_rcba_base == NULL)
1370 return;
1371}
1372
1373static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1374{
1375 u32 val;
1376
1377 if (likely(!asus_hides_smbus || !asus_rcba_base))
1378 return;
1379 /* read the Function Disable register, dword mode only */
1380 val = readl(asus_rcba_base + 0x3418);
1381 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1382}
1383
1384static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1385{
1386 if (likely(!asus_hides_smbus || !asus_rcba_base))
1387 return;
1388 iounmap(asus_rcba_base);
1389 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001390 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001391}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001392
1393static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1394{
1395 asus_hides_smbus_lpc_ich6_suspend(dev);
1396 asus_hides_smbus_lpc_ich6_resume_early(dev);
1397 asus_hides_smbus_lpc_ich6_resume(dev);
1398}
Andrew Morton652c5382007-11-21 15:07:13 -08001399DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001400DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1401DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1402DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001403
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404/*
1405 * SiS 96x south bridge: BIOS typically hides SMBus device...
1406 */
Alan Cox1597cac2006-12-04 15:14:45 -08001407static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408{
1409 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001411 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001412 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001413 pci_write_config_byte(dev, 0x77, val & ~0x10);
1414 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415}
Andrew Morton652c5382007-11-21 15:07:13 -08001416DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1417DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1418DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1419DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001420DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1421DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1422DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1423DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425/*
1426 * ... This is further complicated by the fact that some SiS96x south
1427 * bridges pretend to be 85C503/5513 instead. In that case see if we
1428 * spotted a compatible north bridge to make sure.
1429 * (pci_find_device doesn't work yet)
1430 *
1431 * We can also enable the sis96x bit in the discovery register..
1432 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433#define SIS_DETECT_REGISTER 0x40
1434
Alan Cox1597cac2006-12-04 15:14:45 -08001435static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436{
1437 u8 reg;
1438 u16 devid;
1439
1440 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1441 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1442 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1443 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1444 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1445 return;
1446 }
1447
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001449 * Ok, it now shows up as a 96x.. run the 96x quirk by
1450 * hand in case it has already been processed.
1451 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452 */
1453 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001454 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455}
Andrew Morton652c5382007-11-21 15:07:13 -08001456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001457DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001460/*
1461 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1462 * and MC97 modem controller are disabled when a second PCI soundcard is
1463 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1464 * -- bjd
1465 */
Alan Cox1597cac2006-12-04 15:14:45 -08001466static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001467{
1468 u8 val;
1469 int asus_hides_ac97 = 0;
1470
1471 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1472 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1473 asus_hides_ac97 = 1;
1474 }
1475
1476 if (!asus_hides_ac97)
1477 return;
1478
1479 pci_read_config_byte(dev, 0x50, &val);
1480 if (val & 0xc0) {
1481 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1482 pci_read_config_byte(dev, 0x50, &val);
1483 if (val & 0xc0)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001484 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1485 val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001486 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001487 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001488 }
1489}
Andrew Morton652c5382007-11-21 15:07:13 -08001490DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001491DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001492
Tejun Heo77967052006-08-19 03:54:39 +09001493#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001494
1495/*
1496 * If we are using libata we can drive this chip properly but must
1497 * do this early on to make the additional device appear during
1498 * the PCI scanning.
1499 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001500static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001501{
Tejun Heoe34bb372007-02-26 20:24:03 +09001502 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001503 u8 hdr;
1504
1505 /* Only poke fn 0 */
1506 if (PCI_FUNC(pdev->devfn))
1507 return;
1508
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001509 pci_read_config_dword(pdev, 0x40, &conf1);
1510 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001511
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001512 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1513 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001514
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001515 switch (pdev->device) {
Tejun Heo4daedcf2010-06-03 11:57:04 +02001516 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1517 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001518 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001519 /* The controller should be in single function ahci mode */
1520 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1521 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001522
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001523 case PCI_DEVICE_ID_JMICRON_JMB365:
1524 case PCI_DEVICE_ID_JMICRON_JMB366:
1525 /* Redirect IDE second PATA port to the right spot */
1526 conf5 |= (1 << 24);
1527 /* Fall through */
1528 case PCI_DEVICE_ID_JMICRON_JMB361:
1529 case PCI_DEVICE_ID_JMICRON_JMB363:
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001530 case PCI_DEVICE_ID_JMICRON_JMB369:
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001531 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1532 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001533 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001534 break;
1535
1536 case PCI_DEVICE_ID_JMICRON_JMB368:
1537 /* The controller should be in single function IDE mode */
1538 conf1 |= 0x00C00000; /* Set 22, 23 */
1539 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001540 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001541
1542 pci_write_config_dword(pdev, 0x40, conf1);
1543 pci_write_config_dword(pdev, 0x80, conf5);
1544
1545 /* Update pdev accordingly */
1546 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1547 pdev->hdr_type = hdr & 0x7f;
1548 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001549
1550 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1551 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001552}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001553DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1554DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001555DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001556DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001557DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001558DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1559DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1560DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001561DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001562DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1563DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001564DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001565DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001566DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001567DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1568DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1569DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001570DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001571
1572#endif
1573
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574#ifdef CONFIG_X86_IO_APIC
Bill Pemberton15856ad2012-11-21 15:35:00 -05001575static void quirk_alder_ioapic(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576{
1577 int i;
1578
1579 if ((pdev->class >> 8) != 0xff00)
1580 return;
1581
1582 /* the first BAR is the location of the IO APIC...we must
1583 * not touch this (and it's already covered by the fixmap), so
1584 * forcibly insert it into the resource tree */
1585 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1586 insert_resource(&iomem_resource, &pdev->resource[0]);
1587
1588 /* The next five BARs all seem to be rubbish, so just clean
1589 * them out */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001590 for (i = 1; i < 6; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001592}
Andrew Morton652c5382007-11-21 15:07:13 -08001593DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594#endif
1595
Bill Pemberton15856ad2012-11-21 15:35:00 -05001596static void quirk_pcie_mch(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597{
Eric W. Biederman0ba379e2009-09-06 21:48:35 -07001598 pdev->no_msi = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599}
Andrew Morton652c5382007-11-21 15:07:13 -08001600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603
Kristen Accardi4602b882005-08-16 15:15:58 -07001604
1605/*
1606 * It's possible for the MSI to get corrupted if shpc and acpi
1607 * are used together on certain PXH-based systems.
1608 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001609static void quirk_pcie_pxh(struct pci_dev *dev)
Kristen Accardi4602b882005-08-16 15:15:58 -07001610{
Kristen Accardi4602b882005-08-16 15:15:58 -07001611 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001612 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001613}
1614DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1615DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1616DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1617DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1618DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1619
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001620/*
1621 * Some Intel PCI Express chipsets have trouble with downstream
1622 * device power management.
1623 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001624static void quirk_intel_pcie_pm(struct pci_dev *dev)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001625{
1626 pci_pm_d3_delay = 120;
1627 dev->no_d1d2 = 1;
1628}
1629
1630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1646DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1647DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1648DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001651
Stefan Assmann426b3b82008-06-11 16:35:16 +02001652#ifdef CONFIG_X86_IO_APIC
1653/*
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001654 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1655 * remap the original interrupt in the linux kernel to the boot interrupt, so
1656 * that a PCI device's interrupt handler is installed on the boot interrupt
1657 * line instead.
1658 */
1659static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1660{
Stefan Assmann41b9eb22008-07-15 13:48:55 +02001661 if (noioapicquirk || noioapicreroute)
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001662 return;
1663
1664 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001665 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1666 dev->vendor, dev->device);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001667}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1676DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1677DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1678DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1679DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1680DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1681DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1682DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1683DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001684
1685/*
Stefan Assmann426b3b82008-06-11 16:35:16 +02001686 * On some chipsets we can disable the generation of legacy INTx boot
1687 * interrupts.
1688 */
1689
1690/*
1691 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1692 * 300641-004US, section 5.7.3.
1693 */
1694#define INTEL_6300_IOAPIC_ABAR 0x40
1695#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1696
1697static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1698{
1699 u16 pci_config_word;
1700
1701 if (noioapicquirk)
1702 return;
1703
1704 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1705 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1706 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1707
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001708 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1709 dev->vendor, dev->device);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001710}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1712DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001713
1714/*
1715 * disable boot interrupts on HT-1000
1716 */
1717#define BC_HT1000_FEATURE_REG 0x64
1718#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1719#define BC_HT1000_MAP_IDX 0xC00
1720#define BC_HT1000_MAP_DATA 0xC01
1721
1722static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1723{
1724 u32 pci_config_dword;
1725 u8 irq;
1726
1727 if (noioapicquirk)
1728 return;
1729
1730 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1731 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1732 BC_HT1000_PIC_REGS_ENABLE);
1733
1734 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1735 outb(irq, BC_HT1000_MAP_IDX);
1736 outb(0x00, BC_HT1000_MAP_DATA);
1737 }
1738
1739 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1740
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001741 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1742 dev->vendor, dev->device);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001743}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001744DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1745DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001746
1747/*
1748 * disable boot interrupts on AMD and ATI chipsets
1749 */
1750/*
1751 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1752 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1753 * (due to an erratum).
1754 */
1755#define AMD_813X_MISC 0x40
1756#define AMD_813X_NOIOAMODE (1<<0)
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001757#define AMD_813X_REV_B1 0x12
Stefan Assmannbbe19442009-02-26 10:46:48 -08001758#define AMD_813X_REV_B2 0x13
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001759
1760static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1761{
1762 u32 pci_config_dword;
1763
1764 if (noioapicquirk)
1765 return;
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001766 if ((dev->revision == AMD_813X_REV_B1) ||
1767 (dev->revision == AMD_813X_REV_B2))
Stefan Assmannbbe19442009-02-26 10:46:48 -08001768 return;
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001769
1770 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1771 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1772 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1773
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001774 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1775 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001776}
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001777DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1778DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1779DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1780DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001781
1782#define AMD_8111_PCI_IRQ_ROUTING 0x56
1783
1784static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1785{
1786 u16 pci_config_word;
1787
1788 if (noioapicquirk)
1789 return;
1790
1791 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1792 if (!pci_config_word) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001793 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1794 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001795 return;
1796 }
1797 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001798 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1799 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001800}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001801DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1802DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001803#endif /* CONFIG_X86_IO_APIC */
1804
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001805/*
1806 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1807 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1808 * Re-allocate the region if needed...
1809 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001810static void quirk_tc86c001_ide(struct pci_dev *dev)
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001811{
1812 struct resource *r = &dev->resource[0];
1813
1814 if (r->start & 0x8) {
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001815 r->flags |= IORESOURCE_UNSET;
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001816 r->start = 0;
1817 r->end = 0xf;
1818 }
1819}
1820DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1821 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1822 quirk_tc86c001_ide);
1823
Ian Abbott21c5fd92012-10-30 17:25:53 +00001824/*
1825 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1826 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1827 * being read correctly if bit 7 of the base address is set.
1828 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1829 * Re-allocate the regions to a 256-byte boundary if necessary.
1830 */
Linus Torvalds193c0d62012-12-13 12:14:47 -08001831static void quirk_plx_pci9050(struct pci_dev *dev)
Ian Abbott21c5fd92012-10-30 17:25:53 +00001832{
1833 unsigned int bar;
1834
1835 /* Fixed in revision 2 (PCI 9052). */
1836 if (dev->revision >= 2)
1837 return;
1838 for (bar = 0; bar <= 1; bar++)
1839 if (pci_resource_len(dev, bar) == 0x80 &&
1840 (pci_resource_start(dev, bar) & 0x80)) {
1841 struct resource *r = &dev->resource[bar];
Ryan Desfosses227f0642014-04-18 20:13:50 -04001842 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
Ian Abbott21c5fd92012-10-30 17:25:53 +00001843 bar);
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001844 r->flags |= IORESOURCE_UNSET;
Ian Abbott21c5fd92012-10-30 17:25:53 +00001845 r->start = 0;
1846 r->end = 0xff;
1847 }
1848}
1849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1850 quirk_plx_pci9050);
Ian Abbott2794bb22012-10-29 14:40:18 +00001851/*
1852 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1853 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1854 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1855 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1856 *
1857 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1858 * driver.
1859 */
1860DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1861DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
Ian Abbott21c5fd92012-10-30 17:25:53 +00001862
Bill Pemberton15856ad2012-11-21 15:35:00 -05001863static void quirk_netmos(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001864{
1865 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1866 unsigned int num_serial = dev->subsystem_device & 0xf;
1867
1868 /*
1869 * These Netmos parts are multiport serial devices with optional
1870 * parallel ports. Even when parallel ports are present, they
1871 * are identified as class SERIAL, which means the serial driver
1872 * will claim them. To prevent this, mark them as class OTHER.
1873 * These combo devices should be claimed by parport_serial.
1874 *
1875 * The subdevice ID is of the form 0x00PS, where <P> is the number
1876 * of parallel ports and <S> is the number of serial ports.
1877 */
1878 switch (dev->device) {
Jiri Slaby4c9c1682008-12-08 16:19:14 +01001879 case PCI_DEVICE_ID_NETMOS_9835:
1880 /* Well, this rule doesn't hold for the following 9835 device */
1881 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1882 dev->subsystem_device == 0x0299)
1883 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884 case PCI_DEVICE_ID_NETMOS_9735:
1885 case PCI_DEVICE_ID_NETMOS_9745:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886 case PCI_DEVICE_ID_NETMOS_9845:
1887 case PCI_DEVICE_ID_NETMOS_9855:
Yinghai Lu08803ef2012-02-23 23:46:56 -08001888 if (num_parallel) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001889 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001890 dev->device, num_parallel, num_serial);
1891 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1892 (dev->class & 0xff);
1893 }
1894 }
1895}
Yinghai Lu08803ef2012-02-23 23:46:56 -08001896DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1897 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898
Bill Pemberton15856ad2012-11-21 15:35:00 -05001899static void quirk_e100_interrupt(struct pci_dev *dev)
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001900{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001901 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001902 u8 __iomem *csr;
1903 u8 cmd_hi;
1904
1905 switch (dev->device) {
1906 /* PCI IDs taken from drivers/net/e100.c */
1907 case 0x1029:
1908 case 0x1030 ... 0x1034:
1909 case 0x1038 ... 0x103E:
1910 case 0x1050 ... 0x1057:
1911 case 0x1059:
1912 case 0x1064 ... 0x106B:
1913 case 0x1091 ... 0x1095:
1914 case 0x1209:
1915 case 0x1229:
1916 case 0x2449:
1917 case 0x2459:
1918 case 0x245D:
1919 case 0x27DC:
1920 break;
1921 default:
1922 return;
1923 }
1924
1925 /*
1926 * Some firmware hands off the e100 with interrupts enabled,
1927 * which can cause a flood of interrupts if packets are
1928 * received before the driver attaches to the device. So
1929 * disable all e100 interrupts here. The driver will
1930 * re-enable them when it's ready.
1931 */
1932 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001933
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001934 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001935 return;
1936
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001937 /*
1938 * Check that the device is in the D0 power state. If it's not,
1939 * there is no point to look any further.
1940 */
Yijing Wang728cdb72013-06-18 16:22:14 +08001941 if (dev->pm_cap) {
1942 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001943 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1944 return;
1945 }
1946
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001947 /* Convert from PCI bus to resource space. */
1948 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001949 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001950 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001951 return;
1952 }
1953
1954 cmd_hi = readb(csr + 3);
1955 if (cmd_hi == 0) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001956 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001957 writeb(1, csr + 3);
1958 }
1959
1960 iounmap(csr);
1961}
Yinghai Lu4c5b28e2012-02-23 23:46:57 -08001962DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1963 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001964
Alexander Duyck649426e2009-03-05 13:57:28 -05001965/*
1966 * The 82575 and 82598 may experience data corruption issues when transitioning
1967 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1968 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001969static void quirk_disable_aspm_l0s(struct pci_dev *dev)
Alexander Duyck649426e2009-03-05 13:57:28 -05001970{
1971 dev_info(&dev->dev, "Disabling L0s\n");
1972 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1973}
1974DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1975DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1976DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1979DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1980DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1981DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1982DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1983DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1984DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1985DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1987DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1988
Bill Pemberton15856ad2012-11-21 15:35:00 -05001989static void fixup_rev1_53c810(struct pci_dev *dev)
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001990{
Bjorn Helgaase6323e32015-06-19 15:36:45 -05001991 u32 class = dev->class;
1992
1993 /*
1994 * rev 1 ncr53c810 chips don't set the class at all which means
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001995 * they don't get their resources remapped. Fix that here.
1996 */
Bjorn Helgaase6323e32015-06-19 15:36:45 -05001997 if (class)
1998 return;
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001999
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002000 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2001 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2002 class, dev->class);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002003}
2004DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2005
Daniel Yeisley9d265122005-12-05 07:06:43 -05002006/* Enable 1k I/O space granularity on the Intel P64H2 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002007static void quirk_p64h2_1k_io(struct pci_dev *dev)
Daniel Yeisley9d265122005-12-05 07:06:43 -05002008{
2009 u16 en1k;
Daniel Yeisley9d265122005-12-05 07:06:43 -05002010
2011 pci_read_config_word(dev, 0x40, &en1k);
2012
2013 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002014 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -06002015 dev->io_window_1k = 1;
Daniel Yeisley9d265122005-12-05 07:06:43 -05002016 }
2017}
2018DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2019
Brice Goglincf34a8e2006-06-13 14:35:42 -04002020/* Under some circumstances, AER is not linked with extended capabilities.
2021 * Force it to be linked by setting the corresponding control bit in the
2022 * config space.
2023 */
Alan Cox1597cac2006-12-04 15:14:45 -08002024static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04002025{
2026 uint8_t b;
2027 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2028 if (!(b & 0x20)) {
2029 pci_write_config_byte(dev, 0xf41, b | 0x20);
Ryan Desfosses227f0642014-04-18 20:13:50 -04002030 dev_info(&dev->dev, "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04002031 }
2032 }
2033}
2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2035 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02002036DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08002037 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04002038
Bill Pemberton15856ad2012-11-21 15:35:00 -05002039static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
Tim Yamin53a9bf42007-11-01 23:14:54 +00002040{
2041 /*
2042 * Disable PCI Bus Parking and PCI Master read caching on CX700
2043 * which causes unspecified timing errors with a VT6212L on the PCI
Tim Yaminca846392010-03-19 14:22:58 -07002044 * bus leading to USB2.0 packet loss.
2045 *
2046 * This quirk is only enabled if a second (on the external PCI bus)
2047 * VT6212L is found -- the CX700 core itself also contains a USB
2048 * host controller with the same PCI ID as the VT6212L.
Tim Yamin53a9bf42007-11-01 23:14:54 +00002049 */
2050
Tim Yaminca846392010-03-19 14:22:58 -07002051 /* Count VT6212L instances */
2052 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2053 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002054 uint8_t b;
Tim Yaminca846392010-03-19 14:22:58 -07002055
2056 /* p should contain the first (internal) VT6212L -- see if we have
2057 an external one by searching again */
2058 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2059 if (!p)
2060 return;
2061 pci_dev_put(p);
2062
Tim Yamin53a9bf42007-11-01 23:14:54 +00002063 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2064 if (b & 0x40) {
2065 /* Turn off PCI Bus Parking */
2066 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2067
Ryan Desfosses227f0642014-04-18 20:13:50 -04002068 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
Tim Yaminbc043272008-03-30 20:58:59 +01002069 }
2070 }
2071
2072 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2073 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00002074 /* Turn off PCI Master read caching */
2075 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01002076
2077 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002078 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01002079
2080 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002081 pci_write_config_byte(dev, 0x77, 0x0);
2082
Ryan Desfosses227f0642014-04-18 20:13:50 -04002083 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00002084 }
2085 }
2086}
Tim Yaminca846392010-03-19 14:22:58 -07002087DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002088
Benjamin Li99cb233d2008-07-02 10:59:04 -07002089/*
2090 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2091 * VPD end tag will hang the device. This problem was initially
2092 * observed when a vpd entry was created in sysfs
2093 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2094 * will dump 32k of data. Reading a full 32k will cause an access
2095 * beyond the VPD end tag causing the device to hang. Once the device
2096 * is hung, the bnx2 driver will not be able to reset the device.
2097 * We believe that it is legal to read beyond the end tag and
2098 * therefore the solution is to limit the read/write length.
2099 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002100static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
Benjamin Li99cb233d2008-07-02 10:59:04 -07002101{
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002102 /*
Dean Hildebrand35405f22008-08-07 17:31:45 -07002103 * Only disable the VPD capability for 5706, 5706S, 5708,
2104 * 5708S and 5709 rev. A
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002105 */
Benjamin Li99cb233d2008-07-02 10:59:04 -07002106 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
Dean Hildebrand35405f22008-08-07 17:31:45 -07002107 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002108 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002109 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002110 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2111 (dev->revision & 0xf0) == 0x0)) {
2112 if (dev->vpd)
2113 dev->vpd->len = 0x80;
2114 }
2115}
2116
Yu Zhaobffadff2008-10-28 14:44:11 +08002117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2118 PCI_DEVICE_ID_NX2_5706,
2119 quirk_brcm_570x_limit_vpd);
2120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2121 PCI_DEVICE_ID_NX2_5706S,
2122 quirk_brcm_570x_limit_vpd);
2123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2124 PCI_DEVICE_ID_NX2_5708,
2125 quirk_brcm_570x_limit_vpd);
2126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2127 PCI_DEVICE_ID_NX2_5708S,
2128 quirk_brcm_570x_limit_vpd);
2129DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2130 PCI_DEVICE_ID_NX2_5709,
2131 quirk_brcm_570x_limit_vpd);
2132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2133 PCI_DEVICE_ID_NX2_5709S,
2134 quirk_brcm_570x_limit_vpd);
Benjamin Li99cb233d2008-07-02 10:59:04 -07002135
Myron Stowe25e742b2012-07-09 15:36:14 -06002136static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
Matt Carlson0b471502012-02-27 09:44:48 +00002137{
2138 u32 rev;
2139
2140 pci_read_config_dword(dev, 0xf4, &rev);
2141
2142 /* Only CAP the MRRS if the device is a 5719 A0 */
2143 if (rev == 0x05719000) {
2144 int readrq = pcie_get_readrq(dev);
2145 if (readrq > 2048)
2146 pcie_set_readrq(dev, 2048);
2147 }
2148}
2149
2150DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2151 PCI_DEVICE_ID_TIGON3_5719,
2152 quirk_brcm_5719_limit_mrrs);
2153
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002154/* Originally in EDAC sources for i82875P:
2155 * Intel tells BIOS developers to hide device 6 which
2156 * configures the overflow device access containing
2157 * the DRBs - this is where we expose device 6.
2158 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2159 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002160static void quirk_unhide_mch_dev6(struct pci_dev *dev)
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002161{
2162 u8 reg;
2163
2164 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2165 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2166 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2167 }
2168}
2169
2170DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2171 quirk_unhide_mch_dev6);
2172DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2173 quirk_unhide_mch_dev6);
2174
Chris Metcalf12962262012-04-07 17:10:17 -04002175#ifdef CONFIG_TILEPRO
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002176/*
Chris Metcalf12962262012-04-07 17:10:17 -04002177 * The Tilera TILEmpower tilepro platform needs to set the link speed
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002178 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2179 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2180 * capability register of the PEX8624 PCIe switch. The switch
2181 * supports link speed auto negotiation, but falsely sets
2182 * the link speed to 5GT/s.
2183 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002184static void quirk_tile_plx_gen1(struct pci_dev *dev)
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002185{
2186 if (tile_plx_gen1) {
2187 pci_write_config_dword(dev, 0x98, 0x1);
2188 mdelay(50);
2189 }
2190}
2191DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
Chris Metcalf12962262012-04-07 17:10:17 -04002192#endif /* CONFIG_TILEPRO */
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002193
Brice Goglin3f79e102006-08-31 01:54:56 -04002194#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07002195/* Some chipsets do not support MSI. We cannot easily rely on setting
2196 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002197 * some other buses controlled by the chipset even if Linux is not
2198 * aware of it. Instead of setting the flag on all buses in the
Tejun Heoebdf7d32007-05-31 00:40:48 -07002199 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04002200 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002201static void quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002202{
Michael Ellerman88187df2007-01-25 19:34:07 +11002203 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002204 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002205}
Tejun Heoebdf7d32007-05-31 00:40:48 -07002206DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2207DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Tejun Heo66d715c2008-07-04 09:59:32 -07002209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05002210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Thomas Renninger162dedd2009-04-03 06:34:00 -07002211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
Tejun Heo549e1562010-05-23 10:22:55 +02002212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04002213
2214/* Disable MSI on chipsets that are known to not support it */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002215static void quirk_disable_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002216{
2217 if (dev->subordinate) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002218 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002219 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2220 }
2221}
2222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Matthew Wilcox134b3452010-03-24 07:11:01 -06002223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
Alex Deucher9313ff42010-05-18 10:42:53 -04002224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04002225
Clemens Ladischaff61362010-05-26 12:21:10 +02002226/*
2227 * The APC bridge device in AMD 780 family northbridges has some random
2228 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2229 * we use the possible vendor/device IDs of the host bridge for the
2230 * declared quirk, and search for the APC bridge by slot number.
2231 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002232static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
Clemens Ladischaff61362010-05-26 12:21:10 +02002233{
2234 struct pci_dev *apc_bridge;
2235
2236 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2237 if (apc_bridge) {
2238 if (apc_bridge->device == 0x9602)
2239 quirk_disable_msi(apc_bridge);
2240 pci_dev_put(apc_bridge);
2241 }
2242}
2243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2245
Brice Goglin6397c752006-08-31 01:55:32 -04002246/* Go through the list of Hypertransport capabilities and
2247 * return 1 if a HT MSI capability is found and enabled */
Myron Stowe25e742b2012-07-09 15:36:14 -06002248static int msi_ht_cap_enabled(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002249{
Michael Ellerman7a380502006-11-22 18:26:21 +11002250 int pos, ttl = 48;
2251
2252 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2253 while (pos && ttl--) {
2254 u8 flags;
2255
2256 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002257 &flags) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002258 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11002259 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002260 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11002261 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04002262 }
Michael Ellerman7a380502006-11-22 18:26:21 +11002263
2264 pos = pci_find_next_ht_capability(dev, pos,
2265 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04002266 }
2267 return 0;
2268}
2269
2270/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
Myron Stowe25e742b2012-07-09 15:36:14 -06002271static void quirk_msi_ht_cap(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002272{
2273 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002274 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002275 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2276 }
2277}
2278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2279 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08002280
Brice Goglin6397c752006-08-31 01:55:32 -04002281/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2282 * MSI are supported if the MSI capability set in any of these mappings.
2283 */
Myron Stowe25e742b2012-07-09 15:36:14 -06002284static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002285{
2286 struct pci_dev *pdev;
2287
2288 if (!dev->subordinate)
2289 return;
2290
2291 /* check HT MSI cap on this chipset and the root one.
2292 * a single one having MSI is enough to be sure that MSI are supported.
2293 */
Alan Cox11f242f2006-10-10 14:39:00 -07002294 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08002295 if (!pdev)
2296 return;
David Rientjes0c875c22006-12-03 11:55:34 -08002297 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002298 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002299 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2300 }
Alan Cox11f242f2006-10-10 14:39:00 -07002301 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04002302}
2303DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2304 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07002305
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002306/* Force enable MSI mapping capability on HT bridges */
Myron Stowe25e742b2012-07-09 15:36:14 -06002307static void ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08002308{
2309 int pos, ttl = 48;
2310
2311 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2312 while (pos && ttl--) {
2313 u8 flags;
2314
2315 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2316 &flags) == 0) {
2317 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2318
2319 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2320 flags | HT_MSI_FLAGS_ENABLE);
2321 }
2322 pos = pci_find_next_ht_capability(dev, pos,
2323 HT_CAPTYPE_MSI_MAPPING);
2324 }
2325}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2327 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2328 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08002329
Yinghai Lue0ae4f52009-02-17 20:40:09 -08002330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2331 ht_enable_msi_mapping);
2332
Ben Hutchingse4146bb2010-05-16 02:28:49 +01002333/* The P5N32-SLI motherboards from Asus have a problem with msi
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002334 * for the MCP55 NIC. It is not yet determined whether the msi problem
2335 * also affects other devices. As for now, turn off msi for this device.
2336 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002337static void nvenet_msi_disable(struct pci_dev *dev)
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002338{
Jean Delvare9251bac2011-05-15 18:13:46 +02002339 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2340
2341 if (board_name &&
2342 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2343 strstr(board_name, "P5N32-E SLI"))) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002344 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002345 dev->no_msi = 1;
2346 }
2347}
2348DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2349 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2350 nvenet_msi_disable);
2351
Neil Horman66db60e2010-09-21 13:54:39 -04002352/*
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002353 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2354 * config register. This register controls the routing of legacy
2355 * interrupts from devices that route through the MCP55. If this register
2356 * is misprogrammed, interrupts are only sent to the BSP, unlike
2357 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2358 * having this register set properly prevents kdump from booting up
2359 * properly, so let's make sure that we have it set correctly.
2360 * Note that this is an undocumented register.
Neil Horman66db60e2010-09-21 13:54:39 -04002361 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002362static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
Neil Horman66db60e2010-09-21 13:54:39 -04002363{
2364 u32 cfg;
2365
Neil Horman49c2fa082010-12-08 09:47:48 -05002366 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2367 return;
2368
Neil Horman66db60e2010-09-21 13:54:39 -04002369 pci_read_config_dword(dev, 0x74, &cfg);
2370
2371 if (cfg & ((1 << 2) | (1 << 15))) {
2372 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2373 cfg &= ~((1 << 2) | (1 << 15));
2374 pci_write_config_dword(dev, 0x74, cfg);
2375 }
2376}
2377
2378DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2379 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2380 nvbridge_check_legacy_irq_routing);
2381
2382DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2383 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2384 nvbridge_check_legacy_irq_routing);
2385
Myron Stowe25e742b2012-07-09 15:36:14 -06002386static int ht_check_msi_mapping(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002387{
2388 int pos, ttl = 48;
2389 int found = 0;
2390
2391 /* check if there is HT MSI cap or enabled on this device */
2392 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2393 while (pos && ttl--) {
2394 u8 flags;
2395
2396 if (found < 1)
2397 found = 1;
2398 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2399 &flags) == 0) {
2400 if (flags & HT_MSI_FLAGS_ENABLE) {
2401 if (found < 2) {
2402 found = 2;
2403 break;
2404 }
2405 }
2406 }
2407 pos = pci_find_next_ht_capability(dev, pos,
2408 HT_CAPTYPE_MSI_MAPPING);
2409 }
2410
2411 return found;
2412}
2413
Myron Stowe25e742b2012-07-09 15:36:14 -06002414static int host_bridge_with_leaf(struct pci_dev *host_bridge)
Yinghai Lude745302009-03-20 19:29:41 -07002415{
2416 struct pci_dev *dev;
2417 int pos;
2418 int i, dev_no;
2419 int found = 0;
2420
2421 dev_no = host_bridge->devfn >> 3;
2422 for (i = dev_no + 1; i < 0x20; i++) {
2423 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2424 if (!dev)
2425 continue;
2426
2427 /* found next host bridge ?*/
2428 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2429 if (pos != 0) {
2430 pci_dev_put(dev);
2431 break;
2432 }
2433
2434 if (ht_check_msi_mapping(dev)) {
2435 found = 1;
2436 pci_dev_put(dev);
2437 break;
2438 }
2439 pci_dev_put(dev);
2440 }
2441
2442 return found;
2443}
2444
Yinghai Lueeafda72009-03-29 12:30:05 -07002445#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2446#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2447
Myron Stowe25e742b2012-07-09 15:36:14 -06002448static int is_end_of_ht_chain(struct pci_dev *dev)
Yinghai Lueeafda72009-03-29 12:30:05 -07002449{
2450 int pos, ctrl_off;
2451 int end = 0;
2452 u16 flags, ctrl;
2453
2454 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2455
2456 if (!pos)
2457 goto out;
2458
2459 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2460
2461 ctrl_off = ((flags >> 10) & 1) ?
2462 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2463 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2464
2465 if (ctrl & (1 << 6))
2466 end = 1;
2467
2468out:
2469 return end;
2470}
2471
Myron Stowe25e742b2012-07-09 15:36:14 -06002472static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002473{
2474 struct pci_dev *host_bridge;
2475 int pos;
2476 int i, dev_no;
2477 int found = 0;
2478
2479 dev_no = dev->devfn >> 3;
2480 for (i = dev_no; i >= 0; i--) {
2481 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2482 if (!host_bridge)
2483 continue;
2484
2485 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2486 if (pos != 0) {
2487 found = 1;
2488 break;
2489 }
2490 pci_dev_put(host_bridge);
2491 }
2492
2493 if (!found)
2494 return;
2495
Yinghai Lueeafda72009-03-29 12:30:05 -07002496 /* don't enable end_device/host_bridge with leaf directly here */
2497 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2498 host_bridge_with_leaf(host_bridge))
Yinghai Lude745302009-03-20 19:29:41 -07002499 goto out;
2500
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002501 /* root did that ! */
2502 if (msi_ht_cap_enabled(host_bridge))
2503 goto out;
2504
2505 ht_enable_msi_mapping(dev);
2506
2507out:
2508 pci_dev_put(host_bridge);
2509}
2510
Myron Stowe25e742b2012-07-09 15:36:14 -06002511static void ht_disable_msi_mapping(struct pci_dev *dev)
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002512{
2513 int pos, ttl = 48;
2514
2515 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2516 while (pos && ttl--) {
2517 u8 flags;
2518
2519 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2520 &flags) == 0) {
Prakash Punnoor6a958d52009-03-06 10:10:35 +01002521 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002522
2523 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2524 flags & ~HT_MSI_FLAGS_ENABLE);
2525 }
2526 pos = pci_find_next_ht_capability(dev, pos,
2527 HT_CAPTYPE_MSI_MAPPING);
2528 }
2529}
2530
Myron Stowe25e742b2012-07-09 15:36:14 -06002531static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
Peer Chen9dc625e2008-02-04 23:50:13 -08002532{
2533 struct pci_dev *host_bridge;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002534 int pos;
2535 int found;
2536
Rafael J. Wysocki3d2a5312010-07-23 22:19:55 +02002537 if (!pci_msi_enabled())
2538 return;
2539
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002540 /* check if there is HT MSI cap or enabled on this device */
2541 found = ht_check_msi_mapping(dev);
2542
2543 /* no HT MSI CAP */
2544 if (found == 0)
2545 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002546
2547 /*
2548 * HT MSI mapping should be disabled on devices that are below
2549 * a non-Hypertransport host bridge. Locate the host bridge...
2550 */
2551 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2552 if (host_bridge == NULL) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002553 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
Peer Chen9dc625e2008-02-04 23:50:13 -08002554 return;
2555 }
2556
2557 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2558 if (pos != 0) {
2559 /* Host bridge is to HT */
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002560 if (found == 1) {
2561 /* it is not enabled, try to enable it */
Yinghai Lude745302009-03-20 19:29:41 -07002562 if (all)
2563 ht_enable_msi_mapping(dev);
2564 else
2565 nv_ht_enable_msi_mapping(dev);
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002566 }
Myron Stowedff3aef2012-07-09 15:36:08 -06002567 goto out;
Peer Chen9dc625e2008-02-04 23:50:13 -08002568 }
2569
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002570 /* HT MSI is not enabled */
2571 if (found == 1)
Myron Stowedff3aef2012-07-09 15:36:08 -06002572 goto out;
Peer Chen9dc625e2008-02-04 23:50:13 -08002573
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002574 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2575 ht_disable_msi_mapping(dev);
Myron Stowedff3aef2012-07-09 15:36:08 -06002576
2577out:
2578 pci_dev_put(host_bridge);
Peer Chen9dc625e2008-02-04 23:50:13 -08002579}
Yinghai Lude745302009-03-20 19:29:41 -07002580
Myron Stowe25e742b2012-07-09 15:36:14 -06002581static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002582{
2583 return __nv_msi_ht_cap_quirk(dev, 1);
2584}
2585
Myron Stowe25e742b2012-07-09 15:36:14 -06002586static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002587{
2588 return __nv_msi_ht_cap_quirk(dev, 0);
2589}
2590
2591DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Yinghai Lude745302009-03-20 19:29:41 -07002593
2594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002595DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Peer Chen9dc625e2008-02-04 23:50:13 -08002596
Bill Pemberton15856ad2012-11-21 15:35:00 -05002597static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
David Millerba698ad2007-10-25 01:16:30 -07002598{
2599 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2600}
Bill Pemberton15856ad2012-11-21 15:35:00 -05002601static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
Shane Huang4600c9d2008-01-25 15:46:24 +09002602{
2603 struct pci_dev *p;
2604
2605 /* SB700 MSI issue will be fixed at HW level from revision A21,
2606 * we need check PCI REVISION ID of SMBus controller to get SB700
2607 * revision.
2608 */
2609 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2610 NULL);
2611 if (!p)
2612 return;
2613
2614 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2615 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2616 pci_dev_put(p);
2617}
Xiong Huang70588812013-03-07 08:55:16 +00002618static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2619{
2620 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2621 if (dev->revision < 0x18) {
2622 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2623 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2624 }
2625}
David Millerba698ad2007-10-25 01:16:30 -07002626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2627 PCI_DEVICE_ID_TIGON3_5780,
2628 quirk_msi_intx_disable_bug);
2629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2630 PCI_DEVICE_ID_TIGON3_5780S,
2631 quirk_msi_intx_disable_bug);
2632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2633 PCI_DEVICE_ID_TIGON3_5714,
2634 quirk_msi_intx_disable_bug);
2635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2636 PCI_DEVICE_ID_TIGON3_5714S,
2637 quirk_msi_intx_disable_bug);
2638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2639 PCI_DEVICE_ID_TIGON3_5715,
2640 quirk_msi_intx_disable_bug);
2641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2642 PCI_DEVICE_ID_TIGON3_5715S,
2643 quirk_msi_intx_disable_bug);
2644
David Millerbc38b412007-10-25 01:16:52 -07002645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d2008-01-25 15:46:24 +09002646 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002647DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d2008-01-25 15:46:24 +09002648 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d2008-01-25 15:46:24 +09002650 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d2008-01-25 15:46:24 +09002652 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d2008-01-25 15:46:24 +09002654 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002655
2656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2657 quirk_msi_intx_disable_bug);
2658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2659 quirk_msi_intx_disable_bug);
2660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2661 quirk_msi_intx_disable_bug);
2662
Huang, Xiong7cb6a292012-04-30 15:38:49 +00002663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2664 quirk_msi_intx_disable_bug);
2665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2666 quirk_msi_intx_disable_bug);
2667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2668 quirk_msi_intx_disable_bug);
2669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2670 quirk_msi_intx_disable_bug);
2671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2672 quirk_msi_intx_disable_bug);
2673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2674 quirk_msi_intx_disable_bug);
Xiong Huang70588812013-03-07 08:55:16 +00002675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2676 quirk_msi_intx_disable_qca_bug);
2677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2678 quirk_msi_intx_disable_qca_bug);
2679DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2680 quirk_msi_intx_disable_qca_bug);
2681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2682 quirk_msi_intx_disable_qca_bug);
2683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2684 quirk_msi_intx_disable_qca_bug);
Brice Goglin3f79e102006-08-31 01:54:56 -04002685#endif /* CONFIG_PCI_MSI */
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002686
Felix Radensky33223402010-03-28 16:02:02 +03002687/* Allow manual resource allocation for PCI hotplug bridges
2688 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2689 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002690 * kernel fails to allocate resources when hotplug device is
Felix Radensky33223402010-03-28 16:02:02 +03002691 * inserted and PCI bus is rescanned.
2692 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002693static void quirk_hotplug_bridge(struct pci_dev *dev)
Felix Radensky33223402010-03-28 16:02:02 +03002694{
2695 dev->is_hotplug_bridge = 1;
2696}
2697
2698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2699
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002700/*
2701 * This is a quirk for the Ricoh MMC controller found as a part of
2702 * some mulifunction chips.
2703
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002704 * This is very similar and based on the ricoh_mmc driver written by
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002705 * Philip Langdale. Thank you for these magic sequences.
2706 *
2707 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2708 * and one or both of cardbus or firewire.
2709 *
2710 * It happens that they implement SD and MMC
2711 * support as separate controllers (and PCI functions). The linux SDHCI
2712 * driver supports MMC cards but the chip detects MMC cards in hardware
2713 * and directs them to the MMC controller - so the SDHCI driver never sees
2714 * them.
2715 *
2716 * To get around this, we must disable the useless MMC controller.
2717 * At that point, the SDHCI controller will start seeing them
2718 * It seems to be the case that the relevant PCI registers to deactivate the
2719 * MMC controller live on PCI function 0, which might be the cardbus controller
2720 * or the firewire controller, depending on the particular chip in question
2721 *
2722 * This has to be done early, because as soon as we disable the MMC controller
2723 * other pci functions shift up one level, e.g. function #2 becomes function
2724 * #1, and this will confuse the pci core.
2725 */
2726
2727#ifdef CONFIG_MMC_RICOH_MMC
2728static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2729{
2730 /* disable via cardbus interface */
2731 u8 write_enable;
2732 u8 write_target;
2733 u8 disable;
2734
2735 /* disable must be done via function #0 */
2736 if (PCI_FUNC(dev->devfn))
2737 return;
2738
2739 pci_read_config_byte(dev, 0xB7, &disable);
2740 if (disable & 0x02)
2741 return;
2742
2743 pci_read_config_byte(dev, 0x8E, &write_enable);
2744 pci_write_config_byte(dev, 0x8E, 0xAA);
2745 pci_read_config_byte(dev, 0x8D, &write_target);
2746 pci_write_config_byte(dev, 0x8D, 0xB7);
2747 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2748 pci_write_config_byte(dev, 0x8E, write_enable);
2749 pci_write_config_byte(dev, 0x8D, write_target);
2750
2751 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2752 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2753}
2754DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2755DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2756
2757static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2758{
2759 /* disable via firewire interface */
2760 u8 write_enable;
2761 u8 disable;
2762
2763 /* disable must be done via function #0 */
2764 if (PCI_FUNC(dev->devfn))
2765 return;
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002766 /*
Andy Lutomirski812089e2012-12-01 12:37:20 -08002767 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002768 * certain types of SD/MMC cards. Lowering the SD base
2769 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2770 *
2771 * 0x150 - SD2.0 mode enable for changing base clock
2772 * frequency to 50Mhz
2773 * 0xe1 - Base clock frequency
2774 * 0x32 - 50Mhz new clock frequency
2775 * 0xf9 - Key register for 0x150
2776 * 0xfc - key register for 0xe1
2777 */
Andy Lutomirski812089e2012-12-01 12:37:20 -08002778 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2779 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002780 pci_write_config_byte(dev, 0xf9, 0xfc);
2781 pci_write_config_byte(dev, 0x150, 0x10);
2782 pci_write_config_byte(dev, 0xf9, 0x00);
2783 pci_write_config_byte(dev, 0xfc, 0x01);
2784 pci_write_config_byte(dev, 0xe1, 0x32);
2785 pci_write_config_byte(dev, 0xfc, 0x00);
2786
2787 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2788 }
Josh Boyer3e309cd2011-10-05 11:44:50 -04002789
2790 pci_read_config_byte(dev, 0xCB, &disable);
2791
2792 if (disable & 0x02)
2793 return;
2794
2795 pci_read_config_byte(dev, 0xCA, &write_enable);
2796 pci_write_config_byte(dev, 0xCA, 0x57);
2797 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2798 pci_write_config_byte(dev, 0xCA, write_enable);
2799
2800 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2801 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2802
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002803}
2804DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2805DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
Andy Lutomirski812089e2012-12-01 12:37:20 -08002806DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2807DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
Manoj Iyerbe98ca62011-05-26 11:19:05 -05002808DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2809DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002810#endif /*CONFIG_MMC_RICOH_MMC*/
2811
Suresh Siddhad3f13812011-08-23 17:05:25 -07002812#ifdef CONFIG_DMAR_TABLE
Suresh Siddha254e42002010-12-06 12:26:30 -08002813#define VTUNCERRMSK_REG 0x1ac
2814#define VTD_MSK_SPEC_ERRORS (1 << 31)
2815/*
2816 * This is a quirk for masking vt-d spec defined errors to platform error
2817 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2818 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2819 * on the RAS config settings of the platform) when a vt-d fault happens.
2820 * The resulting SMI caused the system to hang.
2821 *
2822 * VT-d spec related errors are already handled by the VT-d OS code, so no
2823 * need to report the same error through other channels.
2824 */
2825static void vtd_mask_spec_errors(struct pci_dev *dev)
2826{
2827 u32 word;
2828
2829 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2830 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2831}
2832DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2833DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2834#endif
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002835
Bill Pemberton15856ad2012-11-21 15:35:00 -05002836static void fixup_ti816x_class(struct pci_dev *dev)
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302837{
2838 /* TI 816x devices do not have class code set when in PCIe boot mode */
Yinghai Lu40c96232012-02-23 23:46:58 -08002839 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2840 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302841}
Yinghai Lu40c96232012-02-23 23:46:58 -08002842DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2843 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302844
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002845/* Some PCIe devices do not work reliably with the claimed maximum
2846 * payload size supported.
2847 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002848static void fixup_mpss_256(struct pci_dev *dev)
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002849{
2850 dev->pcie_mpss = 1; /* 256 bytes */
2851}
2852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2853 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2855 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2857 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2858
Jon Masond387a8d2011-10-14 14:56:13 -05002859/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2860 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2861 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2862 * until all of the devices are discovered and buses walked, read completion
2863 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2864 * it is possible to hotplug a device with MPS of 256B.
2865 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002866static void quirk_intel_mc_errata(struct pci_dev *dev)
Jon Masond387a8d2011-10-14 14:56:13 -05002867{
2868 int err;
2869 u16 rcc;
2870
2871 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2872 return;
2873
2874 /* Intel errata specifies bits to change but does not say what they are.
2875 * Keeping them magical until such time as the registers and values can
2876 * be explained.
2877 */
2878 err = pci_read_config_word(dev, 0x48, &rcc);
2879 if (err) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002880 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002881 return;
2882 }
2883
2884 if (!(rcc & (1 << 10)))
2885 return;
2886
2887 rcc &= ~(1 << 10);
2888
2889 err = pci_write_config_word(dev, 0x48, rcc);
2890 if (err) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002891 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002892 return;
2893 }
2894
Ryan Desfosses227f0642014-04-18 20:13:50 -04002895 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002896}
2897/* Intel 5000 series memory controllers and ports 2-7 */
2898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2908DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2909DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2910DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2911DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2912/* Intel 5100 series memory controllers and ports 2-7 */
2913DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2915DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2916DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2917DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2918DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2919DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2920DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2921DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2922DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2923DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2924
Arjan van de Ven32098742012-01-30 20:52:07 -08002925
Jon Mason12b03182013-05-06 08:03:33 +00002926/*
2927 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2928 * work around this, query the size it should be configured to by the device and
2929 * modify the resource end to correspond to this new size.
2930 */
2931static void quirk_intel_ntb(struct pci_dev *dev)
2932{
2933 int rc;
2934 u8 val;
2935
2936 rc = pci_read_config_byte(dev, 0x00D0, &val);
2937 if (rc)
2938 return;
2939
2940 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2941
2942 rc = pci_read_config_byte(dev, 0x00D1, &val);
2943 if (rc)
2944 return;
2945
2946 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2947}
2948DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2950
Myron Stowe2729d5b2012-07-09 15:36:02 -06002951static ktime_t fixup_debug_start(struct pci_dev *dev,
2952 void (*fn)(struct pci_dev *dev))
Arjan van de Ven32098742012-01-30 20:52:07 -08002953{
Myron Stowe2729d5b2012-07-09 15:36:02 -06002954 ktime_t calltime = ktime_set(0, 0);
2955
2956 dev_dbg(&dev->dev, "calling %pF\n", fn);
2957 if (initcall_debug) {
2958 pr_debug("calling %pF @ %i for %s\n",
2959 fn, task_pid_nr(current), dev_name(&dev->dev));
2960 calltime = ktime_get();
2961 }
2962
2963 return calltime;
2964}
2965
2966static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2967 void (*fn)(struct pci_dev *dev))
2968{
2969 ktime_t delta, rettime;
Arjan van de Ven32098742012-01-30 20:52:07 -08002970 unsigned long long duration;
2971
Myron Stowe2729d5b2012-07-09 15:36:02 -06002972 if (initcall_debug) {
2973 rettime = ktime_get();
2974 delta = ktime_sub(rettime, calltime);
2975 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2976 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2977 fn, duration, dev_name(&dev->dev));
2978 }
Arjan van de Ven32098742012-01-30 20:52:07 -08002979}
2980
Thomas Jaroschf67fd552011-12-07 22:08:11 +01002981/*
2982 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2983 * even though no one is handling them (f.e. i915 driver is never loaded).
2984 * Additionally the interrupt destination is not set up properly
2985 * and the interrupt ends up -somewhere-.
2986 *
2987 * These spurious interrupts are "sticky" and the kernel disables
2988 * the (shared) interrupt line after 100.000+ generated interrupts.
2989 *
2990 * Fix it by disabling the still enabled interrupts.
2991 * This resolves crashes often seen on monitor unplug.
2992 */
2993#define I915_DEIER_REG 0x4400c
Bill Pemberton15856ad2012-11-21 15:35:00 -05002994static void disable_igfx_irq(struct pci_dev *dev)
Thomas Jaroschf67fd552011-12-07 22:08:11 +01002995{
2996 void __iomem *regs = pci_iomap(dev, 0, 0);
2997 if (regs == NULL) {
2998 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2999 return;
3000 }
3001
3002 /* Check if any interrupt line is still enabled */
3003 if (readl(regs + I915_DEIER_REG) != 0) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04003004 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003005
3006 writel(0, regs + I915_DEIER_REG);
3007 }
3008
3009 pci_iounmap(dev, regs);
3010}
3011DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3012DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
Thomas Jarosch7c821262014-04-07 15:10:32 +02003013DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003014
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003015/*
Todd E Brandtb8cac702013-09-10 16:10:43 -07003016 * PCI devices which are on Intel chips can skip the 10ms delay
3017 * before entering D3 mode.
3018 */
3019static void quirk_remove_d3_delay(struct pci_dev *dev)
3020{
3021 dev->d3_delay = 0;
3022}
3023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3030DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
Srinidhi Kasagar4a118752015-06-19 11:52:46 +05303037/* Intel Cherrytrail devices do not need 10ms d3_delay */
3038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3045DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3046DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
Todd E Brandtb8cac702013-09-10 16:10:43 -07003047/*
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003048 * Some devices may pass our check in pci_intx_mask_supported if
3049 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3050 * support this feature.
3051 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05003052static void quirk_broken_intx_masking(struct pci_dev *dev)
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003053{
3054 dev->broken_intx_masking = 1;
3055}
Jan Kiszkade509f92012-06-07 10:30:59 +02003056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
3057 quirk_broken_intx_masking);
Alex Williamson0bdb3b22012-06-07 11:01:59 -06003058DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3059 quirk_broken_intx_masking);
Alex Williamson3cb30b72014-05-01 14:36:31 -06003060/*
3061 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3062 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3063 *
3064 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3065 */
3066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3067 quirk_broken_intx_masking);
Gavin Shan11e42532014-09-05 15:35:30 -06003068DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3069 quirk_broken_intx_masking);
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003070
Alex Williamsonc3e59ee2015-01-15 18:17:12 -06003071static void quirk_no_bus_reset(struct pci_dev *dev)
3072{
3073 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3074}
3075
3076/*
3077 * Atheros AR93xx chips do not behave after a bus reset. The device will
3078 * throw a Link Down error on AER-capable systems and regardless of AER,
3079 * config space of the device is never accessible again and typically
3080 * causes the system to hang or reset when access is attempted.
3081 * http://www.spinics.net/lists/linux-pci/msg34797.html
3082 */
3083DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3084
Alex Williamsond84f3172014-11-21 11:24:14 -07003085static void quirk_no_pm_reset(struct pci_dev *dev)
3086{
3087 /*
3088 * We can't do a bus reset on root bus devices, but an ineffective
3089 * PM reset may be better than nothing.
3090 */
3091 if (!pci_is_root_bus(dev->bus))
3092 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3093}
3094
3095/*
3096 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3097 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3098 * to have no effect on the device: it retains the framebuffer contents and
3099 * monitor sync. Advertising this support makes other layers, like VFIO,
3100 * assume pci_reset_function() is viable for this device. Mark it as
3101 * unavailable to skip it when testing reset methods.
3102 */
3103DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3104 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3105
Andreas Noever1df51722014-06-03 22:04:10 +02003106#ifdef CONFIG_ACPI
3107/*
3108 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3109 *
3110 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3111 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3112 * be present after resume if a device was plugged in before suspend.
3113 *
3114 * The thunderbolt controller consists of a pcie switch with downstream
3115 * bridges leading to the NHI and to the tunnel pci bridges.
3116 *
3117 * This quirk cuts power to the whole chip. Therefore we have to apply it
3118 * during suspend_noirq of the upstream bridge.
3119 *
3120 * Power is automagically restored before resume. No action is needed.
3121 */
3122static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3123{
3124 acpi_handle bridge, SXIO, SXFP, SXLV;
3125
3126 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3127 return;
3128 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3129 return;
3130 bridge = ACPI_HANDLE(&dev->dev);
3131 if (!bridge)
3132 return;
3133 /*
3134 * SXIO and SXLV are present only on machines requiring this quirk.
3135 * TB bridges in external devices might have the same device id as those
3136 * on the host, but they will not have the associated ACPI methods. This
3137 * implicitly checks that we are at the right bridge.
3138 */
3139 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3140 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3141 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3142 return;
3143 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3144
3145 /* magic sequence */
3146 acpi_execute_simple_method(SXIO, NULL, 1);
3147 acpi_execute_simple_method(SXFP, NULL, 0);
3148 msleep(300);
3149 acpi_execute_simple_method(SXLV, NULL, 0);
3150 acpi_execute_simple_method(SXIO, NULL, 0);
3151 acpi_execute_simple_method(SXLV, NULL, 0);
3152}
3153DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547,
3154 quirk_apple_poweroff_thunderbolt);
3155
3156/*
3157 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3158 *
3159 * During suspend the thunderbolt controller is reset and all pci
3160 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3161 * during resume. We have to manually wait for the NHI since there is
3162 * no parent child relationship between the NHI and the tunneled
3163 * bridges.
3164 */
3165static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3166{
3167 struct pci_dev *sibling = NULL;
3168 struct pci_dev *nhi = NULL;
3169
3170 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3171 return;
3172 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3173 return;
3174 /*
3175 * Find the NHI and confirm that we are a bridge on the tb host
3176 * controller and not on a tb endpoint.
3177 */
3178 sibling = pci_get_slot(dev->bus, 0x0);
3179 if (sibling == dev)
3180 goto out; /* we are the downstream bridge to the NHI */
3181 if (!sibling || !sibling->subordinate)
3182 goto out;
3183 nhi = pci_get_slot(sibling->subordinate, 0x0);
3184 if (!nhi)
3185 goto out;
3186 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3187 || (nhi->device != 0x1547 && nhi->device != 0x156c)
3188 || nhi->subsystem_vendor != 0x2222
3189 || nhi->subsystem_device != 0x1111)
3190 goto out;
Darrick J. Wongc89ac442015-03-31 19:38:38 -07003191 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
Andreas Noever1df51722014-06-03 22:04:10 +02003192 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3193out:
3194 pci_dev_put(nhi);
3195 pci_dev_put(sibling);
3196}
3197DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547,
3198 quirk_apple_wait_for_thunderbolt);
3199DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d,
3200 quirk_apple_wait_for_thunderbolt);
3201#endif
3202
Jesse Barnesbfb0f332008-10-27 17:50:21 -07003203static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3204 struct pci_fixup *end)
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003205{
Myron Stowe2729d5b2012-07-09 15:36:02 -06003206 ktime_t calltime;
3207
Yinghai Luf4ca5c62012-02-23 23:46:49 -08003208 for (; f < end; f++)
3209 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3210 f->class == (u32) PCI_ANY_ID) &&
3211 (f->vendor == dev->vendor ||
3212 f->vendor == (u16) PCI_ANY_ID) &&
3213 (f->device == dev->device ||
3214 f->device == (u16) PCI_ANY_ID)) {
Myron Stowe2729d5b2012-07-09 15:36:02 -06003215 calltime = fixup_debug_start(dev, f->hook);
3216 f->hook(dev);
3217 fixup_debug_report(dev, calltime, f->hook);
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003218 }
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003219}
3220
3221extern struct pci_fixup __start_pci_fixups_early[];
3222extern struct pci_fixup __end_pci_fixups_early[];
3223extern struct pci_fixup __start_pci_fixups_header[];
3224extern struct pci_fixup __end_pci_fixups_header[];
3225extern struct pci_fixup __start_pci_fixups_final[];
3226extern struct pci_fixup __end_pci_fixups_final[];
3227extern struct pci_fixup __start_pci_fixups_enable[];
3228extern struct pci_fixup __end_pci_fixups_enable[];
3229extern struct pci_fixup __start_pci_fixups_resume[];
3230extern struct pci_fixup __end_pci_fixups_resume[];
3231extern struct pci_fixup __start_pci_fixups_resume_early[];
3232extern struct pci_fixup __end_pci_fixups_resume_early[];
3233extern struct pci_fixup __start_pci_fixups_suspend[];
3234extern struct pci_fixup __end_pci_fixups_suspend[];
Andreas Noever7d2a01b2014-06-03 22:04:09 +02003235extern struct pci_fixup __start_pci_fixups_suspend_late[];
3236extern struct pci_fixup __end_pci_fixups_suspend_late[];
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003237
Myron Stowe95df8b82012-07-13 14:29:00 -06003238static bool pci_apply_fixup_final_quirks;
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003239
3240void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3241{
3242 struct pci_fixup *start, *end;
3243
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003244 switch (pass) {
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003245 case pci_fixup_early:
3246 start = __start_pci_fixups_early;
3247 end = __end_pci_fixups_early;
3248 break;
3249
3250 case pci_fixup_header:
3251 start = __start_pci_fixups_header;
3252 end = __end_pci_fixups_header;
3253 break;
3254
3255 case pci_fixup_final:
Myron Stowe95df8b82012-07-13 14:29:00 -06003256 if (!pci_apply_fixup_final_quirks)
3257 return;
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003258 start = __start_pci_fixups_final;
3259 end = __end_pci_fixups_final;
3260 break;
3261
3262 case pci_fixup_enable:
3263 start = __start_pci_fixups_enable;
3264 end = __end_pci_fixups_enable;
3265 break;
3266
3267 case pci_fixup_resume:
3268 start = __start_pci_fixups_resume;
3269 end = __end_pci_fixups_resume;
3270 break;
3271
3272 case pci_fixup_resume_early:
3273 start = __start_pci_fixups_resume_early;
3274 end = __end_pci_fixups_resume_early;
3275 break;
3276
3277 case pci_fixup_suspend:
3278 start = __start_pci_fixups_suspend;
3279 end = __end_pci_fixups_suspend;
3280 break;
3281
Andreas Noever7d2a01b2014-06-03 22:04:09 +02003282 case pci_fixup_suspend_late:
3283 start = __start_pci_fixups_suspend_late;
3284 end = __end_pci_fixups_suspend_late;
3285 break;
3286
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003287 default:
3288 /* stupid compiler warning, you would think with an enum... */
3289 return;
3290 }
3291 pci_do_fixups(dev, start, end);
3292}
Rafael J. Wysocki93177a72010-01-02 22:57:24 +01003293EXPORT_SYMBOL(pci_fixup_device);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003294
Myron Stowe735bff12012-07-09 15:36:46 -06003295
David Woodhouse00010262009-10-12 12:50:34 +01003296static int __init pci_apply_final_quirks(void)
David Woodhouse8d86fb22009-10-12 12:48:43 +01003297{
3298 struct pci_dev *dev = NULL;
Jesse Barnesac1aa472009-10-26 13:20:44 -07003299 u8 cls = 0;
3300 u8 tmp;
3301
3302 if (pci_cache_line_size)
3303 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3304 pci_cache_line_size << 2);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003305
Myron Stowe95df8b82012-07-13 14:29:00 -06003306 pci_apply_fixup_final_quirks = true;
Kulikov Vasiliy4e344b12010-07-03 20:04:39 +04003307 for_each_pci_dev(dev) {
David Woodhouse8d86fb22009-10-12 12:48:43 +01003308 pci_fixup_device(pci_fixup_final, dev);
Jesse Barnesac1aa472009-10-26 13:20:44 -07003309 /*
3310 * If arch hasn't set it explicitly yet, use the CLS
3311 * value shared by all PCI devices. If there's a
3312 * mismatch, fall back to the default value.
3313 */
3314 if (!pci_cache_line_size) {
3315 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3316 if (!cls)
3317 cls = tmp;
3318 if (!tmp || cls == tmp)
3319 continue;
3320
Ryan Desfosses227f0642014-04-18 20:13:50 -04003321 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3322 cls << 2, tmp << 2,
Jesse Barnesac1aa472009-10-26 13:20:44 -07003323 pci_dfl_cache_line_size << 2);
3324 pci_cache_line_size = pci_dfl_cache_line_size;
3325 }
3326 }
Myron Stowe735bff12012-07-09 15:36:46 -06003327
Jesse Barnesac1aa472009-10-26 13:20:44 -07003328 if (!pci_cache_line_size) {
3329 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3330 cls << 2, pci_dfl_cache_line_size << 2);
Csaba Henk2820f332009-12-15 17:55:25 +05303331 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
David Woodhouse8d86fb22009-10-12 12:48:43 +01003332 }
3333
3334 return 0;
3335}
3336
David Woodhousecf6f3bf2009-10-12 12:51:22 +01003337fs_initcall_sync(pci_apply_final_quirks);
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003338
3339/*
3340 * Followings are device-specific reset methods which can be used to
3341 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3342 * not available.
3343 */
Dexuan Cuiaeb30012009-12-07 13:03:22 +08003344static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3345{
3346 int pos;
3347
3348 /* only implement PCI_CLASS_SERIAL_USB at present */
3349 if (dev->class == PCI_CLASS_SERIAL_USB) {
3350 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3351 if (!pos)
3352 return -ENOTTY;
3353
3354 if (probe)
3355 return 0;
3356
3357 pci_write_config_byte(dev, pos + 0x4, 1);
3358 msleep(100);
3359
3360 return 0;
3361 } else {
3362 return -ENOTTY;
3363 }
3364}
3365
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003366static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3367{
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003368 /*
3369 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3370 *
3371 * The 82599 supports FLR on VFs, but FLR support is reported only
3372 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3373 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3374 */
3375
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003376 if (probe)
3377 return 0;
3378
Casey Leedom4d708ab2013-08-06 15:48:39 +05303379 if (!pci_wait_for_pending_transaction(dev))
3380 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003381
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003382 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3383
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003384 msleep(100);
3385
3386 return 0;
3387}
3388
Xudong Haodf558de2012-04-27 09:16:46 -06003389#include "../gpu/drm/i915/i915_reg.h"
3390#define MSG_CTL 0x45010
3391#define NSDE_PWR_STATE 0xd0100
3392#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3393
3394static int reset_ivb_igd(struct pci_dev *dev, int probe)
3395{
3396 void __iomem *mmio_base;
3397 unsigned long timeout;
3398 u32 val;
3399
3400 if (probe)
3401 return 0;
3402
3403 mmio_base = pci_iomap(dev, 0, 0);
3404 if (!mmio_base)
3405 return -ENOMEM;
3406
3407 iowrite32(0x00000002, mmio_base + MSG_CTL);
3408
3409 /*
3410 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3411 * driver loaded sets the right bits. However, this's a reset and
3412 * the bits have been set by i915 previously, so we clobber
3413 * SOUTH_CHICKEN2 register directly here.
3414 */
3415 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3416
3417 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3418 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3419
3420 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3421 do {
3422 val = ioread32(mmio_base + PCH_PP_STATUS);
3423 if ((val & 0xb0000000) == 0)
3424 goto reset_complete;
3425 msleep(10);
3426 } while (time_before(jiffies, timeout));
3427 dev_warn(&dev->dev, "timeout during reset\n");
3428
3429reset_complete:
3430 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3431
3432 pci_iounmap(dev, mmio_base);
3433 return 0;
3434}
3435
Casey Leedom2c6217e2013-08-06 15:48:37 +05303436/*
3437 * Device-specific reset method for Chelsio T4-based adapters.
3438 */
3439static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3440{
3441 u16 old_command;
3442 u16 msix_flags;
3443
3444 /*
3445 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3446 * that we have no device-specific reset method.
3447 */
3448 if ((dev->device & 0xf000) != 0x4000)
3449 return -ENOTTY;
3450
3451 /*
3452 * If this is the "probe" phase, return 0 indicating that we can
3453 * reset this device.
3454 */
3455 if (probe)
3456 return 0;
3457
3458 /*
3459 * T4 can wedge if there are DMAs in flight within the chip and Bus
3460 * Master has been disabled. We need to have it on till the Function
3461 * Level Reset completes. (BUS_MASTER is disabled in
3462 * pci_reset_function()).
3463 */
3464 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3465 pci_write_config_word(dev, PCI_COMMAND,
3466 old_command | PCI_COMMAND_MASTER);
3467
3468 /*
3469 * Perform the actual device function reset, saving and restoring
3470 * configuration information around the reset.
3471 */
3472 pci_save_state(dev);
3473
3474 /*
3475 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3476 * are disabled when an MSI-X interrupt message needs to be delivered.
3477 * So we briefly re-enable MSI-X interrupts for the duration of the
3478 * FLR. The pci_restore_state() below will restore the original
3479 * MSI-X state.
3480 */
3481 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3482 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3483 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3484 msix_flags |
3485 PCI_MSIX_FLAGS_ENABLE |
3486 PCI_MSIX_FLAGS_MASKALL);
3487
3488 /*
3489 * Start of pcie_flr() code sequence. This reset code is a copy of
3490 * the guts of pcie_flr() because that's not an exported function.
3491 */
3492
3493 if (!pci_wait_for_pending_transaction(dev))
3494 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3495
3496 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3497 msleep(100);
3498
3499 /*
3500 * End of pcie_flr() code sequence.
3501 */
3502
3503 /*
3504 * Restore the configuration information (BAR values, etc.) including
3505 * the original PCI Configuration Space Command word, and return
3506 * success.
3507 */
3508 pci_restore_state(dev);
3509 pci_write_config_word(dev, PCI_COMMAND, old_command);
3510 return 0;
3511}
3512
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003513#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
Xudong Haodf558de2012-04-27 09:16:46 -06003514#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3515#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003516
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003517static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003518 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3519 reset_intel_82599_sfp_virtfn },
Xudong Haodf558de2012-04-27 09:16:46 -06003520 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3521 reset_ivb_igd },
3522 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3523 reset_ivb_igd },
Dexuan Cuiaeb30012009-12-07 13:03:22 +08003524 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3525 reset_intel_generic_dev },
Casey Leedom2c6217e2013-08-06 15:48:37 +05303526 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3527 reset_chelsio_generic_dev },
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003528 { 0 }
3529};
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003530
Xudong Haodf558de2012-04-27 09:16:46 -06003531/*
3532 * These device-specific reset methods are here rather than in a driver
3533 * because when a host assigns a device to a guest VM, the host may need
3534 * to reset the device but probably doesn't have a driver for it.
3535 */
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003536int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3537{
Linus Torvaldsdf9d1e82009-12-31 16:44:43 -08003538 const struct pci_dev_reset_methods *i;
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003539
3540 for (i = pci_dev_reset_methods; i->reset; i++) {
3541 if ((i->vendor == dev->vendor ||
3542 i->vendor == (u16)PCI_ANY_ID) &&
3543 (i->device == dev->device ||
3544 i->device == (u16)PCI_ANY_ID))
3545 return i->reset(dev, probe);
3546 }
3547
3548 return -ENOTTY;
3549}
Alex Williamson12ea6ca2012-06-11 05:26:55 +00003550
Alex Williamsonec637fb2014-05-22 17:07:49 -06003551static void quirk_dma_func0_alias(struct pci_dev *dev)
3552{
3553 if (PCI_FUNC(dev->devfn) != 0) {
3554 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
3555 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3556 }
3557}
3558
3559/*
3560 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3561 *
3562 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3563 */
3564DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3565DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3566
Alex Williamsoncc346a42014-05-28 14:54:00 -06003567static void quirk_dma_func1_alias(struct pci_dev *dev)
3568{
3569 if (PCI_FUNC(dev->devfn) != 1) {
3570 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
3571 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3572 }
3573}
3574
3575/*
3576 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3577 * SKUs function 1 is present and is a legacy IDE controller, in other
3578 * SKUs this function is not present, making this a ghost requester.
3579 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3580 */
Sakari Ailus247de692015-05-22 00:03:38 +03003581DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3582 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3584 quirk_dma_func1_alias);
3585/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3587 quirk_dma_func1_alias);
3588/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3590 quirk_dma_func1_alias);
3591/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3593 quirk_dma_func1_alias);
3594/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3596 quirk_dma_func1_alias);
3597/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3599 quirk_dma_func1_alias);
Jérôme Carreteroc2e0fb92014-06-03 15:41:56 -04003600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3601 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003602/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3604 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3605 quirk_dma_func1_alias);
3606
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003607/*
Alex Williamsond3d2ab42015-01-13 11:26:50 -07003608 * Some devices DMA with the wrong devfn, not just the wrong function.
3609 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3610 * the alias is "fixed" and independent of the device devfn.
3611 *
3612 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3613 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3614 * single device on the secondary bus. In reality, the single exposed
3615 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3616 * that provides a bridge to the internal bus of the I/O processor. The
3617 * controller supports private devices, which can be hidden from PCI config
3618 * space. In the case of the Adaptec 3405, a private device at 01.0
3619 * appears to be the DMA engine, which therefore needs to become a DMA
3620 * alias for the device.
3621 */
3622static const struct pci_device_id fixed_dma_alias_tbl[] = {
3623 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3624 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3625 .driver_data = PCI_DEVFN(1, 0) },
3626 { 0 }
3627};
3628
3629static void quirk_fixed_dma_alias(struct pci_dev *dev)
3630{
3631 const struct pci_device_id *id;
3632
3633 id = pci_match_id(fixed_dma_alias_tbl, dev);
3634 if (id) {
3635 dev->dma_alias_devfn = id->driver_data;
3636 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3637 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
3638 PCI_SLOT(dev->dma_alias_devfn),
3639 PCI_FUNC(dev->dma_alias_devfn));
3640 }
3641}
3642
3643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3644
3645/*
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003646 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3647 * using the wrong DMA alias for the device. Some of these devices can be
3648 * used as either forward or reverse bridges, so we need to test whether the
3649 * device is operating in the correct mode. We could probably apply this
3650 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3651 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3652 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3653 */
3654static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3655{
3656 if (!pci_is_root_bus(pdev->bus) &&
3657 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3658 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3659 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3660 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3661}
3662/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3664 quirk_use_pcie_bridge_dma_alias);
3665/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3666DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
Alex Williamson98ca50d2014-06-09 12:43:25 -06003667/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3668DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
Alex Williamson8ab4abb2014-07-05 15:26:52 -06003669/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3670DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003671
Alex Williamson15b100d2013-06-27 16:40:00 -06003672/*
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003673 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3674 * class code. Fix it.
3675 */
3676static void quirk_tw686x_class(struct pci_dev *pdev)
3677{
3678 u32 class = pdev->class;
3679
3680 /* Use "Multimedia controller" class */
3681 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3682 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3683 class, pdev->class);
3684}
3685DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 0,
3686 quirk_tw686x_class);
3687DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 0,
3688 quirk_tw686x_class);
3689DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 0,
3690 quirk_tw686x_class);
3691DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 0,
3692 quirk_tw686x_class);
3693
3694/*
Alex Williamson15b100d2013-06-27 16:40:00 -06003695 * AMD has indicated that the devices below do not support peer-to-peer
3696 * in any system where they are found in the southbridge with an AMD
3697 * IOMMU in the system. Multifunction devices that do not support
3698 * peer-to-peer between functions can claim to support a subset of ACS.
3699 * Such devices effectively enable request redirect (RR) and completion
3700 * redirect (CR) since all transactions are redirected to the upstream
3701 * root complex.
3702 *
3703 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3704 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3705 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3706 *
3707 * 1002:4385 SBx00 SMBus Controller
3708 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3709 * 1002:4383 SBx00 Azalia (Intel HDA)
3710 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3711 * 1002:4384 SBx00 PCI to PCI Bridge
3712 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
Marti Raudsepp3587e622014-10-02 08:50:31 -06003713 *
3714 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
3715 *
3716 * 1022:780f [AMD] FCH PCI Bridge
3717 * 1022:7809 [AMD] FCH USB OHCI Controller
Alex Williamson15b100d2013-06-27 16:40:00 -06003718 */
3719static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3720{
3721#ifdef CONFIG_ACPI
3722 struct acpi_table_header *header = NULL;
3723 acpi_status status;
3724
3725 /* Targeting multifunction devices on the SB (appears on root bus) */
3726 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3727 return -ENODEV;
3728
3729 /* The IVRS table describes the AMD IOMMU */
3730 status = acpi_get_table("IVRS", 0, &header);
3731 if (ACPI_FAILURE(status))
3732 return -ENODEV;
3733
3734 /* Filter out flags not applicable to multifunction */
3735 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3736
3737 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3738#else
3739 return -ENODEV;
3740#endif
3741}
3742
Alex Williamsond99321b2014-02-03 14:27:46 -07003743/*
3744 * Many Intel PCH root ports do provide ACS-like features to disable peer
3745 * transactions and validate bus numbers in requests, but do not provide an
3746 * actual PCIe ACS capability. This is the list of device IDs known to fall
3747 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3748 */
3749static const u16 pci_quirk_intel_pch_acs_ids[] = {
3750 /* Ibexpeak PCH */
3751 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3752 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3753 /* Cougarpoint PCH */
3754 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3755 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3756 /* Pantherpoint PCH */
3757 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3758 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3759 /* Lynxpoint-H PCH */
3760 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3761 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3762 /* Lynxpoint-LP PCH */
3763 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3764 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3765 /* Wildcat PCH */
3766 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3767 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
Alex Williamson1a30fd02014-03-31 12:21:38 -06003768 /* Patsburg (X79) PCH */
3769 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
Alex Williamson78e88352015-01-22 11:15:43 -07003770 /* Wellsburg (X99) PCH */
3771 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
3772 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
Alex Williamsondca230d2015-05-01 13:20:13 -06003773 /* Lynx Point (9 series) PCH */
3774 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
Alex Williamsond99321b2014-02-03 14:27:46 -07003775};
3776
3777static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3778{
3779 int i;
3780
3781 /* Filter out a few obvious non-matches first */
3782 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3783 return false;
3784
3785 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
3786 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
3787 return true;
3788
3789 return false;
3790}
3791
3792#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3793
3794static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3795{
3796 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
3797 INTEL_PCH_ACS_FLAGS : 0;
3798
3799 if (!pci_quirk_intel_pch_acs_match(dev))
3800 return -ENOTTY;
3801
3802 return acs_flags & ~flags ? 0 : 1;
3803}
3804
Alex Williamson100ebb22014-09-26 17:07:59 -06003805static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
Alex Williamson89b51cb2014-09-17 08:59:36 -06003806{
3807 /*
3808 * SV, TB, and UF are not relevant to multifunction endpoints.
3809 *
Alex Williamson100ebb22014-09-26 17:07:59 -06003810 * Multifunction devices are only required to implement RR, CR, and DT
3811 * in their ACS capability if they support peer-to-peer transactions.
3812 * Devices matching this quirk have been verified by the vendor to not
3813 * perform peer-to-peer with other functions, allowing us to mask out
3814 * these bits as if they were unimplemented in the ACS capability.
Alex Williamson89b51cb2014-09-17 08:59:36 -06003815 */
3816 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3817 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3818
3819 return acs_flags ? 0 : 1;
3820}
3821
Alex Williamsonad805752012-06-11 05:27:07 +00003822static const struct pci_dev_acs_enabled {
3823 u16 vendor;
3824 u16 device;
3825 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3826} pci_dev_acs_enabled[] = {
Alex Williamson15b100d2013-06-27 16:40:00 -06003827 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3828 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3829 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3830 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3831 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3832 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
Marti Raudsepp3587e622014-10-02 08:50:31 -06003833 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
3834 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
Alex Williamson100ebb22014-09-26 17:07:59 -06003835 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
3836 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
3837 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
3838 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
3839 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
3840 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
3841 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
3842 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
3843 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
3844 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
3845 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
3846 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
3847 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
3848 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
3849 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
3850 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
3851 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
3852 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
3853 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
3854 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
3855 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
3856 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
Alex Williamsond7488042015-03-20 12:27:57 -06003857 /* 82580 */
3858 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
3859 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
3860 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
3861 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
3862 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
3863 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
3864 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
3865 /* 82576 */
3866 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
3867 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
3868 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
3869 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
3870 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
3871 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
3872 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
3873 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
3874 /* 82575 */
3875 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
3876 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
3877 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
3878 /* I350 */
3879 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
3880 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
3881 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
3882 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
3883 /* 82571 (Quads omitted due to non-ACS switch) */
3884 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
3885 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
3886 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
3887 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
3888 /* Intel PCH root ports */
Alex Williamsond99321b2014-02-03 14:27:46 -07003889 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
Vasundhara Volam6a3763d2015-01-13 01:22:23 -05003890 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
3891 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
Alex Williamsonad805752012-06-11 05:27:07 +00003892 { 0 }
3893};
3894
3895int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3896{
3897 const struct pci_dev_acs_enabled *i;
3898 int ret;
3899
3900 /*
3901 * Allow devices that do not expose standard PCIe ACS capabilities
3902 * or control to indicate their support here. Multi-function express
3903 * devices which do not allow internal peer-to-peer between functions,
3904 * but do not implement PCIe ACS may wish to return true here.
3905 */
3906 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3907 if ((i->vendor == dev->vendor ||
3908 i->vendor == (u16)PCI_ANY_ID) &&
3909 (i->device == dev->device ||
3910 i->device == (u16)PCI_ANY_ID)) {
3911 ret = i->acs_enabled(dev, acs_flags);
3912 if (ret >= 0)
3913 return ret;
3914 }
3915 }
3916
3917 return -ENOTTY;
3918}
Alex Williamson2c744242014-02-03 14:27:33 -07003919
Alex Williamsond99321b2014-02-03 14:27:46 -07003920/* Config space offset of Root Complex Base Address register */
3921#define INTEL_LPC_RCBA_REG 0xf0
3922/* 31:14 RCBA address */
3923#define INTEL_LPC_RCBA_MASK 0xffffc000
3924/* RCBA Enable */
3925#define INTEL_LPC_RCBA_ENABLE (1 << 0)
3926
3927/* Backbone Scratch Pad Register */
3928#define INTEL_BSPR_REG 0x1104
3929/* Backbone Peer Non-Posted Disable */
3930#define INTEL_BSPR_REG_BPNPD (1 << 8)
3931/* Backbone Peer Posted Disable */
3932#define INTEL_BSPR_REG_BPPD (1 << 9)
3933
3934/* Upstream Peer Decode Configuration Register */
3935#define INTEL_UPDCR_REG 0x1114
3936/* 5:0 Peer Decode Enable bits */
3937#define INTEL_UPDCR_REG_MASK 0x3f
3938
3939static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
3940{
3941 u32 rcba, bspr, updcr;
3942 void __iomem *rcba_mem;
3943
3944 /*
3945 * Read the RCBA register from the LPC (D31:F0). PCH root ports
3946 * are D28:F* and therefore get probed before LPC, thus we can't
3947 * use pci_get_slot/pci_read_config_dword here.
3948 */
3949 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
3950 INTEL_LPC_RCBA_REG, &rcba);
3951 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
3952 return -EINVAL;
3953
3954 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
3955 PAGE_ALIGN(INTEL_UPDCR_REG));
3956 if (!rcba_mem)
3957 return -ENOMEM;
3958
3959 /*
3960 * The BSPR can disallow peer cycles, but it's set by soft strap and
3961 * therefore read-only. If both posted and non-posted peer cycles are
3962 * disallowed, we're ok. If either are allowed, then we need to use
3963 * the UPDCR to disable peer decodes for each port. This provides the
3964 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
3965 */
3966 bspr = readl(rcba_mem + INTEL_BSPR_REG);
3967 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
3968 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
3969 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
3970 if (updcr & INTEL_UPDCR_REG_MASK) {
3971 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
3972 updcr &= ~INTEL_UPDCR_REG_MASK;
3973 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
3974 }
3975 }
3976
3977 iounmap(rcba_mem);
3978 return 0;
3979}
3980
3981/* Miscellaneous Port Configuration register */
3982#define INTEL_MPC_REG 0xd8
3983/* MPC: Invalid Receive Bus Number Check Enable */
3984#define INTEL_MPC_REG_IRBNCE (1 << 26)
3985
3986static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
3987{
3988 u32 mpc;
3989
3990 /*
3991 * When enabled, the IRBNCE bit of the MPC register enables the
3992 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
3993 * ensures that requester IDs fall within the bus number range
3994 * of the bridge. Enable if not already.
3995 */
3996 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
3997 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
3998 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
3999 mpc |= INTEL_MPC_REG_IRBNCE;
4000 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4001 }
4002}
4003
4004static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4005{
4006 if (!pci_quirk_intel_pch_acs_match(dev))
4007 return -ENOTTY;
4008
4009 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4010 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4011 return 0;
4012 }
4013
4014 pci_quirk_enable_intel_rp_mpc_acs(dev);
4015
4016 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4017
4018 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4019
4020 return 0;
4021}
4022
Alex Williamson2c744242014-02-03 14:27:33 -07004023static const struct pci_dev_enable_acs {
4024 u16 vendor;
4025 u16 device;
4026 int (*enable_acs)(struct pci_dev *dev);
4027} pci_dev_enable_acs[] = {
Alex Williamsond99321b2014-02-03 14:27:46 -07004028 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
Alex Williamson2c744242014-02-03 14:27:33 -07004029 { 0 }
4030};
4031
4032void pci_dev_specific_enable_acs(struct pci_dev *dev)
4033{
4034 const struct pci_dev_enable_acs *i;
4035 int ret;
4036
4037 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4038 if ((i->vendor == dev->vendor ||
4039 i->vendor == (u16)PCI_ANY_ID) &&
4040 (i->device == dev->device ||
4041 i->device == (u16)PCI_ANY_ID)) {
4042 ret = i->enable_acs(dev);
4043 if (ret >= 0)
4044 return;
4045 }
4046 }
4047}