blob: 8a5b52250bda5ce13dd5aaeadb547339a38a572c [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
8 */
9#include <linux/config.h>
10#include <linux/kernel.h>
11#include <linux/mm.h>
12#include <linux/bootmem.h>
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/pci.h>
16
17/*
18 * Indicate whether we respect the PCI setup left by the firmware.
19 *
20 * Make this long-lived so that we know when shutting down
21 * whether we probed only or not.
22 */
23int pci_probe_only;
24
25#define PCI_ASSIGN_ALL_BUSSES 1
26
27unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
28
29/*
30 * The PCI controller list.
31 */
32
33struct pci_controller *hose_head, **hose_tail = &hose_head;
34struct pci_controller *pci_isa_hose;
35
36unsigned long PCIBIOS_MIN_IO = 0x0000;
37unsigned long PCIBIOS_MIN_MEM = 0;
38
39/*
40 * We need to avoid collisions with `mirrored' VGA ports
41 * and other strange ISA hardware, so we always want the
42 * addresses to be allocated in the 0x000-0x0ff region
43 * modulo 0x400.
44 *
45 * Why? Because some silly external IO cards only decode
46 * the low 10 bits of the IO address. The 0x00-0xff region
47 * is reserved for motherboard devices that decode all 16
48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
49 * but we want to try to avoid allocating at 0x2900-0x2bff
50 * which might have be mirrored at 0x0100-0x03ff..
51 */
52void
53pcibios_align_resource(void *data, struct resource *res,
54 unsigned long size, unsigned long align)
55{
56 struct pci_dev *dev = data;
57 struct pci_controller *hose = dev->sysdata;
58 unsigned long start = res->start;
59
60 if (res->flags & IORESOURCE_IO) {
61 /* Make sure we start at our min on all hoses */
62 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
63 start = PCIBIOS_MIN_IO + hose->io_resource->start;
64
65 /*
66 * Put everything into 0x00-0xff region modulo 0x400
67 */
68 if (start & 0x300)
69 start = (start + 0x3ff) & ~0x3ff;
70 } else if (res->flags & IORESOURCE_MEM) {
71 /* Make sure we start at our min on all hoses */
72 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
74 }
75
76 res->start = start;
77}
78
79struct pci_controller * __init alloc_pci_controller(void)
80{
81 return alloc_bootmem(sizeof(struct pci_controller));
82}
83
84void __init register_pci_controller(struct pci_controller *hose)
85{
86 *hose_tail = hose;
87 hose_tail = &hose->next;
88}
89
90/* Most MIPS systems have straight-forward swizzling needs. */
91
92static inline u8 bridge_swizzle(u8 pin, u8 slot)
93{
94 return (((pin - 1) + slot) % 4) + 1;
95}
96
97static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
98{
99 u8 pin = *pinp;
100
101 while (dev->bus->parent) {
102 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
103 /* Move up the chain of bridges. */
104 dev = dev->bus->self;
105 }
106 *pinp = pin;
107
108 /* The slot is the slot of the last bridge. */
109 return PCI_SLOT(dev->devfn);
110}
111
112static int __init pcibios_init(void)
113{
114 struct pci_controller *hose;
115 struct pci_bus *bus;
116 int next_busno;
117 int need_domain_info = 0;
118
119 /* Scan all of the recorded PCI controllers. */
120 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
121
122 if (request_resource(&iomem_resource, hose->mem_resource) < 0)
123 goto out;
124 if (request_resource(&ioport_resource, hose->io_resource) < 0)
125 goto out_free_mem_resource;
126
127 if (!hose->iommu)
128 PCI_DMA_BUS_IS_PHYS = 1;
129
130 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
131 hose->bus = bus;
132 hose->need_domain_info = need_domain_info;
133 next_busno = bus->subordinate + 1;
134 /* Don't allow 8-bit bus number overflow inside the hose -
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700135 reserve some space for bridges. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 if (next_busno > 224) {
137 next_busno = 0;
138 need_domain_info = 1;
139 }
140 continue;
141
142out_free_mem_resource:
143 release_resource(hose->mem_resource);
144
145out:
146 printk(KERN_WARNING
147 "Skipping PCI bus scan due to resource conflict\n");
148 }
149
150 if (!pci_probe_only)
151 pci_assign_unassigned_resources();
152 pci_fixup_irqs(common_swizzle, pcibios_map_irq);
153
154 return 0;
155}
156
157subsys_initcall(pcibios_init);
158
159static int pcibios_enable_resources(struct pci_dev *dev, int mask)
160{
161 u16 cmd, old_cmd;
162 int idx;
163 struct resource *r;
164
165 pci_read_config_word(dev, PCI_COMMAND, &cmd);
166 old_cmd = cmd;
167 for(idx=0; idx<6; idx++) {
168 /* Only set up the requested stuff */
169 if (!(mask & (1<<idx)))
170 continue;
171
172 r = &dev->resource[idx];
173 if (!r->start && r->end) {
174 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
175 return -EINVAL;
176 }
177 if (r->flags & IORESOURCE_IO)
178 cmd |= PCI_COMMAND_IO;
179 if (r->flags & IORESOURCE_MEM)
180 cmd |= PCI_COMMAND_MEMORY;
181 }
182 if (dev->resource[PCI_ROM_RESOURCE].start)
183 cmd |= PCI_COMMAND_MEMORY;
184 if (cmd != old_cmd) {
185 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
186 pci_write_config_word(dev, PCI_COMMAND, cmd);
187 }
188 return 0;
189}
190
191/*
192 * If we set up a device for bus mastering, we need to check the latency
193 * timer as certain crappy BIOSes forget to set it properly.
194 */
195unsigned int pcibios_max_latency = 255;
196
197void pcibios_set_master(struct pci_dev *dev)
198{
199 u8 lat;
200 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
201 if (lat < 16)
202 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
203 else if (lat > pcibios_max_latency)
204 lat = pcibios_max_latency;
205 else
206 return;
207 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
208 pci_name(dev), lat);
209 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
210}
211
212unsigned int pcibios_assign_all_busses(void)
213{
214 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
215}
216
217int pcibios_enable_device(struct pci_dev *dev, int mask)
218{
219 int err;
220
221 if ((err = pcibios_enable_resources(dev, mask)) < 0)
222 return err;
223
224 return pcibios_plat_dev_init(dev);
225}
226
227static void __init pcibios_fixup_device_resources(struct pci_dev *dev,
228 struct pci_bus *bus)
229{
230 /* Update device resources. */
231 struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
232 unsigned long offset = 0;
233 int i;
234
235 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
236 if (!dev->resource[i].start)
237 continue;
238 if (dev->resource[i].flags & IORESOURCE_IO)
239 offset = hose->io_offset;
240 else if (dev->resource[i].flags & IORESOURCE_MEM)
241 offset = hose->mem_offset;
242
243 dev->resource[i].start += offset;
244 dev->resource[i].end += offset;
245 }
246}
247
248void __devinit pcibios_fixup_bus(struct pci_bus *bus)
249{
250 /* Propagate hose info into the subordinate devices. */
251
252 struct pci_controller *hose = bus->sysdata;
253 struct list_head *ln;
254 struct pci_dev *dev = bus->self;
255
256 if (!dev) {
257 bus->resource[0] = hose->io_resource;
258 bus->resource[1] = hose->mem_resource;
259 } else if (pci_probe_only &&
260 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
261 pci_read_bridge_bases(bus);
262 pcibios_fixup_device_resources(dev, bus);
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700263 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
265 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
266 struct pci_dev *dev = pci_dev_b(ln);
267
268 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
269 pcibios_fixup_device_resources(dev, bus);
270 }
271}
272
273void __init
274pcibios_update_irq(struct pci_dev *dev, int irq)
275{
276 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
277}
278
279void __devinit
280pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
281 struct resource *res)
282{
283 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
284 unsigned long offset = 0;
285
286 if (res->flags & IORESOURCE_IO)
287 offset = hose->io_offset;
288 else if (res->flags & IORESOURCE_MEM)
289 offset = hose->mem_offset;
290
291 region->start = res->start - offset;
292 region->end = res->end - offset;
293}
294
295#ifdef CONFIG_HOTPLUG
296EXPORT_SYMBOL(pcibios_resource_to_bus);
297EXPORT_SYMBOL(PCIBIOS_MIN_IO);
298EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
299#endif
300
301char *pcibios_setup(char *str)
302{
303 return str;
304}