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gerrit-public.fairphone.software / kernel / msm-4.9 / fdf8ec0a176ea29e7694ad0edd2cd34c820a3077 / . / arch / arm / boot / dts / r8a7792.dtsi
blob: 6017ea5280a00d20be4ebf99d47f57398857bfd5 [file] [log] [blame]
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7792-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a15";
28 reg = <0>;
29 clock-frequency = <1000000000>;
30 clocks = <&cpg_clocks R8A7792_CLK_Z>;
31 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
32 next-level-cache = <&L2_CA15>;
33 };
34
35 L2_CA15: cache-controller@0 {
36 compatible = "cache";
37 reg = <0>;
38 cache-unified;
39 cache-level = <2>;
40 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
41 };
42 };
43
44 soc {
45 compatible = "simple-bus";
46 interrupt-parent = <&gic>;
47
48 #address-cells = <2>;
49 #size-cells = <2>;
50 ranges;
51
52 gic: interrupt-controller@f1001000 {
53 compatible = "arm,gic-400";
54 #interrupt-cells = <3>;
55 interrupt-controller;
56 reg = <0 0xf1001000 0 0x1000>,
57 <0 0xf1002000 0 0x1000>,
58 <0 0xf1004000 0 0x2000>,
59 <0 0xf1006000 0 0x2000>;
60 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
61 IRQ_TYPE_LEVEL_HIGH)>;
62 };
63
64 timer {
65 compatible = "arm,armv7-timer";
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
67 IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
69 IRQ_TYPE_LEVEL_LOW)>,
70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
71 IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
73 IRQ_TYPE_LEVEL_LOW)>;
74 };
75
76 sysc: system-controller@e6180000 {
77 compatible = "renesas,r8a7792-sysc";
78 reg = <0 0xe6180000 0 0x0200>;
79 #power-domain-cells = <1>;
80 };
81
Sergei Shtylyovfdf8ec02016-06-13 00:08:18 +0300[diff] [blame^]82 dmac0: dma-controller@e6700000 {
83 compatible = "renesas,dmac-r8a7792",
84 "renesas,rcar-dmac";
85 reg = <0 0xe6700000 0 0x20000>;
86 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
87 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
88 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
89 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
90 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
91 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
92 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
93 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-names = "error",
103 "ch0", "ch1", "ch2", "ch3",
104 "ch4", "ch5", "ch6", "ch7",
105 "ch8", "ch9", "ch10", "ch11",
106 "ch12", "ch13", "ch14";
107 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
108 clock-names = "fck";
109 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
110 #dma-cells = <1>;
111 dma-channels = <15>;
112 };
113
114 dmac1: dma-controller@e6720000 {
115 compatible = "renesas,dmac-r8a7792",
116 "renesas,rcar-dmac";
117 reg = <0 0xe6720000 0 0x20000>;
118 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
123 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
124 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
125 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
126 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
127 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
128 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
129 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
130 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
131 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
132 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
133 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "error",
135 "ch0", "ch1", "ch2", "ch3",
136 "ch4", "ch5", "ch6", "ch7",
137 "ch8", "ch9", "ch10", "ch11",
138 "ch12", "ch13", "ch14";
139 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
140 clock-names = "fck";
141 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
142 #dma-cells = <1>;
143 dma-channels = <15>;
144 };
145
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]146 /* Special CPG clocks */
147 cpg_clocks: cpg_clocks@e6150000 {
148 compatible = "renesas,r8a7792-cpg-clocks",
149 "renesas,rcar-gen2-cpg-clocks";
150 reg = <0 0xe6150000 0 0x1000>;
151 clocks = <&extal_clk>;
152 #clock-cells = <1>;
153 clock-output-names = "main", "pll0", "pll1", "pll3",
154 "lb", "qspi", "z", "adsp";
155 #power-domain-cells = <0>;
156 };
157
158 /* Fixed factor clocks */
159 zs_clk: zs {
160 compatible = "fixed-factor-clock";
161 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
162 #clock-cells = <0>;
163 clock-div = <6>;
164 clock-mult = <1>;
165 };
166 p_clk: p {
167 compatible = "fixed-factor-clock";
168 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
169 #clock-cells = <0>;
170 clock-div = <24>;
171 clock-mult = <1>;
172 };
173 cp_clk: cp {
174 compatible = "fixed-factor-clock";
175 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
176 #clock-cells = <0>;
177 clock-div = <48>;
178 clock-mult = <1>;
179 };
180
181 /* Gate clocks */
182 mstp2_clks: mstp2_clks@e6150138 {
183 compatible = "renesas,r8a7792-mstp-clocks",
184 "renesas,cpg-mstp-clocks";
185 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
186 clocks = <&zs_clk>, <&zs_clk>;
187 #clock-cells = <1>;
188 clock-indices = <
189 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
190 >;
191 clock-output-names = "sys-dmac1", "sys-dmac0";
192 };
193 mstp4_clks: mstp4_clks@e6150140 {
194 compatible = "renesas,r8a7792-mstp-clocks",
195 "renesas,cpg-mstp-clocks";
196 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
197 clocks = <&cp_clk>;
198 #clock-cells = <1>;
199 clock-indices = <R8A7792_CLK_IRQC>;
200 clock-output-names = "irqc";
201 };
202 mstp7_clks: mstp7_clks@e615014c {
203 compatible = "renesas,r8a7792-mstp-clocks",
204 "renesas,cpg-mstp-clocks";
205 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
206 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
207 <&p_clk>, <&p_clk>;
208 #clock-cells = <1>;
209 clock-indices = <
210 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
211 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
212 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
213 >;
214 clock-output-names = "hscif1", "hscif0", "scif3",
215 "scif2", "scif1", "scif0";
216 };
217 };
218
219 /* External root clock */
220 extal_clk: extal {
221 compatible = "fixed-clock";
222 #clock-cells = <0>;
223 /* This value must be overridden by the board. */
224 clock-frequency = <0>;
225 };
226
227 /* External SCIF clock */
228 scif_clk: scif {
229 compatible = "fixed-clock";
230 #clock-cells = <0>;
231 /* This value must be overridden by the board. */
232 clock-frequency = <0>;
233 };
234};