blob: aacc00d059801bbfef78faa9251c276f9e4bf8da [file] [log] [blame]
Colin Cross73625e32010-06-23 15:49:17 -07001/*
Colin Cross73625e32010-06-23 15:49:17 -07002 * Copyright (C) 2010 Google, Inc.
Danny Huang7495b2e2013-03-18 19:17:34 +08003 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
Colin Cross73625e32010-06-23 15:49:17 -07004 *
5 * Author:
6 * Colin Cross <ccross@android.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
Olof Johansson9a1086d2011-10-13 00:31:20 -070019#ifndef __MACH_TEGRA_FUSE_H
20#define __MACH_TEGRA_FUSE_H
21
22enum tegra_revision {
23 TEGRA_REVISION_UNKNOWN = 0,
24 TEGRA_REVISION_A01,
25 TEGRA_REVISION_A02,
26 TEGRA_REVISION_A03,
27 TEGRA_REVISION_A03p,
28 TEGRA_REVISION_A04,
29 TEGRA_REVISION_MAX,
30};
31
32#define SKU_ID_T20 8
33#define SKU_ID_T25SE 20
34#define SKU_ID_AP25 23
35#define SKU_ID_T25 24
36#define SKU_ID_AP25E 27
37#define SKU_ID_T25E 28
38
Peter De Schrijver35b14982012-02-10 01:47:41 +020039#define TEGRA20 0x20
40#define TEGRA30 0x30
Hiroshi Doyu7b30d452013-01-24 01:10:22 +000041#define TEGRA114 0x35
Peter De Schrijver35b14982012-02-10 01:47:41 +020042
Olof Johansson9a1086d2011-10-13 00:31:20 -070043extern int tegra_sku_id;
44extern int tegra_cpu_process_id;
45extern int tegra_core_process_id;
Peter De Schrijver4c4ad662012-02-10 01:47:42 +020046extern int tegra_chip_id;
Danny Huangf8ddda72012-11-15 15:42:34 +080047extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
Danny Huang25cd5a32012-11-15 15:42:33 +080048extern int tegra_soc_speedo_id;
Olof Johansson9a1086d2011-10-13 00:31:20 -070049extern enum tegra_revision tegra_revision;
50
Olof Johanssondee47182011-10-17 16:39:24 -070051extern int tegra_bct_strapping;
52
Colin Cross73625e32010-06-23 15:49:17 -070053unsigned long long tegra_chip_uid(void);
Colin Cross73625e32010-06-23 15:49:17 -070054void tegra_init_fuse(void);
Danny Huang1f851a22012-11-15 15:42:32 +080055bool tegra_spare_fuse(int bit);
56u32 tegra_fuse_readl(unsigned long offset);
Olof Johansson9a1086d2011-10-13 00:31:20 -070057
Danny Huang25cd5a32012-11-15 15:42:33 +080058#ifdef CONFIG_ARCH_TEGRA_2x_SOC
59void tegra20_init_speedo_data(void);
60#else
61static inline void tegra20_init_speedo_data(void) {}
62#endif
63
Danny Huangf8ddda72012-11-15 15:42:34 +080064#ifdef CONFIG_ARCH_TEGRA_3x_SOC
65void tegra30_init_speedo_data(void);
66#else
67static inline void tegra30_init_speedo_data(void) {}
68#endif
69
Danny Huang7495b2e2013-03-18 19:17:34 +080070#ifdef CONFIG_ARCH_TEGRA_114_SOC
71void tegra114_init_speedo_data(void);
72#else
73static inline void tegra114_init_speedo_data(void) {}
74#endif
75
Olof Johansson9a1086d2011-10-13 00:31:20 -070076#endif