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Sourav Poddar505a1492013-08-20 18:55:48 +05301/*
2 * TI QSPI driver
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/omap-dma.h>
25#include <linux/platform_device.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28#include <linux/io.h>
29#include <linux/slab.h>
30#include <linux/pm_runtime.h>
31#include <linux/of.h>
32#include <linux/of_device.h>
33#include <linux/pinctrl/consumer.h>
34
35#include <linux/spi/spi.h>
36
37struct ti_qspi_regs {
38 u32 clkctrl;
39};
40
41struct ti_qspi {
42 struct completion transfer_complete;
43
Sourav Poddar505a1492013-08-20 18:55:48 +053044 /* list synchronization */
45 struct mutex list_lock;
46
47 struct spi_master *master;
48 void __iomem *base;
Sourav Poddar6b3938a2013-12-06 19:54:43 +053049 void __iomem *ctrl_base;
50 void __iomem *mmap_base;
Sourav Poddar505a1492013-08-20 18:55:48 +053051 struct clk *fclk;
52 struct device *dev;
53
54 struct ti_qspi_regs ctx_reg;
55
56 u32 spi_max_frequency;
57 u32 cmd;
58 u32 dc;
Sourav Poddar6b3938a2013-12-06 19:54:43 +053059
60 bool ctrl_mod;
Sourav Poddar505a1492013-08-20 18:55:48 +053061};
62
63#define QSPI_PID (0x0)
64#define QSPI_SYSCONFIG (0x10)
65#define QSPI_INTR_STATUS_RAW_SET (0x20)
66#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
67#define QSPI_INTR_ENABLE_SET_REG (0x28)
68#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
69#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
70#define QSPI_SPI_DC_REG (0x44)
71#define QSPI_SPI_CMD_REG (0x48)
72#define QSPI_SPI_STATUS_REG (0x4c)
73#define QSPI_SPI_DATA_REG (0x50)
74#define QSPI_SPI_SETUP0_REG (0x54)
75#define QSPI_SPI_SWITCH_REG (0x64)
76#define QSPI_SPI_SETUP1_REG (0x58)
77#define QSPI_SPI_SETUP2_REG (0x5c)
78#define QSPI_SPI_SETUP3_REG (0x60)
79#define QSPI_SPI_DATA_REG_1 (0x68)
80#define QSPI_SPI_DATA_REG_2 (0x6c)
81#define QSPI_SPI_DATA_REG_3 (0x70)
82
83#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
84
85#define QSPI_FCLK 192000000
86
87/* Clock Control */
88#define QSPI_CLK_EN (1 << 31)
89#define QSPI_CLK_DIV_MAX 0xffff
90
91/* Command */
92#define QSPI_EN_CS(n) (n << 28)
93#define QSPI_WLEN(n) ((n - 1) << 19)
94#define QSPI_3_PIN (1 << 18)
95#define QSPI_RD_SNGL (1 << 16)
96#define QSPI_WR_SNGL (2 << 16)
97#define QSPI_RD_DUAL (3 << 16)
98#define QSPI_RD_QUAD (7 << 16)
99#define QSPI_INVAL (4 << 16)
100#define QSPI_WC_CMD_INT_EN (1 << 14)
101#define QSPI_FLEN(n) ((n - 1) << 0)
Vignesh Rf682c4f2015-08-20 16:00:59 +0530102#define QSPI_WLEN_MAX_BITS 128
103#define QSPI_WLEN_MAX_BYTES 16
Sourav Poddar505a1492013-08-20 18:55:48 +0530104
105/* STATUS REGISTER */
Mugunthan V N00611042015-02-18 00:33:51 +0530106#define BUSY 0x01
Sourav Poddar505a1492013-08-20 18:55:48 +0530107#define WC 0x02
108
109/* INTERRUPT REGISTER */
110#define QSPI_WC_INT_EN (1 << 1)
111#define QSPI_WC_INT_DISABLE (1 << 1)
112
113/* Device Control */
114#define QSPI_DD(m, n) (m << (3 + n * 8))
115#define QSPI_CKPHA(n) (1 << (2 + n * 8))
116#define QSPI_CSPOL(n) (1 << (1 + n * 8))
117#define QSPI_CKPOL(n) (1 << (n * 8))
118
119#define QSPI_FRAME 4096
120
121#define QSPI_AUTOSUSPEND_TIMEOUT 2000
122
123static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
124 unsigned long reg)
125{
126 return readl(qspi->base + reg);
127}
128
129static inline void ti_qspi_write(struct ti_qspi *qspi,
130 unsigned long val, unsigned long reg)
131{
132 writel(val, qspi->base + reg);
133}
134
135static int ti_qspi_setup(struct spi_device *spi)
136{
137 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
138 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
139 int clk_div = 0, ret;
140 u32 clk_ctrl_reg, clk_rate, clk_mask;
141
142 if (spi->master->busy) {
143 dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
144 return -EBUSY;
145 }
146
147 if (!qspi->spi_max_frequency) {
148 dev_err(qspi->dev, "spi max frequency not defined\n");
149 return -EINVAL;
150 }
151
152 clk_rate = clk_get_rate(qspi->fclk);
153
154 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
155
156 if (clk_div < 0) {
157 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
158 return -EINVAL;
159 }
160
161 if (clk_div > QSPI_CLK_DIV_MAX) {
162 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
163 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
164 return -EINVAL;
165 }
166
167 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
168 qspi->spi_max_frequency, clk_div);
169
170 ret = pm_runtime_get_sync(qspi->dev);
Sourav Poddar05b96672013-11-19 18:37:15 +0530171 if (ret < 0) {
Sourav Poddar505a1492013-08-20 18:55:48 +0530172 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
173 return ret;
174 }
175
176 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
177
178 clk_ctrl_reg &= ~QSPI_CLK_EN;
179
180 /* disable SCLK */
181 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
182
183 /* enable SCLK */
184 clk_mask = QSPI_CLK_EN | clk_div;
185 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
186 ctx_reg->clkctrl = clk_mask;
187
188 pm_runtime_mark_last_busy(qspi->dev);
189 ret = pm_runtime_put_autosuspend(qspi->dev);
190 if (ret < 0) {
191 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
192 return ret;
193 }
194
195 return 0;
196}
197
198static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
199{
200 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
201
202 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
203}
204
Mugunthan V N00611042015-02-18 00:33:51 +0530205static inline u32 qspi_is_busy(struct ti_qspi *qspi)
206{
207 u32 stat;
208 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
209
210 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
211 while ((stat & BUSY) && time_after(timeout, jiffies)) {
212 cpu_relax();
213 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
214 }
215
216 WARN(stat & BUSY, "qspi busy\n");
217 return stat & BUSY;
218}
219
Sourav Poddar505a1492013-08-20 18:55:48 +0530220static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
221{
Vignesh Rf682c4f2015-08-20 16:00:59 +0530222 int wlen, count, xfer_len;
Sourav Poddar505a1492013-08-20 18:55:48 +0530223 unsigned int cmd;
224 const u8 *txbuf;
Vignesh Rf682c4f2015-08-20 16:00:59 +0530225 u32 data;
Sourav Poddar505a1492013-08-20 18:55:48 +0530226
227 txbuf = t->tx_buf;
228 cmd = qspi->cmd | QSPI_WR_SNGL;
229 count = t->len;
Axel Lin3ab54622014-01-12 14:40:22 +0800230 wlen = t->bits_per_word >> 3; /* in bytes */
Vignesh Rf682c4f2015-08-20 16:00:59 +0530231 xfer_len = wlen;
Sourav Poddar505a1492013-08-20 18:55:48 +0530232
233 while (count) {
Mugunthan V N00611042015-02-18 00:33:51 +0530234 if (qspi_is_busy(qspi))
235 return -EBUSY;
236
Sourav Poddar505a1492013-08-20 18:55:48 +0530237 switch (wlen) {
Axel Lin3ab54622014-01-12 14:40:22 +0800238 case 1:
Sourav Poddar505a1492013-08-20 18:55:48 +0530239 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
240 cmd, qspi->dc, *txbuf);
Vignesh Rf682c4f2015-08-20 16:00:59 +0530241 if (count >= QSPI_WLEN_MAX_BYTES) {
242 u32 *txp = (u32 *)txbuf;
243
244 data = cpu_to_be32(*txp++);
245 writel(data, qspi->base +
246 QSPI_SPI_DATA_REG_3);
247 data = cpu_to_be32(*txp++);
248 writel(data, qspi->base +
249 QSPI_SPI_DATA_REG_2);
250 data = cpu_to_be32(*txp++);
251 writel(data, qspi->base +
252 QSPI_SPI_DATA_REG_1);
253 data = cpu_to_be32(*txp++);
254 writel(data, qspi->base +
255 QSPI_SPI_DATA_REG);
256 xfer_len = QSPI_WLEN_MAX_BYTES;
257 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
258 } else {
259 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
260 cmd = qspi->cmd | QSPI_WR_SNGL;
261 xfer_len = wlen;
262 cmd |= QSPI_WLEN(wlen);
263 }
Sourav Poddar505a1492013-08-20 18:55:48 +0530264 break;
Axel Lin3ab54622014-01-12 14:40:22 +0800265 case 2:
Sourav Poddar505a1492013-08-20 18:55:48 +0530266 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
267 cmd, qspi->dc, *txbuf);
268 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530269 break;
Axel Lin3ab54622014-01-12 14:40:22 +0800270 case 4:
Sourav Poddar505a1492013-08-20 18:55:48 +0530271 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
272 cmd, qspi->dc, *txbuf);
273 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530274 break;
275 }
Axel Lin3ab54622014-01-12 14:40:22 +0800276
277 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
Nicholas Mc Guire060556a2015-02-05 10:03:42 -0500278 if (!wait_for_completion_timeout(&qspi->transfer_complete,
279 QSPI_COMPLETION_TIMEOUT)) {
Axel Lin3ab54622014-01-12 14:40:22 +0800280 dev_err(qspi->dev, "write timed out\n");
281 return -ETIMEDOUT;
282 }
Vignesh Rf682c4f2015-08-20 16:00:59 +0530283 txbuf += xfer_len;
284 count -= xfer_len;
Sourav Poddar505a1492013-08-20 18:55:48 +0530285 }
286
287 return 0;
288}
289
290static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
291{
Nicholas Mc Guire060556a2015-02-05 10:03:42 -0500292 int wlen, count;
Sourav Poddar505a1492013-08-20 18:55:48 +0530293 unsigned int cmd;
294 u8 *rxbuf;
295
296 rxbuf = t->rx_buf;
Sourav Poddar70e2e972013-08-23 15:12:16 +0530297 cmd = qspi->cmd;
298 switch (t->rx_nbits) {
299 case SPI_NBITS_DUAL:
300 cmd |= QSPI_RD_DUAL;
301 break;
302 case SPI_NBITS_QUAD:
303 cmd |= QSPI_RD_QUAD;
304 break;
305 default:
306 cmd |= QSPI_RD_SNGL;
307 break;
308 }
Sourav Poddar505a1492013-08-20 18:55:48 +0530309 count = t->len;
Axel Lin3ab54622014-01-12 14:40:22 +0800310 wlen = t->bits_per_word >> 3; /* in bytes */
Sourav Poddar505a1492013-08-20 18:55:48 +0530311
312 while (count) {
313 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
Mugunthan V N00611042015-02-18 00:33:51 +0530314 if (qspi_is_busy(qspi))
315 return -EBUSY;
316
Sourav Poddar505a1492013-08-20 18:55:48 +0530317 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
Nicholas Mc Guire060556a2015-02-05 10:03:42 -0500318 if (!wait_for_completion_timeout(&qspi->transfer_complete,
319 QSPI_COMPLETION_TIMEOUT)) {
Sourav Poddar505a1492013-08-20 18:55:48 +0530320 dev_err(qspi->dev, "read timed out\n");
321 return -ETIMEDOUT;
322 }
323 switch (wlen) {
Axel Lin3ab54622014-01-12 14:40:22 +0800324 case 1:
Sourav Poddar505a1492013-08-20 18:55:48 +0530325 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530326 break;
Axel Lin3ab54622014-01-12 14:40:22 +0800327 case 2:
Sourav Poddar505a1492013-08-20 18:55:48 +0530328 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530329 break;
Axel Lin3ab54622014-01-12 14:40:22 +0800330 case 4:
Sourav Poddar505a1492013-08-20 18:55:48 +0530331 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530332 break;
333 }
Axel Lin3ab54622014-01-12 14:40:22 +0800334 rxbuf += wlen;
335 count -= wlen;
Sourav Poddar505a1492013-08-20 18:55:48 +0530336 }
337
338 return 0;
339}
340
341static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
342{
343 int ret;
344
345 if (t->tx_buf) {
346 ret = qspi_write_msg(qspi, t);
347 if (ret) {
348 dev_dbg(qspi->dev, "Error while writing\n");
349 return ret;
350 }
351 }
352
353 if (t->rx_buf) {
354 ret = qspi_read_msg(qspi, t);
355 if (ret) {
356 dev_dbg(qspi->dev, "Error while reading\n");
357 return ret;
358 }
359 }
360
361 return 0;
362}
363
364static int ti_qspi_start_transfer_one(struct spi_master *master,
365 struct spi_message *m)
366{
367 struct ti_qspi *qspi = spi_master_get_devdata(master);
368 struct spi_device *spi = m->spi;
369 struct spi_transfer *t;
370 int status = 0, ret;
371 int frame_length;
372
373 /* setup device control reg */
374 qspi->dc = 0;
375
376 if (spi->mode & SPI_CPHA)
377 qspi->dc |= QSPI_CKPHA(spi->chip_select);
378 if (spi->mode & SPI_CPOL)
379 qspi->dc |= QSPI_CKPOL(spi->chip_select);
380 if (spi->mode & SPI_CS_HIGH)
381 qspi->dc |= QSPI_CSPOL(spi->chip_select);
382
383 frame_length = (m->frame_length << 3) / spi->bits_per_word;
384
385 frame_length = clamp(frame_length, 0, QSPI_FRAME);
386
387 /* setup command reg */
388 qspi->cmd = 0;
389 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
390 qspi->cmd |= QSPI_FLEN(frame_length);
391 qspi->cmd |= QSPI_WC_CMD_INT_EN;
392
393 ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
394 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
395
396 mutex_lock(&qspi->list_lock);
397
398 list_for_each_entry(t, &m->transfers, transfer_list) {
399 qspi->cmd |= QSPI_WLEN(t->bits_per_word);
400
401 ret = qspi_transfer_msg(qspi, t);
402 if (ret) {
403 dev_dbg(qspi->dev, "transfer message failed\n");
Wei Yongjunb6460362013-09-01 09:01:00 +0800404 mutex_unlock(&qspi->list_lock);
Sourav Poddar505a1492013-08-20 18:55:48 +0530405 return -EINVAL;
406 }
407
408 m->actual_length += t->len;
409 }
410
411 mutex_unlock(&qspi->list_lock);
412
413 m->status = status;
414 spi_finalize_current_message(master);
415
416 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
417
418 return status;
419}
420
421static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
422{
423 struct ti_qspi *qspi = dev_id;
424 u16 int_stat;
Sebastian Andrzej Siewior3b3a8002013-10-02 16:45:25 +0200425 u32 stat;
Sourav Poddar505a1492013-08-20 18:55:48 +0530426
427 irqreturn_t ret = IRQ_HANDLED;
428
Sourav Poddar505a1492013-08-20 18:55:48 +0530429 int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
Sebastian Andrzej Siewior3b3a8002013-10-02 16:45:25 +0200430 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530431
432 if (!int_stat) {
433 dev_dbg(qspi->dev, "No IRQ triggered\n");
434 ret = IRQ_NONE;
435 goto out;
436 }
437
Sourav Poddar505a1492013-08-20 18:55:48 +0530438 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
439 QSPI_INTR_STATUS_ENABLED_CLEAR);
Sebastian Andrzej Siewior3b3a8002013-10-02 16:45:25 +0200440 if (stat & WC)
Sourav Poddar505a1492013-08-20 18:55:48 +0530441 complete(&qspi->transfer_complete);
Sebastian Andrzej Siewior3b3a8002013-10-02 16:45:25 +0200442out:
443 return ret;
Sourav Poddar505a1492013-08-20 18:55:48 +0530444}
445
446static int ti_qspi_runtime_resume(struct device *dev)
447{
448 struct ti_qspi *qspi;
Sourav Poddar505a1492013-08-20 18:55:48 +0530449
Sourav Poddarf17414c2013-12-20 18:22:57 +0530450 qspi = dev_get_drvdata(dev);
Sourav Poddar505a1492013-08-20 18:55:48 +0530451 ti_qspi_restore_ctx(qspi);
452
453 return 0;
454}
455
456static const struct of_device_id ti_qspi_match[] = {
457 {.compatible = "ti,dra7xxx-qspi" },
Sourav Poddar09222fc2013-08-27 19:42:24 +0530458 {.compatible = "ti,am4372-qspi" },
Sourav Poddar505a1492013-08-20 18:55:48 +0530459 {},
460};
Sourav Poddare1432d32013-08-27 12:41:20 +0530461MODULE_DEVICE_TABLE(of, ti_qspi_match);
Sourav Poddar505a1492013-08-20 18:55:48 +0530462
463static int ti_qspi_probe(struct platform_device *pdev)
464{
465 struct ti_qspi *qspi;
466 struct spi_master *master;
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530467 struct resource *r, *res_ctrl, *res_mmap;
Sourav Poddar505a1492013-08-20 18:55:48 +0530468 struct device_node *np = pdev->dev.of_node;
469 u32 max_freq;
470 int ret = 0, num_cs, irq;
471
472 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
473 if (!master)
474 return -ENOMEM;
475
Sourav Poddar633795b2013-09-24 20:41:23 +0530476 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
Sourav Poddar505a1492013-08-20 18:55:48 +0530477
Sourav Poddar505a1492013-08-20 18:55:48 +0530478 master->flags = SPI_MASTER_HALF_DUPLEX;
479 master->setup = ti_qspi_setup;
480 master->auto_runtime_pm = true;
481 master->transfer_one_message = ti_qspi_start_transfer_one;
482 master->dev.of_node = pdev->dev.of_node;
Axel Linaa188f92014-02-05 21:59:18 +0800483 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
484 SPI_BPW_MASK(8);
Sourav Poddar505a1492013-08-20 18:55:48 +0530485
486 if (!of_property_read_u32(np, "num-cs", &num_cs))
487 master->num_chipselect = num_cs;
488
Sourav Poddar505a1492013-08-20 18:55:48 +0530489 qspi = spi_master_get_devdata(master);
490 qspi->master = master;
491 qspi->dev = &pdev->dev;
Wei Yongjun160a0612013-11-11 14:13:41 +0800492 platform_set_drvdata(pdev, qspi);
Sourav Poddar505a1492013-08-20 18:55:48 +0530493
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530494 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
495 if (r == NULL) {
496 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
497 if (r == NULL) {
498 dev_err(&pdev->dev, "missing platform data\n");
499 return -ENODEV;
500 }
501 }
502
503 res_mmap = platform_get_resource_byname(pdev,
504 IORESOURCE_MEM, "qspi_mmap");
505 if (res_mmap == NULL) {
506 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
507 if (res_mmap == NULL) {
508 dev_err(&pdev->dev,
509 "memory mapped resource not required\n");
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530510 }
511 }
512
513 res_ctrl = platform_get_resource_byname(pdev,
514 IORESOURCE_MEM, "qspi_ctrlmod");
515 if (res_ctrl == NULL) {
516 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
517 if (res_ctrl == NULL) {
518 dev_dbg(&pdev->dev,
519 "control module resources not required\n");
520 }
521 }
Sourav Poddar505a1492013-08-20 18:55:48 +0530522
523 irq = platform_get_irq(pdev, 0);
524 if (irq < 0) {
525 dev_err(&pdev->dev, "no irq resource?\n");
526 return irq;
527 }
528
Sourav Poddar505a1492013-08-20 18:55:48 +0530529 mutex_init(&qspi->list_lock);
530
531 qspi->base = devm_ioremap_resource(&pdev->dev, r);
532 if (IS_ERR(qspi->base)) {
533 ret = PTR_ERR(qspi->base);
534 goto free_master;
535 }
536
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530537 if (res_ctrl) {
538 qspi->ctrl_mod = true;
539 qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
540 if (IS_ERR(qspi->ctrl_base)) {
541 ret = PTR_ERR(qspi->ctrl_base);
542 goto free_master;
543 }
544 }
545
546 if (res_mmap) {
547 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
548 if (IS_ERR(qspi->mmap_base)) {
549 ret = PTR_ERR(qspi->mmap_base);
550 goto free_master;
551 }
552 }
553
Sebastian Andrzej Siewior3b3a8002013-10-02 16:45:25 +0200554 ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
Sourav Poddar505a1492013-08-20 18:55:48 +0530555 dev_name(&pdev->dev), qspi);
556 if (ret < 0) {
557 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
558 irq);
559 goto free_master;
560 }
561
562 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
563 if (IS_ERR(qspi->fclk)) {
564 ret = PTR_ERR(qspi->fclk);
565 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
566 }
567
568 init_completion(&qspi->transfer_complete);
569
570 pm_runtime_use_autosuspend(&pdev->dev);
571 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
572 pm_runtime_enable(&pdev->dev);
573
574 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
575 qspi->spi_max_frequency = max_freq;
576
Jingoo Han7388c032013-09-24 13:52:37 +0900577 ret = devm_spi_register_master(&pdev->dev, master);
Sourav Poddar505a1492013-08-20 18:55:48 +0530578 if (ret)
579 goto free_master;
580
581 return 0;
582
583free_master:
584 spi_master_put(master);
585 return ret;
586}
587
588static int ti_qspi_remove(struct platform_device *pdev)
589{
Axel Line3d8bee2014-01-07 19:04:03 +0800590 struct ti_qspi *qspi = platform_get_drvdata(pdev);
Sourav Poddarcbcabb72013-11-19 18:37:16 +0530591 int ret;
592
Sourav Poddarcbcabb72013-11-19 18:37:16 +0530593 ret = pm_runtime_get_sync(qspi->dev);
594 if (ret < 0) {
595 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
596 return ret;
597 }
Sourav Poddar505a1492013-08-20 18:55:48 +0530598
Sebastian Andrzej Siewior3b3a8002013-10-02 16:45:25 +0200599 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530600
Sourav Poddarcbcabb72013-11-19 18:37:16 +0530601 pm_runtime_put(qspi->dev);
602 pm_runtime_disable(&pdev->dev);
603
Sourav Poddar505a1492013-08-20 18:55:48 +0530604 return 0;
605}
606
607static const struct dev_pm_ops ti_qspi_pm_ops = {
608 .runtime_resume = ti_qspi_runtime_resume,
609};
610
611static struct platform_driver ti_qspi_driver = {
612 .probe = ti_qspi_probe,
Mark Browndabefd52013-10-07 12:02:26 +0100613 .remove = ti_qspi_remove,
Sourav Poddar505a1492013-08-20 18:55:48 +0530614 .driver = {
Axel Lin5a33d302014-01-12 15:02:32 +0800615 .name = "ti-qspi",
Sourav Poddar505a1492013-08-20 18:55:48 +0530616 .pm = &ti_qspi_pm_ops,
617 .of_match_table = ti_qspi_match,
618 }
619};
620
621module_platform_driver(ti_qspi_driver);
622
623MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
624MODULE_LICENSE("GPL v2");
625MODULE_DESCRIPTION("TI QSPI controller driver");
Axel Lin5a33d302014-01-12 15:02:32 +0800626MODULE_ALIAS("platform:ti-qspi");