Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 1 | MSM SuperSpeed USB3.0 SoC controller |
| 2 | |
| 3 | Required properties : |
| 4 | - compatible : should be "qcom,dwc-usb3-msm" |
| 5 | - reg: Address and length of the register set for the device |
| 6 | Required regs are: |
| 7 | "core_base" : usb controller register set |
| 8 | - interrupts: IRQ lines used by this controller |
| 9 | - interrupt-names : Interrupt resource entries are : |
| 10 | "hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM. |
| 11 | "pwr_event_irq" : Interrupt to controller for asynchronous events in LPM. |
| 12 | Used for SS-USB power events. |
| 13 | - clocks: a list of phandles to the controller clocks. Use as per |
| 14 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 15 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
| 16 | property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk" |
| 17 | and "utmi_clk". |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 18 | - resets: reset specifier pair consists of phandle for the reset provider |
| 19 | and reset lines used by this controller. |
| 20 | - reset-names: reset signal name strings sorted in the same order as the resets |
| 21 | property. |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 22 | |
| 23 | Optional properties : |
| 24 | - reg: Additional registers |
| 25 | "tcsr_base" : top-level CSR register to be written during power-on reset |
| 26 | initialize the internal MUX that controls whether to use USB3 controller |
| 27 | with primary port. |
| 28 | "ahb2phy_base" : top-level register to configure read/write wait cycle with |
| 29 | both QMP and QUSB PHY registers. |
| 30 | - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for |
| 31 | below optional properties: |
| 32 | - qcom,msm_bus,name |
| 33 | - qcom,msm_bus,num_cases |
| 34 | - qcom,msm_bus,num_paths |
| 35 | - qcom,msm_bus,vectors |
| 36 | - interrupt-names : Optional interrupt resource entries are: |
| 37 | "pmic_id_irq" : Interrupt from PMIC for external ID pin notification. |
| 38 | "ss_phy_irq" : Interrupt from super speed phy for wake up notification. |
| 39 | - clocks: a list of phandles to the controller clocks. Use as per |
| 40 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 41 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 42 | property. Optional clocks are "bus_aggr_clk", "noc_aggr_clk" and "cfg_ahb_clk". |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 43 | - qcom,charging-disabled: If present then battery charging using USB |
| 44 | is disabled. |
| 45 | - vbus_dwc3-supply: phandle to the 5V VBUS supply regulator used for host mode. |
| 46 | - USB3_GDSC-supply : phandle to the globally distributed switch controller |
| 47 | regulator node to the USB controller. |
| 48 | - qcom,dwc-usb3-msm-tx-fifo-size: If present, represents RAM size available for |
| 49 | TX fifo allocation in bytes |
| 50 | - qcom,usb-dbm : phandle for the DBM device |
| 51 | - qcom,lpm-to-suspend-delay-ms: Indicates timeout (in milliseconds) to release wakeup source |
| 52 | after USB is kept into LPM. |
| 53 | - qcom,ext-hub-reset-gpio: This corresponds to gpio which is used for HUB reset. |
| 54 | - qcom,disable-dev-mode-pm: If present, it disables PM runtime functionality for device mode. |
| 55 | - qcom,disable-host-mode-pm: If present, it disables XHCI PM runtime functionality when USB |
| 56 | host mode is used. |
Vijayavardhan Vennapusa | 3e668f3 | 2016-01-08 15:58:35 +0530 | [diff] [blame] | 57 | - qcom,core-clk-rate: If present, indicates clock frequency to be set for USB master clock. |
Hemant Kumar | 8e4c2f2 | 2017-01-24 18:13:07 -0800 | [diff] [blame] | 58 | - qcom,core-clk-rate-hs: If present, indicates min core clock frequency required to support |
| 59 | hs speed. |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 60 | - extcon: phandles to external connector devices. First phandle should point to |
| 61 | external connector, which provide "USB" cable events, the second |
| 62 | should point to external connector device, which provide "USB-HOST" |
| 63 | cable events. A single phandle may be specified if a single connector |
| 64 | device provides both "USB" and "USB-HOST" events. |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 65 | - qcom,num-gsi-evt-buffs: If present, specifies number of GSI based hardware accelerated |
| 66 | event buffers. 1 event buffer is needed per h/w accelerated endpoint. |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame^] | 67 | - qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs, |
| 68 | which is used as a vote by driver to get max performance in perf mode. |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 69 | |
| 70 | Sub nodes: |
| 71 | - Sub node for "DWC3- USB3 controller". |
| 72 | This sub node is required property for device node. The properties of this subnode |
| 73 | are specified in dwc3.txt. |
| 74 | |
| 75 | Example MSM USB3.0 controller device node : |
| 76 | usb@f9200000 { |
| 77 | compatible = "qcom,dwc-usb3-msm"; |
| 78 | reg = <0xf9200000 0xfc000>, |
| 79 | <0xfd4ab000 0x4>, |
| 80 | <0xf9b3e000 0x3ff>; |
| 81 | reg-names = "core_base", |
| 82 | "tcsr_base", |
| 83 | "ahb2phy_base", |
| 84 | interrupts = <0 133 0>; |
| 85 | interrupt-names = "hs_phy_irq"; |
| 86 | vbus_dwc3-supply = <&pm8941_mvs1>; |
| 87 | USB3_GDSC-supply = <&gdsc_usb30>; |
| 88 | qcom,dwc-usb3-msm-dbm-eps = <4> |
| 89 | qcom,dwc_usb3-adc_tm = <&pm8941_adc_tm>; |
| 90 | qcom,dwc-usb3-msm-tx-fifo-size = <29696>; |
| 91 | qcom,usb-dbm = <&dbm_1p4>; |
| 92 | qcom,lpm-to-suspend-delay-ms = <2>; |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 93 | qcom,num-gsi-evt-buffs = <0x2>; |
Vijayavardhan Vennapusa | e6d3f80 | 2016-12-15 13:48:39 +0530 | [diff] [blame^] | 94 | qcom,pm-qos-latency = <2>; |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 95 | |
| 96 | qcom,msm_bus,name = "usb3"; |
| 97 | qcom,msm_bus,num_cases = <2>; |
| 98 | qcom,msm_bus,num_paths = <1>; |
| 99 | qcom,msm_bus,vectors = |
| 100 | <61 512 0 0>, |
| 101 | <61 512 240000000 960000000>; |
| 102 | |
| 103 | clocks = <&clock_gcc clk_gcc_usb30_master_clk>, |
| 104 | <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, |
| 105 | <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 106 | <&clock_rpmcc RPM_AGGR2_NOC_CLK>, |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 107 | <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, |
| 108 | <&clock_gcc clk_gcc_usb30_sleep_clk>, |
| 109 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, |
| 110 | <&clock_gcc clk_cxo_dwc3_clk>; |
| 111 | |
Vijayavardhan Vennapusa | 934d9cd | 2016-11-30 13:10:01 +0530 | [diff] [blame] | 112 | clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "noc_aggr_clk", |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 113 | "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; |
| 114 | |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 115 | resets = <&clock_gcc GCC_USB_30_BCR>; |
| 116 | reset-names = "core_reset"; |
| 117 | |
Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame] | 118 | dwc3@f9200000 { |
| 119 | compatible = "synopsys,dwc3"; |
| 120 | reg = <0xf9200000 0xfc000>; |
| 121 | interrupts = <0 131 0>, <0 179 0>; |
| 122 | interrupt-names = "irq", "otg_irq"; |
| 123 | tx-fifo-resize; |
| 124 | }; |
| 125 | }; |