blob: bb7cc90bafb22f8c5bdbc61672b527a78442a715 [file] [log] [blame]
Larry Fingerc592e632012-10-25 13:46:32 -05001/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include <linux/vmalloc.h>
32#include <linux/module.h>
33
34#include "../core.h"
35#include "../pci.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "dm.h"
40#include "hw.h"
41#include "sw.h"
42#include "trx.h"
43#include "led.h"
44#include "table.h"
45#include "hal_btc.h"
46
47static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
48{
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 /*close ASPM for AMD defaultly */
52 rtlpci->const_amdpci_aspm = 0;
53
54 /* ASPM PS mode.
55 * 0 - Disable ASPM,
56 * 1 - Enable ASPM without Clock Req,
57 * 2 - Enable ASPM with Clock Req,
58 * 3 - Alwyas Enable ASPM with Clock Req,
59 * 4 - Always Enable ASPM without Clock Req.
60 * set defult to RTL8192CE:3 RTL8192E:2
61 */
62 rtlpci->const_pci_aspm = 3;
63
64 /*Setting for PCI-E device */
65 rtlpci->const_devicepci_aspm_setting = 0x03;
66
67 /*Setting for PCI-E bridge */
68 rtlpci->const_hostpci_aspm_setting = 0x02;
69
70 /* In Hw/Sw Radio Off situation.
71 * 0 - Default,
72 * 1 - From ASPM setting without low Mac Pwr,
73 * 2 - From ASPM setting with low Mac Pwr,
74 * 3 - Bus D3
75 * set default to RTL8192CE:0 RTL8192SE:2
76 */
77 rtlpci->const_hwsw_rfoff_d3 = 0;
78
79 /* This setting works for those device with
80 * backdoor ASPM setting such as EPHY setting.
81 * 0 - Not support ASPM,
82 * 1 - Support ASPM,
83 * 2 - According to chipset.
84 */
85 rtlpci->const_support_pciaspm = 1;
86}
87
88int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
89{
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
93 int err;
94
95 rtl8723ae_bt_reg_init(hw);
96 rtlpriv->dm.dm_initialgain_enable = 1;
97 rtlpriv->dm.dm_flag = 0;
98 rtlpriv->dm.disable_framebursting = 0;
99 rtlpriv->dm.thermalvalue = 0;
100 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
101
102 /* compatible 5G band 88ce just 2.4G band & smsp */
103 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
104 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
105 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
106
107 rtlpci->receive_config = (RCR_APPFCS |
108 RCR_APP_MIC |
109 RCR_APP_ICV |
110 RCR_APP_PHYST_RXFF |
111 RCR_HTC_LOC_CTRL |
112 RCR_AMF |
113 RCR_ACF |
114 RCR_ADF |
115 RCR_AICV |
116 RCR_AB |
117 RCR_AM |
118 RCR_APM |
119 0);
120
121 rtlpci->irq_mask[0] =
122 (u32) (PHIMR_ROK |
123 PHIMR_RDU |
124 PHIMR_VODOK |
125 PHIMR_VIDOK |
126 PHIMR_BEDOK |
127 PHIMR_BKDOK |
128 PHIMR_MGNTDOK |
129 PHIMR_HIGHDOK |
130 PHIMR_C2HCMD |
131 PHIMR_HISRE_IND |
132 PHIMR_TSF_BIT32_TOGGLE |
133 PHIMR_TXBCNOK |
134 PHIMR_PSTIMEOUT |
135 0);
136
137 rtlpci->irq_mask[1] = (u32)(PHIMR_RXFOVW | 0);
138
139 /* for debug level */
140 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
141 /* for LPS & IPS */
142 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
143 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
144 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
145 rtlpriv->psc.reg_fwctrl_lps = 3;
146 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
147 /* for ASPM, you can close aspm through
148 * set const_support_pciaspm = 0
149 */
150 rtl8723ae_init_aspm_vars(hw);
151
152 if (rtlpriv->psc.reg_fwctrl_lps == 1)
153 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
154 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
155 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
156 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
157 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
158
159 /* for firmware buf */
160 rtlpriv->rtlhal.pfirmware = vmalloc(0x6000);
161 if (!rtlpriv->rtlhal.pfirmware) {
162 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
163 "Can't alloc buffer for fw.\n");
164 return 1;
165 }
166
167 if (IS_VENDOR_8723_A_CUT(rtlhal->version))
168 rtlpriv->cfg->fw_name = "rtlwifi/rtl8723fw.bin";
169 else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
170 rtlpriv->cfg->fw_name = "rtlwifi/rtl8723fw_B.bin";
171
172 rtlpriv->max_fw_size = 0x6000;
173 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
174 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
175 rtlpriv->io.dev, GFP_KERNEL, hw,
176 rtl_fw_cb);
177 if (err) {
178 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
179 "Failed to request firmware!\n");
180 return 1;
181 }
182 return 0;
183}
184
185void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw)
186{
187 struct rtl_priv *rtlpriv = rtl_priv(hw);
188
189 if (rtlpriv->rtlhal.pfirmware) {
190 vfree(rtlpriv->rtlhal.pfirmware);
191 rtlpriv->rtlhal.pfirmware = NULL;
192 }
193}
194
195static struct rtl_hal_ops rtl8723ae_hal_ops = {
196 .init_sw_vars = rtl8723ae_init_sw_vars,
197 .deinit_sw_vars = rtl8723ae_deinit_sw_vars,
198 .read_eeprom_info = rtl8723ae_read_eeprom_info,
199 .interrupt_recognized = rtl8723ae_interrupt_recognized,
200 .hw_init = rtl8723ae_hw_init,
201 .hw_disable = rtl8723ae_card_disable,
202 .hw_suspend = rtl8723ae_suspend,
203 .hw_resume = rtl8723ae_resume,
204 .enable_interrupt = rtl8723ae_enable_interrupt,
205 .disable_interrupt = rtl8723ae_disable_interrupt,
206 .set_network_type = rtl8723ae_set_network_type,
207 .set_chk_bssid = rtl8723ae_set_check_bssid,
208 .set_qos = rtl8723ae_set_qos,
209 .set_bcn_reg = rtl8723ae_set_beacon_related_registers,
210 .set_bcn_intv = rtl8723ae_set_beacon_interval,
211 .update_interrupt_mask = rtl8723ae_update_interrupt_mask,
212 .get_hw_reg = rtl8723ae_get_hw_reg,
213 .set_hw_reg = rtl8723ae_set_hw_reg,
214 .update_rate_tbl = rtl8723ae_update_hal_rate_tbl,
215 .fill_tx_desc = rtl8723ae_tx_fill_desc,
216 .fill_tx_cmddesc = rtl8723ae_tx_fill_cmddesc,
217 .query_rx_desc = rtl8723ae_rx_query_desc,
218 .set_channel_access = rtl8723ae_update_channel_access_setting,
219 .radio_onoff_checking = rtl8723ae_gpio_radio_on_off_checking,
220 .set_bw_mode = rtl8723ae_phy_set_bw_mode,
221 .switch_channel = rtl8723ae_phy_sw_chnl,
222 .dm_watchdog = rtl8723ae_dm_watchdog,
223 .scan_operation_backup = rtl8723ae_phy_scan_operation_backup,
224 .set_rf_power_state = rtl8723ae_phy_set_rf_power_state,
225 .led_control = rtl8723ae_led_control,
226 .set_desc = rtl8723ae_set_desc,
227 .get_desc = rtl8723ae_get_desc,
228 .tx_polling = rtl8723ae_tx_polling,
229 .enable_hw_sec = rtl8723ae_enable_hw_security_config,
230 .set_key = rtl8723ae_set_key,
231 .init_sw_leds = rtl8723ae_init_sw_leds,
232 .allow_all_destaddr = rtl8723ae_allow_all_destaddr,
233 .get_bbreg = rtl8723ae_phy_query_bb_reg,
234 .set_bbreg = rtl8723ae_phy_set_bb_reg,
235 .get_rfreg = rtl8723ae_phy_query_rf_reg,
236 .set_rfreg = rtl8723ae_phy_set_rf_reg,
237 .c2h_command_handle = rtl_8723e_c2h_command_handle,
238 .bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify,
239 .bt_coex_off_before_lps = rtl8723ae_bt_coex_off_before_lps,
240};
241
242static struct rtl_mod_params rtl8723ae_mod_params = {
243 .sw_crypto = false,
244 .inactiveps = true,
245 .swctrl_lps = false,
246 .fwctrl_lps = true,
247 .debug = DBG_EMERG,
248};
249
250static struct rtl_hal_cfg rtl8723ae_hal_cfg = {
251 .bar_id = 2,
252 .write_readback = true,
253 .name = "rtl8723ae_pci",
254 .fw_name = "rtlwifi/rtl8723aefw.bin",
255 .ops = &rtl8723ae_hal_ops,
256 .mod_params = &rtl8723ae_mod_params,
257 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
258 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
259 .maps[SYS_CLK] = REG_SYS_CLKR,
260 .maps[MAC_RCR_AM] = AM,
261 .maps[MAC_RCR_AB] = AB,
262 .maps[MAC_RCR_ACRC32] = ACRC32,
263 .maps[MAC_RCR_ACF] = ACF,
264 .maps[MAC_RCR_AAP] = AAP,
265 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
266 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
267 .maps[EFUSE_CLK] = 0,
268 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
269 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
270 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
271 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
272 .maps[EFUSE_ANA8M] = ANA8M,
273 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
274 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
275 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
276 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
277
278 .maps[RWCAM] = REG_CAMCMD,
279 .maps[WCAMI] = REG_CAMWRITE,
280 .maps[RCAMO] = REG_CAMREAD,
281 .maps[CAMDBG] = REG_CAMDBG,
282 .maps[SECR] = REG_SECCFG,
283 .maps[SEC_CAM_NONE] = CAM_NONE,
284 .maps[SEC_CAM_WEP40] = CAM_WEP40,
285 .maps[SEC_CAM_TKIP] = CAM_TKIP,
286 .maps[SEC_CAM_AES] = CAM_AES,
287 .maps[SEC_CAM_WEP104] = CAM_WEP104,
288
289 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
290 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
291 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
292 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
293 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
294 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
295 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
296 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
297 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
298 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
299 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
300 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
301 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
302 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
303 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
304 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
305
306 .maps[RTL_IMR_TXFOVW] = PHIMR_TXFOVW,
307 .maps[RTL_IMR_PSTIMEOUT] = PHIMR_PSTIMEOUT,
308 .maps[RTL_IMR_BcnInt] = PHIMR_BCNDMAINT0,
309 .maps[RTL_IMR_RXFOVW] = PHIMR_RXFOVW,
310 .maps[RTL_IMR_RDU] = PHIMR_RDU,
311 .maps[RTL_IMR_ATIMEND] = PHIMR_ATIMEND_E,
312 .maps[RTL_IMR_BDOK] = PHIMR_BCNDOK0,
313 .maps[RTL_IMR_MGNTDOK] = PHIMR_MGNTDOK,
314 .maps[RTL_IMR_TBDER] = PHIMR_TXBCNERR,
315 .maps[RTL_IMR_HIGHDOK] = PHIMR_HIGHDOK,
316 .maps[RTL_IMR_TBDOK] = PHIMR_TXBCNOK,
317 .maps[RTL_IMR_BKDOK] = PHIMR_BKDOK,
318 .maps[RTL_IMR_BEDOK] = PHIMR_BEDOK,
319 .maps[RTL_IMR_VIDOK] = PHIMR_VIDOK,
320 .maps[RTL_IMR_VODOK] = PHIMR_VODOK,
321 .maps[RTL_IMR_ROK] = PHIMR_ROK,
322 .maps[RTL_IBSS_INT_MASKS] = (PHIMR_BCNDMAINT0 |
323 PHIMR_TXBCNOK | PHIMR_TXBCNERR),
324 .maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD,
325
326
327 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
328 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
329 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
330 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
331 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
332 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
333 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
334 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
335 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
336 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
337 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
338 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
339
340 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
341 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
342};
343
Greg KH03ce7582012-12-21 13:42:15 +0000344static struct pci_device_id rtl8723ae_pci_ids[] = {
Larry Fingerc592e632012-10-25 13:46:32 -0500345 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723ae_hal_cfg)},
346 {},
347};
348
349MODULE_DEVICE_TABLE(pci, rtl8723ae_pci_ids);
350
351MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
352MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
353MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
354MODULE_LICENSE("GPL");
355MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless");
356MODULE_FIRMWARE("rtlwifi/rtl8723aefw.bin");
357MODULE_FIRMWARE("rtlwifi/rtl8723aefw_B.bin");
358
359module_param_named(swenc, rtl8723ae_mod_params.sw_crypto, bool, 0444);
360module_param_named(debug, rtl8723ae_mod_params.debug, int, 0444);
361module_param_named(ips, rtl8723ae_mod_params.inactiveps, bool, 0444);
362module_param_named(swlps, rtl8723ae_mod_params.swctrl_lps, bool, 0444);
363module_param_named(fwlps, rtl8723ae_mod_params.fwctrl_lps, bool, 0444);
364MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
365MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
366MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
367MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
368MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
369
Hauke Mehrtens244a77e2012-11-29 23:27:17 +0100370static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
Larry Fingerc592e632012-10-25 13:46:32 -0500371
372static struct pci_driver rtl8723ae_driver = {
373 .name = KBUILD_MODNAME,
374 .id_table = rtl8723ae_pci_ids,
375 .probe = rtl_pci_probe,
376 .remove = rtl_pci_disconnect,
377 .driver.pm = &rtlwifi_pm_ops,
378};
379
380module_pci_driver(rtl8723ae_driver);