Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "i915_drv.h" |
| 29 | #include "intel_drv.h" |
| 30 | |
| 31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
| 32 | * them for both DP and FDI transports, allowing those ports to |
| 33 | * automatically adapt to HDMI connections as well |
| 34 | */ |
| 35 | static const u32 hsw_ddi_translations_dp[] = { |
| 36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ |
| 37 | 0x00D75FFF, 0x0005000A, |
| 38 | 0x00C30FFF, 0x00040006, |
| 39 | 0x80AAAFFF, 0x000B0000, |
| 40 | 0x00FFFFFF, 0x0005000A, |
| 41 | 0x00D75FFF, 0x000C0004, |
| 42 | 0x80C30FFF, 0x000B0000, |
| 43 | 0x00FFFFFF, 0x00040006, |
| 44 | 0x80D75FFF, 0x000B0000, |
| 45 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ |
| 46 | }; |
| 47 | |
| 48 | static const u32 hsw_ddi_translations_fdi[] = { |
| 49 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ |
| 50 | 0x00D75FFF, 0x000F000A, |
| 51 | 0x00C30FFF, 0x00060006, |
| 52 | 0x00AAAFFF, 0x001E0000, |
| 53 | 0x00FFFFFF, 0x000F000A, |
| 54 | 0x00D75FFF, 0x00160004, |
| 55 | 0x00C30FFF, 0x001E0000, |
| 56 | 0x00FFFFFF, 0x00060006, |
| 57 | 0x00D75FFF, 0x001E0000, |
| 58 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ |
| 59 | }; |
| 60 | |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 61 | static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
| 62 | { |
Paulo Zanoni | 0bdee30 | 2012-10-15 15:51:38 -0300 | [diff] [blame] | 63 | struct drm_encoder *encoder = &intel_encoder->base; |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 64 | int type = intel_encoder->type; |
| 65 | |
Paulo Zanoni | 0bdee30 | 2012-10-15 15:51:38 -0300 | [diff] [blame] | 66 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
| 67 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 68 | return intel_dp->port; |
| 69 | |
| 70 | } else if (type == INTEL_OUTPUT_HDMI) { |
| 71 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 72 | return intel_hdmi->ddi_port; |
Paulo Zanoni | 0bdee30 | 2012-10-15 15:51:38 -0300 | [diff] [blame] | 73 | |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 74 | } else if (type == INTEL_OUTPUT_ANALOG) { |
| 75 | return PORT_E; |
Paulo Zanoni | 0bdee30 | 2012-10-15 15:51:38 -0300 | [diff] [blame] | 76 | |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 77 | } else { |
| 78 | DRM_ERROR("Invalid DDI encoder type %d\n", type); |
| 79 | BUG(); |
| 80 | } |
| 81 | } |
| 82 | |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 83 | /* On Haswell, DDI port buffers must be programmed with correct values |
| 84 | * in advance. The buffer values are different for FDI and DP modes, |
| 85 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
| 86 | * in either FDI or DP modes only, as HDMI connections will work with both |
| 87 | * of those |
| 88 | */ |
| 89 | void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode) |
| 90 | { |
| 91 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 92 | u32 reg; |
| 93 | int i; |
| 94 | const u32 *ddi_translations = ((use_fdi_mode) ? |
| 95 | hsw_ddi_translations_fdi : |
| 96 | hsw_ddi_translations_dp); |
| 97 | |
| 98 | DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n", |
| 99 | port_name(port), |
| 100 | use_fdi_mode ? "FDI" : "DP"); |
| 101 | |
| 102 | WARN((use_fdi_mode && (port != PORT_E)), |
| 103 | "Programming port %c in FDI mode, this probably will not work.\n", |
| 104 | port_name(port)); |
| 105 | |
| 106 | for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { |
| 107 | I915_WRITE(reg, ddi_translations[i]); |
| 108 | reg += 4; |
| 109 | } |
| 110 | } |
| 111 | |
| 112 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP |
| 113 | * mode and port E for FDI. |
| 114 | */ |
| 115 | void intel_prepare_ddi(struct drm_device *dev) |
| 116 | { |
| 117 | int port; |
| 118 | |
| 119 | if (IS_HASWELL(dev)) { |
| 120 | for (port = PORT_A; port < PORT_E; port++) |
| 121 | intel_prepare_ddi_buffers(dev, port, false); |
| 122 | |
| 123 | /* DDI E is the suggested one to work in FDI mode, so program is as such by |
| 124 | * default. It will have to be re-programmed in case a digital DP output |
| 125 | * will be detected on it |
| 126 | */ |
| 127 | intel_prepare_ddi_buffers(dev, PORT_E, true); |
| 128 | } |
| 129 | } |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 130 | |
| 131 | static const long hsw_ddi_buf_ctl_values[] = { |
| 132 | DDI_BUF_EMP_400MV_0DB_HSW, |
| 133 | DDI_BUF_EMP_400MV_3_5DB_HSW, |
| 134 | DDI_BUF_EMP_400MV_6DB_HSW, |
| 135 | DDI_BUF_EMP_400MV_9_5DB_HSW, |
| 136 | DDI_BUF_EMP_600MV_0DB_HSW, |
| 137 | DDI_BUF_EMP_600MV_3_5DB_HSW, |
| 138 | DDI_BUF_EMP_600MV_6DB_HSW, |
| 139 | DDI_BUF_EMP_800MV_0DB_HSW, |
| 140 | DDI_BUF_EMP_800MV_3_5DB_HSW |
| 141 | }; |
| 142 | |
| 143 | |
| 144 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
| 145 | * connection to the PCH-located connectors. For this, it is necessary to train |
| 146 | * both the DDI port and PCH receiver for the desired DDI buffer settings. |
| 147 | * |
| 148 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, |
| 149 | * please note that when FDI mode is active on DDI E, it shares 2 lines with |
| 150 | * DDI A (which is used for eDP) |
| 151 | */ |
| 152 | |
| 153 | void hsw_fdi_link_train(struct drm_crtc *crtc) |
| 154 | { |
| 155 | struct drm_device *dev = crtc->dev; |
| 156 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 157 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 158 | int pipe = intel_crtc->pipe; |
| 159 | u32 reg, temp, i; |
| 160 | |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 161 | /* Start the training iterating through available voltages and emphasis */ |
| 162 | for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) { |
| 163 | /* Configure DP_TP_CTL with auto-training */ |
| 164 | I915_WRITE(DP_TP_CTL(PORT_E), |
| 165 | DP_TP_CTL_FDI_AUTOTRAIN | |
| 166 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
| 167 | DP_TP_CTL_LINK_TRAIN_PAT1 | |
| 168 | DP_TP_CTL_ENABLE); |
| 169 | |
| 170 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */ |
| 171 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
| 172 | temp = (temp & ~DDI_BUF_EMP_MASK); |
| 173 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
| 174 | temp | |
| 175 | DDI_BUF_CTL_ENABLE | |
| 176 | DDI_PORT_WIDTH_X2 | |
| 177 | hsw_ddi_buf_ctl_values[i]); |
| 178 | |
| 179 | udelay(600); |
| 180 | |
Eugeni Dodonov | 4acf518 | 2012-07-04 20:15:16 -0300 | [diff] [blame] | 181 | /* We need to program FDI_RX_MISC with the default TP1 to TP2 |
| 182 | * values before enabling the receiver, and configure the delay |
| 183 | * for the FDI timing generator to 90h. Luckily, all the other |
| 184 | * bits are supposed to be zeroed, so we can write those values |
| 185 | * directly. |
| 186 | */ |
| 187 | I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 | |
| 188 | FDI_RX_FDI_DELAY_90); |
| 189 | |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 190 | /* Enable CPU FDI Receiver with auto-training */ |
| 191 | reg = FDI_RX_CTL(pipe); |
| 192 | I915_WRITE(reg, |
| 193 | I915_READ(reg) | |
| 194 | FDI_LINK_TRAIN_AUTO | |
| 195 | FDI_RX_ENABLE | |
| 196 | FDI_LINK_TRAIN_PATTERN_1_CPT | |
| 197 | FDI_RX_ENHANCE_FRAME_ENABLE | |
| 198 | FDI_PORT_WIDTH_2X_LPT | |
| 199 | FDI_RX_PLL_ENABLE); |
| 200 | POSTING_READ(reg); |
| 201 | udelay(100); |
| 202 | |
| 203 | temp = I915_READ(DP_TP_STATUS(PORT_E)); |
| 204 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { |
| 205 | DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i); |
| 206 | |
| 207 | /* Enable normal pixel sending for FDI */ |
| 208 | I915_WRITE(DP_TP_CTL(PORT_E), |
| 209 | DP_TP_CTL_FDI_AUTOTRAIN | |
| 210 | DP_TP_CTL_LINK_TRAIN_NORMAL | |
| 211 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
| 212 | DP_TP_CTL_ENABLE); |
| 213 | |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 214 | break; |
| 215 | } else { |
| 216 | DRM_ERROR("Error training BUF_CTL %d\n", i); |
| 217 | |
| 218 | /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */ |
| 219 | I915_WRITE(DP_TP_CTL(PORT_E), |
| 220 | I915_READ(DP_TP_CTL(PORT_E)) & |
| 221 | ~DP_TP_CTL_ENABLE); |
| 222 | I915_WRITE(FDI_RX_CTL(pipe), |
| 223 | I915_READ(FDI_RX_CTL(pipe)) & |
| 224 | ~FDI_RX_PLL_ENABLE); |
| 225 | continue; |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 230 | } |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 231 | |
| 232 | /* For DDI connections, it is possible to support different outputs over the |
| 233 | * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by |
| 234 | * the time the output is detected what exactly is on the other end of it. This |
| 235 | * function aims at providing support for this detection and proper output |
| 236 | * configuration. |
| 237 | */ |
| 238 | void intel_ddi_init(struct drm_device *dev, enum port port) |
| 239 | { |
| 240 | /* For now, we don't do any proper output detection and assume that we |
| 241 | * handle HDMI only */ |
| 242 | |
| 243 | switch(port){ |
| 244 | case PORT_A: |
| 245 | /* We don't handle eDP and DP yet */ |
| 246 | DRM_DEBUG_DRIVER("Found digital output on DDI port A\n"); |
| 247 | break; |
| 248 | /* Assume that the ports B, C and D are working in HDMI mode for now */ |
| 249 | case PORT_B: |
| 250 | case PORT_C: |
| 251 | case PORT_D: |
Daniel Vetter | 08d644a | 2012-07-12 20:19:59 +0200 | [diff] [blame] | 252 | intel_hdmi_init(dev, DDI_BUF_CTL(port), port); |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 253 | break; |
| 254 | default: |
| 255 | DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n", |
| 256 | port); |
| 257 | break; |
| 258 | } |
| 259 | } |
Eugeni Dodonov | 12a13a3 | 2012-05-09 15:37:29 -0300 | [diff] [blame] | 260 | |
| 261 | /* WRPLL clock dividers */ |
| 262 | struct wrpll_tmds_clock { |
| 263 | u32 clock; |
| 264 | u16 p; /* Post divider */ |
| 265 | u16 n2; /* Feedback divider */ |
| 266 | u16 r2; /* Reference divider */ |
| 267 | }; |
| 268 | |
Paulo Zanoni | 126e9be | 2012-08-10 10:03:03 -0300 | [diff] [blame] | 269 | /* Table of matching values for WRPLL clocks programming for each frequency. |
| 270 | * The code assumes this table is sorted. */ |
Eugeni Dodonov | 12a13a3 | 2012-05-09 15:37:29 -0300 | [diff] [blame] | 271 | static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = { |
| 272 | {19750, 38, 25, 18}, |
| 273 | {20000, 48, 32, 18}, |
| 274 | {21000, 36, 21, 15}, |
| 275 | {21912, 42, 29, 17}, |
| 276 | {22000, 36, 22, 15}, |
| 277 | {23000, 36, 23, 15}, |
| 278 | {23500, 40, 40, 23}, |
| 279 | {23750, 26, 16, 14}, |
Eugeni Dodonov | 12a13a3 | 2012-05-09 15:37:29 -0300 | [diff] [blame] | 280 | {24000, 36, 24, 15}, |
| 281 | {25000, 36, 25, 15}, |
| 282 | {25175, 26, 40, 33}, |
| 283 | {25200, 30, 21, 15}, |
| 284 | {26000, 36, 26, 15}, |
| 285 | {27000, 30, 21, 14}, |
| 286 | {27027, 18, 100, 111}, |
| 287 | {27500, 30, 29, 19}, |
| 288 | {28000, 34, 30, 17}, |
| 289 | {28320, 26, 30, 22}, |
| 290 | {28322, 32, 42, 25}, |
| 291 | {28750, 24, 23, 18}, |
| 292 | {29000, 30, 29, 18}, |
| 293 | {29750, 32, 30, 17}, |
| 294 | {30000, 30, 25, 15}, |
| 295 | {30750, 30, 41, 24}, |
| 296 | {31000, 30, 31, 18}, |
| 297 | {31500, 30, 28, 16}, |
| 298 | {32000, 30, 32, 18}, |
| 299 | {32500, 28, 32, 19}, |
| 300 | {33000, 24, 22, 15}, |
| 301 | {34000, 28, 30, 17}, |
| 302 | {35000, 26, 32, 19}, |
| 303 | {35500, 24, 30, 19}, |
| 304 | {36000, 26, 26, 15}, |
| 305 | {36750, 26, 46, 26}, |
| 306 | {37000, 24, 23, 14}, |
| 307 | {37762, 22, 40, 26}, |
| 308 | {37800, 20, 21, 15}, |
| 309 | {38000, 24, 27, 16}, |
| 310 | {38250, 24, 34, 20}, |
| 311 | {39000, 24, 26, 15}, |
| 312 | {40000, 24, 32, 18}, |
| 313 | {40500, 20, 21, 14}, |
| 314 | {40541, 22, 147, 89}, |
| 315 | {40750, 18, 19, 14}, |
| 316 | {41000, 16, 17, 14}, |
| 317 | {41500, 22, 44, 26}, |
| 318 | {41540, 22, 44, 26}, |
| 319 | {42000, 18, 21, 15}, |
| 320 | {42500, 22, 45, 26}, |
| 321 | {43000, 20, 43, 27}, |
| 322 | {43163, 20, 24, 15}, |
| 323 | {44000, 18, 22, 15}, |
| 324 | {44900, 20, 108, 65}, |
| 325 | {45000, 20, 25, 15}, |
| 326 | {45250, 20, 52, 31}, |
| 327 | {46000, 18, 23, 15}, |
| 328 | {46750, 20, 45, 26}, |
| 329 | {47000, 20, 40, 23}, |
| 330 | {48000, 18, 24, 15}, |
| 331 | {49000, 18, 49, 30}, |
| 332 | {49500, 16, 22, 15}, |
| 333 | {50000, 18, 25, 15}, |
| 334 | {50500, 18, 32, 19}, |
| 335 | {51000, 18, 34, 20}, |
| 336 | {52000, 18, 26, 15}, |
| 337 | {52406, 14, 34, 25}, |
| 338 | {53000, 16, 22, 14}, |
| 339 | {54000, 16, 24, 15}, |
| 340 | {54054, 16, 173, 108}, |
| 341 | {54500, 14, 24, 17}, |
| 342 | {55000, 12, 22, 18}, |
| 343 | {56000, 14, 45, 31}, |
| 344 | {56250, 16, 25, 15}, |
| 345 | {56750, 14, 25, 17}, |
| 346 | {57000, 16, 27, 16}, |
| 347 | {58000, 16, 43, 25}, |
| 348 | {58250, 16, 38, 22}, |
| 349 | {58750, 16, 40, 23}, |
| 350 | {59000, 14, 26, 17}, |
| 351 | {59341, 14, 40, 26}, |
| 352 | {59400, 16, 44, 25}, |
| 353 | {60000, 16, 32, 18}, |
| 354 | {60500, 12, 39, 29}, |
| 355 | {61000, 14, 49, 31}, |
| 356 | {62000, 14, 37, 23}, |
| 357 | {62250, 14, 42, 26}, |
| 358 | {63000, 12, 21, 15}, |
| 359 | {63500, 14, 28, 17}, |
| 360 | {64000, 12, 27, 19}, |
| 361 | {65000, 14, 32, 19}, |
| 362 | {65250, 12, 29, 20}, |
| 363 | {65500, 12, 32, 22}, |
| 364 | {66000, 12, 22, 15}, |
| 365 | {66667, 14, 38, 22}, |
| 366 | {66750, 10, 21, 17}, |
| 367 | {67000, 14, 33, 19}, |
| 368 | {67750, 14, 58, 33}, |
| 369 | {68000, 14, 30, 17}, |
| 370 | {68179, 14, 46, 26}, |
| 371 | {68250, 14, 46, 26}, |
| 372 | {69000, 12, 23, 15}, |
| 373 | {70000, 12, 28, 18}, |
| 374 | {71000, 12, 30, 19}, |
| 375 | {72000, 12, 24, 15}, |
| 376 | {73000, 10, 23, 17}, |
| 377 | {74000, 12, 23, 14}, |
| 378 | {74176, 8, 100, 91}, |
| 379 | {74250, 10, 22, 16}, |
| 380 | {74481, 12, 43, 26}, |
| 381 | {74500, 10, 29, 21}, |
| 382 | {75000, 12, 25, 15}, |
| 383 | {75250, 10, 39, 28}, |
| 384 | {76000, 12, 27, 16}, |
| 385 | {77000, 12, 53, 31}, |
| 386 | {78000, 12, 26, 15}, |
| 387 | {78750, 12, 28, 16}, |
| 388 | {79000, 10, 38, 26}, |
| 389 | {79500, 10, 28, 19}, |
| 390 | {80000, 12, 32, 18}, |
| 391 | {81000, 10, 21, 14}, |
| 392 | {81081, 6, 100, 111}, |
| 393 | {81624, 8, 29, 24}, |
| 394 | {82000, 8, 17, 14}, |
| 395 | {83000, 10, 40, 26}, |
| 396 | {83950, 10, 28, 18}, |
| 397 | {84000, 10, 28, 18}, |
| 398 | {84750, 6, 16, 17}, |
| 399 | {85000, 6, 17, 18}, |
| 400 | {85250, 10, 30, 19}, |
| 401 | {85750, 10, 27, 17}, |
| 402 | {86000, 10, 43, 27}, |
| 403 | {87000, 10, 29, 18}, |
| 404 | {88000, 10, 44, 27}, |
| 405 | {88500, 10, 41, 25}, |
| 406 | {89000, 10, 28, 17}, |
| 407 | {89012, 6, 90, 91}, |
| 408 | {89100, 10, 33, 20}, |
| 409 | {90000, 10, 25, 15}, |
| 410 | {91000, 10, 32, 19}, |
| 411 | {92000, 10, 46, 27}, |
| 412 | {93000, 10, 31, 18}, |
| 413 | {94000, 10, 40, 23}, |
| 414 | {94500, 10, 28, 16}, |
| 415 | {95000, 10, 44, 25}, |
| 416 | {95654, 10, 39, 22}, |
| 417 | {95750, 10, 39, 22}, |
| 418 | {96000, 10, 32, 18}, |
| 419 | {97000, 8, 23, 16}, |
| 420 | {97750, 8, 42, 29}, |
| 421 | {98000, 8, 45, 31}, |
| 422 | {99000, 8, 22, 15}, |
| 423 | {99750, 8, 34, 23}, |
| 424 | {100000, 6, 20, 18}, |
| 425 | {100500, 6, 19, 17}, |
| 426 | {101000, 6, 37, 33}, |
| 427 | {101250, 8, 21, 14}, |
| 428 | {102000, 6, 17, 15}, |
| 429 | {102250, 6, 25, 22}, |
| 430 | {103000, 8, 29, 19}, |
| 431 | {104000, 8, 37, 24}, |
| 432 | {105000, 8, 28, 18}, |
| 433 | {106000, 8, 22, 14}, |
| 434 | {107000, 8, 46, 29}, |
| 435 | {107214, 8, 27, 17}, |
| 436 | {108000, 8, 24, 15}, |
| 437 | {108108, 8, 173, 108}, |
| 438 | {109000, 6, 23, 19}, |
Eugeni Dodonov | 12a13a3 | 2012-05-09 15:37:29 -0300 | [diff] [blame] | 439 | {110000, 6, 22, 18}, |
| 440 | {110013, 6, 22, 18}, |
| 441 | {110250, 8, 49, 30}, |
| 442 | {110500, 8, 36, 22}, |
| 443 | {111000, 8, 23, 14}, |
| 444 | {111264, 8, 150, 91}, |
| 445 | {111375, 8, 33, 20}, |
| 446 | {112000, 8, 63, 38}, |
| 447 | {112500, 8, 25, 15}, |
| 448 | {113100, 8, 57, 34}, |
| 449 | {113309, 8, 42, 25}, |
| 450 | {114000, 8, 27, 16}, |
| 451 | {115000, 6, 23, 18}, |
| 452 | {116000, 8, 43, 25}, |
| 453 | {117000, 8, 26, 15}, |
| 454 | {117500, 8, 40, 23}, |
| 455 | {118000, 6, 38, 29}, |
| 456 | {119000, 8, 30, 17}, |
| 457 | {119500, 8, 46, 26}, |
| 458 | {119651, 8, 39, 22}, |
| 459 | {120000, 8, 32, 18}, |
| 460 | {121000, 6, 39, 29}, |
| 461 | {121250, 6, 31, 23}, |
| 462 | {121750, 6, 23, 17}, |
| 463 | {122000, 6, 42, 31}, |
| 464 | {122614, 6, 30, 22}, |
| 465 | {123000, 6, 41, 30}, |
| 466 | {123379, 6, 37, 27}, |
| 467 | {124000, 6, 51, 37}, |
| 468 | {125000, 6, 25, 18}, |
| 469 | {125250, 4, 13, 14}, |
| 470 | {125750, 4, 27, 29}, |
| 471 | {126000, 6, 21, 15}, |
| 472 | {127000, 6, 24, 17}, |
| 473 | {127250, 6, 41, 29}, |
| 474 | {128000, 6, 27, 19}, |
| 475 | {129000, 6, 43, 30}, |
| 476 | {129859, 4, 25, 26}, |
| 477 | {130000, 6, 26, 18}, |
| 478 | {130250, 6, 42, 29}, |
| 479 | {131000, 6, 32, 22}, |
| 480 | {131500, 6, 38, 26}, |
| 481 | {131850, 6, 41, 28}, |
| 482 | {132000, 6, 22, 15}, |
| 483 | {132750, 6, 28, 19}, |
| 484 | {133000, 6, 34, 23}, |
| 485 | {133330, 6, 37, 25}, |
| 486 | {134000, 6, 61, 41}, |
| 487 | {135000, 6, 21, 14}, |
| 488 | {135250, 6, 167, 111}, |
| 489 | {136000, 6, 62, 41}, |
| 490 | {137000, 6, 35, 23}, |
| 491 | {138000, 6, 23, 15}, |
| 492 | {138500, 6, 40, 26}, |
| 493 | {138750, 6, 37, 24}, |
| 494 | {139000, 6, 34, 22}, |
| 495 | {139050, 6, 34, 22}, |
| 496 | {139054, 6, 34, 22}, |
| 497 | {140000, 6, 28, 18}, |
| 498 | {141000, 6, 36, 23}, |
| 499 | {141500, 6, 22, 14}, |
| 500 | {142000, 6, 30, 19}, |
| 501 | {143000, 6, 27, 17}, |
| 502 | {143472, 4, 17, 16}, |
| 503 | {144000, 6, 24, 15}, |
| 504 | {145000, 6, 29, 18}, |
| 505 | {146000, 6, 47, 29}, |
| 506 | {146250, 6, 26, 16}, |
| 507 | {147000, 6, 49, 30}, |
| 508 | {147891, 6, 23, 14}, |
| 509 | {148000, 6, 23, 14}, |
| 510 | {148250, 6, 28, 17}, |
| 511 | {148352, 4, 100, 91}, |
| 512 | {148500, 6, 33, 20}, |
| 513 | {149000, 6, 48, 29}, |
| 514 | {150000, 6, 25, 15}, |
| 515 | {151000, 4, 19, 17}, |
| 516 | {152000, 6, 27, 16}, |
| 517 | {152280, 6, 44, 26}, |
| 518 | {153000, 6, 34, 20}, |
| 519 | {154000, 6, 53, 31}, |
| 520 | {155000, 6, 31, 18}, |
| 521 | {155250, 6, 50, 29}, |
| 522 | {155750, 6, 45, 26}, |
| 523 | {156000, 6, 26, 15}, |
| 524 | {157000, 6, 61, 35}, |
| 525 | {157500, 6, 28, 16}, |
| 526 | {158000, 6, 65, 37}, |
| 527 | {158250, 6, 44, 25}, |
| 528 | {159000, 6, 53, 30}, |
| 529 | {159500, 6, 39, 22}, |
| 530 | {160000, 6, 32, 18}, |
| 531 | {161000, 4, 31, 26}, |
| 532 | {162000, 4, 18, 15}, |
| 533 | {162162, 4, 131, 109}, |
| 534 | {162500, 4, 53, 44}, |
| 535 | {163000, 4, 29, 24}, |
| 536 | {164000, 4, 17, 14}, |
| 537 | {165000, 4, 22, 18}, |
| 538 | {166000, 4, 32, 26}, |
| 539 | {167000, 4, 26, 21}, |
| 540 | {168000, 4, 46, 37}, |
| 541 | {169000, 4, 104, 83}, |
| 542 | {169128, 4, 64, 51}, |
| 543 | {169500, 4, 39, 31}, |
| 544 | {170000, 4, 34, 27}, |
| 545 | {171000, 4, 19, 15}, |
| 546 | {172000, 4, 51, 40}, |
| 547 | {172750, 4, 32, 25}, |
| 548 | {172800, 4, 32, 25}, |
| 549 | {173000, 4, 41, 32}, |
| 550 | {174000, 4, 49, 38}, |
| 551 | {174787, 4, 22, 17}, |
| 552 | {175000, 4, 35, 27}, |
| 553 | {176000, 4, 30, 23}, |
| 554 | {177000, 4, 38, 29}, |
| 555 | {178000, 4, 29, 22}, |
| 556 | {178500, 4, 37, 28}, |
| 557 | {179000, 4, 53, 40}, |
| 558 | {179500, 4, 73, 55}, |
| 559 | {180000, 4, 20, 15}, |
| 560 | {181000, 4, 55, 41}, |
| 561 | {182000, 4, 31, 23}, |
| 562 | {183000, 4, 42, 31}, |
| 563 | {184000, 4, 30, 22}, |
| 564 | {184750, 4, 26, 19}, |
| 565 | {185000, 4, 37, 27}, |
| 566 | {186000, 4, 51, 37}, |
| 567 | {187000, 4, 36, 26}, |
| 568 | {188000, 4, 32, 23}, |
| 569 | {189000, 4, 21, 15}, |
| 570 | {190000, 4, 38, 27}, |
| 571 | {190960, 4, 41, 29}, |
| 572 | {191000, 4, 41, 29}, |
| 573 | {192000, 4, 27, 19}, |
| 574 | {192250, 4, 37, 26}, |
| 575 | {193000, 4, 20, 14}, |
| 576 | {193250, 4, 53, 37}, |
| 577 | {194000, 4, 23, 16}, |
| 578 | {194208, 4, 23, 16}, |
| 579 | {195000, 4, 26, 18}, |
| 580 | {196000, 4, 45, 31}, |
| 581 | {197000, 4, 35, 24}, |
| 582 | {197750, 4, 41, 28}, |
| 583 | {198000, 4, 22, 15}, |
| 584 | {198500, 4, 25, 17}, |
| 585 | {199000, 4, 28, 19}, |
| 586 | {200000, 4, 37, 25}, |
| 587 | {201000, 4, 61, 41}, |
| 588 | {202000, 4, 112, 75}, |
| 589 | {202500, 4, 21, 14}, |
| 590 | {203000, 4, 146, 97}, |
| 591 | {204000, 4, 62, 41}, |
| 592 | {204750, 4, 44, 29}, |
| 593 | {205000, 4, 38, 25}, |
| 594 | {206000, 4, 29, 19}, |
| 595 | {207000, 4, 23, 15}, |
| 596 | {207500, 4, 40, 26}, |
| 597 | {208000, 4, 37, 24}, |
| 598 | {208900, 4, 48, 31}, |
| 599 | {209000, 4, 48, 31}, |
| 600 | {209250, 4, 31, 20}, |
| 601 | {210000, 4, 28, 18}, |
| 602 | {211000, 4, 25, 16}, |
| 603 | {212000, 4, 22, 14}, |
| 604 | {213000, 4, 30, 19}, |
| 605 | {213750, 4, 38, 24}, |
| 606 | {214000, 4, 46, 29}, |
| 607 | {214750, 4, 35, 22}, |
| 608 | {215000, 4, 43, 27}, |
| 609 | {216000, 4, 24, 15}, |
| 610 | {217000, 4, 37, 23}, |
| 611 | {218000, 4, 42, 26}, |
| 612 | {218250, 4, 42, 26}, |
| 613 | {218750, 4, 34, 21}, |
| 614 | {219000, 4, 47, 29}, |
Eugeni Dodonov | 12a13a3 | 2012-05-09 15:37:29 -0300 | [diff] [blame] | 615 | {220000, 4, 44, 27}, |
| 616 | {220640, 4, 49, 30}, |
| 617 | {220750, 4, 36, 22}, |
| 618 | {221000, 4, 36, 22}, |
| 619 | {222000, 4, 23, 14}, |
| 620 | {222525, 4, 28, 17}, |
| 621 | {222750, 4, 33, 20}, |
| 622 | {227000, 4, 37, 22}, |
| 623 | {230250, 4, 29, 17}, |
| 624 | {233500, 4, 38, 22}, |
| 625 | {235000, 4, 40, 23}, |
| 626 | {238000, 4, 30, 17}, |
| 627 | {241500, 2, 17, 19}, |
| 628 | {245250, 2, 20, 22}, |
| 629 | {247750, 2, 22, 24}, |
| 630 | {253250, 2, 15, 16}, |
| 631 | {256250, 2, 18, 19}, |
| 632 | {262500, 2, 31, 32}, |
| 633 | {267250, 2, 66, 67}, |
| 634 | {268500, 2, 94, 95}, |
| 635 | {270000, 2, 14, 14}, |
| 636 | {272500, 2, 77, 76}, |
| 637 | {273750, 2, 57, 56}, |
| 638 | {280750, 2, 24, 23}, |
| 639 | {281250, 2, 23, 22}, |
| 640 | {286000, 2, 17, 16}, |
| 641 | {291750, 2, 26, 24}, |
| 642 | {296703, 2, 56, 51}, |
| 643 | {297000, 2, 22, 20}, |
| 644 | {298000, 2, 21, 19}, |
| 645 | }; |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 646 | |
| 647 | void intel_ddi_mode_set(struct drm_encoder *encoder, |
| 648 | struct drm_display_mode *mode, |
| 649 | struct drm_display_mode *adjusted_mode) |
| 650 | { |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 651 | struct drm_crtc *crtc = encoder->crtc; |
| 652 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 653 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 654 | int port = intel_ddi_get_encoder_port(intel_encoder); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 655 | int pipe = intel_crtc->pipe; |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 656 | int type = intel_encoder->type; |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 657 | |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 658 | DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n", |
| 659 | port_name(port), pipe_name(pipe)); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 660 | |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 661 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
| 662 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Wang Xingchao | 4f07854 | 2012-08-09 16:52:16 +0800 | [diff] [blame] | 663 | |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 664 | intel_dp->DP = DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; |
| 665 | switch (intel_dp->lane_count) { |
| 666 | case 1: |
| 667 | intel_dp->DP |= DDI_PORT_WIDTH_X1; |
| 668 | break; |
| 669 | case 2: |
| 670 | intel_dp->DP |= DDI_PORT_WIDTH_X2; |
| 671 | break; |
| 672 | case 4: |
| 673 | intel_dp->DP |= DDI_PORT_WIDTH_X4; |
| 674 | break; |
| 675 | default: |
| 676 | intel_dp->DP |= DDI_PORT_WIDTH_X4; |
| 677 | WARN(1, "Unexpected DP lane count %d\n", |
| 678 | intel_dp->lane_count); |
| 679 | break; |
| 680 | } |
| 681 | |
| 682 | intel_dp_init_link_config(intel_dp); |
| 683 | |
| 684 | } else if (type == INTEL_OUTPUT_HDMI) { |
| 685 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 686 | |
| 687 | if (intel_hdmi->has_audio) { |
| 688 | /* Proper support for digital audio needs a new logic |
| 689 | * and a new set of registers, so we leave it for future |
| 690 | * patch bombing. |
| 691 | */ |
| 692 | DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", |
| 693 | pipe_name(intel_crtc->pipe)); |
| 694 | |
| 695 | /* write eld */ |
| 696 | DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); |
| 697 | intel_write_eld(encoder, adjusted_mode); |
| 698 | } |
| 699 | |
| 700 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 701 | } |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 702 | } |
| 703 | |
| 704 | static struct intel_encoder * |
| 705 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) |
| 706 | { |
| 707 | struct drm_device *dev = crtc->dev; |
| 708 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 709 | struct intel_encoder *intel_encoder, *ret = NULL; |
| 710 | int num_encoders = 0; |
| 711 | |
| 712 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 713 | ret = intel_encoder; |
| 714 | num_encoders++; |
| 715 | } |
| 716 | |
| 717 | if (num_encoders != 1) |
| 718 | WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders, |
| 719 | intel_crtc->pipe); |
| 720 | |
| 721 | BUG_ON(ret == NULL); |
| 722 | return ret; |
| 723 | } |
| 724 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 725 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
| 726 | { |
| 727 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 728 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
| 729 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 730 | uint32_t val; |
| 731 | |
| 732 | switch (intel_crtc->ddi_pll_sel) { |
| 733 | case PORT_CLK_SEL_SPLL: |
| 734 | plls->spll_refcount--; |
| 735 | if (plls->spll_refcount == 0) { |
| 736 | DRM_DEBUG_KMS("Disabling SPLL\n"); |
| 737 | val = I915_READ(SPLL_CTL); |
| 738 | WARN_ON(!(val & SPLL_PLL_ENABLE)); |
| 739 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
| 740 | POSTING_READ(SPLL_CTL); |
| 741 | } |
| 742 | break; |
| 743 | case PORT_CLK_SEL_WRPLL1: |
| 744 | plls->wrpll1_refcount--; |
| 745 | if (plls->wrpll1_refcount == 0) { |
| 746 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); |
| 747 | val = I915_READ(WRPLL_CTL1); |
| 748 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); |
| 749 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); |
| 750 | POSTING_READ(WRPLL_CTL1); |
| 751 | } |
| 752 | break; |
| 753 | case PORT_CLK_SEL_WRPLL2: |
| 754 | plls->wrpll2_refcount--; |
| 755 | if (plls->wrpll2_refcount == 0) { |
| 756 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); |
| 757 | val = I915_READ(WRPLL_CTL2); |
| 758 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); |
| 759 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); |
| 760 | POSTING_READ(WRPLL_CTL2); |
| 761 | } |
| 762 | break; |
| 763 | } |
| 764 | |
| 765 | WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); |
| 766 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); |
| 767 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); |
| 768 | |
| 769 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; |
| 770 | } |
| 771 | |
| 772 | static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2) |
| 773 | { |
| 774 | u32 i; |
| 775 | |
| 776 | for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++) |
| 777 | if (clock <= wrpll_tmds_clock_table[i].clock) |
| 778 | break; |
| 779 | |
| 780 | if (i == ARRAY_SIZE(wrpll_tmds_clock_table)) |
| 781 | i--; |
| 782 | |
| 783 | *p = wrpll_tmds_clock_table[i].p; |
| 784 | *n2 = wrpll_tmds_clock_table[i].n2; |
| 785 | *r2 = wrpll_tmds_clock_table[i].r2; |
| 786 | |
| 787 | if (wrpll_tmds_clock_table[i].clock != clock) |
| 788 | DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n", |
| 789 | wrpll_tmds_clock_table[i].clock, clock); |
| 790 | |
| 791 | DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n", |
| 792 | clock, *p, *n2, *r2); |
| 793 | } |
| 794 | |
| 795 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock) |
| 796 | { |
| 797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 798 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
Paulo Zanoni | 068759b | 2012-10-15 15:51:31 -0300 | [diff] [blame] | 799 | struct drm_encoder *encoder = &intel_encoder->base; |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 800 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 801 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
| 802 | int type = intel_encoder->type; |
| 803 | enum pipe pipe = intel_crtc->pipe; |
| 804 | uint32_t reg, val; |
| 805 | |
| 806 | /* TODO: reuse PLLs when possible (compare values) */ |
| 807 | |
| 808 | intel_ddi_put_crtc_pll(crtc); |
| 809 | |
Paulo Zanoni | 068759b | 2012-10-15 15:51:31 -0300 | [diff] [blame] | 810 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
| 811 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 812 | |
| 813 | switch (intel_dp->link_bw) { |
| 814 | case DP_LINK_BW_1_62: |
| 815 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
| 816 | break; |
| 817 | case DP_LINK_BW_2_7: |
| 818 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
| 819 | break; |
| 820 | case DP_LINK_BW_5_4: |
| 821 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
| 822 | break; |
| 823 | default: |
| 824 | DRM_ERROR("Link bandwidth %d unsupported\n", |
| 825 | intel_dp->link_bw); |
| 826 | return false; |
| 827 | } |
| 828 | |
| 829 | /* We don't need to turn any PLL on because we'll use LCPLL. */ |
| 830 | return true; |
| 831 | |
| 832 | } else if (type == INTEL_OUTPUT_HDMI) { |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 833 | int p, n2, r2; |
| 834 | |
| 835 | if (plls->wrpll1_refcount == 0) { |
| 836 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", |
| 837 | pipe_name(pipe)); |
| 838 | plls->wrpll1_refcount++; |
| 839 | reg = WRPLL_CTL1; |
| 840 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; |
| 841 | } else if (plls->wrpll2_refcount == 0) { |
| 842 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", |
| 843 | pipe_name(pipe)); |
| 844 | plls->wrpll2_refcount++; |
| 845 | reg = WRPLL_CTL2; |
| 846 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; |
| 847 | } else { |
| 848 | DRM_ERROR("No WRPLLs available!\n"); |
| 849 | return false; |
| 850 | } |
| 851 | |
| 852 | WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, |
| 853 | "WRPLL already enabled\n"); |
| 854 | |
| 855 | intel_ddi_calculate_wrpll(clock, &p, &n2, &r2); |
| 856 | |
| 857 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | |
| 858 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
| 859 | WRPLL_DIVIDER_POST(p); |
| 860 | |
| 861 | } else if (type == INTEL_OUTPUT_ANALOG) { |
| 862 | if (plls->spll_refcount == 0) { |
| 863 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", |
| 864 | pipe_name(pipe)); |
| 865 | plls->spll_refcount++; |
| 866 | reg = SPLL_CTL; |
| 867 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
| 868 | } |
| 869 | |
| 870 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, |
| 871 | "SPLL already enabled\n"); |
| 872 | |
Damien Lespiau | 39bc66c | 2012-10-11 15:24:04 +0100 | [diff] [blame] | 873 | val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 874 | |
| 875 | } else { |
| 876 | WARN(1, "Invalid DDI encoder type %d\n", type); |
| 877 | return false; |
| 878 | } |
| 879 | |
| 880 | I915_WRITE(reg, val); |
| 881 | udelay(20); |
| 882 | |
| 883 | return true; |
| 884 | } |
| 885 | |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 886 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
| 887 | { |
| 888 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 890 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 891 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 892 | int type = intel_encoder->type; |
| 893 | uint32_t temp; |
| 894 | |
| 895 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
| 896 | |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 897 | temp = TRANS_MSA_SYNC_CLK; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 898 | switch (intel_crtc->bpp) { |
| 899 | case 18: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 900 | temp |= TRANS_MSA_6_BPC; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 901 | break; |
| 902 | case 24: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 903 | temp |= TRANS_MSA_8_BPC; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 904 | break; |
| 905 | case 30: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 906 | temp |= TRANS_MSA_10_BPC; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 907 | break; |
| 908 | case 36: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 909 | temp |= TRANS_MSA_12_BPC; |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 910 | break; |
| 911 | default: |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 912 | temp |= TRANS_MSA_8_BPC; |
| 913 | WARN(1, "%d bpp unsupported by DDI function\n", |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 914 | intel_crtc->bpp); |
| 915 | } |
Paulo Zanoni | c980979 | 2012-10-23 18:30:00 -0200 | [diff] [blame] | 916 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
Paulo Zanoni | dae8479 | 2012-10-15 15:51:30 -0300 | [diff] [blame] | 917 | } |
| 918 | } |
| 919 | |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 920 | void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) |
| 921 | { |
| 922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 923 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 924 | struct drm_encoder *encoder = &intel_encoder->base; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 925 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 926 | enum pipe pipe = intel_crtc->pipe; |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 927 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 928 | int type = intel_encoder->type; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 929 | uint32_t temp; |
| 930 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 931 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
| 932 | temp = TRANS_DDI_FUNC_ENABLE; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 933 | |
| 934 | switch (intel_crtc->bpp) { |
| 935 | case 18: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 936 | temp |= TRANS_DDI_BPC_6; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 937 | break; |
| 938 | case 24: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 939 | temp |= TRANS_DDI_BPC_8; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 940 | break; |
| 941 | case 30: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 942 | temp |= TRANS_DDI_BPC_10; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 943 | break; |
| 944 | case 36: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 945 | temp |= TRANS_DDI_BPC_12; |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 946 | break; |
| 947 | default: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 948 | WARN(1, "%d bpp unsupported by transcoder DDI function\n", |
Paulo Zanoni | dfcef25 | 2012-08-08 14:15:29 -0300 | [diff] [blame] | 949 | intel_crtc->bpp); |
| 950 | } |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 951 | |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 952 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 953 | temp |= TRANS_DDI_PVSYNC; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 954 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 955 | temp |= TRANS_DDI_PHSYNC; |
Paulo Zanoni | f63eb7c | 2012-08-08 14:15:28 -0300 | [diff] [blame] | 956 | |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 957 | if (type == INTEL_OUTPUT_HDMI) { |
| 958 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 959 | |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 960 | if (intel_hdmi->has_hdmi_sink) |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 961 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 962 | else |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 963 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 964 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 965 | temp |= TRANS_DDI_SELECT_PORT(intel_hdmi->ddi_port); |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 966 | |
| 967 | } else if (type == INTEL_OUTPUT_ANALOG) { |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 968 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
| 969 | temp |= TRANS_DDI_SELECT_PORT(PORT_E); |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 970 | |
| 971 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || |
| 972 | type == INTEL_OUTPUT_EDP) { |
| 973 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 974 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 975 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
| 976 | temp |= TRANS_DDI_SELECT_PORT(intel_dp->port); |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 977 | |
| 978 | switch (intel_dp->lane_count) { |
| 979 | case 1: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 980 | temp |= TRANS_DDI_PORT_WIDTH_X1; |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 981 | break; |
| 982 | case 2: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 983 | temp |= TRANS_DDI_PORT_WIDTH_X2; |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 984 | break; |
| 985 | case 4: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 986 | temp |= TRANS_DDI_PORT_WIDTH_X4; |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 987 | break; |
| 988 | default: |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 989 | temp |= TRANS_DDI_PORT_WIDTH_X4; |
Paulo Zanoni | 7739c33 | 2012-10-15 15:51:29 -0300 | [diff] [blame] | 990 | WARN(1, "Unsupported lane count %d\n", |
| 991 | intel_dp->lane_count); |
| 992 | } |
| 993 | |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 994 | } else { |
| 995 | WARN(1, "Invalid encoder type %d for pipe %d\n", |
| 996 | intel_encoder->type, pipe); |
| 997 | } |
| 998 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 999 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1000 | } |
| 1001 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1002 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| 1003 | enum transcoder cpu_transcoder) |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1004 | { |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1005 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1006 | uint32_t val = I915_READ(reg); |
| 1007 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1008 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
| 1009 | val |= TRANS_DDI_PORT_NONE; |
Paulo Zanoni | 8d9ddbc | 2012-10-05 12:05:53 -0300 | [diff] [blame] | 1010 | I915_WRITE(reg, val); |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 1011 | } |
| 1012 | |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1013 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
| 1014 | enum pipe *pipe) |
| 1015 | { |
| 1016 | struct drm_device *dev = encoder->base.dev; |
| 1017 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | fe43d3f | 2012-10-15 15:51:39 -0300 | [diff] [blame] | 1018 | enum port port = intel_ddi_get_encoder_port(encoder); |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1019 | u32 tmp; |
| 1020 | int i; |
| 1021 | |
Paulo Zanoni | fe43d3f | 2012-10-15 15:51:39 -0300 | [diff] [blame] | 1022 | tmp = I915_READ(DDI_BUF_CTL(port)); |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1023 | |
| 1024 | if (!(tmp & DDI_BUF_CTL_ENABLE)) |
| 1025 | return false; |
| 1026 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1027 | if (port == PORT_A) { |
| 1028 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1029 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1030 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
| 1031 | case TRANS_DDI_EDP_INPUT_A_ON: |
| 1032 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
| 1033 | *pipe = PIPE_A; |
| 1034 | break; |
| 1035 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
| 1036 | *pipe = PIPE_B; |
| 1037 | break; |
| 1038 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
| 1039 | *pipe = PIPE_C; |
| 1040 | break; |
| 1041 | } |
| 1042 | |
| 1043 | return true; |
| 1044 | } else { |
| 1045 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
| 1046 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); |
| 1047 | |
| 1048 | if ((tmp & TRANS_DDI_PORT_MASK) |
| 1049 | == TRANS_DDI_SELECT_PORT(port)) { |
| 1050 | *pipe = i; |
| 1051 | return true; |
| 1052 | } |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1053 | } |
| 1054 | } |
| 1055 | |
Paulo Zanoni | fe43d3f | 2012-10-15 15:51:39 -0300 | [diff] [blame] | 1056 | DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1057 | |
| 1058 | return true; |
| 1059 | } |
| 1060 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1061 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
| 1062 | enum pipe pipe) |
| 1063 | { |
| 1064 | uint32_t temp, ret; |
| 1065 | enum port port; |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1066 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1067 | pipe); |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1068 | int i; |
| 1069 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 1070 | if (cpu_transcoder == TRANSCODER_EDP) { |
| 1071 | port = PORT_A; |
| 1072 | } else { |
| 1073 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
| 1074 | temp &= TRANS_DDI_PORT_MASK; |
| 1075 | |
| 1076 | for (i = PORT_B; i <= PORT_E; i++) |
| 1077 | if (temp == TRANS_DDI_SELECT_PORT(i)) |
| 1078 | port = i; |
| 1079 | } |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1080 | |
| 1081 | ret = I915_READ(PORT_CLK_SEL(port)); |
| 1082 | |
| 1083 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n", |
| 1084 | pipe_name(pipe), port_name(port), ret); |
| 1085 | |
| 1086 | return ret; |
| 1087 | } |
| 1088 | |
| 1089 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) |
| 1090 | { |
| 1091 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1092 | enum pipe pipe; |
| 1093 | struct intel_crtc *intel_crtc; |
| 1094 | |
| 1095 | for_each_pipe(pipe) { |
| 1096 | intel_crtc = |
| 1097 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 1098 | |
| 1099 | if (!intel_crtc->active) |
| 1100 | continue; |
| 1101 | |
| 1102 | intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, |
| 1103 | pipe); |
| 1104 | |
| 1105 | switch (intel_crtc->ddi_pll_sel) { |
| 1106 | case PORT_CLK_SEL_SPLL: |
| 1107 | dev_priv->ddi_plls.spll_refcount++; |
| 1108 | break; |
| 1109 | case PORT_CLK_SEL_WRPLL1: |
| 1110 | dev_priv->ddi_plls.wrpll1_refcount++; |
| 1111 | break; |
| 1112 | case PORT_CLK_SEL_WRPLL2: |
| 1113 | dev_priv->ddi_plls.wrpll2_refcount++; |
| 1114 | break; |
| 1115 | } |
| 1116 | } |
| 1117 | } |
| 1118 | |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1119 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
| 1120 | { |
| 1121 | struct drm_crtc *crtc = &intel_crtc->base; |
| 1122 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 1123 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
| 1124 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
Paulo Zanoni | bb523fc | 2012-10-23 18:29:56 -0200 | [diff] [blame] | 1125 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1126 | |
Paulo Zanoni | bb523fc | 2012-10-23 18:29:56 -0200 | [diff] [blame] | 1127 | if (cpu_transcoder != TRANSCODER_EDP) |
| 1128 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
| 1129 | TRANS_CLK_SEL_PORT(port)); |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1130 | } |
| 1131 | |
| 1132 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) |
| 1133 | { |
| 1134 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
Paulo Zanoni | bb523fc | 2012-10-23 18:29:56 -0200 | [diff] [blame] | 1135 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1136 | |
Paulo Zanoni | bb523fc | 2012-10-23 18:29:56 -0200 | [diff] [blame] | 1137 | if (cpu_transcoder != TRANSCODER_EDP) |
| 1138 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
| 1139 | TRANS_CLK_SEL_DISABLED); |
Paulo Zanoni | fc91463 | 2012-10-05 12:05:54 -0300 | [diff] [blame] | 1140 | } |
| 1141 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1142 | void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
| 1143 | { |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1144 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1145 | struct drm_crtc *crtc = encoder->crtc; |
| 1146 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1148 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 1149 | |
| 1150 | WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); |
| 1151 | |
| 1152 | I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1153 | |
| 1154 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { |
| 1155 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1156 | |
| 1157 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 1158 | intel_dp_start_link_train(intel_dp); |
| 1159 | intel_dp_complete_link_train(intel_dp); |
| 1160 | } |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1161 | } |
| 1162 | |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 1163 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
| 1164 | enum port port) |
| 1165 | { |
| 1166 | uint32_t reg = DDI_BUF_CTL(port); |
| 1167 | int i; |
| 1168 | |
| 1169 | for (i = 0; i < 8; i++) { |
| 1170 | udelay(1); |
| 1171 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) |
| 1172 | return; |
| 1173 | } |
| 1174 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); |
| 1175 | } |
| 1176 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1177 | void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
| 1178 | { |
| 1179 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1180 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 1181 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 1182 | uint32_t val; |
Paulo Zanoni | a836bdf | 2012-10-15 15:51:32 -0300 | [diff] [blame] | 1183 | bool wait = false; |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 1184 | |
| 1185 | val = I915_READ(DDI_BUF_CTL(port)); |
| 1186 | if (val & DDI_BUF_CTL_ENABLE) { |
| 1187 | val &= ~DDI_BUF_CTL_ENABLE; |
| 1188 | I915_WRITE(DDI_BUF_CTL(port), val); |
Paulo Zanoni | a836bdf | 2012-10-15 15:51:32 -0300 | [diff] [blame] | 1189 | wait = true; |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 1190 | } |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1191 | |
Paulo Zanoni | a836bdf | 2012-10-15 15:51:32 -0300 | [diff] [blame] | 1192 | val = I915_READ(DP_TP_CTL(port)); |
| 1193 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
| 1194 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 1195 | I915_WRITE(DP_TP_CTL(port), val); |
| 1196 | |
| 1197 | if (wait) |
| 1198 | intel_wait_ddi_buf_idle(dev_priv, port); |
| 1199 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1200 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
| 1201 | } |
| 1202 | |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 1203 | void intel_enable_ddi(struct intel_encoder *intel_encoder) |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 1204 | { |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 1205 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1206 | struct drm_device *dev = encoder->dev; |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 1207 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 1208 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 1209 | int type = intel_encoder->type; |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 1210 | |
Paulo Zanoni | 6547fef | 2012-10-15 15:51:40 -0300 | [diff] [blame] | 1211 | if (type == INTEL_OUTPUT_HDMI) { |
| 1212 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
| 1213 | * are ignored so nothing special needs to be done besides |
| 1214 | * enabling the port. |
| 1215 | */ |
| 1216 | I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE); |
| 1217 | } |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 1218 | } |
| 1219 | |
| 1220 | void intel_disable_ddi(struct intel_encoder *encoder) |
| 1221 | { |
Paulo Zanoni | 2886e93 | 2012-10-05 12:06:00 -0300 | [diff] [blame] | 1222 | /* This will be needed in the future, so leave it here for now */ |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 1223 | } |
Paulo Zanoni | 79f689a | 2012-10-05 12:05:52 -0300 | [diff] [blame] | 1224 | |
| 1225 | static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
| 1226 | { |
| 1227 | if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 1228 | return 450; |
| 1229 | else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) == |
| 1230 | LCPLL_CLK_FREQ_450) |
| 1231 | return 450; |
| 1232 | else |
| 1233 | return 540; |
| 1234 | } |
| 1235 | |
| 1236 | void intel_ddi_pll_init(struct drm_device *dev) |
| 1237 | { |
| 1238 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1239 | uint32_t val = I915_READ(LCPLL_CTL); |
| 1240 | |
| 1241 | /* The LCPLL register should be turned on by the BIOS. For now let's |
| 1242 | * just check its state and print errors in case something is wrong. |
| 1243 | * Don't even try to turn it on. |
| 1244 | */ |
| 1245 | |
| 1246 | DRM_DEBUG_KMS("CDCLK running at %dMHz\n", |
| 1247 | intel_ddi_get_cdclk_freq(dev_priv)); |
| 1248 | |
| 1249 | if (val & LCPLL_CD_SOURCE_FCLK) |
| 1250 | DRM_ERROR("CDCLK source is not LCPLL\n"); |
| 1251 | |
| 1252 | if (val & LCPLL_PLL_DISABLE) |
| 1253 | DRM_ERROR("LCPLL is disabled\n"); |
| 1254 | } |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1255 | |
| 1256 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) |
| 1257 | { |
| 1258 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1259 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 1260 | enum port port = intel_dp->port; |
| 1261 | bool wait; |
| 1262 | uint32_t val; |
| 1263 | |
| 1264 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { |
| 1265 | val = I915_READ(DDI_BUF_CTL(port)); |
| 1266 | if (val & DDI_BUF_CTL_ENABLE) { |
| 1267 | val &= ~DDI_BUF_CTL_ENABLE; |
| 1268 | I915_WRITE(DDI_BUF_CTL(port), val); |
| 1269 | wait = true; |
| 1270 | } |
| 1271 | |
| 1272 | val = I915_READ(DP_TP_CTL(port)); |
| 1273 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
| 1274 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 1275 | I915_WRITE(DP_TP_CTL(port), val); |
| 1276 | POSTING_READ(DP_TP_CTL(port)); |
| 1277 | |
| 1278 | if (wait) |
| 1279 | intel_wait_ddi_buf_idle(dev_priv, port); |
| 1280 | } |
| 1281 | |
| 1282 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | |
| 1283 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
| 1284 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
| 1285 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
| 1286 | I915_WRITE(DP_TP_CTL(port), val); |
| 1287 | POSTING_READ(DP_TP_CTL(port)); |
| 1288 | |
| 1289 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; |
| 1290 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); |
| 1291 | POSTING_READ(DDI_BUF_CTL(port)); |
| 1292 | |
| 1293 | udelay(600); |
| 1294 | } |