blob: ea04b21928222a711a862f1aa6e3e1989c17cd40 [file] [log] [blame]
Matt Porterc2dde5f2012-08-22 21:09:34 -04001/*
2 * TI EDMA DMA engine driver
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26
Matt Porter3ad7a422013-03-06 11:15:31 -050027#include <linux/platform_data/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040028
29#include "dmaengine.h"
30#include "virt-dma.h"
31
32/*
33 * This will go away when the private EDMA API is folded
34 * into this driver and the platform device(s) are
35 * instantiated in the arch code. We can only get away
36 * with this simplification because DA8XX may not be built
37 * in the same kernel image with other DaVinci parts. This
38 * avoids having to sprinkle dmaengine driver platform devices
39 * and data throughout all the existing board files.
40 */
41#ifdef CONFIG_ARCH_DAVINCI_DA8XX
42#define EDMA_CTLRS 2
43#define EDMA_CHANS 32
44#else
45#define EDMA_CTLRS 1
46#define EDMA_CHANS 64
47#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
48
Joel Fernandes2abd5f12013-09-23 18:05:15 -050049/*
50 * Max of 20 segments per channel to conserve PaRAM slots
51 * Also note that MAX_NR_SG should be atleast the no.of periods
52 * that are required for ASoC, otherwise DMA prep calls will
53 * fail. Today davinci-pcm is the only user of this driver and
54 * requires atleast 17 slots, so we setup the default to 20.
55 */
56#define MAX_NR_SG 20
Matt Porterc2dde5f2012-08-22 21:09:34 -040057#define EDMA_MAX_SLOTS MAX_NR_SG
58#define EDMA_DESCRIPTORS 16
59
60struct edma_desc {
61 struct virt_dma_desc vdesc;
62 struct list_head node;
Joel Fernandes50a9c702013-10-31 16:31:23 -050063 int cyclic;
Matt Porterc2dde5f2012-08-22 21:09:34 -040064 int absync;
65 int pset_nr;
Joel Fernandes53407062013-09-03 10:02:46 -050066 int processed;
Matt Porterc2dde5f2012-08-22 21:09:34 -040067 struct edmacc_param pset[0];
68};
69
70struct edma_cc;
71
72struct edma_chan {
73 struct virt_dma_chan vchan;
74 struct list_head node;
75 struct edma_desc *edesc;
76 struct edma_cc *ecc;
77 int ch_num;
78 bool alloced;
79 int slot[EDMA_MAX_SLOTS];
Joel Fernandesc5f47992013-08-29 18:05:43 -050080 int missed;
Matt Porter661f7cb2013-01-10 13:41:04 -050081 struct dma_slave_config cfg;
Matt Porterc2dde5f2012-08-22 21:09:34 -040082};
83
84struct edma_cc {
85 int ctlr;
86 struct dma_device dma_slave;
87 struct edma_chan slave_chans[EDMA_CHANS];
88 int num_slave_chans;
89 int dummy_slot;
90};
91
92static inline struct edma_cc *to_edma_cc(struct dma_device *d)
93{
94 return container_of(d, struct edma_cc, dma_slave);
95}
96
97static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
98{
99 return container_of(c, struct edma_chan, vchan.chan);
100}
101
102static inline struct edma_desc
103*to_edma_desc(struct dma_async_tx_descriptor *tx)
104{
105 return container_of(tx, struct edma_desc, vdesc.tx);
106}
107
108static void edma_desc_free(struct virt_dma_desc *vdesc)
109{
110 kfree(container_of(vdesc, struct edma_desc, vdesc));
111}
112
113/* Dispatch a queued descriptor to the controller (caller holds lock) */
114static void edma_execute(struct edma_chan *echan)
115{
Joel Fernandes53407062013-09-03 10:02:46 -0500116 struct virt_dma_desc *vdesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400117 struct edma_desc *edesc;
Joel Fernandes53407062013-09-03 10:02:46 -0500118 struct device *dev = echan->vchan.chan.device->dev;
119 int i, j, left, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400120
Joel Fernandes53407062013-09-03 10:02:46 -0500121 /* If either we processed all psets or we're still not started */
122 if (!echan->edesc ||
123 echan->edesc->pset_nr == echan->edesc->processed) {
124 /* Get next vdesc */
125 vdesc = vchan_next_desc(&echan->vchan);
126 if (!vdesc) {
127 echan->edesc = NULL;
128 return;
129 }
130 list_del(&vdesc->node);
131 echan->edesc = to_edma_desc(&vdesc->tx);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400132 }
133
Joel Fernandes53407062013-09-03 10:02:46 -0500134 edesc = echan->edesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400135
Joel Fernandes53407062013-09-03 10:02:46 -0500136 /* Find out how many left */
137 left = edesc->pset_nr - edesc->processed;
138 nslots = min(MAX_NR_SG, left);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400139
140 /* Write descriptor PaRAM set(s) */
Joel Fernandes53407062013-09-03 10:02:46 -0500141 for (i = 0; i < nslots; i++) {
142 j = i + edesc->processed;
143 edma_write_slot(echan->slot[i], &edesc->pset[j]);
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300144 dev_vdbg(echan->vchan.chan.device->dev,
Matt Porterc2dde5f2012-08-22 21:09:34 -0400145 "\n pset[%d]:\n"
146 " chnum\t%d\n"
147 " slot\t%d\n"
148 " opt\t%08x\n"
149 " src\t%08x\n"
150 " dst\t%08x\n"
151 " abcnt\t%08x\n"
152 " ccnt\t%08x\n"
153 " bidx\t%08x\n"
154 " cidx\t%08x\n"
155 " lkrld\t%08x\n",
Joel Fernandes53407062013-09-03 10:02:46 -0500156 j, echan->ch_num, echan->slot[i],
157 edesc->pset[j].opt,
158 edesc->pset[j].src,
159 edesc->pset[j].dst,
160 edesc->pset[j].a_b_cnt,
161 edesc->pset[j].ccnt,
162 edesc->pset[j].src_dst_bidx,
163 edesc->pset[j].src_dst_cidx,
164 edesc->pset[j].link_bcntrld);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400165 /* Link to the previous slot if not the last set */
Joel Fernandes53407062013-09-03 10:02:46 -0500166 if (i != (nslots - 1))
Matt Porterc2dde5f2012-08-22 21:09:34 -0400167 edma_link(echan->slot[i], echan->slot[i+1]);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400168 }
169
Joel Fernandes53407062013-09-03 10:02:46 -0500170 edesc->processed += nslots;
171
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500172 /*
173 * If this is either the last set in a set of SG-list transactions
174 * then setup a link to the dummy slot, this results in all future
175 * events being absorbed and that's OK because we're done
176 */
Joel Fernandes50a9c702013-10-31 16:31:23 -0500177 if (edesc->processed == edesc->pset_nr) {
178 if (edesc->cyclic)
179 edma_link(echan->slot[nslots-1], echan->slot[1]);
180 else
181 edma_link(echan->slot[nslots-1],
182 echan->ecc->dummy_slot);
183 }
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500184
Joel Fernandes53407062013-09-03 10:02:46 -0500185 if (edesc->processed <= MAX_NR_SG) {
186 dev_dbg(dev, "first transfer starting %d\n", echan->ch_num);
187 edma_start(echan->ch_num);
Sekhar Nori5fc68a62014-03-19 11:25:50 +0530188 } else {
189 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
190 echan->ch_num, edesc->processed);
191 edma_resume(echan->ch_num);
Joel Fernandes53407062013-09-03 10:02:46 -0500192 }
Joel Fernandesc5f47992013-08-29 18:05:43 -0500193
194 /*
195 * This happens due to setup times between intermediate transfers
196 * in long SG lists which have to be broken up into transfers of
197 * MAX_NR_SG
198 */
199 if (echan->missed) {
200 dev_dbg(dev, "missed event in execute detected\n");
201 edma_clean_channel(echan->ch_num);
202 edma_stop(echan->ch_num);
203 edma_start(echan->ch_num);
204 edma_trigger_channel(echan->ch_num);
205 echan->missed = 0;
206 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400207}
208
209static int edma_terminate_all(struct edma_chan *echan)
210{
211 unsigned long flags;
212 LIST_HEAD(head);
213
214 spin_lock_irqsave(&echan->vchan.lock, flags);
215
216 /*
217 * Stop DMA activity: we assume the callback will not be called
218 * after edma_dma() returns (even if it does, it will see
219 * echan->edesc is NULL and exit.)
220 */
221 if (echan->edesc) {
222 echan->edesc = NULL;
223 edma_stop(echan->ch_num);
224 }
225
226 vchan_get_all_descriptors(&echan->vchan, &head);
227 spin_unlock_irqrestore(&echan->vchan.lock, flags);
228 vchan_dma_desc_free_list(&echan->vchan, &head);
229
230 return 0;
231}
232
Matt Porterc2dde5f2012-08-22 21:09:34 -0400233static int edma_slave_config(struct edma_chan *echan,
Matt Porter661f7cb2013-01-10 13:41:04 -0500234 struct dma_slave_config *cfg)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400235{
Matt Porter661f7cb2013-01-10 13:41:04 -0500236 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
237 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400238 return -EINVAL;
239
Matt Porter661f7cb2013-01-10 13:41:04 -0500240 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
Matt Porterc2dde5f2012-08-22 21:09:34 -0400241
242 return 0;
243}
244
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300245static int edma_dma_pause(struct edma_chan *echan)
246{
247 /* Pause/Resume only allowed with cyclic mode */
248 if (!echan->edesc->cyclic)
249 return -EINVAL;
250
251 edma_pause(echan->ch_num);
252 return 0;
253}
254
255static int edma_dma_resume(struct edma_chan *echan)
256{
257 /* Pause/Resume only allowed with cyclic mode */
258 if (!echan->edesc->cyclic)
259 return -EINVAL;
260
261 edma_resume(echan->ch_num);
262 return 0;
263}
264
Matt Porterc2dde5f2012-08-22 21:09:34 -0400265static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
266 unsigned long arg)
267{
268 int ret = 0;
269 struct dma_slave_config *config;
270 struct edma_chan *echan = to_edma_chan(chan);
271
272 switch (cmd) {
273 case DMA_TERMINATE_ALL:
274 edma_terminate_all(echan);
275 break;
276 case DMA_SLAVE_CONFIG:
277 config = (struct dma_slave_config *)arg;
278 ret = edma_slave_config(echan, config);
279 break;
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300280 case DMA_PAUSE:
281 ret = edma_dma_pause(echan);
282 break;
283
284 case DMA_RESUME:
285 ret = edma_dma_resume(echan);
286 break;
287
Matt Porterc2dde5f2012-08-22 21:09:34 -0400288 default:
289 ret = -ENOSYS;
290 }
291
292 return ret;
293}
294
Joel Fernandesfd009032013-09-23 18:05:13 -0500295/*
296 * A PaRAM set configuration abstraction used by other modes
297 * @chan: Channel who's PaRAM set we're configuring
298 * @pset: PaRAM set to initialize and setup.
299 * @src_addr: Source address of the DMA
300 * @dst_addr: Destination address of the DMA
301 * @burst: In units of dev_width, how much to send
302 * @dev_width: How much is the dev_width
303 * @dma_length: Total length of the DMA transfer
304 * @direction: Direction of the transfer
305 */
306static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
307 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
308 enum dma_slave_buswidth dev_width, unsigned int dma_length,
309 enum dma_transfer_direction direction)
310{
311 struct edma_chan *echan = to_edma_chan(chan);
312 struct device *dev = chan->device->dev;
313 int acnt, bcnt, ccnt, cidx;
314 int src_bidx, dst_bidx, src_cidx, dst_cidx;
315 int absync;
316
317 acnt = dev_width;
Peter Ujfalusib2b617d2014-04-14 14:41:58 +0300318
319 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
320 if (!burst)
321 burst = 1;
Joel Fernandesfd009032013-09-23 18:05:13 -0500322 /*
323 * If the maxburst is equal to the fifo width, use
324 * A-synced transfers. This allows for large contiguous
325 * buffer transfers using only one PaRAM set.
326 */
327 if (burst == 1) {
328 /*
329 * For the A-sync case, bcnt and ccnt are the remainder
330 * and quotient respectively of the division of:
331 * (dma_length / acnt) by (SZ_64K -1). This is so
332 * that in case bcnt over flows, we have ccnt to use.
333 * Note: In A-sync tranfer only, bcntrld is used, but it
334 * only applies for sg_dma_len(sg) >= SZ_64K.
335 * In this case, the best way adopted is- bccnt for the
336 * first frame will be the remainder below. Then for
337 * every successive frame, bcnt will be SZ_64K-1. This
338 * is assured as bcntrld = 0xffff in end of function.
339 */
340 absync = false;
341 ccnt = dma_length / acnt / (SZ_64K - 1);
342 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
343 /*
344 * If bcnt is non-zero, we have a remainder and hence an
345 * extra frame to transfer, so increment ccnt.
346 */
347 if (bcnt)
348 ccnt++;
349 else
350 bcnt = SZ_64K - 1;
351 cidx = acnt;
352 } else {
353 /*
354 * If maxburst is greater than the fifo address_width,
355 * use AB-synced transfers where A count is the fifo
356 * address_width and B count is the maxburst. In this
357 * case, we are limited to transfers of C count frames
358 * of (address_width * maxburst) where C count is limited
359 * to SZ_64K-1. This places an upper bound on the length
360 * of an SG segment that can be handled.
361 */
362 absync = true;
363 bcnt = burst;
364 ccnt = dma_length / (acnt * bcnt);
365 if (ccnt > (SZ_64K - 1)) {
366 dev_err(dev, "Exceeded max SG segment size\n");
367 return -EINVAL;
368 }
369 cidx = acnt * bcnt;
370 }
371
372 if (direction == DMA_MEM_TO_DEV) {
373 src_bidx = acnt;
374 src_cidx = cidx;
375 dst_bidx = 0;
376 dst_cidx = 0;
377 } else if (direction == DMA_DEV_TO_MEM) {
378 src_bidx = 0;
379 src_cidx = 0;
380 dst_bidx = acnt;
381 dst_cidx = cidx;
382 } else {
383 dev_err(dev, "%s: direction not implemented yet\n", __func__);
384 return -EINVAL;
385 }
386
387 pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
388 /* Configure A or AB synchronized transfers */
389 if (absync)
390 pset->opt |= SYNCDIM;
391
392 pset->src = src_addr;
393 pset->dst = dst_addr;
394
395 pset->src_dst_bidx = (dst_bidx << 16) | src_bidx;
396 pset->src_dst_cidx = (dst_cidx << 16) | src_cidx;
397
398 pset->a_b_cnt = bcnt << 16 | acnt;
399 pset->ccnt = ccnt;
400 /*
401 * Only time when (bcntrld) auto reload is required is for
402 * A-sync case, and in this case, a requirement of reload value
403 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
404 * and then later will be populated by edma_execute.
405 */
406 pset->link_bcntrld = 0xffffffff;
407 return absync;
408}
409
Matt Porterc2dde5f2012-08-22 21:09:34 -0400410static struct dma_async_tx_descriptor *edma_prep_slave_sg(
411 struct dma_chan *chan, struct scatterlist *sgl,
412 unsigned int sg_len, enum dma_transfer_direction direction,
413 unsigned long tx_flags, void *context)
414{
415 struct edma_chan *echan = to_edma_chan(chan);
416 struct device *dev = chan->device->dev;
417 struct edma_desc *edesc;
Joel Fernandesfd009032013-09-23 18:05:13 -0500418 dma_addr_t src_addr = 0, dst_addr = 0;
Matt Porter661f7cb2013-01-10 13:41:04 -0500419 enum dma_slave_buswidth dev_width;
420 u32 burst;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400421 struct scatterlist *sg;
Joel Fernandesfd009032013-09-23 18:05:13 -0500422 int i, nslots, ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400423
424 if (unlikely(!echan || !sgl || !sg_len))
425 return NULL;
426
Matt Porter661f7cb2013-01-10 13:41:04 -0500427 if (direction == DMA_DEV_TO_MEM) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500428 src_addr = echan->cfg.src_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -0500429 dev_width = echan->cfg.src_addr_width;
430 burst = echan->cfg.src_maxburst;
431 } else if (direction == DMA_MEM_TO_DEV) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500432 dst_addr = echan->cfg.dst_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -0500433 dev_width = echan->cfg.dst_addr_width;
434 burst = echan->cfg.dst_maxburst;
435 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +0300436 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Matt Porter661f7cb2013-01-10 13:41:04 -0500437 return NULL;
438 }
439
440 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300441 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400442 return NULL;
443 }
444
Matt Porterc2dde5f2012-08-22 21:09:34 -0400445 edesc = kzalloc(sizeof(*edesc) + sg_len *
446 sizeof(edesc->pset[0]), GFP_ATOMIC);
447 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300448 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400449 return NULL;
450 }
451
452 edesc->pset_nr = sg_len;
453
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500454 /* Allocate a PaRAM slot, if needed */
455 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
456
457 for (i = 0; i < nslots; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -0400458 if (echan->slot[i] < 0) {
459 echan->slot[i] =
460 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
461 EDMA_SLOT_ANY);
462 if (echan->slot[i] < 0) {
Valentin Ilie4b6271a2013-10-24 16:14:22 +0300463 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +0300464 dev_err(dev, "%s: Failed to allocate slot\n",
465 __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400466 return NULL;
467 }
468 }
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500469 }
470
471 /* Configure PaRAM sets for each SG */
472 for_each_sg(sgl, sg, sg_len, i) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500473 /* Get address for each SG */
474 if (direction == DMA_DEV_TO_MEM)
475 dst_addr = sg_dma_address(sg);
476 else
477 src_addr = sg_dma_address(sg);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400478
Joel Fernandesfd009032013-09-23 18:05:13 -0500479 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
480 dst_addr, burst, dev_width,
481 sg_dma_len(sg), direction);
Vinod Koulb967aec2013-10-30 13:07:18 +0530482 if (ret < 0) {
483 kfree(edesc);
Joel Fernandesfd009032013-09-23 18:05:13 -0500484 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400485 }
486
Joel Fernandesfd009032013-09-23 18:05:13 -0500487 edesc->absync = ret;
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500488
489 /* If this is the last in a current SG set of transactions,
490 enable interrupts so that next set is processed */
491 if (!((i+1) % MAX_NR_SG))
492 edesc->pset[i].opt |= TCINTEN;
493
Matt Porterc2dde5f2012-08-22 21:09:34 -0400494 /* If this is the last set, enable completion interrupt flag */
495 if (i == sg_len - 1)
496 edesc->pset[i].opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400497 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400498
Matt Porterc2dde5f2012-08-22 21:09:34 -0400499 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
500}
Matt Porterc2dde5f2012-08-22 21:09:34 -0400501
Joel Fernandes50a9c702013-10-31 16:31:23 -0500502static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
503 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
504 size_t period_len, enum dma_transfer_direction direction,
505 unsigned long tx_flags, void *context)
506{
507 struct edma_chan *echan = to_edma_chan(chan);
508 struct device *dev = chan->device->dev;
509 struct edma_desc *edesc;
510 dma_addr_t src_addr, dst_addr;
511 enum dma_slave_buswidth dev_width;
512 u32 burst;
513 int i, ret, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400514
Joel Fernandes50a9c702013-10-31 16:31:23 -0500515 if (unlikely(!echan || !buf_len || !period_len))
516 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400517
Joel Fernandes50a9c702013-10-31 16:31:23 -0500518 if (direction == DMA_DEV_TO_MEM) {
519 src_addr = echan->cfg.src_addr;
520 dst_addr = buf_addr;
521 dev_width = echan->cfg.src_addr_width;
522 burst = echan->cfg.src_maxburst;
523 } else if (direction == DMA_MEM_TO_DEV) {
524 src_addr = buf_addr;
525 dst_addr = echan->cfg.dst_addr;
526 dev_width = echan->cfg.dst_addr_width;
527 burst = echan->cfg.dst_maxburst;
528 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +0300529 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500530 return NULL;
531 }
532
533 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300534 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500535 return NULL;
536 }
537
538 if (unlikely(buf_len % period_len)) {
539 dev_err(dev, "Period should be multiple of Buffer length\n");
540 return NULL;
541 }
542
543 nslots = (buf_len / period_len) + 1;
544
545 /*
546 * Cyclic DMA users such as audio cannot tolerate delays introduced
547 * by cases where the number of periods is more than the maximum
548 * number of SGs the EDMA driver can handle at a time. For DMA types
549 * such as Slave SGs, such delays are tolerable and synchronized,
550 * but the synchronization is difficult to achieve with Cyclic and
551 * cannot be guaranteed, so we error out early.
552 */
553 if (nslots > MAX_NR_SG)
554 return NULL;
555
556 edesc = kzalloc(sizeof(*edesc) + nslots *
557 sizeof(edesc->pset[0]), GFP_ATOMIC);
558 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300559 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500560 return NULL;
561 }
562
563 edesc->cyclic = 1;
564 edesc->pset_nr = nslots;
565
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300566 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
567 __func__, echan->ch_num, nslots, period_len, buf_len);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500568
569 for (i = 0; i < nslots; i++) {
570 /* Allocate a PaRAM slot, if needed */
571 if (echan->slot[i] < 0) {
572 echan->slot[i] =
573 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
574 EDMA_SLOT_ANY);
575 if (echan->slot[i] < 0) {
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100576 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +0300577 dev_err(dev, "%s: Failed to allocate slot\n",
578 __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500579 return NULL;
580 }
581 }
582
583 if (i == nslots - 1) {
584 memcpy(&edesc->pset[i], &edesc->pset[0],
585 sizeof(edesc->pset[0]));
586 break;
587 }
588
589 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
590 dst_addr, burst, dev_width, period_len,
591 direction);
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100592 if (ret < 0) {
593 kfree(edesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500594 return NULL;
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100595 }
Joel Fernandes50a9c702013-10-31 16:31:23 -0500596
597 if (direction == DMA_DEV_TO_MEM)
598 dst_addr += period_len;
599 else
600 src_addr += period_len;
601
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300602 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
603 dev_vdbg(dev,
Joel Fernandes50a9c702013-10-31 16:31:23 -0500604 "\n pset[%d]:\n"
605 " chnum\t%d\n"
606 " slot\t%d\n"
607 " opt\t%08x\n"
608 " src\t%08x\n"
609 " dst\t%08x\n"
610 " abcnt\t%08x\n"
611 " ccnt\t%08x\n"
612 " bidx\t%08x\n"
613 " cidx\t%08x\n"
614 " lkrld\t%08x\n",
615 i, echan->ch_num, echan->slot[i],
616 edesc->pset[i].opt,
617 edesc->pset[i].src,
618 edesc->pset[i].dst,
619 edesc->pset[i].a_b_cnt,
620 edesc->pset[i].ccnt,
621 edesc->pset[i].src_dst_bidx,
622 edesc->pset[i].src_dst_cidx,
623 edesc->pset[i].link_bcntrld);
624
625 edesc->absync = ret;
626
627 /*
628 * Enable interrupts for every period because callback
629 * has to be called for every period.
630 */
631 edesc->pset[i].opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400632 }
633
634 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
635}
636
637static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
638{
639 struct edma_chan *echan = data;
640 struct device *dev = echan->vchan.chan.device->dev;
641 struct edma_desc *edesc;
642 unsigned long flags;
Joel Fernandesc5f47992013-08-29 18:05:43 -0500643 struct edmacc_param p;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400644
Joel Fernandes50a9c702013-10-31 16:31:23 -0500645 edesc = echan->edesc;
646
647 /* Pause the channel for non-cyclic */
648 if (!edesc || (edesc && !edesc->cyclic))
649 edma_pause(echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400650
651 switch (ch_status) {
Vinod Kouldb60d8d2013-10-30 18:22:30 +0530652 case EDMA_DMA_COMPLETE:
Matt Porterc2dde5f2012-08-22 21:09:34 -0400653 spin_lock_irqsave(&echan->vchan.lock, flags);
654
Matt Porterc2dde5f2012-08-22 21:09:34 -0400655 if (edesc) {
Joel Fernandes50a9c702013-10-31 16:31:23 -0500656 if (edesc->cyclic) {
657 vchan_cyclic_callback(&edesc->vdesc);
658 } else if (edesc->processed == edesc->pset_nr) {
Joel Fernandes53407062013-09-03 10:02:46 -0500659 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
660 edma_stop(echan->ch_num);
661 vchan_cookie_complete(&edesc->vdesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500662 edma_execute(echan);
Joel Fernandes53407062013-09-03 10:02:46 -0500663 } else {
664 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500665 edma_execute(echan);
Joel Fernandes53407062013-09-03 10:02:46 -0500666 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400667 }
668
669 spin_unlock_irqrestore(&echan->vchan.lock, flags);
670
671 break;
Vinod Kouldb60d8d2013-10-30 18:22:30 +0530672 case EDMA_DMA_CC_ERROR:
Joel Fernandesc5f47992013-08-29 18:05:43 -0500673 spin_lock_irqsave(&echan->vchan.lock, flags);
674
675 edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
676
677 /*
678 * Issue later based on missed flag which will be sure
679 * to happen as:
680 * (1) we finished transmitting an intermediate slot and
681 * edma_execute is coming up.
682 * (2) or we finished current transfer and issue will
683 * call edma_execute.
684 *
685 * Important note: issuing can be dangerous here and
686 * lead to some nasty recursion when we are in a NULL
687 * slot. So we avoid doing so and set the missed flag.
688 */
689 if (p.a_b_cnt == 0 && p.ccnt == 0) {
690 dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
691 echan->missed = 1;
692 } else {
693 /*
694 * The slot is already programmed but the event got
695 * missed, so its safe to issue it here.
696 */
697 dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
698 edma_clean_channel(echan->ch_num);
699 edma_stop(echan->ch_num);
700 edma_start(echan->ch_num);
701 edma_trigger_channel(echan->ch_num);
702 }
703
704 spin_unlock_irqrestore(&echan->vchan.lock, flags);
705
Matt Porterc2dde5f2012-08-22 21:09:34 -0400706 break;
707 default:
708 break;
709 }
710}
711
712/* Alloc channel resources */
713static int edma_alloc_chan_resources(struct dma_chan *chan)
714{
715 struct edma_chan *echan = to_edma_chan(chan);
716 struct device *dev = chan->device->dev;
717 int ret;
718 int a_ch_num;
719 LIST_HEAD(descs);
720
721 a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
722 chan, EVENTQ_DEFAULT);
723
724 if (a_ch_num < 0) {
725 ret = -ENODEV;
726 goto err_no_chan;
727 }
728
729 if (a_ch_num != echan->ch_num) {
730 dev_err(dev, "failed to allocate requested channel %u:%u\n",
731 EDMA_CTLR(echan->ch_num),
732 EDMA_CHAN_SLOT(echan->ch_num));
733 ret = -ENODEV;
734 goto err_wrong_chan;
735 }
736
737 echan->alloced = true;
738 echan->slot[0] = echan->ch_num;
739
Ezequiel Garcia0e772c62013-12-13 11:06:18 -0300740 dev_dbg(dev, "allocated channel for %u:%u\n",
741 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
Matt Porterc2dde5f2012-08-22 21:09:34 -0400742
743 return 0;
744
745err_wrong_chan:
746 edma_free_channel(a_ch_num);
747err_no_chan:
748 return ret;
749}
750
751/* Free channel resources */
752static void edma_free_chan_resources(struct dma_chan *chan)
753{
754 struct edma_chan *echan = to_edma_chan(chan);
755 struct device *dev = chan->device->dev;
756 int i;
757
758 /* Terminate transfers */
759 edma_stop(echan->ch_num);
760
761 vchan_free_chan_resources(&echan->vchan);
762
763 /* Free EDMA PaRAM slots */
764 for (i = 1; i < EDMA_MAX_SLOTS; i++) {
765 if (echan->slot[i] >= 0) {
766 edma_free_slot(echan->slot[i]);
767 echan->slot[i] = -1;
768 }
769 }
770
771 /* Free EDMA channel */
772 if (echan->alloced) {
773 edma_free_channel(echan->ch_num);
774 echan->alloced = false;
775 }
776
Ezequiel Garcia0e772c62013-12-13 11:06:18 -0300777 dev_dbg(dev, "freeing channel for %u\n", echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400778}
779
780/* Send pending descriptor to hardware */
781static void edma_issue_pending(struct dma_chan *chan)
782{
783 struct edma_chan *echan = to_edma_chan(chan);
784 unsigned long flags;
785
786 spin_lock_irqsave(&echan->vchan.lock, flags);
787 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
788 edma_execute(echan);
789 spin_unlock_irqrestore(&echan->vchan.lock, flags);
790}
791
792static size_t edma_desc_size(struct edma_desc *edesc)
793{
794 int i;
795 size_t size;
796
797 if (edesc->absync)
798 for (size = i = 0; i < edesc->pset_nr; i++)
799 size += (edesc->pset[i].a_b_cnt & 0xffff) *
800 (edesc->pset[i].a_b_cnt >> 16) *
801 edesc->pset[i].ccnt;
802 else
803 size = (edesc->pset[0].a_b_cnt & 0xffff) *
804 (edesc->pset[0].a_b_cnt >> 16) +
805 (edesc->pset[0].a_b_cnt & 0xffff) *
806 (SZ_64K - 1) * edesc->pset[0].ccnt;
807
808 return size;
809}
810
811/* Check request completion status */
812static enum dma_status edma_tx_status(struct dma_chan *chan,
813 dma_cookie_t cookie,
814 struct dma_tx_state *txstate)
815{
816 struct edma_chan *echan = to_edma_chan(chan);
817 struct virt_dma_desc *vdesc;
818 enum dma_status ret;
819 unsigned long flags;
820
821 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul9d386ec2013-10-16 13:42:15 +0530822 if (ret == DMA_COMPLETE || !txstate)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400823 return ret;
824
825 spin_lock_irqsave(&echan->vchan.lock, flags);
826 vdesc = vchan_find_desc(&echan->vchan, cookie);
827 if (vdesc) {
828 txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
829 } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
830 struct edma_desc *edesc = echan->edesc;
831 txstate->residue = edma_desc_size(edesc);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400832 }
833 spin_unlock_irqrestore(&echan->vchan.lock, flags);
834
835 return ret;
836}
837
838static void __init edma_chan_init(struct edma_cc *ecc,
839 struct dma_device *dma,
840 struct edma_chan *echans)
841{
842 int i, j;
843
844 for (i = 0; i < EDMA_CHANS; i++) {
845 struct edma_chan *echan = &echans[i];
846 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
847 echan->ecc = ecc;
848 echan->vchan.desc_free = edma_desc_free;
849
850 vchan_init(&echan->vchan, dma);
851
852 INIT_LIST_HEAD(&echan->node);
853 for (j = 0; j < EDMA_MAX_SLOTS; j++)
854 echan->slot[j] = -1;
855 }
856}
857
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +0300858#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
859 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
860 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
861
862static int edma_dma_device_slave_caps(struct dma_chan *dchan,
863 struct dma_slave_caps *caps)
864{
865 caps->src_addr_widths = EDMA_DMA_BUSWIDTHS;
866 caps->dstn_addr_widths = EDMA_DMA_BUSWIDTHS;
867 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
868 caps->cmd_pause = true;
869 caps->cmd_terminate = true;
870 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
871
872 return 0;
873}
874
Matt Porterc2dde5f2012-08-22 21:09:34 -0400875static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
876 struct device *dev)
877{
878 dma->device_prep_slave_sg = edma_prep_slave_sg;
Joel Fernandes50a9c702013-10-31 16:31:23 -0500879 dma->device_prep_dma_cyclic = edma_prep_dma_cyclic;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400880 dma->device_alloc_chan_resources = edma_alloc_chan_resources;
881 dma->device_free_chan_resources = edma_free_chan_resources;
882 dma->device_issue_pending = edma_issue_pending;
883 dma->device_tx_status = edma_tx_status;
884 dma->device_control = edma_control;
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +0300885 dma->device_slave_caps = edma_dma_device_slave_caps;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400886 dma->dev = dev;
887
888 INIT_LIST_HEAD(&dma->channels);
889}
890
Bill Pemberton463a1f82012-11-19 13:22:55 -0500891static int edma_probe(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400892{
893 struct edma_cc *ecc;
894 int ret;
895
Russell King94cb0e72013-06-27 13:45:16 +0100896 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
897 if (ret)
898 return ret;
899
Matt Porterc2dde5f2012-08-22 21:09:34 -0400900 ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
901 if (!ecc) {
902 dev_err(&pdev->dev, "Can't allocate controller\n");
903 return -ENOMEM;
904 }
905
906 ecc->ctlr = pdev->id;
907 ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
908 if (ecc->dummy_slot < 0) {
909 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
910 return -EIO;
911 }
912
913 dma_cap_zero(ecc->dma_slave.cap_mask);
914 dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
Peter Ujfalusi232b223d2014-04-14 14:42:00 +0300915 dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400916
917 edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
918
919 edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
920
921 ret = dma_async_device_register(&ecc->dma_slave);
922 if (ret)
923 goto err_reg1;
924
925 platform_set_drvdata(pdev, ecc);
926
927 dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
928
929 return 0;
930
931err_reg1:
932 edma_free_slot(ecc->dummy_slot);
933 return ret;
934}
935
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -0800936static int edma_remove(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400937{
938 struct device *dev = &pdev->dev;
939 struct edma_cc *ecc = dev_get_drvdata(dev);
940
941 dma_async_device_unregister(&ecc->dma_slave);
942 edma_free_slot(ecc->dummy_slot);
943
944 return 0;
945}
946
947static struct platform_driver edma_driver = {
948 .probe = edma_probe,
Bill Pembertona7d6e3e2012-11-19 13:20:04 -0500949 .remove = edma_remove,
Matt Porterc2dde5f2012-08-22 21:09:34 -0400950 .driver = {
951 .name = "edma-dma-engine",
952 .owner = THIS_MODULE,
953 },
954};
955
956bool edma_filter_fn(struct dma_chan *chan, void *param)
957{
958 if (chan->device->dev->driver == &edma_driver.driver) {
959 struct edma_chan *echan = to_edma_chan(chan);
960 unsigned ch_req = *(unsigned *)param;
961 return ch_req == echan->ch_num;
962 }
963 return false;
964}
965EXPORT_SYMBOL(edma_filter_fn);
966
967static struct platform_device *pdev0, *pdev1;
968
969static const struct platform_device_info edma_dev_info0 = {
970 .name = "edma-dma-engine",
971 .id = 0,
Russell King94cb0e72013-06-27 13:45:16 +0100972 .dma_mask = DMA_BIT_MASK(32),
Matt Porterc2dde5f2012-08-22 21:09:34 -0400973};
974
975static const struct platform_device_info edma_dev_info1 = {
976 .name = "edma-dma-engine",
977 .id = 1,
Russell King94cb0e72013-06-27 13:45:16 +0100978 .dma_mask = DMA_BIT_MASK(32),
Matt Porterc2dde5f2012-08-22 21:09:34 -0400979};
980
981static int edma_init(void)
982{
983 int ret = platform_driver_register(&edma_driver);
984
985 if (ret == 0) {
986 pdev0 = platform_device_register_full(&edma_dev_info0);
987 if (IS_ERR(pdev0)) {
988 platform_driver_unregister(&edma_driver);
989 ret = PTR_ERR(pdev0);
990 goto out;
991 }
992 }
993
994 if (EDMA_CTLRS == 2) {
995 pdev1 = platform_device_register_full(&edma_dev_info1);
996 if (IS_ERR(pdev1)) {
997 platform_driver_unregister(&edma_driver);
998 platform_device_unregister(pdev0);
999 ret = PTR_ERR(pdev1);
1000 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001001 }
1002
1003out:
1004 return ret;
1005}
1006subsys_initcall(edma_init);
1007
1008static void __exit edma_exit(void)
1009{
1010 platform_device_unregister(pdev0);
1011 if (pdev1)
1012 platform_device_unregister(pdev1);
1013 platform_driver_unregister(&edma_driver);
1014}
1015module_exit(edma_exit);
1016
Josh Boyerd71505b2013-09-04 10:32:50 -04001017MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
Matt Porterc2dde5f2012-08-22 21:09:34 -04001018MODULE_DESCRIPTION("TI EDMA DMA engine driver");
1019MODULE_LICENSE("GPL v2");