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David Gibson26ef5c02005-11-10 11:50:16 +11001#ifndef _ASM_POWERPC_CACHE_H
2#define _ASM_POWERPC_CACHE_H
3
4#ifdef __KERNEL__
5
David Gibson26ef5c02005-11-10 11:50:16 +11006
7/* bytes per L1 cache line */
8#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
9#define L1_CACHE_SHIFT 4
10#define MAX_COPY_PREFETCH 1
Kumar Gala3dfa8772008-06-16 09:41:32 -050011#elif defined(CONFIG_PPC_E500MC)
12#define L1_CACHE_SHIFT 6
13#define MAX_COPY_PREFETCH 4
David Gibson26ef5c02005-11-10 11:50:16 +110014#elif defined(CONFIG_PPC32)
15#define L1_CACHE_SHIFT 5
16#define MAX_COPY_PREFETCH 4
17#else /* CONFIG_PPC64 */
18#define L1_CACHE_SHIFT 7
19#endif
20
21#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
22
23#define SMP_CACHE_BYTES L1_CACHE_BYTES
David Gibson26ef5c02005-11-10 11:50:16 +110024
25#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
26struct ppc64_caches {
27 u32 dsize; /* L1 d-cache size */
28 u32 dline_size; /* L1 d-cache line size */
29 u32 log_dline_size;
30 u32 dlines_per_page;
31 u32 isize; /* L1 i-cache size */
32 u32 iline_size; /* L1 i-cache line size */
33 u32 log_iline_size;
34 u32 ilines_per_page;
35};
36
37extern struct ppc64_caches ppc64_caches;
38#endif /* __powerpc64__ && ! __ASSEMBLY__ */
39
Tony Breedsbd67fcf2007-07-04 14:04:31 +100040#if !defined(__ASSEMBLY__)
41#define __read_mostly __attribute__((__section__(".data.read_mostly")))
42#endif
43
David Gibson26ef5c02005-11-10 11:50:16 +110044#endif /* __KERNEL__ */
45#endif /* _ASM_POWERPC_CACHE_H */