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Kumar Gala10b35d92005-09-23 14:08:58 -05001#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
Kumar Gala10b35d92005-09-23 14:08:58 -05004#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +100015#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +110016#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +110020#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb022006-03-01 15:07:07 +110021#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +100023#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -050024#define PPC_FEATURE_PA6T 0x00000800
Paul Mackerras974a76f2006-11-10 20:38:53 +110025#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
Michael Neulinge952e6c2008-06-18 10:47:26 +100027#define PPC_FEATURE_ARCH_2_06 0x00000100
Michael Neulingb962ce92008-06-25 14:07:18 +100028#define PPC_FEATURE_HAS_VSX 0x00000080
Kumar Gala10b35d92005-09-23 14:08:58 -050029
Nathan Lynch0f473312008-07-10 01:06:57 +100030#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
31 0x00000040
32
Paul Mackerrasfab5db92006-06-07 16:14:40 +100033#define PPC_FEATURE_TRUE_LE 0x00000002
34#define PPC_FEATURE_PPC_LE 0x00000001
35
Kumar Gala10b35d92005-09-23 14:08:58 -050036#ifdef __KERNEL__
Adrian Bunkd1cdcf22008-06-24 03:48:21 +100037
38#include <asm/asm-compat.h>
Michael Ellermanc5157e52008-06-24 11:32:39 +100039#include <asm/feature-fixups.h>
Adrian Bunkd1cdcf22008-06-24 03:48:21 +100040
Kumar Gala10b35d92005-09-23 14:08:58 -050041#ifndef __ASSEMBLY__
42
43/* This structure can grow, it's real size is used by head.S code
44 * via the mkdefs mechanism.
45 */
46struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -050047
Kumar Gala10b35d92005-09-23 14:08:58 -050048typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -050049typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -050050
Anton Blanchard32a33992006-01-09 15:41:31 +110051enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +000052 PPC_OPROFILE_INVALID = 0,
53 PPC_OPROFILE_RS64 = 1,
54 PPC_OPROFILE_POWER4 = 2,
55 PPC_OPROFILE_G4 = 3,
Andy Fleming39aef682008-02-04 18:27:55 -060056 PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson18f21902006-11-20 18:45:16 +010057 PPC_OPROFILE_CELL = 5,
Olof Johansson25fc5302007-04-18 16:38:21 +100058 PPC_OPROFILE_PA6T = 6,
Anton Blanchard32a33992006-01-09 15:41:31 +110059};
60
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060061enum powerpc_pmc_type {
62 PPC_PMC_DEFAULT = 0,
63 PPC_PMC_IBM = 1,
64 PPC_PMC_PA6T = 2,
Benjamin Herrenschmidtb950bdd2008-08-18 14:23:51 +100065 PPC_PMC_G4 = 3,
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060066};
67
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +110068struct pt_regs;
69
70extern int machine_check_generic(struct pt_regs *regs);
71extern int machine_check_4xx(struct pt_regs *regs);
72extern int machine_check_440A(struct pt_regs *regs);
73extern int machine_check_e500(struct pt_regs *regs);
74extern int machine_check_e200(struct pt_regs *regs);
75
Paul Mackerras87a72f92007-10-04 14:18:01 +100076/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala10b35d92005-09-23 14:08:58 -050077struct cpu_spec {
78 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
79 unsigned int pvr_mask;
80 unsigned int pvr_value;
81
82 char *cpu_name;
83 unsigned long cpu_features; /* Kernel features */
84 unsigned int cpu_user_features; /* Userland features */
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000085 unsigned int mmu_features; /* MMU features */
Kumar Gala10b35d92005-09-23 14:08:58 -050086
87 /* cache line sizes */
88 unsigned int icache_bsize;
89 unsigned int dcache_bsize;
90
91 /* number of performance monitor counters */
92 unsigned int num_pmcs;
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060093 enum powerpc_pmc_type pmc_type;
Kumar Gala10b35d92005-09-23 14:08:58 -050094
95 /* this is called to initialize various CPU bits like L1 cache,
96 * BHT, SPD, etc... from head.S before branching to identify_machine
97 */
98 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -050099 /* Used to restore cpu setup on secondary processors and at resume */
100 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500101
102 /* Used by oprofile userspace to select the right counters */
103 char *oprofile_cpu_type;
104
105 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100106 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100107
Michael Neulinge78dbc82006-06-08 14:42:34 +1000108 /* Bit locations inside the mmcra change */
109 unsigned long oprofile_mmcra_sihv;
110 unsigned long oprofile_mmcra_sipr;
111
112 /* Bits to clear during an oprofile exception */
113 unsigned long oprofile_mmcra_clear;
114
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100115 /* Name of processor class, for the ELF AT_PLATFORM entry */
116 char *platform;
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100117
118 /* Processor specific machine check handling. Return negative
119 * if the error is fatal, 1 if it was fully recovered and 0 to
120 * pass up (not CPU originated) */
121 int (*machine_check)(struct pt_regs *regs);
Kumar Gala10b35d92005-09-23 14:08:58 -0500122};
123
Kumar Gala10b35d92005-09-23 14:08:58 -0500124extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500125
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000126extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
127
Paul Mackerras974a76f2006-11-10 20:38:53 +1100128extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000129extern void do_feature_fixups(unsigned long value, void *fixup_start,
130 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000131
Nathan Lynch9115d132008-07-16 09:58:51 +1000132extern const char *powerpc_base_platform;
133
Kumar Gala10b35d92005-09-23 14:08:58 -0500134#endif /* __ASSEMBLY__ */
135
136/* CPU kernel features */
137
138/* Retain the 32b definitions all use bottom half of word */
David Gibson4508dc22007-06-13 14:52:57 +1000139#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
Kumar Gala10b35d92005-09-23 14:08:58 -0500140#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
141#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
142#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
143#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
144#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
145#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
Kumar Galaaba11fc2008-06-19 09:40:31 -0500146#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
Kumar Gala10b35d92005-09-23 14:08:58 -0500147#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
Kumar Gala620165f2009-02-12 13:54:53 +0000148#define CPU_FTR_DBELL ASM_CONST(0x0000000000000200)
Kumar Gala10b35d92005-09-23 14:08:58 -0500149#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
150#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
151#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
152#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
153#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
154#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500155#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
156#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100157#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000158#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
159#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kim Phillipsaa42c692006-12-08 02:43:30 -0600160#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
David Gibson4508dc22007-06-13 14:52:57 +1000161#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
Kumar Gala5e14d212007-09-13 01:44:20 -0500162#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
Becky Bruceb64f87c2007-11-10 09:17:49 +1100163#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000164#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100165#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000166#define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500167
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000168/*
169 * Add the 64-bit processor unique features in the top half of the word;
170 * on 32-bit, make the names available but defined to be 0.
171 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500172#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000173#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500174#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000175#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500176#endif
177
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000178#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
179#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
180#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000181#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
182#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
183#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
184#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000185#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
186#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
187#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
188#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000189#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
Paul Mackerras974a76f2006-11-10 20:38:53 +1100190#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
Anton Blanchard4c1985572006-12-08 17:46:58 +1100191#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
Paul Mackerras1189be62007-10-11 20:37:10 +1000192#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
Olof Johanssonf66bce52007-10-16 00:58:59 +1000193#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
Michael Neulingb962ce92008-06-25 14:07:18 +1000194#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
Dave Kleikamp37907042008-07-08 00:28:53 +1000195#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
Mark Nelson2a929432008-08-22 14:36:19 +1000196#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
Mark Nelson4ec577a2008-10-27 00:43:02 +0000197#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000198
Kumar Gala10b35d92005-09-23 14:08:58 -0500199#ifndef __ASSEMBLY__
200
Stephen Rothwell04704662006-11-30 11:46:22 +1100201#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
202 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
203 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
Kumar Gala10b35d92005-09-23 14:08:58 -0500204
205/* We only set the altivec features if the kernel was compiled with altivec
206 * support
207 */
208#ifdef CONFIG_ALTIVEC
209#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
210#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
211#else
212#define CPU_FTR_ALTIVEC_COMP 0
213#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
214#endif
215
Michael Neulingb962ce92008-06-25 14:07:18 +1000216/* We only set the VSX features if the kernel was compiled with VSX
217 * support
218 */
219#ifdef CONFIG_VSX
220#define CPU_FTR_VSX_COMP CPU_FTR_VSX
221#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
222#else
223#define CPU_FTR_VSX_COMP 0
224#define PPC_FEATURE_HAS_VSX_COMP 0
225#endif
226
Kumar Gala5e14d212007-09-13 01:44:20 -0500227/* We only set the spe features if the kernel was compiled with spe
228 * support
229 */
230#ifdef CONFIG_SPE
231#define CPU_FTR_SPE_COMP CPU_FTR_SPE
232#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
233#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
234#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
235#else
236#define CPU_FTR_SPE_COMP 0
237#define PPC_FEATURE_HAS_SPE_COMP 0
238#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
239#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
240#endif
241
Scott Wood11af1192007-09-14 15:32:14 -0500242/* We need to mark all pages as being coherent if we're SMP or we have a
243 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
244 * require it for PCI "streaming/prefetch" to work properly.
Piotr Ziecikc9310922009-03-17 09:17:50 -0600245 * This is also required by 52xx family.
Kumar Gala10b35d92005-09-23 14:08:58 -0500246 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600247#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
Piotr Ziecikc9310922009-03-17 09:17:50 -0600248 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
249 || defined(CONFIG_PPC_MPC52xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500250#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
251#else
252#define CPU_FTR_COMMON 0
253#endif
254
255/* The powersave features NAP & DOZE seems to confuse BDI when
256 debugging. So if a BDI is used, disable theses
257 */
258#ifndef CONFIG_BDI_SWITCH
259#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
260#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
261#else
262#define CPU_FTR_MAYBE_CAN_DOZE 0
263#define CPU_FTR_MAYBE_CAN_NAP 0
264#endif
265
266#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
267 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
268 !defined(CONFIG_BOOKE))
269
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000270#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
David Gibson4508dc22007-06-13 14:52:57 +1000271 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
272#define CPU_FTRS_603 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100273 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000274 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000275#define CPU_FTRS_604 (CPU_FTR_COMMON | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000276 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000277#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100278 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000279 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000280#define CPU_FTRS_740 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100281 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000282 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000283 CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000284#define CPU_FTRS_750 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100285 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000286 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000287 CPU_FTR_PPC_LE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000288#define CPU_FTRS_750CL (CPU_FTRS_750)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000289#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
290#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000291#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000292#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson4508dc22007-06-13 14:52:57 +1000293#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100294 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000295 CPU_FTR_ALTIVEC_COMP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000297#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100298 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000299 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000301#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100302 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000303 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100304 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000305#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100306 CPU_FTR_USE_TB | \
307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000308 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000311#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100312 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000316#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100317 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100318 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000319 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000320#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100321 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100322 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000323 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100324 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000325 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000326#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100327 CPU_FTR_USE_TB | \
328 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000329 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100330 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000331#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100332 CPU_FTR_USE_TB | \
333 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000334 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100335 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
336 CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000337#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100338 CPU_FTR_USE_TB | \
339 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000340 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100341 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000342#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100343 CPU_FTR_USE_TB | \
344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000345 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100346 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000347#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
James.Yang3d372542007-05-02 16:34:43 -0500348 CPU_FTR_USE_TB | \
349 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000350 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100351 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000352#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100353 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
Scott Wood11af1192007-09-14 15:32:14 -0500354#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000355 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
David Gibson4508dc22007-06-13 14:52:57 +1000356#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100358 CPU_FTR_COMMON)
David Gibson4508dc22007-06-13 14:52:57 +1000359#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000360 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
Kim Phillipsaa42c692006-12-08 02:43:30 -0600361 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000362#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
David Gibson4508dc22007-06-13 14:52:57 +1000363#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100364#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
365#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000366#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
367 CPU_FTR_INDEXED_DCR)
Kumar Gala5e14d212007-09-13 01:44:20 -0500368#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
369 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100370 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
Kumar Galafc4033b2008-06-18 16:26:52 -0500371#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100372 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
373 CPU_FTR_NOEXECUTE)
Kumar Galafc4033b2008-06-18 16:26:52 -0500374#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000375 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100376 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
Kumar Galafc4033b2008-06-18 16:26:52 -0500377#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000378 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
Kumar Gala620165f2009-02-12 13:54:53 +0000379 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
380 CPU_FTR_DBELL)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100381#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Michael Ellerman0b8e2e12006-11-23 00:46:46 +0100382
383/* 64-bit CPUs */
Kumar Gala2d1b2022008-07-02 01:16:40 +1000384#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000385 CPU_FTR_IABR | CPU_FTR_PPC_LE)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000386#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000387 CPU_FTR_IABR | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100388 CPU_FTR_MMCRA | CPU_FTR_CTRL)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000389#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000390 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Mark Nelson2a929432008-08-22 14:36:19 +1000391 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000392#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000393 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Mark Nelson2a929432008-08-22 14:36:19 +1000394 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
395 CPU_FTR_CP_USE_DCBTZ)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000396#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000397 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100398 CPU_FTR_MMCRA | CPU_FTR_SMT | \
399 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000400 CPU_FTR_PURR)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000401#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000402 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000403 CPU_FTR_MMCRA | CPU_FTR_SMT | \
404 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Anton Blanchard4c1985572006-12-08 17:46:58 +1100405 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Mark Nelson4ec577a2008-10-27 00:43:02 +0000406 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000407#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000409 CPU_FTR_MMCRA | CPU_FTR_SMT | \
410 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
411 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Dave Kleikamp37907042008-07-08 00:28:53 +1000412 CPU_FTR_DSCR | CPU_FTR_SAO)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000413#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000414 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100415 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Mark Nelson2a929432008-08-22 14:36:19 +1000416 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
Mark Nelson4ec577a2008-10-27 00:43:02 +0000417 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
418 CPU_FTR_UNALIGNED_LD_STD)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000419#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000420 CPU_FTR_PPCAS_ARCH_V2 | \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500421 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
Olof Johanssonf66bce52007-10-16 00:58:59 +1000422 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000423#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500424
Anton Blanchard2406f602005-12-13 07:45:33 +1100425#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100426#define CPU_FTRS_POSSIBLE \
427 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000428 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000429 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
Michael Neulingb962ce92008-06-25 14:07:18 +1000430 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
Anton Blanchard2406f602005-12-13 07:45:33 +1100431#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100432enum {
433 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500434#if CLASSIC_PPC
435 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
436 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
437 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
438 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
439 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
440 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
441 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
Kim Phillipsaa42c692006-12-08 02:43:30 -0600442 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
443 CPU_FTRS_CLASSIC32 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500444#else
445 CPU_FTRS_GENERIC_32 |
446#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500447#ifdef CONFIG_8xx
448 CPU_FTRS_8XX |
449#endif
450#ifdef CONFIG_40x
451 CPU_FTRS_40X |
452#endif
453#ifdef CONFIG_44x
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000454 CPU_FTRS_44X | CPU_FTRS_440x6 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500455#endif
456#ifdef CONFIG_E200
457 CPU_FTRS_E200 |
458#endif
459#ifdef CONFIG_E500
Kumar Gala3dfa8772008-06-16 09:41:32 -0500460 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
Kumar Gala10b35d92005-09-23 14:08:58 -0500461#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500462 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100463};
464#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500465
Anton Blanchard2406f602005-12-13 07:45:33 +1100466#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100467#define CPU_FTRS_ALWAYS \
468 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000469 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000470 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100471#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100472enum {
473 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500474#if CLASSIC_PPC
475 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
476 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
477 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
478 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
479 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
480 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
481 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillipsaa42c692006-12-08 02:43:30 -0600482 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
483 CPU_FTRS_CLASSIC32 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500484#else
485 CPU_FTRS_GENERIC_32 &
486#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500487#ifdef CONFIG_8xx
488 CPU_FTRS_8XX &
489#endif
490#ifdef CONFIG_40x
491 CPU_FTRS_40X &
492#endif
493#ifdef CONFIG_44x
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000494 CPU_FTRS_44X & CPU_FTRS_440x6 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500495#endif
496#ifdef CONFIG_E200
497 CPU_FTRS_E200 &
498#endif
499#ifdef CONFIG_E500
Kumar Gala3dfa8772008-06-16 09:41:32 -0500500 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
Kumar Gala10b35d92005-09-23 14:08:58 -0500501#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500502 CPU_FTRS_POSSIBLE,
503};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100504#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500505
506static inline int cpu_has_feature(unsigned long feature)
507{
508 return (CPU_FTRS_ALWAYS & feature) ||
509 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500510 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500511 & feature);
512}
513
514#endif /* !__ASSEMBLY__ */
515
Kumar Gala10b35d92005-09-23 14:08:58 -0500516#endif /* __KERNEL__ */
517#endif /* __ASM_POWERPC_CPUTABLE_H */