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Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +00001/*
2 * This file contains low-level functions for performing various
3 * types of TLB invalidations on various processors with no hash
4 * table.
5 *
6 * This file implements the following functions for all no-hash
7 * processors. Some aren't implemented for some variants. Some
8 * are inline in tlbflush.h
9 *
10 * - tlbil_va
11 * - tlbil_pid
12 * - tlbil_all
13 * - tlbivax_bcast (not yet)
14 *
15 * Code mostly moved over from misc_32.S
16 *
17 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
18 *
19 * Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
20 * Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
26 *
27 */
28
29#include <asm/reg.h>
30#include <asm/page.h>
31#include <asm/cputable.h>
32#include <asm/mmu.h>
33#include <asm/ppc_asm.h>
34#include <asm/asm-offsets.h>
35#include <asm/processor.h>
36
37#if defined(CONFIG_40x)
38
39/*
40 * 40x implementation needs only tlbil_va
41 */
Benjamin Herrenschmidtd4e167d2009-07-23 23:15:24 +000042_GLOBAL(__tlbil_va)
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +000043 /* We run the search with interrupts disabled because we have to change
44 * the PID and I don't want to preempt when that happens.
45 */
46 mfmsr r5
47 mfspr r6,SPRN_PID
48 wrteei 0
49 mtspr SPRN_PID,r4
50 tlbsx. r3, 0, r3
51 mtspr SPRN_PID,r6
52 wrtee r5
53 bne 1f
54 sync
55 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
56 * clear. Since 25 is the V bit in the TLB_TAG, loading this value
57 * will invalidate the TLB entry. */
58 tlbwe r3, r3, TLB_TAG
59 isync
601: blr
61
62#elif defined(CONFIG_8xx)
63
64/*
65 * Nothing to do for 8xx, everything is inline
66 */
67
68#elif defined(CONFIG_44x)
69
70/*
71 * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
72 * of the TLB for everything else.
73 */
Benjamin Herrenschmidtd4e167d2009-07-23 23:15:24 +000074_GLOBAL(__tlbil_va)
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +000075 mfspr r5,SPRN_MMUCR
76 rlwimi r5,r4,0,24,31 /* Set TID */
77
Benjamin Herrenschmidt760ec0e2008-12-18 19:13:46 +000078 /* We have to run the search with interrupts disabled, otherwise
79 * an interrupt which causes a TLB miss can clobber the MMUCR
80 * between the mtspr and the tlbsx.
81 *
82 * Critical and Machine Check interrupts take care of saving
83 * and restoring MMUCR, so only normal interrupts have to be
84 * taken care of.
85 */
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +000086 mfmsr r4
Benjamin Herrenschmidt760ec0e2008-12-18 19:13:46 +000087 wrteei 0
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +000088 mtspr SPRN_MMUCR,r5
89 tlbsx. r3, 0, r3
Benjamin Herrenschmidt760ec0e2008-12-18 19:13:46 +000090 wrtee r4
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +000091 bne 1f
92 sync
93 /* There are only 64 TLB entries, so r3 < 64,
94 * which means bit 22, is clear. Since 22 is
95 * the V bit in the TLB_PAGEID, loading this
96 * value will invalidate the TLB entry.
97 */
98 tlbwe r3, r3, PPC44x_TLB_PAGEID
99 isync
1001: blr
101
102_GLOBAL(_tlbil_all)
103_GLOBAL(_tlbil_pid)
104 li r3,0
105 sync
106
107 /* Load high watermark */
108 lis r4,tlb_44x_hwater@ha
109 lwz r5,tlb_44x_hwater@l(r4)
110
1111: tlbwe r3,r3,PPC44x_TLB_PAGEID
112 addi r3,r3,1
113 cmpw 0,r3,r5
114 ble 1b
115
116 isync
117 blr
118
119#elif defined(CONFIG_FSL_BOOKE)
120/*
Kumar Galac3071952009-02-10 22:26:06 -0600121 * FSL BookE implementations.
122 *
123 * Since feature sections are using _SECTION_ELSE we need
124 * to have the larger code path before the _SECTION_ELSE
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000125 */
126
127/*
128 * Flush MMU TLB on the local processor
129 */
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000130_GLOBAL(_tlbil_all)
Kumar Galac3071952009-02-10 22:26:06 -0600131BEGIN_MMU_FTR_SECTION
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000132 li r3,(MMUCSR0_TLBFI)@l
133 mtspr SPRN_MMUCSR0, r3
1341:
135 mfspr r3,SPRN_MMUCSR0
136 andi. r3,r3,MMUCSR0_TLBFI@l
137 bne 1b
Kumar Galac3071952009-02-10 22:26:06 -0600138MMU_FTR_SECTION_ELSE
Kumar Gala323d23a2009-04-23 08:51:22 -0500139 PPC_TLBILX_ALL(0,0)
Kumar Galac3071952009-02-10 22:26:06 -0600140ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
141 msync
142 isync
143 blr
144
145_GLOBAL(_tlbil_pid)
146BEGIN_MMU_FTR_SECTION
147 slwi r3,r3,16
148 mfmsr r10
149 wrteei 0
150 mfspr r4,SPRN_MAS6 /* save MAS6 */
151 mtspr SPRN_MAS6,r3
152 PPC_TLBILX_PID(0,0)
153 mtspr SPRN_MAS6,r4 /* restore MAS6 */
154 wrtee r10
155MMU_FTR_SECTION_ELSE
156 li r3,(MMUCSR0_TLBFI)@l
157 mtspr SPRN_MMUCSR0, r3
1581:
159 mfspr r3,SPRN_MMUCSR0
160 andi. r3,r3,MMUCSR0_TLBFI@l
161 bne 1b
162ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000163 msync
164 isync
165 blr
166
167/*
168 * Flush MMU TLB for a particular address, but only on the local processor
169 * (no broadcast)
170 */
Benjamin Herrenschmidtd4e167d2009-07-23 23:15:24 +0000171_GLOBAL(__tlbil_va)
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000172 mfmsr r10
173 wrteei 0
174 slwi r4,r4,16
Kumar Galac3071952009-02-10 22:26:06 -0600175 ori r4,r4,(MAS6_ISIZE(BOOK3E_PAGESZ_4K))@l
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000176 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
Kumar Galac3071952009-02-10 22:26:06 -0600177BEGIN_MMU_FTR_SECTION
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000178 tlbsx 0,r3
179 mfspr r4,SPRN_MAS1 /* check valid */
180 andis. r3,r4,MAS1_VALID@h
181 beq 1f
182 rlwinm r4,r4,0,1,31
183 mtspr SPRN_MAS1,r4
184 tlbwe
Kumar Galac3071952009-02-10 22:26:06 -0600185MMU_FTR_SECTION_ELSE
186 PPC_TLBILX_VA(0,r3)
187ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000188 msync
189 isync
1901: wrtee r10
191 blr
Benjamin Herrenschmidt25d21ad2009-07-23 23:15:47 +0000192#elif defined(CONFIG_PPC_BOOK3E)
193/*
194 * New Book3E (>= 2.06) implementation
195 *
196 * Note: We may be able to get away without the interrupt masking stuff
197 * if we save/restore MAS6 on exceptions that might modify it
198 */
199_GLOBAL(_tlbil_pid)
200 slwi r4,r3,MAS6_SPID_SHIFT
201 mfmsr r10
202 wrteei 0
203 mtspr SPRN_MAS6,r4
204 PPC_TLBILX_PID(0,0)
205 wrtee r10
206 msync
207 isync
208 blr
209
210_GLOBAL(_tlbil_pid_noind)
211 slwi r4,r3,MAS6_SPID_SHIFT
212 mfmsr r10
213 ori r4,r4,MAS6_SIND
214 wrteei 0
215 mtspr SPRN_MAS6,r4
216 PPC_TLBILX_PID(0,0)
217 wrtee r10
218 msync
219 isync
220 blr
221
222_GLOBAL(_tlbil_all)
223 PPC_TLBILX_ALL(0,0)
224 msync
225 isync
226 blr
227
228_GLOBAL(_tlbil_va)
229 mfmsr r10
230 wrteei 0
231 cmpwi cr0,r6,0
232 slwi r4,r4,MAS6_SPID_SHIFT
233 rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
234 beq 1f
235 rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
2361: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
237 PPC_TLBILX_VA(0,r3)
238 msync
239 isync
240 wrtee r10
241 blr
242
243_GLOBAL(_tlbivax_bcast)
244 mfmsr r10
245 wrteei 0
246 cmpwi cr0,r6,0
247 slwi r4,r4,MAS6_SPID_SHIFT
248 rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
249 beq 1f
250 rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
2511: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
252 PPC_TLBIVAX(0,r3)
253 eieio
254 tlbsync
255 sync
256 wrtee r10
257 blr
258
259_GLOBAL(set_context)
260#ifdef CONFIG_BDI_SWITCH
261 /* Context switch the PTE pointer for the Abatron BDI2000.
262 * The PGDIR is the second parameter.
263 */
264 lis r5, abatron_pteptrs@h
265 ori r5, r5, abatron_pteptrs@l
266 stw r4, 0x4(r5)
267#endif
268 mtspr SPRN_PID,r3
269 isync /* Force context change */
270 blr
Stephen Rothwellb62c31a2009-04-23 22:56:11 +1000271#else
Benjamin Herrenschmidt2a4aca112008-12-18 19:13:42 +0000272#error Unsupported processor type !
273#endif